Display device and method for manufacturing a display device

Abstract

A display device and a manufacturing method of a display device are provided. The manufacturing method includes: stacking a release layer on a first substrate; forming a conductor pattern on the release layer; forming a sacrificial layer on the conductor pattern; forming a second substrate including a polymer layer on the sacrificial layer; forming an electronic element including a conductor on the second substrate; forming a pattern corresponding to the conductor pattern in the sacrificial layer; transferring the conductor pattern from the release layer to a surface of the second substrate; and removing the first substrate, the release layer, and the sacrificial layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0033686, filed on March 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a display device and a manufacturing method of the display device. BACKGROUND

[0003] A display device such as an organic light emitting diode display includes a display panel. The display panel can be manufactured by forming pixels and circuit elements for driving the pixels on a substrate.

[0004] The display panel can include a display area on which an image is displayed and a non-display area in which a driving circuit, a signal line, etc. are disposed. The display area can form a screen of the display panel. The non-display area can be positioned at an edge of the display panel. A pad portion in which a pad (or referred to as a "bonding pad") for inputting / outputting a signal is disposed can be formed in the non-display area of the display panel, and a flexible circuit film can be bonded to the pad portion.

[0005] There is an increasing demand for electronic devices (e.g., a smart phone, a tablet personal computer, a laptop computer, a television, a monitor, etc.) having a large screen-to-body ratio. The size of the non-display area of the display panel prevents the screen-to-body ratio of the electronic device from increasing. Accordingly, the size of the non-display area is decreasing. However, in order to decrease the non-display area, elements disposed in the non-display area are designed compactly or omitted, thereby reducing the reliability of the display device.

[0006] There is also a demand for a high-resolution display device. In order to produce a high-resolution display device, the number of signals transmitted to the display panel increases, and the number of pads increases. In order to increase the number of pads in a limited pad portion, a pad pitch is decreased; however, this can have constraints such as a tolerance limit and bonding reliability. In addition, because more wirings are finally disposed in the display area and / or the non-display area, a wiring resistance increases, thereby causing a reduction in display quality and an increase in power consumption. SUMMARY

[0007] A manufacturing method of a display device according to one or more embodiments includes the steps of: stacking a release layer on a first substrate; forming a conductor pattern on the release layer; forming a sacrificial layer on the conductor pattern; forming a second substrate including a polymer layer on the sacrificial layer; forming an electronic element including a conductor on the second substrate; forming a pattern corresponding to the conductor pattern in the sacrificial layer; transferring the conductor pattern from the release layer to a surface of the second substrate; and removing the first substrate, the release layer, and the sacrificial layer.

[0008] The release layer can be a dynamic release layer.

[0009] The pattern in the sacrificial layer can be an engraved pattern, and the step of forming the pattern in the sacrificial layer can include irradiating the conductor pattern with a laser to remove portions of the sacrificial layer that overlap the conductor pattern.

[0010] The step of removing the portions of the sacrificial layer that overlap the conductor pattern can include evaporating the portions of the sacrificial layer that overlap the conductor pattern.

[0011] The step of transferring the conductor pattern to the surface of the second substrate can include irradiating the conductor pattern with a laser to melt the conductor pattern and fuse the melted conductor pattern into the pattern in the sacrificial layer.

[0012] The method of manufacturing a display device can further include forming an overcoat layer covering the conductor pattern after forming the conductor pattern and before forming the sacrificial layer.

[0013] The method of manufacturing a display device can further include electrically connecting the conductor pattern and the conductor.

[0014] The step of removing the first substrate, the release layer, and the sacrificial layer can include removing the sacrificial layer after simultaneously separating the first substrate and the release layer from the sacrificial layer.

[0015] The electronic element can include a transistor and a light emitting element.

[0016] The conductor can include a pad, a power line, or a data line.

[0017] The conductor pattern can include a pad, a power line, or a data line.

[0018] The sacrificial layer can include a porous polymer.

[0019] The pattern in the sacrificial layer can be a porous pattern, and the step of forming the pattern in the sacrificial layer can include irradiating the conductor pattern with a laser to increase a porosity of portions of the sacrificial layer corresponding to the conductor pattern.

[0020] The step of transferring the conductor pattern from the release layer to the surface of the second substrate can include fusing the conductor pattern into the pattern in the sacrificial layer.

[0021] The surface of the second substrate on which the conductor pattern is transferred can be a rear surface of the second substrate.

[0022] A display device according to one or more embodiments includes a substrate, an electronic element disposed over the substrate and including a conductor, a conductor pattern positioned under the substrate, and a connector that penetrates the substrate and electrically connects the conductor and the conductor pattern, wherein the conductor pattern can include a pad, a power line, or a data line.

[0023] The conductor pattern can be disposed on a rear surface of the substrate.

[0024] The substrate can be a polymer layer having a thickness less than 100 micrometers.

[0025] The conductor pattern can include a conductive material and a polymer.

[0026] The conductor pattern can include a porous polymer and a conductive material filled in the porous polymer.

[0027] The electronic element can include a circuit element and a light emitting element, the circuit element can include a conductor, and the conductor can include a power line or a data line.

[0028] The substrate can include a display area on which an image is displayed and a non-display area adjacent to the display area, and the conductor pattern can include a portion superposed with the display area.

[0029] A method of manufacturing a display device according to one or more embodiments includes the steps of: stacking a release layer on a first substrate; forming a conductor pattern on the release layer; forming a sacrificial layer on the conductor pattern; forming a second substrate on the sacrificial layer; forming a conductor on the second substrate; irradiating a laser to the conductor pattern to remove a portion of the sacrificial layer superposed with the conductor pattern and to transfer the conductor pattern to the second substrate in a space formed in the sacrificial layer; and removing the first substrate, the release layer, and the sacrificial layer.

[0030] The sacrificial layer can include a porous polymer.

[0031] The laser can be irradiated from a first surface of the first substrate to the conductor pattern disposed at a second surface of the first substrate facing away from the first surface. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A schematic front view of a display device according to an exemplary embodiment of the present application is illustrated.

[0033] Figure 2 A schematic rear view of the display device illustrated in FIG. Figure 1

[0034] Figure 3 A schematic cross-sectional view of a display device according to an exemplary embodiment of the present application is illustrated.

[0035] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 ​、 Figure 14 and Figure 15 A cross-sectional view of a manufacturing process of the display device shown in Figure 3 A cross-sectional view of a manufacturing process of the display device shown in

[0036] Figure 16 A cross-sectional view of a manufacturing process of the display device shown in

[0037] Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 and Figure 21 A cross-sectional view of a manufacturing process of the display device shown in Figure 16 A cross-sectional view of a manufacturing process of the display device shown in

[0038] Figure 22 A cross-sectional view of a manufacturing process of the display device shown in

[0039] Figure 23 A cross-sectional view of a manufacturing process of the display device shown in

[0040] Figure 24 A cross-sectional view of a manufacturing process of the display device shown in DETAILED DESCRIPTION

[0041] Hereinafter, exemplary embodiments of the present application will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present application can be modified in various different ways as those skilled in the art will understand. Like reference numerals can be used to refer to like elements throughout this specification.

[0042] Throughout the specification, like reference numerals can be used to refer to like elements throughout this specification.

[0043] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity.

[0044] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements can also be present.

[0045] Spatially relative terms, such as "under", "below", "lower", "above", "upper", "on", "over", "higher", "side", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. The words "on", "over", and "down" can mean from the top side of the object as viewed in the direction of the normal to the surfaces of the object and the words "under", "below", and "down" can mean from the bottom side of the object as viewed in the direction of the normal to the surfaces of the object throughout the specification. The term "on" as used herein means in direct contact with.

[0046] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises", "comprising", and / or "including" and / or their variants are intended to be construed as open ended, meaning that the stated features, integers, steps, operations, elements, components and / or groups thereof, can be present in a combination, but not necessarily in all combinations, and that one or more features, integers, steps, operations, elements, components and / or groups thereof, can be present in a combination, but not necessarily in all combinations.

[0047] In the drawings, as the symbols for indicating directions, x is a first direction, y is a second direction perpendicular to the first direction, and z is a third direction perpendicular to the first direction and the second direction. The first direction x, the second direction y, and the third direction z can correspond to a horizontal direction, a vertical direction, and a thickness direction of the display device, respectively.

[0048] Exemplary embodiments of a display device according to the present application will now be described in detail with reference to the accompanying drawings.

[0049] Figure 1 A schematic front view of a display device according to exemplary embodiments of the present application is shown, Figure 2 A schematic rear view of the display device shown in Figure 1 FIG. 1 is shown. Here, a front surface of the display device is one surface of a substrate of the display panel 10, and a rear surface of the display device is another surface of the substrate of the display panel 10.

[0050] Referring to Figure 1 , the display device includes a display panel 10, and the display panel 10 includes a display area DA and a non-display area NA, the display area DA being an inner area of a boundary line BL indicated by a dotted line, and the non-display area NA being an outer area of the boundary line BL. In the display panel 10, the display area DA corresponds to a screen on which an image is displayed. The display area DA is also referred to as an active area. Circuits and / or signal lines for generating and / or transmitting various signals to be applied to the display area DA are provided in the non-display area NA around the display area DA. The non-display area NA can surround the display area DA.

[0051] In the display region DA of the display panel 10, for example, the pixels PX are arranged in a matrix. When the display device is an organic light-emitting diode display, signal lines such as the gate lines GL, the data lines DL, and the drive voltage lines DVL are also provided in the display region DA. The gate lines GL, the data lines DL, and the drive voltage lines DVL extend to the non-display region NA. In other words, the gate lines GL, the data lines DL, and the drive voltage lines DVL can be provided in the non-display region NA. In the display region DA, the gate lines GL can extend in a first direction x, and the data lines DL and the drive voltage lines DVL can extend in a second direction y. A common voltage line CVL for transmitting a common voltage can be provided in the non-display region NA.

[0052] The gate lines GL, the data lines DL, and the drive voltage lines DVL are connected to each of the pixels PX. Each of the pixels PX can receive a gate signal, a data signal, and a drive voltage from the gate line GL, the data line DL, and the drive voltage line DVL connected thereto. Each of the pixels PX can include a light-emitting element, which can be an organic light-emitting diode. Signal lines such as a sensing line or an emission control line, or signal lines for transmitting signals different from the above-mentioned signals, which can be connected to the pixels PX, can also be provided in the display region DA. A touch sensor layer for sensing a contact touch or a non-contact touch of a user can be provided in the display region DA.

[0053] Referring to Figure 2 A pad portion PP including pads P for receiving signals from the outside of the display panel 10 is provided on the rear surface of the display panel 10. The display device can include a flexible printed circuit film bonded to the pad portion PP. The pads of the flexible printed circuit film can be electrically connected to the pads P of the pad portion PP by an anisotropic conductive film or the like.

[0054] In general, the pad portion PP is provided in the non-display region NA at the front surface of the display panel 10. Since the pad portion PP requires a predetermined area for bonding to the flexible printed circuit film, the pad portion PP causes the size of the non-display region NA to increase. As in the present embodiment, by forming the pad portion PP on the rear surface of the display panel 10, the size of the non-display region NA can be reduced, and thus, the screen-to-body ratio of the display device can be increased. The pads P of the pad portion PP can be electrically connected to signal lines such as the data lines DL, the drive voltage lines DVL, and the common voltage line CVL provided on the front surface of the display panel 10 by a connecting member formed through the substrate. The connecting member can be formed of a conductive material such as a metal or a metal alloy.

[0055] The pad portion PP can extend along the vicinity of one edge in the rear surface of the display panel 10. For example, the pad portion PP can extend in the first direction x. When the display panel 10 is a front emission type light emitting display panel, no image is displayed on the rear surface of the display panel 10. Thus, the entire rear surface of the display panel 10 can be a non-display area, and the pad portion PP can be disposed at any position on the rear surface of the display panel 10. Further, the pad portion PP can overlap the display area DA of the front surface of the display panel 10. Thus, even if the number of pads P increases according to high resolution, the design margin for arranging the pads P can increase. Thus, the size and pitch of the pads P of the pad portion PP can be designed more freely, and the reliability of the engagement with the flexible printed circuit film can increase.

[0056] Power supply lines such as the drive voltage lines DVL' and the common voltage lines CVL' can be positioned on the rear surface of the display panel 10. The data lines DL' can also be positioned on the rear surface of the display panel 10. The drive voltage lines DVL', the common voltage lines CVL', and the data lines DL' can be connected to the drive voltage lines DVL, the common voltage lines CVL, and the data lines DL, respectively, disposed on the front surface of the display panel 10 through the connectors formed through the substrate. As such, the signal lines (DVL', CVL', DL') are formed on the rear surface of the display panel 10, and they are electrically connected to the signal lines (DVL, CVL, DL) formed on the front surface of the display panel 10, thereby reducing the resistance and load effect of the signal lines. Thus, the display quality such as the brightness uniformity of the display area DA can increase, and the color crosstalk of red, green, and blue (RGB) can decrease.

[0057] Hereinafter, the pads P, the drive voltage lines DVL', the common voltage lines CVL', the data lines DL', etc. formed on the rear surface of the display panel 10 are referred to as a conductor pattern, and the data lines DL, the drive voltage lines DVL, the common voltage lines CVL, etc. disposed on the front surface of the display panel 10 and electrically connected to the conductor pattern through the connectors are referred to as a conductor.

[0058] The display device includes a driving unit. The driving unit can generate and / or process various signals for driving the display panel 10. The driving unit can include a data driver for applying a data signal to the data lines DL, a gate driver for applying a gate signal to the gate lines GL, and a signal controller for controlling the data driver and the gate driver. The gate driver, the data driver, and / or the signal controller can be positioned in the non-display area NA of the display panel 10. Also, the gate driver, the data driver, and / or the signal controller can be positioned on a flexible printed circuit film or a printed circuit board electrically connected to the flexible printed circuit film. For example, the gate driver can be integrated in the non-display area NA of the display panel 10, and the data driver and the signal controller can be mounted on the flexible printed circuit film as a type of integrated circuit chip.

[0059] Figure 3 A schematic cross-sectional view of a display device according to an exemplary embodiment of the present application is shown.

[0060] Figure 3 A cross-sectional structure for explaining the positional relationship in cross-sectional view of constituent elements in the display device shown in Figure 1 and Figure 2 is schematically shown. Thus, Figure 3 constituent elements are shown in a different manner from that shown in Figure 1 and Figure 2 . Thus, the planar positions of the constituent elements do not necessarily correspond to the constituent elements shown in Figure 1 and Figure 2 .

[0061] Referring to Figure 3 , the display panel 10 includes a substrate SB, an electronic element EE disposed on the substrate SB, and a transfer conductor pattern TCP disposed below the substrate SB. The substrate SB can be a polymer layer having a thickness of less than about 100 micrometers. The upper side of the substrate SB on which the electronic element EE is disposed corresponds to the front side (in other words, the area in which the screen exists) of the display panel 10 or the substrate SB. The lower side of the substrate SB on which the transfer conductor pattern TCP is disposed corresponds to the rear surface of the display panel 10 or the substrate SB.

[0062] The electronic elements EE include the pixels PX of the display panel 10 and the electrical and / or electronic elements formed or arranged on the substrate SB for driving the pixels PX. The electronic elements EE include circuit elements such as transistors, capacitors, and signal lines. When the display panel 10 is an organic light emitting display panel, the electronic elements EE include light emitting elements such as organic light emitting diodes. The circuit elements of the electronic elements EE can be formed by forming conductive layers on the substrate SB and patterning the conductive layers, and insulating layers can be formed between the conductive layers for insulation between the conductive layers. The circuit elements of the electronic elements EE include the conductors CT electrically connected to the transfer conductor pattern TCP through the connection CN. As described above, the conductors CT can include the data lines DL, the drive voltage lines DVL, and / or the common voltage lines CVL. Further, the conductors CT can have a configuration in which the electronic elements EE are included and through which electrical signals can be transmitted. For example, the conductors CT can be one electrode of a transistor.

[0063] The display panel 10 can include an encapsulation layer EC for encapsulating the electronic elements EE. The encapsulation layer EC encapsulates the display area DA to prevent water or oxygen from permeating into the display panel 10 (specifically, the display area DA).

[0064] The transfer conductor pattern TCP disposed on the rear surface of the substrate SB below the substrate SB can include at least one of the pads P, the drive voltage lines DVL', the common voltage lines CVL', and the data lines DL' described above. The transfer conductor pattern TCP is not initially formed on the rear surface of the substrate SB, but is transferred to the rear surface of the substrate SB after being formed on a transfer paper. The transfer conductor pattern TCP can be formed by using a laser transfer technique. The transfer conductor pattern TCP can be formed of various conductive materials such as metals, metal alloys, transparent conductive oxides, and conductive polymers. For example, the transfer conductor pattern TCP can be formed of copper, a copper alloy, aluminum, an aluminum alloy, or the like.

[0065] Because the electronic elements EE of the display panel 10 are formed on the substrate SB, in order to transmit signals or voltages input to the transfer conductor pattern TCP to the electronic elements EE, the connection CN for electrically connecting the transfer conductor pattern TCP and the conductor CT is disposed in the substrate SB. In other words, the connection CN is disposed in the hole of the substrate SB, and one end thereof and the other end thereof are connected to the transfer conductor pattern TCP and the conductor CT, respectively. The hole of the substrate SB and the connection CN can be formed in a third direction z substantially perpendicular to the planar surface of the substrate SB.

[0066] The structural features of the display device according to the exemplary embodiment of the present application have been described so far. Now, a method of manufacturing the display device as shown in FIG. 1 will be described. Figure 3

[0067] Figures 4 to 15 ​A cross-sectional view of a manufacturing process of the display apparatus shown in FIG. 1 is shown. Figure 3 A cross-sectional view of a manufacturing process of the display apparatus shown in FIG. 1 is shown.

[0068] Referring to Figure 4 A release layer RL such as a dynamic release layer is stacked on the carrier substrate CS. The release layer RL can be formed by coating the carrier substrate CS with a material such as an ultraviolet (UV) degradable photopolymer, and the release layer RL can be attached to the carrier substrate CS by an adhesive. A triazene polymer can be used as the UV degradable photopolymer. The release layer RL can be used as a light-to-heat conversion layer.

[0069] A transparent substrate such as a glass substrate can be used as the carrier substrate CS. The carrier substrate CS can have a characteristic that a laser can be transmitted therethrough, so that laser energy can be transmitted through the carrier substrate CS.

[0070] Referring to Figure 5 A conductor pattern CP is formed by forming a conductive layer on the release layer RL and patterning the conductive layer. The conductive layer can be formed according to a material by various methods such as sputtering, vapor deposition, and coating. The patterning can be performed by a photolithography process.

[0071] Referring to Figure 6 An overcoat layer OC is formed on the release layer RL on which the conductor pattern CP is formed. The overcoat layer OC planarizes a surface that is not planar due to the conductor pattern CP. The overcoat layer OC can be omitted.

[0072] Referring to Figure 7 A sacrificial layer SL is formed on the overcoat layer OC. A porous polymer can be used as the sacrificial layer SL. The porous polymer can be formed by coating a hydrophobic polymer solution under a humid condition and evaporating water droplets in the hydrophobic polymer solution. The pores of the porous polymer can be controlled by controlling humidity, temperature, moving speed, etc., and the pore size can be about 100 nanometers to several tens of micrometers.

[0073] Referring to Figure 8 A substrate SB is stacked on the sacrificial layer SL. The substrate SB can be a flexible substrate formed by coating a polymer such as polyimide (PI), polyamide (PA), or polyethylene terephthalate (PET) on the sacrificial layer SL. The substrate SB can have a thin thickness such as less than about 100 micrometers, less than about 50 micrometers, less than about 30 micrometers, or less than about 15 micrometers.

[0074] Referring to Figure 9An electronic element EE is formed on the substrate SB. The step of forming the electronic element EE can include forming conductors CT such as signal lines, transistors, and capacitors on the substrate SB, and forming light emitting elements (e.g., organic light emitting diodes or light emitting diodes) connected to the signal lines, transistors, and / or capacitors. An encapsulation layer EC can be formed on the electronic element EE to cover and seal the electronic element EE.

[0075] Referring to Figure 10 Laser light is irradiated from the rear surface of the carrier substrate CS onto the conductor pattern CP to remove the portions of the overcoat layer OC and the sacrificial layer SL that are superimposed with the conductor pattern CP. In other words, the portions of the overcoat layer OC and the sacrificial layer SL to be removed are ablated by the laser light. The laser light can be focused on the conductor pattern CP. The portions of the overcoat layer OC and the sacrificial layer SL that are superimposed with the conductor pattern CP can be evaporated and removed by heat of the conductor pattern CP heated by the laser energy. Because the sacrificial layer SL is porous, the evaporated material can escape through the pores of the sacrificial layer SL. By such laser irradiation, an imprint pattern corresponding to the conductor pattern CP can be formed in the sacrificial layer SL. The imprint pattern formed in the sacrificial layer SL is formed by removing the portions of the sacrificial layer SL corresponding to the conductor pattern CP in the sacrificial layer SL. The imprint pattern in the sacrificial layer SL can be formed through the sacrificial layer SL. In other words, the imprint pattern can pass through from one side of the sacrificial layer SL to the other side of the sacrificial layer SL. For example, the imprint pattern can be an opening or a space formed in the sacrificial layer SL. Accordingly, the portions of the substrate SB corresponding to the conductor pattern CP can not be covered with the sacrificial layer SL.

[0076] Referring to Figure 11 Laser light is irradiated from the rear surface of the carrier substrate CS onto the conductor pattern CP to fuse the conductor pattern CP into the imprint pattern in the sacrificial layer SL. The laser light can be focused on the conductor pattern CP. The conductor pattern CP can be melted by the laser energy. In addition, due to the local heating in the region superimposed with the conductor pattern CP, a blister can be generated at the interface between the release layer RL and the carrier substrate CS. The release layer RL can be a photothermal conversion layer that receives light (e.g., the laser light) and generates heat, and due to the generated heat, the blister can expand. When the blister expands, the release layer RL pushes the melted conductor pattern MCP in the third direction z, and thus, the melted conductor pattern MCP can be accurately fused into the imprint pattern in the sacrificial layer SL. Accordingly, as shown in Figure 12 The conductor pattern CP formed on the release layer RL is transferred to the rear surface of the substrate SB to form a transferred conductor pattern TCP.

[0077] Hereinafter, referring to Figure 13 The release layer RL is separated from the overcoat layer OC together with the carrier substrate CS by a laser lift-off method. Then, referring toFigure 14 The overcoat layer OC and the sacrificial layer SL remaining on the rear surface of the substrate SB are removed. The overcoat layer OC and the sacrificial layer SL can be separated from the substrate SB together by a laser lift-off method in which a laser is irradiated between the substrate SB and the sacrificial layer SL.

[0078] Referring to Figure 15 The conductor CT provided on the front surface of the substrate SB and the transfer conductor pattern TCP provided on the rear surface of the substrate SB are electrically connected by the connector CN formed in the hole that penetrates the substrate SB. Accordingly, a signal and a voltage applied to the transfer conductor pattern TCP can be transmitted to the electronic element EE positioned on the substrate SB. In addition, a signal from the electronic element EE can be transmitted to the transfer conductor pattern TCP. The hole of the substrate SB and the connector CN can be formed by a through-silicon via (TSV) method and a through-glass via (TGV) method. The hole of the substrate SB and the connector CN can be perpendicular to the flat surface of the substrate SB. The connector CN can be formed of a conductor such as a metal or a metal alloy. The connector CN can be formed before the electronic element EE is formed on the substrate SB or while the electronic element EE is formed, or can be formed after the electronic element EE is formed. A portion of the transfer conductor pattern TCP other than a portion used to form the pad P described above can be covered with a passivation layer such as an insulating layer for preventing oxidation, etc.

[0079] Figure 16 A schematic cross-sectional view of a display device according to an exemplary embodiment of the present application is shown.

[0080] Figure 16 The display device shown in Figure 3 differs from the display device shown in Figure 3 The transfer conductor pattern TCP of Figure 16 may have a conductive material fused into a porous pattern of the sacrificial layer SL. Accordingly, Figure 16 The transfer conductor pattern TCP of Figures 17 to 21 will now be described with reference to

[0081] Figures 17 to 21 A cross-sectional view of a manufacturing process of the display device shown in Figure 16 is shown.

[0082] In the display device shown in Figure 16 the steps of forming the electronic element EE and the encapsulation layer EC on the substrate SB from the step of stacking the release layer RL on the carrier substrate CS are the same as those described with reference to Figures 4 to 9The described steps are the same.

[0083] Then, referring to Figure 17 laser light is irradiated from the back surface of the carrier substrate CS onto the conductor pattern CP to remove the portion of the overcoat layer OC superimposed with the conductor pattern CP, thereby making the portion of the sacrificial layer SL superimposed with the conductor pattern CP more porous. The laser light can be focused on the conductor pattern CP. Unlike the process described with reference to Figure 10 Without completely removing the portion of the sacrificial layer SL superimposed with the conductor pattern CP, the laser energy locally evaporates the portion of the sacrificial layer SL superimposed with the conductor pattern CP to increase the volume of the pores, for example, the size of the pores and / or the number of the pores. Thus, a porous pattern corresponding to the conductor pattern CP can be formed in the sacrificial layer SL. The porous pattern of the sacrificial layer SL is more porous than another portion of the sacrificial layer SL, and thus the porous pattern of the sacrificial layer SL can be distinguished from the other portion of the sacrificial layer SL (in other words, the portion of the sacrificial layer SL not superimposed with the conductor pattern CP). The process of making the portion of the sacrificial layer SL superimposed with the conductor pattern CP more porous without completely removing it can be performed, for example, by appropriately adjusting the material forming the sacrificial layer SL or the laser energy.

[0084] Referring to Figure 18 laser light is irradiated from the back surface of the carrier substrate CS onto the conductor pattern CP to fuse the conductor pattern CP into the porous pattern of the sacrificial layer SL. The laser light can be focused on the conductor pattern CP. The conductor pattern CP can be melted by the laser energy, and a blister caused by local heating in the area superimposed with the conductor pattern CP can be generated at the interface between the release layer RL and the carrier substrate CS. When the blister expands due to the laser energy, the release layer RL pushes away the molten conductor pattern MCP, so that the molten conductor pattern MCP can be accurately fused into the porous pattern of the sacrificial layer SL and then solidified on the back surface of the substrate SB. For example, when the release layer RL pushes away the molten conductor pattern MCP, a space can be formed between the release layer RL and the molten conductor pattern MCP. Thus, as shown in Figure 19 the conductor pattern CP formed on the release layer RL is transferred to the back surface of the substrate SB to form a transferred conductor pattern TCP. The transferred conductor pattern TCP has a state in which the conductive material in which the transferred conductor pattern TCP is formed is fused into the porous pattern of the sacrificial layer SL. Thus, the pores of the porous pattern of the sacrificial layer SL can be filled with the conductive material of the transferred conductor pattern TCP.

[0085] Referring to Figure 20 and Figure 21The laser is irradiated between the release layer RL and the overcoat layer OC to separate the release layer RL together with the carrier substrate CS from the overcoat layer OC. Further, the overcoat layer OC and the sacrificial layer SL remaining on the rear surface of the substrate SB are simultaneously removed in the same process, or the overcoat layer OC and the sacrificial layer SL remaining on the rear surface of the substrate SB are separately removed in separate processes. Then, with reference to Figure 16 , a hole is formed through the substrate SB, a connection CN is formed in the hole, and the conductor CT provided on the front surface of the substrate SB is electrically connected to the transfer conductor pattern TCP provided on the rear surface of the substrate SB.

[0086] Thus far, the display device according to the exemplary embodiment of the present application and the manufacturing method thereof have been described. Hereinafter, the pixel circuit and the stacked structure with respect to the pixel that can be included in the display device according to the exemplary embodiment of the present application will be described in detail.

[0087] Figure 22 An equivalent circuit diagram of one pixel of the display device according to the exemplary embodiment of the present application is shown. Figure 22 The pixel circuit shown in FIG. 1 can be a pixel circuit that can be included in the display device according to the exemplary embodiment of the present application, and various changes can be made to the pixel circuit. Figure 1 , Figure 3 and Figure 16 The pixel circuit shown in FIG. 1 can be a pixel circuit that can be included in the display device according to the exemplary embodiment of the present application, and various changes can be made to the pixel circuit.

[0088] With reference to Figure 22 , the pixel PX includes a plurality of transistors T1, T2, and T3, a storage capacitor SC, and a light emitting element LD. A plurality of signal lines DL, GL, CL, SSL, DVL, and CVL are connected to the pixel PX. Although the pixel PX is shown to be formed with three transistors T1, T2, and T3 and one storage capacitor SC, various changes can be made to the number of transistors and capacitors. Although a structure in which six signal lines DL, GL, CL, SSL, DVL, and CVL are connected to the pixel PX is shown, various modifications can be made to the type and number of signal lines.

[0089] The signal lines DL, GL, CL, SSL, DVL, and VCL can include a data line DL, a gate line GL, a sensing control line CL, a sensing line SSL, a driving voltage line DVL, and a common voltage line CVL. The gate line GL can transmit a gate signal GW to the second transistor T2. The data line DL can transmit a data signal DS, the driving voltage line DVL can transmit a driving voltage ELVDD, and the common voltage line CVL can transmit a common voltage ELVSS. The sensing control line CL can transmit a sensing signal SS, and the sensing line SSL can be connected to a sensing portion. The transfer conductor pattern TCP described above can include a pad P, a driving voltage line DVL', a common voltage line CVL', and / or a data line DL' electrically connected to the signal lines DL, GL, SSL, DVL, and VCL described above, and the transfer conductor pattern TCP can include at least one of the signal lines DL, GL, CL, SSL, DVL, and VCL.

[0090] The transistors T1, T2, and T3 include the first transistor T1 as a driving transistor, the second transistor T2 as a switching transistor, and the third transistor T3 as a sensing transistor. The transistors T1, T2, and T3 are three-terminal elements including gate electrodes G1, G2, and G3, source electrodes S1, S2, and S3, and drain electrodes D1, D2, and D3, respectively. The source and drain electrodes are not fixed, and one of the two terminals of the transistor other than the gate electrode can be referred to as the source electrode, and the other thereof can be referred to as the drain electrode.

[0091] The gate electrode G1 of the first transistor T1 is connected to the first electrode C1 of the storage capacitor SC and the drain electrode D2 of the second transistor T2, the source electrode S1 of the first transistor T1 is connected to the driving voltage line DVL, and the drain electrode D1 of the first transistor T1 is connected to the anode of the light emitting element LD. The first transistor T1 can supply a driving current I D to the light emitting element LD, and the light emitting element LD can emit light having a certain brightness according to the size of the driving current I D . Thus, the pixel PX can display a gray scale by adjusting the amount of current flowing through the first transistor T1 according to the size of the data signal DS. The driving current I D is related to the gate-source voltage (V GS ) between the gate electrode G1 and the source electrode S1 of the first transistor T1. For example, as the gate-source voltage (V GS ) of the first transistor T1 increases, the driving current I D may increase. A light blocking layer LB, which can be laminated with the semiconductor layer of the first transistor T1, is connected to the drain electrode D1 of the first transistor T1 to improve the characteristics of the first transistor T1, such as its output saturation characteristics.

[0092] The gate electrode G2 of the second transistor T2 is connected to the gate line GL, the source electrode S2 of the second transistor T2 is connected to the data line DL, and the drain electrode D2 of the second transistor T2 is connected to the gate electrode G1 of the first transistor T1 and the first electrode C1 of the storage capacitor SC. The second transistor T2 is turned on in response to the gate signal GW transmitted through the gate line GL, so as to supply the data signal DS transmitted through the data line DL to the gate electrode G1 of the first transistor T1 and the first electrode C1 of the storage capacitor SC. This is the switching operation of the second transistor T2.

[0093] The gate electrode G3 of the third transistor T3 is connected to the sensing control line CL, the source electrode S3 of the third transistor T3 is connected to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting element LD, and the drain electrode D3 of the third transistor T3 is connected to the sensing line SSL. The third transistor T3 is used to sense a threshold voltage (V) that causes image quality degradation, such as that of the first transistor T1. th A third transistor T3 is activated in response to a sensing signal SS transmitted via a sensing control line CL, electrically connecting the first transistor T1 to a sensing line SSL. The sensing portion of the sensing line SSL can sense the characteristic information of the first transistor T1 during the sensing period. A compensation data signal is generated by reflecting the characteristic information sensed by the third transistor T3 during the sensing period, allowing external compensation for characteristic deviations of the first transistor T1, which may be different for each pixel PX.

[0094] The first electrode C1 of the storage capacitor SC is connected to the gate electrode G1 of the first transistor T1 and the drain electrode D2 of the second transistor T2, and the second electrode C2 of the storage capacitor SC is connected to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting element LD. The storage capacitor SC can continuously apply the charged data signal DS to the first transistor T1, thereby continuously operating the light-emitting element LD to emit light during the light-emitting period. The cathode of the light-emitting element LD can be connected to the common voltage line CVL for transmitting the common voltage ELVSS.

[0095] The transfer conductor pattern TCP may include portions electrically connected to at least one electrode in transistors T1, T2, and T3 and storage capacitor SC.

[0096] Reference Figure 23 The construction of the display panel 10, which may be included in a display device according to an exemplary embodiment of the present invention, is described.

[0097] Figure 23 A cross-sectional view of the stacked structure of a display panel 10 according to an exemplary embodiment of the present invention is shown. Figure 23The cross-section shown in FIG. 1A can substantially correspond to a cross-section taken along a line A-A' of FIG. 1B. Figure 1 The cross-section shown in FIG. 1A can substantially correspond to a cross-section taken along a line A-A' of FIG. 1B.

[0098] The display panel 10 includes a substrate SB, a transistor T formed on the substrate SB, and an organic light emitting diode OLED connected to the transistor T. The transistor T can be a driving transistor T1 as shown in FIG. 1A. Figure 22 The display panel 10 includes a substrate SB, a transistor T formed on the substrate SB, and an organic light emitting diode OLED connected to the transistor T. The transistor T can be a driving transistor T1 as shown in FIG. 1A.

[0099] The substrate SB can be a flexible substrate formed of a polymer such as polyimide (PI), polyamide (PA), polyethylene terephthalate (PET), or the like. The substrate SB can include a barrier layer for preventing moisture, oxygen, or the like from permeating from the outside. For example, the substrate SB can include at least one polymer layer and at least one barrier layer, and the polymer layer and the barrier layer can be alternately stacked.

[0100] A first insulating layer IN1 is disposed on the substrate SB. The first insulating layer IN1 can be a buffer layer, and it can block diffusion of impurities from the substrate SB to a semiconductor layer A and reduce stress applied to the substrate SB in a process of forming the semiconductor layer A. The barrier layer and the first insulating layer IN1 can include an inorganic insulating material such as silicon oxide or silicon nitride.

[0101] A semiconductor layer A of the transistor T is disposed on the first insulating layer IN1, and a second insulating layer IN2 is disposed on the semiconductor layer A. The semiconductor layer A includes a source region, a drain region, and a channel region between the source region and the drain region. The semiconductor layer A can include a semiconductor material such as polysilicon, oxide semiconductor, and amorphous silicon. The second insulating layer IN2 can be a gate insulating layer, and can include an inorganic insulating material.

[0102] A gate conductor including a gate electrode G of the transistor T and a gate line is disposed on the second insulating layer IN2. The gate conductor can include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti), or a metal alloy thereof.

[0103] A third insulating layer IN3 is disposed on the gate conductor. The third insulating layer IN3 can be an interlayer insulating layer, and can include an inorganic insulating material.

[0104] Data conductors including source and drain electrodes S and D of the transistor T, a driving voltage line DVL, and a data line DL are positioned on the third insulating layer IN3. The source and drain electrodes S and D are connected to a source region and a drain region of the semiconductor layer A, respectively, through contact holes formed in the third insulating layer IN3 and the second insulating layer IN2. The data conductors can include a metal such as aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), gold (Au), platinum (Pt), palladium (Pd), tantalum (Ta), tungsten (W), titanium (Ti), nickel (Ni), or a metal alloy thereof.

[0105] A fourth insulating layer IN4 is disposed on the data conductors. The fourth insulating layer IN4 can be a planarization layer or a passivation layer, and can include an organic insulating material.

[0106] A first electrode E1 is disposed on the fourth insulating layer IN4. The first electrode E1 can be a pixel electrode. The first electrode E1 can be connected to the drain electrode D through a contact hole formed in the fourth insulating layer IN4 to receive a data signal for controlling brightness of the organic light emitting diode OLED.

[0107] A fifth insulating layer IN5 is disposed on the fourth insulating layer IN4. The fifth insulating layer IN5 can be a pixel definition layer, and can be provided with an opening overlapping the first electrode E1. In the opening of the fifth insulating layer IN5, a light emitting layer EL is disposed on the first electrode E1 and a second electrode E2 is disposed on the light emitting layer EL. The second electrode E2 can be a common electrode.

[0108] The first electrode E1, the light emitting layer EL, and the second electrode E2 form a light emitting element (e.g., an organic light emitting diode OLED). The first electrode E1 can be an anode of the organic light emitting diode OLED, and the second electrode E2 can be a cathode of the organic light emitting diode OLED.

[0109] An encapsulation layer EC is disposed on the second electrode E2. The encapsulation layer EC can encapsulate the organic light emitting diode OLED to prevent moisture or oxygen from penetrating from the outside. The encapsulation layer EC can include at least one inorganic material layer and at least one organic material layer, and the inorganic material layer and the organic material layer can be alternately stacked.

[0110] A touch sensor layer TS can be disposed on the encapsulation layer EC. The touch sensor layer TS can include a touch electrode formed of a transparent conductive material such as ITO or IZO, a metal mesh, or the like, and the touch electrode can be formed as a single layer or multiple layers. The touch sensor layer TS can be formed directly on the encapsulation layer EC, or separately formed to be attached to the encapsulation layer EC.

[0111] An anti-reflection layer AR for reducing reflection of external light can be provided on the touch sensor layer TS. The anti-reflection layer AR can include a polarizing layer. The anti-reflection effect can be obtained by forming the encapsulation layer EC and / or the touch sensor layer TS in a refractive index matching structure, without separately forming the anti-reflection layer AR.

[0112] A transfer conductor pattern including power supply voltage lines such as a drive voltage line DVL', data lines DL', and the like is provided under the substrate SB. The drive voltage line DVL' and the data lines DL' are electrically connected to the drive voltage line DVL and the data lines DL provided on the substrate SB through connection members CN formed in the substrate SB and the first, second, and third insulating layers IN1, IN2, and IN3, respectively.

[0113] A passivation layer PL covering the transfer conductor pattern can be provided under the transfer conductor pattern. A passivation film for protecting the display panel 10, which can be formed of PET or the like, can be positioned under the passivation layer PL, and functional sheets such as a cushion layer, a heat dissipation sheet, a light blocking sheet, and a waterproof tape can be provided under the passivation film.

[0114] It has been described that the display panel 10 is an organic light emitting display panel, but the display panel 10 can be a display panel including light emitting diodes (LEDs), a display panel including a liquid crystal layer, or the like.

[0115] Figure 24 A cross-sectional view of a cushion portion of a display device according to an exemplary embodiment of the present application is shown. Figure 24 may correspond to a cross-section taken along a line B-B' of Figure 1 .

[0116] Referring to Figure 24 , the display panel 10 includes a cushion portion PP in which a cushion P provided on a rear surface of the substrate SB is disposed. The cushion P can be the transfer conductor pattern TCP or a portion of the transfer conductor pattern TCP described above. The cushion P can be electrically connected to conductors such as the data lines DL, the drive voltage lines DVL, and the common voltage lines CVL provided on the substrate SB through connection members CN formed through the substrate SB, the first insulating layer IL1, and the second insulating layer IL2.

[0117] Unlike as shown in Figure 23 , the conductors such as the data lines DL, the drive voltage lines DVL, and the common voltage lines CVL connected to the cushion P can be provided between the second insulating layer IN2 and the third insulating layer IN3. The conductors on the substrate SB electrically connected to the transfer conductor pattern TCP can be variously provided between the substrate SB and the first insulating layer IN1, between the first insulating layer IN1 and the second insulating layer IN2, between the second insulating layer IN2 and the third insulating layer IN3, and on the third insulating layer IN3.

[0118] Thus, by forming the pad portion PP on the rear surface of the substrate SB, the non-display area NA of the display panel 10 can be reduced, and the degree of freedom in designing the pad portion PP can be increased. The pad portion PP can overlap the non-display area NA of the display panel 10, can overlap the display area DA, or can overlap both the display area DA and the non-display area NA.

[0119] Exemplary embodiments of the present application provide a display device that improves screen ratio and reliability and a manufacturing method thereof.

[0120] For example, according to embodiments of the present application, the non-display area of a display device can be reduced to increase the screen ratio and to improve the degree of freedom in designing a conductor pattern such as a pad portion and the resistance characteristics of a signal line.

[0121] While the present application has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present application as set forth in the appended claims.

Claims

1. A method for manufacturing a display device, the method comprising the steps of: stacking a release layer over a first substrate; forming a conductor pattern over the release layer; forming a sacrificial layer over the conductor pattern; forming a second substrate comprising a polymer layer over the sacrificial layer; forming an electronic element comprising a conductor over the second substrate; forming a pattern corresponding to the conductor pattern in the sacrificial layer; transferring the conductor pattern from the release layer to a surface of the second substrate; and removing the first substrate, the release layer, and the sacrificial layer.

2. The method for manufacturing a display device according to claim 1, wherein the release layer is a dynamic release layer.

3. The method for manufacturing a display device according to claim 1, wherein the pattern in the sacrificial layer is an imprint pattern, and the step of forming the pattern in the sacrificial layer comprises irradiating the conductor pattern with a laser to remove a portion of the sacrificial layer superimposed with the conductor pattern.

4. The method for manufacturing a display device according to claim 3, wherein the step of removing the portion of the sacrificial layer superimposed with the conductor pattern comprises evaporating the portion of the sacrificial layer superimposed with the conductor pattern.

5. The method for manufacturing a display device according to claim 1, wherein the step of transferring the conductor pattern to the surface of the second substrate comprises irradiating the conductor pattern with a laser to melt the conductor pattern, and fusing the melted conductor pattern into the pattern in the sacrificial layer.

6. The method for manufacturing a display device according to claim 1, further comprising forming an overcoat layer covering the conductor pattern after forming the conductor pattern and before forming the sacrificial layer.

7. The method for manufacturing a display device according to claim 1, further comprising electrically connecting the conductor pattern and the conductor.

8. The method for manufacturing a display device according to claim 1, wherein the step of removing the first substrate, the release layer, and the sacrificial layer comprises removing the sacrificial layer after simultaneously separating the first substrate and the release layer from the sacrificial layer.

9. The method for manufacturing a display device according to claim 1, wherein the sacrificial layer comprises a porous polymer.

10. The method for manufacturing a display device according to claim 9, wherein the pattern in the sacrificial layer is a porous pattern, and the step of forming the pattern in the sacrificial layer comprises irradiating the conductor pattern with a laser to increase a porosity of a portion of the sacrificial layer corresponding to the conductor pattern. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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