Semiconductor device and method of forming the same

Abstract

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. A gate is disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source / drain region is disposed in the device region and on a first side of the gate. A second source / drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source / drain region, and partially covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method of forming the same. Background Art

[0002] A semiconductor device is an electronic component that utilizes the electronic properties of a semiconductor material to affect an electric field or its associated fields. One widely used type of semiconductor device is a field-effect transistor (FET). An FET includes a pair of source / drain regions, a selectively conductive channel, and a gate electrode. An FET is a general-purpose device that can be used in switches, amplifiers, memories, etc. Examples of FETs include metal-oxide-semiconductor field-effect transistors (MOSFETs) and junction gate field-effect transistors (JFETs). Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor device includes an isolation structure, a gate, a first source / drain region, a second source / drain region, and a silicide blocking structure. The isolation structure is disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. The gate is disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. The first source / drain region is disposed in the device region and on a first side of the gate. The second source / drain region is disposed in the device region and on a second side of the gate opposite the first side. The silicide blocking structure partially covers the gate, partially covers the first source / drain region, and partially covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.

[0004] According to an embodiment of the present invention, a semiconductor device includes: an isolation structure, a first source / drain region, a second source / drain region, a gate, a first silicide blocking structure, and a second silicide blocking structure. The isolation structure is disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a plurality of sides of a device region of the semiconductor substrate. The first source / drain region and the second source / drain region are disposed in the device region and spaced apart in a first lateral direction. The gate is disposed over the device region and between the first source / drain region and the second source / drain region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. The first silicide blocking structure covers a first portion of the gate, a first portion of the first source / drain region, and a first portion of the isolation structure. The second silicide blocking structure covers a second portion of the gate, a second portion of the first source / drain region, and a second portion of the isolation structure, wherein the second silicide blocking structure is spaced apart from the first silicide blocking structure in a second lateral direction perpendicular to the first lateral direction.

[0005] According to an embodiment of the present invention, a method of forming a semiconductor device includes: forming an isolation structure in a semiconductor substrate, wherein an inner perimeter of the isolation structure delineates a device region of the semiconductor substrate; forming a gate over the device region and within the inner perimeter of the isolation structure; forming a first source / drain region and a second source / drain region in the device region and on a first opposite side of the gate, wherein the first opposite side of the gate is spaced apart in a first lateral direction; forming a first silicide blocking structure that locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure; forming a second silicide blocking structure that is spaced apart from the first silicide blocking structure in a second lateral direction perpendicular to the first lateral direction, wherein the second silicide blocking structure locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure; and performing a silicide process to form a first silicide layer on the first source / drain region, wherein the first silicide layer is disposed between the first silicide blocking structure and the second silicide blocking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1CIllustrate various perspective views of some embodiments of a field effect transistor (FET) having low flicker noise and low random telegraph noise (RTN).

[0008] Figure 2 Illustrate Figures 1A to 1C Perspective views of some other embodiments of the illustrated FETs.

[0009] Figures 3A to 3D Illustrate Figures 1A to 1C Various diagrams of various more detailed embodiments of the illustrated FETs.

[0010] Figures 4A to 4D Illustrate Figure 2 Various diagrams of various more detailed embodiments of the illustrated FETs.

[0011] Figures 5A to 5D Illustrate Figures 3A to 3D Various diagrams of other embodiments of the illustrated FETs.

[0012] Figures 6A to 6D Illustrate Figures 4A to 4D Various diagrams of other embodiments of the illustrated FETs.

[0013] Figures 7A to 7D To Figures 16A to 16D A series of diagrams illustrating some embodiments of a method of forming an FET having low flicker noise and low RTN.

[0014] Figure 17 A flowchart illustrating some embodiments of a method of forming an FET having low flicker noise and low RTN.

[0015] [Description of Symbols]

[0016] 100: Field effect transistor (FET);

[0017] 102: Semiconductor substrate;

[0018] 104: First well;

[0019] 106: Well pick-up region;

[0020] 108: First silicide layer;

[0021] 110: Isolation structure;

[0022] 110p: Inner perimeter;

[0023] 112: Device region;

[0024] 114a: First source / drain region;

[0025] 114b: Second source / drain region;

[0026] 116: Selective conductive channel;

[0027] 118: Second silicide layer;

[0028] 120: Gate;

[0029] 122: Gate electrode;

[0030] 124: Gate dielectric;

[0031] 126: Third silicide layer;

[0032] 127: Isolation corner;

[0033] 128a, 128b, 128c, 128d: Silicide blocking structure;

[0034] 302: Sidewall spacer;

[0035] 304: Interconnection structure;

[0036] 306: Conductive contact;

[0037] 308: Interlayer dielectric (ILD) layer;

[0038] 310a: First sidewall;

[0039] 310b: Second sidewall;

[0040] 312a, 312b, 312c: Doped region;

[0041] 502: Second well;

[0042] 504: Third well;

[0043] 1002a, 1002b: Lightly doped source / drain extension;

[0044] 1700: Flowchart;

[0045] 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, 1718, 1720, 1722, 1724: Actions;

[0046] A - A’, B - B’, C - C’: Lines;

[0047] D 1 : First distance;

[0048] D 2 : Second distance;

[0049] D 3: The third distance. Detailed implementation mode

[0050] The present invention will now be described with reference to the drawings, where the same reference numerals are used throughout to refer to the same elements, and the structures illustrated are not drawn to scale. It should be understood that this detailed description and the corresponding drawings do not limit the scope of the present invention in any way, and it should be understood that the detailed description and the drawings only provide several examples to illustrate some ways in which the concepts of the present invention can be manifested.

[0051] The present invention provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature "on" or "above" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. Additionally, the present invention may reuse reference numerals and / or letters in various examples. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0052] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0053] Some field effect transistors (FETs) include a semiconductor substrate and a shallow trench isolation (STI) structure. The STI structure is disposed in the semiconductor substrate and defines a device region of the semiconductor substrate. In addition, the FET includes a pair of source / drain regions, a selectively conductive channel, a gate dielectric, and a gate electrode. The source / drain regions are disposed in the device region and are laterally spaced apart. The selectively conductive channel is disposed in the device region and extends from one of the source / drain regions to the other of the source / drain regions. The gate dielectric overlies the selectively conductive channel, and the gate electrode overlies the gate dielectric layer.

[0054] The challenges faced by the above FETs are flicker noise and random telegraph noise (RTN). One of the sources of flicker noise and RTN is the presence of defect states at a pair of STI corners. An STI corner is the top-view corner of a semiconductor substrate that is located in the device region and interfaces with the STI structure. In addition, the STI corners are located on opposite sides of the selective conductive channel, and each extends laterally along the length of the selective conductive channel from one of the source / drain regions to the other of the source / drain regions among the plurality of source / drain regions. Since the STI corners have high mechanical stress and are not bounded by a completely flat surface, the STI corners have a large number of defect states. In addition, since the STI corners have a small radius of curvature, the electric field at the STI corners is strong. Therefore, as current flows through the selective conductive channel, charge carriers are trapped and de-trapped due to the defect states, thereby generating flicker noise and RTN.

[0055] Part of the solution to the above challenges is to use the gate electrode as a mask to move the source / drain regions away from the STI corners. For example, a gate electrode is formed above the device region and above the STI corners. The gate electrode is formed with a pair of source / drain openings that overlap the device region and are spaced apart from the STI corners. With the gate electrode in place, an ion implantation process is performed to form source / drain regions in the semiconductor substrate that are spaced apart from the STI corners. By spacing the source / drain regions from the STI corners, the current flowing along the STI corners can be reduced, thereby reducing the flicker noise and RTN generated at the STI corners. However, although the source / drain regions are spaced apart from the STI corners, when a voltage is applied to the gate and current flows through the selective conductive channel, charge carriers can still be trapped and de-trapped due to the defect states at the STI corners (e.g., such that an inversion region is formed near / along the STI corners). Additionally, by using the gate electrode to move the source / drain regions away from the STI corners, a subsequent silicide formation process (e.g., a salicide process) may form a silicide layer that shorts the FET (e.g., a silicide layer that couples the source / drain regions together).

[0056] Various embodiments of the present application relate to a semiconductor device having low flicker noise and low RTN. For example, the semiconductor device may include an isolation structure (e.g., STI structure) disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. A gate is disposed over the device region, and an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source / drain region is disposed in the device region and on a first side of the gate. A second source / drain region is disposed in the device region on a second side of the gate, the second side being opposite the first side. A silicide blocking structure locally covers the gate, locally covers the first source / drain region, and locally covers the isolation structure.

[0057] Since the perimeter of the gate is disposed within the inner perimeter of the isolation structure, the gate does not overlap with the STI corner. Thus, during operation of the semiconductor device (e.g., when a voltage is applied to the gate to cause current to flow through a selectively conductive channel), charge carriers may not be trapped and detrapped due to defect states at the STI corner, thereby reducing flicker noise and RTN. Further, since the silicide blocking structure locally covers the gate, locally covers the first source / drain region, and locally covers the isolation structure, the silicide blocking structure can prevent a silicide layer that shorts the semiconductor device from being formed by a silicide process.

[0058] Figures 1A to 1C Various perspective views illustrating some embodiments of a field effect transistor (FET) 100 having low flicker noise and low random telegraph noise (RTN). Figure 1A is Figures 1B to 1C a deconstructed perspective view of the illustrated FET. Figure 1B is Figure 1A and Figure 1C a deconstructed perspective view of the illustrated FET. Figure 1C is Figures 1A to 1B a constructed perspective view of the illustrated FET.

[0059] Figure 1A What is meant by "deconstructed" is that the gate 120 and the plurality of silicide blocking structures 128a to 128d are separated from the semiconductor substrate 102 and the isolation structure 110, wherein the gate 120 and the plurality of silicide blocking structures 128a to 128d are normally disposed on / over the semiconductor substrate 102 and the isolation structure 110. Except that the isolation structure 110 is further separated from the semiconductor substrate 102 and the plurality of silicide blocking structures 128a to 128d are further separated from the gate 120, Figure 1B the "deconstructed" manner is the same as Figure 1A wherein the isolation structure 110 is normally disposed on / in the semiconductor substrate 102 and wherein the plurality of silicide blocking structures 128a to 128d are normally disposed on / over the gate 120. Figure 1CWhat is "configured" is that the gate 120 and the plurality of silicide blocking structures 128a to 128d are disposed in their normal positions. The FET can be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a junction gate field effect transistor (JFET), or some other type of field effect transistor.

[0060] As Figures 1A to 1C shown, the FET 100 includes a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 includes any type of semiconductor body (e.g., single crystal silicon / bulk complementary metal oxide semiconductor (CMOS bulk), silicon germanium (SiGe), silicon on insulator (SOI), etc.). In still other embodiments, a first well 104 is disposed in the semiconductor substrate 102. The first well 104 is a region of the semiconductor substrate 102 having a first doping type (e.g., n-type). In yet other embodiments, the first well 104 has a first concentration of a first dopant (e.g., an n-type dopant).

[0061] In some embodiments, a pair of well pickup regions 106 are disposed in the first well 104. The well pickup regions 106 are regions of the semiconductor substrate 102 having the same doping type as the first well 104. In some embodiments, the well pickup regions 106 have a second concentration of the first dopant, the second concentration being greater than the first concentration. In still other embodiments, a pair of first silicide layers 108 are respectively disposed on / in the pair of well pickup regions 106. The first silicide layer 108 can include, for example, nickel (e.g., nickel silicide), titanium (e.g., titanium silicide), cobalt (e.g., cobalt silicide), platinum (e.g., platinum silicide), tungsten (e.g., tungsten silicide), etc.

[0062] An isolation structure 110 is disposed in the semiconductor substrate 102. The inner perimeter 110p of the isolation structure 110 defines a device region 112 of the semiconductor substrate 102. In some embodiments, the isolation structure 110 can include a dielectric structure made of a dielectric material (e.g., silicon dioxide (SiO 2 )). In still other embodiments, the isolation structure 110 can be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or some other isolation structure. In yet other embodiments, the isolation structure 110 has an annular layout that laterally surrounds the device region 112. It should be understood that the annular layout is not limited to a shape in which the inner perimeter or the outer perimeter is circular. Instead, the inner perimeter or the outer perimeter of the annular layout can include any one or more geometric shapes (e.g., square, rectangle, ellipse, etc.) that, when considered together, have a substantially annular layout.

[0063] In device region 112, a first source / drain region 114a and a second source / drain region 114b are provided. The first source / drain region 114a is laterally spaced apart from the second source / drain region 114b. A selectively conductive channel 116 is provided in device region 112, and the selectively conductive channel 116 extends from the first source / drain region 114a to the second source / drain region 114b. In some embodiments, the selectively conductive channel 116 is a region of the first well 104 and provides a channel for electrons (or holes) to flow between the first source / drain region 114a and the second source / drain region 114b. In still other embodiments, the first source / drain region 114a is a first region of the semiconductor substrate 102 having a second doping type (e.g., p-type) different from the first doping type, and the second source / drain region 114b is a second region of the semiconductor substrate 102 having the second doping type.

[0064] In some embodiments, a pair of second silicide layers 118 are respectively provided on / within the first source / drain region 114a and the second source / drain region 114b. For example, one of the second silicide layers in the pair of second silicide layers 118 is provided on the first source / drain region 114a, and the other of the second silicide layers in the pair of second silicide layers 118 is provided on the second source / drain region 114b. The second silicide layer 118 may include, for example, nickel (e.g., nickel silicide), titanium (e.g., titanium silicide), cobalt (e.g., cobalt silicide), platinum (e.g., platinum silicide), tungsten (e.g., tungsten silicide), etc.

[0065] A gate 120 is provided over the semiconductor substrate 102 and the device region 112. The gate 120 includes a gate electrode 122, and the gate electrode 122 is provided on a gate dielectric 124. The gate electrode 122 may include, for example, doped polysilicon, a metal (e.g., tungsten, aluminum, etc.), a silicide (e.g., titanium silicide, nickel silicide, etc.), or some other conductive material. The gate dielectric 124 may include, for example, an oxide (e.g., SiO 2 )), a high-k dielectric (e.g., a dielectric material having a dielectric constant greater than 3.9), or some other dielectric material. In some embodiments, the gate 120 includes a third silicide layer 126 provided on / within the gate electrode 122. In still other embodiments, the third silicide layer 126 may include, for example, nickel (e.g., nickel silicide), titanium (e.g., titanium silicide), cobalt (e.g., cobalt silicide), platinum (e.g., platinum silicide), tungsten (e.g., tungsten silicide), etc.

[0066] In some embodiments, the outer perimeter of the gate 120 is disposed within the inner perimeter 110p of the isolation structure 110. Since the outer perimeter of the gate 120 is disposed within the inner perimeter 110p of the isolation structure 110, the gate 120 does not overlap with a pair of isolation corners 127. The isolation corners 127 are the top-view corners of the semiconductor substrate 102 that are disposed in the device region 112 and interface with the isolation structure 110. In some embodiments, the isolation corners 127 are linear and extend laterally from a first end of the device region 112 to a second end of the device region 112 that is opposite the first end and parallel to the selectively conductive channel 116.

[0067] Since the gate 120 does not overlap with the pair of isolation corners 127, the flicker noise and RTN of the FET 100 can be reduced. For example, since the gate 120 does not overlap with the pair of isolation corners 127, during the operation of the FET (e.g., when a voltage is applied to the gate electrode 122 and current flows through the selectively conductive channel 116), an inversion region may not be formed near / along the isolation corners 127 by the gate 120. This in turn reduces the trapping and detrapping of charge carriers at the isolation corners 127, thereby enabling the FET 100 to have low flicker noise and low RTN.

[0068] In addition, a plurality of silicide blocking structures 128a to 128d are disposed over the semiconductor substrate 102, the gate 120, and the isolation structure 110. For example, a first silicide blocking structure 128a, a second silicide blocking structure 128b, a third silicide blocking structure 128c, and a fourth silicide blocking structure 128d are disposed over the semiconductor substrate 102, the gate 120, and the isolation structure 110. The plurality of silicide blocking structures 128a to 128d are configured to prevent a silicide layer from being formed on the underlying portion of the FET 100 during a silicide process (e.g., a self-aligned silicide process (salicide process)). In some embodiments, the plurality of silicide blocking structures 128a to 128d are disposed on the semiconductor substrate 102, the gate 120, and the isolation structure 110. In still other embodiments, the silicide blocking structures 128a to 128d comprise or are a resist protective oxide (RPO). In yet other embodiments, the silicide blocking structures 128a to 128d may comprise, for example, an oxide (e.g., SiO 2 ), a nitride (e.g., oxygen-doped silicon nitride), a oxynitride (e.g., silicon oxynitride (SiO X N Y )), some other material suitable for preventing silicide formation, or a combination of the foregoing materials.

[0069] In some embodiments, the first silicide blocking structure 128a locally covers the gate 120, locally covers the second source / drain region 114b, and locally covers the isolation structure 110. In still other embodiments, the first silicide blocking structure 128a locally covers the first well pick-up region of the well pick-up region 106. For example, the first silicide blocking structure 128a may cover a first portion of the gate 120, a first portion of the second source / drain region 114b, a first portion of the isolation structure 110, and a first portion of the first well pick-up region.

[0070] Accordingly, the first silicide blocking structure 128a can prevent the silicide process from forming a silicide layer that would short-circuit the FET 100. For example, the first silicide blocking structure 128a can prevent a short circuit between the second source / drain region 114b and the first source / drain region 114a, a short circuit between the second source / drain region 114b and the gate electrode 122, a short circuit between the second source / drain region 114b and the first well pick-up region, some other short circuit scenarios of the FET 100, or a combination of the foregoing short circuit scenarios.

[0071] In some embodiments, the second silicide blocking structure 128b locally covers the gate 120, locally covers the second source / drain region 114b, and locally covers the isolation structure 110. In still other embodiments, the second silicide blocking structure 128b locally covers the second well pick-up region of the well pick-up region 106 that is opposite to the first well pick-up region. For example, the second silicide blocking structure 128b may cover a second portion of the gate 120, a second portion of the second source / drain region 114b, a second portion of the isolation structure 110, and a first portion of the second well pick-up region.

[0072] Accordingly, the second silicide blocking structure 128b can prevent the silicide process from forming a silicide layer that would short-circuit the FET 100. For example, the second silicide blocking structure 128b can prevent a short circuit between the second source / drain region 114b and the first source / drain region 114a, a short circuit between the second source / drain region 114b and the gate electrode 122, a short circuit between the second source / drain region 114b and the second well pick-up region, some other short circuit scenarios of the FET 100, or a combination of the foregoing short circuit scenarios.

[0073] It should be understood that in some embodiments, the third silicide blocking structure 128c and the fourth silicide blocking structure 128d can prevent the silicide process from forming a silicide layer that would short-circuit the FET 100 in a manner substantially similar to that of the first silicide blocking structure 128a and the second silicide blocking structure 128b, but for the first source / drain region 114a. Accordingly, the plurality of silicide blocking structures 128a to 128d can allow a silicide process to be performed on the FET 100 to form a plurality of silicide layers (e.g., the first silicide layer 108, the second silicide layer 118, the third silicide layer 126, etc.), which can improve the contact resistance of the FET 100 while also reducing the flicker noise and RTN of the FET 100 by setting the outer perimeter of the gate 120 within the inner perimeter 110p of the isolation structure 110. It should be understood that in some embodiments, the plurality of silicide blocking structures 128a to 128d can be configured as substantially similar portions of the FET 100 and / or cover substantially similar portions of the FET 100, while in other embodiments, the plurality of silicide blocking structures 128a to 128d can be configured as different portions of the FET 100 and / or cover different portions of the FET 100.

[0074] Figure 2 Description Figures 1A to 1C Perspective view of some other embodiments of the illustrated FET 100.

[0075] As Figure 2 As shown, the first silicide blocking structure 128a extends continuously from outside the first side of the device region 112 and beyond the second side of the device region, the second side being opposite the first side of the device region. In such an embodiment, the first silicide blocking structure 128a can cover a third portion of the isolation structure 110, the third portion including portions of the isolation structure 110 disposed on opposite sides of the device region 112. In still other embodiments, the first silicide blocking structure 128a completely covers the first well pickup region. In such an embodiment, one of the first silicide layers 108 may not be disposed on the first well pickup region.

[0076] In some embodiments, the second silicide blocking structure 128b is spaced apart from the first silicide blocking structure 128a and extends continuously from outside the first side of the device region 112 and beyond the second side of the device region. The second silicide blocking structure 128b can cover a fourth portion of the isolation structure 110, the fourth portion being spaced apart from the third portion of the isolation structure 110, the fourth portion including portions of the isolation structure 110 disposed on opposite sides of the device region 112. In still other embodiments, the second silicide blocking structure 128b completely covers the second well pickup region. In such an embodiment, one of the first silicide layers 108 may not be disposed on the second well pickup region.

[0077] Figures 3A to 3D Description Figures 1A to 1C Various figures of various more detailed embodiments of the FET shown. Figure 3A is Figures 3B to 3D A top view layout diagram of some embodiments of the FET shown, in which the interconnection structure 304, the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126 are removed. Figure 3B is taken along line A-A' Figure 3A A cross-sectional view of some embodiments of the FET shown. Figure 3C is taken along line B-B' Figure 3A A cross-sectional view of some embodiments of the FET shown. Figure 3D is taken along line C-C' Figure 3A A cross-sectional view of some embodiments of the FET shown.

[0078] As Figures 3A to 3D shown, sidewall spacers 302 are provided over the device region 112, and the sidewall spacers 302 are disposed along multiple sides of the gate 120. For example, the sidewall spacers 302 are disposed along multiple sidewalls of the gate electrode 122 and multiple sidewalls of the gate dielectric 124. In some embodiments, the sidewall spacers 302 are disposed along multiple sides of the third silicide layer 126. In still other embodiments, the sidewall spacers 302 laterally surround the gate 120. In yet other embodiments, the sidewall spacers 302 may comprise, for example, an oxide (e.g., SiO 2 ), a nitride (e.g., silicon nitride (e.g., SiN)), a oxynitride (e.g., SiO X N Y ), some other dielectric material, or a combination of the foregoing materials.

[0079] An interconnection structure 304 is provided over the plurality of silicide blocking structures 128a to 128d, the gate 120, the sidewall spacers 302, the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126. The interconnection structure 304 includes a plurality of conductive contacts 306 disposed in an interlayer dielectric (ILD) layer 308. In some embodiments, the conductive contacts 306 may comprise, for example, tungsten, copper, aluminum, some other conductive material, or a combination of the foregoing materials. In still other embodiments, the ILD layer 308 may include or be, for example, a low-k dielectric layer (e.g., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, an oxide layer (e.g., SiO 2 ), some other dielectric layer, or a combination of the foregoing materials. It should be understood that in some embodiments, the interconnection structure 304 includes additional dielectric layers and conductive features (e.g., metal lines, metal vias, etc.) disposed over the ILD layer 308 and the conductive contacts 306.

[0080] A first sidewall 310a of a second silicide blocking structure 128b is disposed between first opposing sidewalls of the gate 120. One of the first opposing sidewalls of the gate 120 is disposed between the first sidewall 310a and a second sidewall 310b of the second silicide blocking structure 128b, and the second sidewall 310b is opposite to the first sidewall 310a. In some embodiments, the first sidewall 310a is spaced apart from the one of the first opposing sidewalls of the gate 120 by a first distance D 1 . In some embodiments, the first distance D 1 is between about 0 micrometers (um) and 1 um. In still other embodiments, the first distance D 1 is about 0.1 um. In yet other embodiments, the shortest distance between the first sidewall 310a and the one of the first opposing sidewalls of the gate 120 is less than or equal to about 1 um.

[0081] The second sidewall 310b may be disposed between an inner perimeter 110p of the isolation structure 110 and an outer perimeter of the isolation structure 110. In still other embodiments, the second sidewall 310b is spaced apart from the inner perimeter 110p of the isolation structure by a second distance D 2 . In still other embodiments, the second distance D 2 is between about 0 um and about 1 um. In still other embodiments, the second distance D 2 is about 0.1 um. In yet other embodiments, the shortest distance between the second sidewall 310b and the inner perimeter 110p of the isolation structure 110 is less than or equal to about 1 um.

[0082] In some embodiments, the one of the first opposing sidewalls of the gate 120 is spaced apart from the inner perimeter 110p of the isolation structure 110 by a third distance D 3 . In still other embodiments, the third distance D 3 is between about 0 um and about 1 um. In still other embodiments, the third distance D 3is about 0.2 um. In some further embodiments, the shortest distance between one of the first opposite sidewalls of the gate 120 and the inner perimeter 110p of the isolation structure 110 is less than or equal to about 1 um. It should be understood that, in some embodiments, the distance separated by the corresponding sidewall of the fourth silicide blocking structure 128d and one of the first opposite sidewalls of the gate 120 and / or the inner perimeter 110p of the isolation structure 110 will be substantially the same as the distance separated by the sidewall of the second silicide blocking structure 128b and one of the first opposite sidewalls of the gate 120 and / or the inner perimeter 110p of the isolation structure 110. It should be understood that, in some embodiments, the distance separated by the corresponding sidewalls of the first silicide blocking structure 128a and the third silicide blocking structure 128c and the other of the first opposite sidewalls of the gate 120 and / or the inner perimeter 110p of the isolation structure 110 will be substantially the same as the distance separated by the sidewall of the second silicide blocking structure 128b and the other of the first opposite sidewalls of the gate 120 and / or the inner perimeter 110p of the isolation structure 110.

[0083] The gate electrode 122 may include a plurality of doped regions 312a to 312c. For example, the gate electrode 122 may include a first doped region 312a, a second doped region 312b, and a third doped region 312c. The second doped region 312b is disposed in the central region of the gate electrode 122 that is between the first doped region 312a and the third doped region 312c. In some embodiments, the first doped region 312a and the third doped region 312c have the same doping type as the first well 104, while the second doped region 312b has a doping type different from that of the first well 104. For example, the first doped region 312a and the third doped region 312c may have a first doping type, and the second doped region 312b may have a second doping type. In still some other embodiments, the first doped region 312a and the third doped region 312c may have a concentration of a first dopant (e.g., an n-type dopant) that is greater than that of the first well 104.

[0084] Since the second doped region 312b is disposed between the first doped region 312a and the third doped region 312c, and since the second doped region 312b has a doping type different from that of the first doped region 312a and the third doped region 312c, the flicker noise and RTN of the FET can be further reduced. For example, during the operation of the FET, an inversion region that is further away from the inner perimeter 110p of the isolation structure 110 can be formed. This in turn reduces the trapping and detrapping of charge carriers at the isolation corner 127, thereby enabling the FET to have low flicker noise and low RTN.

[0085] Figures 4A to 4D Description Figure 2 Various figures of various more detailed embodiments of the illustrated FET. Figure 4A isFigures 4B to 4D Top view layout diagrams of some embodiments of the shown FETs, where the inner connection structure 304, the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126 are removed. Figure 4B taken along line A-A' Figure 4A Cross-sectional views of some embodiments of the shown FETs. Figure 4C taken along line B-B' Figure 4A Cross-sectional views of some embodiments of the shown FETs. Figure 4D taken along line C-C' Figure 4A Cross-sectional views of some embodiments of the shown FETs.

[0086] As Figures 4A to 4D shown, in some embodiments, the third silicide layer 126 is disposed on the second doped region 312b and is spaced apart from the first doped region 312a and the third doped region 312c. In still other embodiments, the second silicide blocking structure 128b can continuously extend from one side of the gate 120 to the opposite side of the gate 120. In still other embodiments, the first silicide blocking structure 128a is spaced apart from the second silicide blocking structure 128b and can also continuously extend from the said one side of the gate 120 to the said opposite side of the gate 120.

[0087] Since the third silicide layer 126 is disposed on the second doped region 312b and is spaced apart from the first doped region 312a and / or the third doped region 312c, the flicker noise and RTN of the FET can be further reduced. For example, during the operation of the FET, the depletion region between the second doped region 312b and the first doped region 312a and / or the second doped region 312b can become larger, so that an inversion region further away from the inner perimeter 110p of the isolation structure 110 can be formed. This in turn reduces the trapping and detrapping of charge carriers at the isolation corner 127, so that the FET has low flicker noise and low RTN.

[0088] Figures 5A to 5D Illustrate Figures 3A to 3D Various diagrams of other embodiments of the shown FETs. Figure 5A is Figures 5B to 5D Top view layout diagrams of some embodiments of the shown FETs, where the inner connection structure 304, the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126 are removed. Figure 5B taken along line A-A' Figure 5A Cross-sectional views of some embodiments of the shown FETs. Figure 5C taken along line B-B' Figure 5A Cross-sectional views of some embodiments of the shown FETs. Figure 5D taken along line C-C'Figure 5A Cross-sectional views of some embodiments of the FET shown.

[0089] As Figures 5A to 5D shown, in some embodiments, a second well 502 is provided in the semiconductor substrate 102. The second well 502 is a region of the semiconductor substrate 102 having the same doping type as the first source / drain region 114a and the second source / drain region 114b. In still other embodiments, the second well 502 is directly provided under the gate 120 and extends continuously from the first source / drain region 114a to the second source / drain region 114b.

[0090] In some embodiments, a third well 504 is provided in the semiconductor substrate 102. The third well 504 is a region of the semiconductor substrate 102 having the same doping type as the first well 104. In still other embodiments, the third well 504 is provided under the gate 120 and extends continuously from the first source / drain region 114a to the second source / drain region 114b. In yet other embodiments, the third well 504 is provided between the gate 120 and the second well 502. Since the second well 502 has the same doping type as the first source / drain region 114a and the second source / drain region 114b, the second well 502 provides a conductive channel between the first source / drain region 114a and the second source / drain region 114b. In such an embodiment, the FET can be referred to as a JFET.

[0091] Figures 6A to 6D Illustrate Figures 4A to 4D Various diagrams of other embodiments of the FET shown. Figure 6A Is Figures 6B to 6D A top view layout diagram of some embodiments of the FET shown, in which the internal connection structure 304, the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126 are removed. Figure 6B Is a cross-sectional view taken along line A-A' of Figure 6A Some embodiments of the FET shown. Figure 6C Is a cross-sectional view taken along line B-B' of Figure 6A Some embodiments of the FET shown. Figure 6D Is a cross-sectional view taken along line C-C' of Figure 6A Some embodiments of the FET shown.

[0092] As Figures 6A to 6D shown, the third well 504 is provided between the gate 120 and the second well 502. Since the second well 502 has the same doping type as the first source / drain region 114a and the second source / drain region 114b, the second well 502 provides a conductive channel between the first source / drain region 114a and the second source / drain region 114b. In such an embodiment, the FET can be referred to as a JFET.

[0093] Figures 7A to 7D to Figures 16A to 16D A series of diagrams illustrating some embodiments of a method of forming a FET having low flicker noise and low RTN. Diagrams with the suffix "A" (e.g., Figure 7A ) are top views of the FET during various steps of the forming method. Diagrams with the suffix "B" (e.g., Figure 7B ) are cross-sectional views of the FET taken along line A-A' in the diagram with the suffix "A". Diagrams with the suffix "C" (e.g., Figure 7C ) are cross-sectional views of the FET taken along line B-B' in the diagram with the suffix "A". Diagrams with the suffix "D" (e.g., Figure 7D ) are cross-sectional views of the FET taken along line C-C' in the diagram with the suffix "A". The FET may be substantially similar to the FET shown, for example, in Figures 3A to 3D .

[0094] As shown in Figures 7A to 7D , an isolation structure 110 is formed in the semiconductor substrate 102. The isolation structure 110 is formed to define a device region 112 of the semiconductor substrate 102. In some embodiments, the isolation structure 110 may be formed by the following steps: selectively etching the semiconductor substrate 102 to form a trench in the semiconductor substrate 102, and then filling the trench with a dielectric material. The semiconductor substrate 102 may be selectively etched by the following steps: forming a masking layer (not shown in the figure) over the semiconductor substrate 102, and then exposing the semiconductor substrate 102 to an etchant that selectively removes the unmasked portion of the semiconductor substrate 102. In still other embodiments, the formation of the isolation structure 110 results in the formation of a pair of isolation corners 127. In still other embodiments, the dielectric material may include oxides (e.g., SiO 2 ), nitrides, carbides, etc.

[0095] As shown in Figures 8A to 8D , a first well 104 is formed in the device region 112 of the semiconductor substrate 102. The first well 104 is a region of the semiconductor substrate 102 having a first doping type (e.g., n-type doping). In some embodiments, the first well 104 has a doping type opposite to that of the adjacent region of the semiconductor substrate 102, or the adjacent region of the semiconductor substrate may be intrinsic. In some embodiments, the first well 104 is formed with a first concentration of a first dopant (e.g., an n-type dopant). In still other embodiments, the first well 104 may be formed by an ion implantation process, and a masking layer (not shown in the figure) may be used to selectively implant ions into the semiconductor substrate 102.

[0096] As shown in Figures 9A to 9DAs shown, a gate 120 is formed over a semiconductor substrate 102 and over a device region 112. The gate 120 is formed to have an outer perimeter within an inner perimeter of an isolation structure 110. The gate includes a gate electrode 122 disposed on a gate dielectric 124. In some embodiments, the gate 120 is formed with a third distance D spaced from the inner perimeter of the isolation structure 110 3 from sidewalls. In still other embodiments, the third distance D 3 is between about 0 um and about 1 um.

[0097] In some embodiments, the process of forming the gate 120 includes depositing or growing a dielectric layer (not shown in the figures) on the semiconductor substrate 102. The dielectric layer can be, for example, silicon dioxide, a high-k dielectric, or some other dielectric. In still other embodiments, the dielectric layer can be deposited or grown by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or some other deposition or growth process.

[0098] Thereafter, a processing layer (not shown in the figures) is formed on the dielectric layer. In some embodiments, the processing layer can be, for example, polysilicon. In other embodiments, the processing layer can be doped polysilicon, a metal, or some other conductor. In still other embodiments, the processing layer can be formed by, for example, CVD, PVD, ALD, sputtering, electroless plating, electroless deposition, or some other deposition or growth process.

[0099] After the processing layer is formed on the dielectric layer, the processing layer and the dielectric layer are patterned into the gate 120. In some embodiments, the process for patterning the processing layer and the dielectric layer includes forming a patterned masking layer (not shown in the figures) on the processing layer. In still other embodiments, the patterned masking layer can be formed by a spin-on process and patterned using photolithography. In still other embodiments, the process includes performing etching into the processing layer and the dielectric layer with the patterned masking layer in place to form the gate electrode 122 and the gate dielectric 124, respectively. Subsequently, the patterned masking layer can be stripped off.

[0100] As Figures 10A to 10DAs shown, a pair of lightly doped source / drain extensions 1002a to 1002b are formed in the first well 104. For example, a first lightly doped source / drain extension 1002a is formed on the first side of the gate 120, and a second lightly doped source / drain extension 1002b is formed on the second side of the gate 120 opposite to the first side. In some embodiments, the lightly doped source / drain extensions 1002a to 1002b include a second doping type different from the first doping type (e.g., p-type doping). In still other embodiments, the lightly doped source / drain extensions 1002a to 1002b are formed with a second concentration of a second dopant (e.g., a p-type dopant). In yet other embodiments, the pair of lightly doped source / drain extensions 1002a to 1002b can be formed by an ion implantation process, and ions can be selectively implanted into the semiconductor substrate 102 using a masking layer (not shown in the figure).

[0101] As Figures 11A to 11D shown, sidewall spacers 302 are formed on the semiconductor substrate 102 and along the sides of the gate 120. In some embodiments, the sidewall spacers 302 can be formed by depositing a spacer layer on the semiconductor substrate 102, the gate 120, and the isolation structure 110. In still other embodiments, the spacer layer can be deposited by PVD, CVD, ALD, sputtering, or some other deposition process. In yet other embodiments, the spacer layer is then etched to remove the spacer layer from the horizontal surfaces, thereby forming the sidewall spacers 302 along multiple sides of the gate 120. The spacer layer can comprise, for example, an oxide (e.g., SiO 2 ), a nitride (e.g., SiN), a oxynitride (e.g., SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some embodiments, the sidewall spacers 302 can be formed before the lightly doped source / drain extensions 1002a to 1002b are formed. In such embodiments, an angled ion implantation process can be used to form the lightly doped source / drain extensions 1002a to 1002b.

[0102] As Figures 12A to 12D shown, a pair of well pick-up regions 106 are formed in the device region 112 on the first opposite sides of the gate 120. The well pick-up regions 106 are regions of the semiconductor substrate 102 having the same doping type as the first well 104. The well pick-up regions 106 are formed with a third concentration of a first dopant that is greater than the first concentration of the first dopant.

[0103] In addition, a first doped region 312a and a third doped region 312c are formed in the gate electrode 122. The first doped region 312a and the third doped region 312c are regions of the gate electrode 122 that include the same doping type as the first well 104. In some embodiments, the first doped region 312a and the third doped region 312c may have a higher concentration of a first dopant (e.g., an n-type dopant) than the first well 104. In still other embodiments, the first doped region 312a and the third doped region 312c may have the same doping concentration as the well pick-up region 106.

[0104] In some embodiments, the well pick-up region 106, the first doped region 312a, and the third doped region 312c may be formed by an ion implantation process that uses a masking layer (not shown in the figures) to selectively implant ions into the semiconductor substrate 102 and the gate electrode 122. In still other embodiments, the well pick-up region 106, the first doped region 312a, and the third doped region 312c may be formed by a single ion implantation process using a single masking layer. In other embodiments, the well pick-up region 106, the first doped region 312a, and / or the third doped region 312c may be formed by a multiple ion implantation process using multiple masking layers.

[0105] As Figures 13A to 13D shown, a first source / drain region 114a and a second source / drain region 114b are formed in the device region 112 on the second opposite side of the gate 120. The second opposite side of the gate 120 is spaced apart in a first lateral direction, and the first opposite side of the gate 120 is spaced apart in a second lateral direction perpendicular to the first lateral direction. The first source / drain region 114a and the second source / drain region 114b are regions of the semiconductor substrate 102 that have the same doping type as the pair of lightly doped source / drain extensions 1002a to 1002b. In still other embodiments, the first source / drain region 114a and the second source / drain region 114b are formed with a fourth concentration of a second dopant that is greater than a second concentration of the second dopant.

[0106] In addition, a second doped region 312b is formed in the gate electrode 122. The second doped region 312b is a region of the gate electrode 122 that includes the same doping type as the first source / drain region 114a and the second source / drain region 114b. In some embodiments, the second doped region 312b may have a higher concentration of the second dopant than the lightly doped source / drain extensions 1002a to 1002b. In still other embodiments, the second doped region 312b may have the same doping concentration as the first source / drain region 114a and / or the second source / drain region 114b.

[0107] In some embodiments, the first source / drain region 114a, the second source / drain region 114b, and the second doped region 312b may be formed by an ion implantation process that uses a masking layer (not shown in the figures) to selectively implant ions into the semiconductor substrate 102 and the gate electrode 122. In still other embodiments, the first source / drain region 114a, the second source / drain region 114b, and the second doped region 312b may be formed by a single ion implantation process using a single masking layer. In other embodiments, the first source / drain region 114a, the second source / drain region 114b, and / or the second doped region 312b may be formed by a multiple ion implantation process using multiple masking layers.

[0108] As Figures 14A to 14D shown, a plurality of silicide blocking structures 128a to 128d are formed on the semiconductor substrate 102, the isolation structure 110, the gate 120, and the sidewall spacers 302. In some embodiments, the plurality of silicide blocking structures 128a to 128d are formed to locally cover the device region 112, locally cover the isolation structure 110, locally cover the gate 120, and locally cover the sidewall spacers 302. For example, the second silicide blocking structure 128b is formed to locally cover the gate 120, locally cover the second source / drain region 114b, locally cover the isolation structure 110, locally cover the sidewall spacers 302, and locally cover one of the well pickup regions 106.

[0109] In some embodiments, the second silicide blocking structure 128b is formed with a first sidewall 310a that is spaced apart from the sidewall of the gate 120 by a first distance D 1 in a second lateral direction. The first distance D 1 may be between about 0 um and about 1 um. In still other embodiments, the second silicide blocking structure 128b is formed with a second sidewall 310b that is spaced apart from the side of the inner perimeter of the isolation structure 110 by a second distance D 2 in a second lateral direction. The second distance D 2 may be between about 0 um and about 1 um.

[0110] In some embodiments, the process of forming the plurality of silicide blocking structures 128a to 128d includes depositing or growing a silicide blocking layer (e.g., a resistive protection oxide (PRO) layer) on the semiconductor substrate 102, the isolation structure 110, the gate 120, and the sidewall spacers 302. The silicide blocking layer can be deposited or grown by thermal oxidation, CVD, PVD, ALD, sputtering, or some other deposition or growth process. In still other embodiments, the silicide blocking layer can be formed as a conformal layer. Thereafter, a patterned masking layer (not shown in the figure) is formed on the silicide blocking layer (e.g., by a spin coating process), and the patterned masking layer is patterned using photolithography. Then, with the patterned masking layer in place, etching is performed on the silicide blocking layer to remove the unmasked portions of the silicide blocking layer, thereby forming the plurality of silicide blocking structures 128a to 128d. In some embodiments, the patterned masking layer is subsequently stripped off. In yet other embodiments, the silicide blocking layer can include, for example, an oxide (e.g., SiO 2 ), a nitride (e.g., oxygen-doped silicon nitride), a oxynitride (e.g., SiO X N Y ), some other material suitable for preventing silicide formation, or a combination of the foregoing materials.

[0111] As Figures 15A to 15D shown, a pair of first silicide layers 108 are formed on / within the well pick-up region 106, a pair of second silicide layers 118 are formed on / within the first source / drain regions 114a and the second source / drain regions 114b, and a third silicide layer 126 is formed on / within the gate electrode 122. In some embodiments, the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126 are formed with sides that are substantially aligned with the sidewalls of the plurality of silicide blocking structures 128a to 128d.

[0112] In some embodiments, the process of forming the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126 includes depositing a transition metal layer covering the plurality of silicide blocking structures 128a to 128d, the semiconductor substrate 102, and the isolation structure 110. Subsequently, the transition metal layer is heated to react with the exposed portions of the semiconductor substrate 102 to form the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126. The plurality of silicide blocking structures 128a to 128d prevent the transition metal from reacting with the portions of the semiconductor substrate 102 and the portions of the gate 120 that they cover. Thus, the plurality of silicide blocking structures 128a to 128d can prevent the formation of silicide layers that would short-circuit the FET 100. In still other embodiments, the process includes removing the unreacted material of the transition metal layer by etching. In yet other embodiments, the process can be a self-aligned process (e.g., a self-aligned silicide process).

[0113] As Figures 16A to 16D shown, an interconnect structure 304 is formed over the semiconductor substrate 102, the gate 120, and the isolation structure 110. In some embodiments, the process of forming the interconnect structure 304 includes: forming an interlayer dielectric (ILD) layer 308, and then forming conductive contacts 306 that extend through the ILD layer 308 to the semiconductor substrate 102 and / or the gate electrode 122. For example, the conductive contacts 306 can extend through the ILD layer 308 to the first silicide layer 108, the second silicide layer 118, and the third silicide layer 126. In still other embodiments, the ILD layer 308 can be formed by CVD, PVD, ALD, sputtering, or some other deposition or growth process. In yet other embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) can be performed on the ILD layer 308 to form a substantially flat upper surface.

[0114] In some embodiments, the process of forming the conductive contacts 306 includes performing an etch in the ILD layer 308 to form contact openings corresponding to the conductive contacts 306. The etch can be performed using a patterned masking layer formed over the ILD layer 308. In still other embodiments, the process includes filling the contact openings with a conductive material (e.g., tungsten). In yet other embodiments, the contact openings can be filled by: depositing a conductive layer covering the ILD layer 308 that fills the contact openings, and then performing a planarization process (e.g., CMP) on the conductive layer. In still other embodiments, the conductive layer can be deposited by, for example, CVD, PVD, ALD, sputtering, electroless plating, electroless deposition, or some other deposition or growth process.

[0115] As Figure 17As shown in FIG. 1700, a flowchart of some embodiments of a method for forming a FET having low flicker noise and low RTN is provided. Although the flowchart 1700 shown herein is illustrated and described as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be construed in a limiting sense. For example, some actions may occur in a different order and / or may occur synchronously with other actions or events other than those illustrated and / or described herein. In addition, it may not be necessary to perform all of the illustrated actions to implement one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be performed in one or more separate actions and / or phases. Figure 17 The flowchart 1700 shown herein is illustrated and described as a series of actions or events. However, it should be understood that the illustrated order of such actions or events should not be construed in a limiting sense. For example, some actions may occur in a different order and / or may occur synchronously with other actions or events other than those illustrated and / or described herein. In addition, it may not be necessary to perform all of the illustrated actions to implement one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be performed in one or more separate actions and / or phases.

[0116] At operation 1702, an isolation structure is formed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. Figures 7A to 7D Various figures illustrating some embodiments corresponding to operation 1702.

[0117] At operation 1704, a well is formed in the device region. Figures 8A to 8D Various figures illustrating some embodiments corresponding to operation 1704.

[0118] At operation 1706, a gate is formed over the device region and within the inner perimeter of the isolation structure, wherein the gate includes a gate electrode disposed on a gate dielectric. Figures 9A to 9D Various figures illustrating some embodiments corresponding to operation 1706.

[0119] At operation 1708, a pair of lightly doped source / drain extensions are formed in the device region and on opposite sides of the gate. Figures 10A to 10D Various figures illustrating some embodiments corresponding to operation 1708.

[0120] At operation 1710, sidewall spacers are formed over the device region and along the sides of the gate. Figures 11A to 11D Various figures illustrating some embodiments corresponding to operation 1710.

[0121] At operation 1712, a pair of well pick-up regions are formed in the device region. Figures 12A to 12D Various figures illustrating some embodiments corresponding to operation 1712.

[0122] At operation 1714, a first doped region and a second doped region are formed in the gate electrode. Figures 12A to 12D Various figures illustrating some embodiments corresponding to operation 1714.

[0123] At operation 1716, a first source / drain region and a second source / drain region are formed in the device region and on opposite sides of the gate. Figures 13A to 13DIllustrate various diagrams of some embodiments corresponding to operation 1716.

[0124] At operation 1718, a third doped region is formed in the gate electrode. Figures 13A to 13D Illustrate various diagrams of some embodiments corresponding to operation 1718.

[0125] At operation 1720, a plurality of silicide blocking structures are formed to locally cover the device region, the gate, and the isolation structure. Figures 14A to 14D Illustrate various diagrams of some embodiments corresponding to operation 1720.

[0126] At operation 1722, a silicide layer is formed on / within the semiconductor substrate and the gate electrode. Figures 15A to 15D Illustrate various diagrams of some embodiments corresponding to operation 1722.

[0127] At operation 1724, an interconnection structure is formed over the semiconductor substrate, the gate, and the isolation structure. Figures 16A to 16D Illustrate various diagrams of some embodiments corresponding to operation 1724.

[0128] In some embodiments, the present application provides a semiconductor device. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source / drain region is disposed in the device region and on a first side of the gate. A second source / drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure locally covers the gate, locally covers the first source / drain region, and locally covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.

[0129] In an embodiment, the silicide blocking structure contacts an upper surface of the gate, an upper surface of the first source / drain region, and an upper surface of the isolation structure. In an embodiment, the first side of the gate is spaced apart from the second side of the gate in a first lateral direction; and the first opposing sidewalls of the gate are spaced apart in a second lateral direction, the second lateral direction being perpendicular to the first lateral direction. In an embodiment, a second sidewall of the silicide blocking structure is disposed outside the inner perimeter of the isolation structure, and wherein the second sidewall of the silicide blocking structure is opposite the first sidewall. In an embodiment, a third sidewall of the silicide blocking structure is disposed between second opposing sidewalls of the gate, and wherein the second opposing sidewalls of the gate are spaced apart in the first lateral direction. In an embodiment, the silicide blocking structure extends continuously from the third sidewall to a fourth sidewall of the silicide blocking structure, the fourth sidewall being opposite the third sidewall, and wherein the fourth sidewall is disposed outside the inner perimeter of the isolation structure. In an embodiment, the second sidewall is disposed between the inner perimeter of the isolation structure and an outer perimeter of the isolation structure. In an embodiment, a shortest distance in the second lateral direction between the inner perimeter of the isolation structure and one of a plurality of sidewalls of the first opposing sidewalls is less than or equal to about 1 micrometer. In an embodiment, a shortest distance in the second lateral direction between one of the plurality of sidewalls of the first opposing sidewalls and the first sidewall is less than or equal to about 1 micrometer. In an embodiment, a shortest distance in the second lateral direction between the second sidewall and the inner perimeter of the isolation structure is less than or equal to about 1 micrometer. In an embodiment, the silicide blocking structure extends continuously from the third sidewall to the fourth sidewall of the silicide blocking structure, the fourth sidewall being opposite the third sidewall, wherein the third sidewall is spaced apart from the fourth sidewall in the first lateral direction, and both the third sidewall and the fourth sidewall are disposed outside the inner perimeter of the isolation structure.

[0130] In other embodiments, the present application provides a semiconductor device. The semiconductor device includes: an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines multiple sides of a device region of the semiconductor substrate. A first source / drain region and a second source / drain region are disposed in the device region and spaced apart in a first lateral direction. A gate is disposed over the device region and between the first source / drain region and the second source / drain region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first silicide blocking structure covers a first portion of the gate, a first portion of the first source / drain region, and a first portion of the isolation structure. A second silicide blocking structure covers a second portion of the gate, a second portion of the first source / drain region, and a second portion of the isolation structure, wherein the second silicide blocking structure is spaced apart from the first silicide blocking structure in a second lateral direction perpendicular to the first lateral direction.

[0131] In an embodiment, the semiconductor device further includes a first conductive contact that is electrically coupled to the first source / drain region, wherein the first conductive contact is disposed between the first silicide blocking structure and the second silicide blocking structure and between the gate and the isolation structure. In an embodiment, the semiconductor device further includes a first pick-up region and a second pick-up region, the first pick-up region and the second pick-up region are disposed in the device region between the first source / drain region and the second source / drain region, wherein: the first pick-up region and the second pick-up region are spaced apart in the second lateral direction and are disposed on opposite sides of the gate; the first pick-up region includes a doping type different from that of the first source / drain region; and the first silicide blocking structure is disposed between the first pick-up region and the first conductive contact. In an embodiment, the first silicide blocking structure at least partially covers the first pick-up region; and the second silicide blocking structure at least partially covers the second pick-up region. In an embodiment, the semiconductor device further includes a third silicide blocking structure and a fourth silicide blocking structure. The third silicide blocking structure covers a third portion of the gate, a first portion of the second source / drain region, and a third portion of the isolation structure. The fourth silicide blocking structure covers a fourth portion of the gate, a second portion of the second source / drain region, and a fourth portion of the isolation structure, wherein: the third silicide blocking structure is spaced apart from the fourth silicide blocking structure in the second lateral direction; and both the third silicide blocking structure and the fourth silicide blocking structure are spaced apart from the first silicide blocking structure and the second silicide blocking structure in the first lateral direction. In an embodiment, the semiconductor device further includes a second conductive contact, a first silicide layer, and a second silicide layer. The second conductive contact is electrically coupled to the first pick-up region, wherein the second conductive contact is disposed between the first silicide blocking structure and the third silicide blocking structure. The first silicide layer is disposed between the first conductive contact and the first source / drain region, wherein the first silicide layer covers a portion of the first source / drain region, and the portion of the first source / drain region is located between the first silicide blocking structure and the second silicide blocking structure and between the gate and the isolation structure. The second silicide layer is disposed between the second conductive contact and the first pick-up region, wherein the second silicide layer covers a portion of the first pick-up region, and the portion of the first pick-up region is located between the first silicide blocking structure and the third silicide blocking structure and between the gate and the isolation structure.In an embodiment, the first silicide blocking structure covers a first portion of the second source / drain region; opposite sidewalls of the first silicide blocking structure are spaced apart in the first lateral direction and are disposed outside the inner perimeter of the isolation structure; the second silicide blocking structure covers a second portion of the second source / drain region; and opposite sidewalls of the second silicide blocking structure are spaced apart in the first lateral direction and are disposed outside the inner perimeter of the isolation structure.

[0132] In still other embodiments, the present application provides a method of forming a semiconductor device. The method includes forming an isolation structure in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. Forming a gate above the device region and within the inner perimeter of the isolation structure. Forming a first source / drain region and a second source / drain region in the device region and on a first opposite side of the gate, wherein the first opposite side of the gate is spaced apart in a first lateral direction. Forming a first silicide blocking structure that locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure. Forming a second silicide blocking structure that is spaced apart from the first silicide blocking structure in a second lateral direction perpendicular to the first lateral direction, wherein the second silicide blocking structure locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure. Performing a silicide process to form a first silicide layer on the first source / drain region, wherein the first silicide layer is disposed between the first silicide blocking structure and the second silicide blocking structure.

[0133] In an embodiment, the method further includes: forming a first pickup region and a second pickup region in the device region and on a second opposite side of the gate, wherein the second opposite side of the gate is spaced apart in the second lateral direction, wherein the silicide process forms a second silicide layer on the first pickup region, and wherein the first silicide blocking structure is disposed between the second silicide layer and the first silicide layer.

[0134] The features of several embodiments are outlined above so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they may readily use the present invention as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, comprising: an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate; a gate disposed above the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure; a first source / drain region disposed in the device region and on a first side of the gate; a second source / drain region disposed in the device region and on a second side of the gate opposite the first side; and a silicide blocking structure that locally covers the gate, locally covers the first source / drain region, and locally covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.

2. The semiconductor device according to claim 1, characterized in that, the silicide blocking structure contacts an upper surface of the gate, an upper surface of the first source / drain region, and an upper surface of the isolation structure.

3. The semiconductor device according to claim 1, characterized in that: the first side of the gate is spaced apart from the second side of the gate in a first lateral direction; and the first opposing sidewalls of the gate are spaced apart in a second lateral direction perpendicular to the first lateral direction.

4. The semiconductor device according to claim 3, characterized in that, a second sidewall of the silicide blocking structure is disposed outside the inner perimeter of the isolation structure, and wherein the second sidewall of the silicide blocking structure is opposite the first sidewall.

5. The semiconductor device according to claim 4, characterized in that, a third sidewall of the silicide blocking structure is disposed between second opposing sidewalls of the gate, and wherein the second opposing sidewalls of the gate are spaced apart in the first lateral direction.

6. The semiconductor device according to claim 5, characterized in that, the silicide blocking structure extends continuously from the third sidewall to a fourth sidewall of the silicide blocking structure, the fourth sidewall being opposite the third sidewall, and wherein the fourth sidewall is disposed outside the inner perimeter of the isolation structure.

7. The semiconductor device according to claim 6, characterized in that, the second sidewall is disposed between the inner perimeter of the isolation structure and an outer perimeter of the isolation structure.

8. The semiconductor device according to claim 7, characterized in that, a shortest distance in the second lateral direction between the inner perimeter of the isolation structure and one of a plurality of sidewalls of the first opposing sidewalls is less than or equal to 1 micrometer.

9. The semiconductor device according to claim 8, characterized in that, a shortest distance in the second lateral direction between the one of the plurality of sidewalls of the first opposing sidewalls and the first sidewall is less than or equal to 1 micrometer.

10. The semiconductor device according to claim 9, characterized in that, a shortest distance in the second lateral direction between the second sidewall and the inner perimeter of the isolation structure is less than or equal to 1 micrometer.

11. The semiconductor device according to claim 4, wherein: the silicide blocking structure continuously extends from a third sidewall of the silicide blocking structure to a fourth sidewall of the silicide blocking structure, the fourth sidewall being opposite to the third sidewall, wherein the third sidewall is spaced apart from the fourth sidewall in the first lateral direction, and both the third sidewall and the fourth sidewall are disposed outside the inner perimeter of the isolation structure.

12. A semiconductor device, wherein: it includes: an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a plurality of sides of a device region of the semiconductor substrate; a first source / drain region and a second source / drain region disposed in the device region and spaced apart in a first lateral direction; a gate disposed above the device region and between the first source / drain region and the second source / drain region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure; a first silicide blocking structure covering a first portion of the gate, a first portion of the first source / drain region, and a first portion of the isolation structure; and a second silicide blocking structure covering a second portion of the gate, a second portion of the first source / drain region, and a second portion of the isolation structure, wherein the second silicide blocking structure is spaced apart from the first silicide blocking structure in a second lateral direction perpendicular to the first lateral direction.

13. The semiconductor device according to claim 12, wherein: it further includes: a first conductive contact electrically coupled to the first source / drain region, wherein the first conductive contact is disposed between the first silicide blocking structure and the second silicide blocking structure and between the gate and the isolation structure.

14. The semiconductor device according to claim 13, wherein: it further includes: a first pick-up region and a second pick-up region disposed in the device region between the first source / drain region and the second source / drain region, wherein: the first pick-up region and the second pick-up region are spaced apart in the second lateral direction and disposed on opposite sides of the gate; the first pick-up region includes a doping type different from that of the first source / drain region; and the first silicide blocking structure is disposed between the first pick-up region and the first conductive contact.

15. The semiconductor device according to claim 14, wherein: the first silicide blocking structure at least partially covers the first pick-up region; and the second silicide blocking structure at least partially covers the second pick-up region.

16. The semiconductor device according to claim 15, wherein: it further includes: a third silicide blocking structure covering a third portion of the gate, a first portion of the second source / drain region, and a third portion of the isolation structure; a fourth silicide blocking structure covering a fourth portion of the gate, a second portion of the second source / drain region, and a fourth portion of the isolation structure, wherein: The third silicide blocking structure is spaced apart from the fourth silicide blocking structure in the second lateral direction; and both the third silicide blocking structure and the fourth silicide blocking structure are spaced apart from the first silicide blocking structure and the second silicide blocking structure in the first lateral direction.

17. The semiconductor device according to claim 16, wherein, further comprising: a second conductive contact electrically coupled to the first pickup region, wherein the second conductive contact is disposed between the first silicide blocking structure and the third silicide blocking structure; a first silicide layer disposed between the first conductive contact and the first source / drain region, wherein the first silicide layer covers a portion of the first source / drain region, and the portion of the first source / drain region is located between the first silicide blocking structure and the second silicide blocking structure and between the gate and the isolation structure; and a second silicide layer disposed between the second conductive contact and the first pickup region, wherein the second silicide layer covers a portion of the first pickup region, and the portion of the first pickup region is located between the first silicide blocking structure and the third silicide blocking structure and between the gate and the isolation structure.

18. The semiconductor device according to claim 15, wherein: the first silicide blocking structure covers a first portion of the second source / drain region; opposite sidewalls of the first silicide blocking structure are spaced apart in the first lateral direction and are disposed outside the inner perimeter of the isolation structure; the second silicide blocking structure covers a second portion of the second source / drain region; and opposite sidewalls of the second silicide blocking structure are spaced apart in the first lateral direction and are disposed outside the inner perimeter of the isolation structure.

19. A method of forming a semiconductor device, wherein, the method comprises: forming an isolation structure in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate; forming a gate over the device region and within the inner perimeter of the isolation structure; forming a first source / drain region and a second source / drain region in the device region and on a first opposite side of the gate, wherein the first opposite side of the gate is spaced apart in a first lateral direction; forming a first silicide blocking structure that locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure; forming a second silicide blocking structure that is spaced apart from the first silicide blocking structure in a second lateral direction perpendicular to the first lateral direction, wherein the second silicide blocking structure locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure; and A silicide process is performed to form a first silicide layer on the first source / drain region, wherein the first silicide layer is disposed between the first silicide blocking structure and the second silicide blocking structure.

20. The method according to claim 19, wherein, further comprising: forming a first pickup region and a second pickup region in the device region and on a second opposite side of the gate, wherein the second opposite side of the gate is spaced apart in the second lateral direction, wherein the silicide process forms a second silicide layer on the first pickup region, and wherein the first silicide blocking structure is disposed between the second silicide layer and the first silicide layer.

21. A semiconductor device, wherein, comprising: an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate; a gate disposed above the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure; a first source / drain region disposed in the device region and on a first side of the gate; a second source / drain region disposed in the device region and on a second side of the gate opposite to the first side; and a silicide blocking structure at least partially covering the gate and at least partially covering the isolation structure.

22. The semiconductor device according to claim 21, wherein, the silicide blocking structure at least partially covers the first source / drain region.

23. The semiconductor device according to claim 21, wherein, further comprising: a silicide layer disposed above the gate, wherein the silicide layer covers a partial upper surface of the gate, and the silicide layer does not cover the entire upper surface of the gate.

24. The semiconductor device according to claim 21, wherein, a first sidewall of the silicide blocking structure is disposed between opposite sidewalls of the gate.

25. The semiconductor device according to claim 24, wherein, the first side of the gate and the second side of the gate are spaced apart in a first direction; and the opposite sidewalls of the gate are spaced apart in a second direction perpendicular to the first direction.

26. The semiconductor device according to claim 21, wherein, further comprising: a first silicide layer disposed above the gate, wherein a first side of the first silicide layer is aligned with a first sidewall of the silicide blocking structure.

27. The semiconductor device according to claim 26, wherein, further comprising: a second silicide layer disposed above the first source / drain region, wherein one side of the second silicide layer is aligned with the first sidewall of the silicide blocking structure.

28. The semiconductor device according to claim 27, wherein, a second side of the first silicide layer is aligned with a second sidewall of the silicide blocking structure.

29. The semiconductor device according to claim 28, wherein, wherein: The first sidewall of the silicide blocking structure extends in a first direction, and the second sidewall of the silicide blocking structure extends in a second direction perpendicular to the first direction.

30. A semiconductor device, characterized in that, comprising: an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a plurality of sides of a device region of the semiconductor substrate; a first source / drain region disposed in the device region; a second source / drain region disposed in the device region and laterally spaced from the first source / drain region; a gate disposed over the device region and between the first source / drain region and the second source / drain region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure; a first silicide blocking structure covering a first portion of the gate and a first portion of the isolation structure; and a second silicide blocking structure covering a second portion of the gate and a second portion of the isolation structure, wherein the second portion of the gate is laterally spaced from the first portion of the gate.

31. The semiconductor device according to claim 30, characterized in that, wherein: the first silicide blocking structure covers a first portion of the first source / drain region; the second silicide blocking structure covers a second portion of the first source / drain region; and the first portion of the first source / drain region is laterally spaced from the second portion of the first source / drain region.

32. The semiconductor device according to claim 30, characterized in that, wherein: a first sidewall of the first silicide blocking structure is disposed between first opposing sidewalls of the gate; a first sidewall of the second silicide blocking structure is disposed between the first opposing sidewalls of the gate; the first opposing sidewalls of the gate are laterally spaced in a first direction; and the first sidewall of the first silicide blocking structure is laterally spaced from the first sidewall of the second silicide blocking structure in the first direction.

33. The semiconductor device according to claim 32, characterized in that, further comprising: a first silicide layer disposed over the first source / drain region, wherein a first side of the first silicide layer is aligned with the first sidewall of the first silicide blocking structure, and a second side of the first silicide layer is aligned with a second sidewall of the second silicide blocking structure.

34. The semiconductor device according to claim 33, characterized in that, wherein: the first side of the first silicide layer extends from the isolation structure along the first sidewall of the first silicide blocking structure; and the second side of the first silicide layer extends from the isolation structure along the first sidewall of the second silicide blocking structure.

35. The semiconductor device according to claim 34, characterized in that, further comprising: A second silicide layer is disposed over the gate, wherein a first side of the second silicide layer is aligned with the first sidewall of the first silicide blocking structure, and a second side of the second silicide layer is aligned with the first sidewall of the second silicide blocking structure.

36. The semiconductor device according to claim 35, wherein: wherein: the first side of the second silicide layer extends between second opposing sidewalls of the gate; the second side of the second silicide layer extends between the second opposing sidewalls of the gate; and the second opposing sidewalls of the gate are spaced apart in a second direction perpendicular to the first direction.

37. The semiconductor device according to claim 35, wherein: wherein: a second sidewall of the first silicide blocking structure is disposed between second opposing sidewalls of the gate; a second sidewall of the second silicide blocking structure is disposed between the second opposing sidewalls of the gate; the second opposing sidewalls of the gate are laterally spaced apart in a second direction perpendicular to the first direction; a third side of the second silicide layer is aligned with the second sidewall of the first silicide blocking structure; and a fourth side of the second silicide layer is aligned with the second sidewall of the second silicide blocking structure.

38. The semiconductor device according to claim 37, wherein: wherein: the third side of the second silicide layer extends from the first side of the second silicide layer to one of the second opposing sidewalls of the gate; and the fourth side of the second silicide layer extends from the second side of the second silicide layer to the other of the second opposing sidewalls of the gate.

39. A method of forming a semiconductor device, wherein: the method includes: forming an isolation structure in a semiconductor substrate; forming a gate over the semiconductor substrate and within an inner perimeter of the isolation structure; forming a first source / drain region and a second source / drain region over the semiconductor substrate and within the inner perimeter of the isolation structure; forming a silicide blocking structure that locally covers the first source / drain region, locally covers the gate, and locally covers the isolation structure; and performing a silicide process by locally covering the first source / drain region, locally covering the gate, and locally covering the isolation structure with the silicide blocking structure to form a first silicide layer over the first source / drain region and a second silicide layer over the gate.

40. The method according to claim 39, wherein: wherein: the silicide blocking structure is formed to cover the second source / drain region; and the silicide process forms a third silicide layer over the second source / drain region.

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