Power Reduction and Performance Enhancement Techniques for Delta-Sigma Modulators

Abstract

Reference scaling, operational amplifier balancing, and chopper stabilization techniques for a delta-sigma modulator for an analog-to-digital converter are provided. For reference scaling, the cell elements in the feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from the active circuitry to achieve three DAC levels. When disconnected, the cell elements do not deliver charge to the device, which results in power savings and a reduction in thermal noise. Operational amplifier balancing involves downsampling the quantizer output, followed by upsampling on the feedback path, and filtering to hold the DAC value of the signal over the duration of the sampling period to generate a feedback signal. Chopper stabilization is performed by chopping the operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 611,586, filed on December 29, 2017, by Ganta et al., entitled "POWER REDUCTION AND PERFORMANCE ENHANCEMENT TECHNIQUES FOR DELTA SIGMA MODULATOR", the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] This disclosure generally relates to data converters, such as analog - to - digital converters (ADCs) and digital - to - analog (DAC) converters, and particularly to delta - sigma modulators for such data converters. Background Art

[0004] Delta - sigma modulation is a popular technique for implementing high - resolution ADCs and digital - to - analog converters (DACs). It is beneficial to reduce power consumption and improve the performance of delta - sigma modulators (Δ∑Ms). Brief Description of the Drawings

[0005] Figure 1 Shows a general implementation of a digital - to - analog converter (DAC) in a discrete - time (DT) delta - sigma modulator (DSM or Δ∑M).

[0006] Figure 2 Is a table showing the DAC switching scheme in a conventional DT DSM.

[0007] Figure 3 Depicts a multi - bit reference scaling technique according to the present disclosure.

[0008] Figure 4 Is a table showing the DAC switching sequence in a DT DSM using reference scaling.

[0009] Figure 5 Shows the DAC input code versus output charge for a reference scaling system with an even number of quantization levels.

[0010] Figure 6 Is a graph showing the simulation dynamic range comparison for the cases discussed with respect to the reference Figure 5 discussed.

[0011] Figure 7 Depicts a multi - bit reference scaling technique for an odd number of quantization levels according to the present disclosure.

[0012] Figure 8 It is a table showing the DAC switching sequence in a DT DSM using reference scaling for an odd number of quantization levels.

[0013] Figure 9 It is a plot showing the comparison of DAC input codes versus output charge for a reference scaling system with an odd number of quantization levels.

[0014] Figure 10 It is showing for the reference Figure 9 A graph of the simulation dynamic range comparison for the case discussed.

[0015] Figure 11 It depicts a block diagram of a reference scaling single-bit delta-sigma modulator.

[0016] Figure 12 It is Figure 11 A schematic depiction of the circuit implementation of the delta-sigma modulator of

[0017] Figure 13 It depicts a block diagram of a general reference scaling implementation for a single-bit delta-sigma modulator.

[0018] Figure 14 It is a plot showing the comparison of DAC input codes versus output charge for a reference scaling system with three-level quantization.

[0019] Figure 15 It is a block diagram of a conventional discrete-time integrator.

[0020] Figure 16 It is a block diagram of a double-sampled discrete-time integrator.

[0021] Figure 17 It depicts an example of a DSM designed using an operational amplifier (Op-Amp) balanced loop filter.

[0022] Figure 18 It shows a DSM using an operational amplifier balanced loop filter ( Figure 17 ) in a spectrum analysis.

[0023] Figure 19 It is a DSM using an operational amplifier balanced loop filter ( Figure 17 ) in a time-domain plot.

[0024] Figure 20 It is a simplified example of a chopper-stabilized differential DT integrator.

[0025] Figure 21 It shows the DAC mapping function for positive and negative offsets.

[0026] Figure 22 It is a model of DAC offset in the design of an operational amplifier balanced loop filter.

[0027] Figure 23 Shows the spectral analysis of a DSM using an operational amplifier balanced loop filter.

[0028] Figure 24 Shows the simulation dynamic range comparison for a multi-bit ADC incorporating the proposed technique.

[0029] Figure 25 Shows a unit DSM in the case of using reference scaling, operational amplifier balancing, and chopping.

[0030] Figure 26 Is a table showing the compensation for delayed and non-delayed integrators.

[0031] Figure 27 Shows an example of a signal transition based on Figure 22 using a non-delayed integrator in H1(z). Detailed Description

[0032] For the purpose of facilitating an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the accompanying drawings and described in the following written specification. It is to be understood that no limitation of the scope of the present disclosure is thereby intended. It is further understood that the present disclosure includes any changes and modifications to the illustrated embodiments and includes further applications of the principles of the present disclosure that would typically occur to one of ordinary skill in the art to which the present disclosure pertains.

[0033] The present disclosure presents techniques for reducing power consumption and improving the performance of a delta-sigma modulator and a delta-sigma ADC. As discussed in more detail below, these techniques include reference scaling, operational amplifier balancing, and chopper stabilization at the sampling frequency.

[0034] The present disclosure presents a low-power delta-sigma ADC using a reference scaling technique that reduces thermal noise and reduces power dissipation by approximately 50%. Refer Figure 1 , previously known multi-bit oversampling delta-sigma ADCs often use a switched-capacitor feedback DAC 10 having two-level (+1, -1) cell elements 12 (e.g., capacitors). As Figure 1 depicted in, the cell elements 12 are driven by a reference voltage V ref- or V ref+ . The output of the DAC is the sum of the voltages of the actuated cell elements 12, which forms a feedback analog signal that substantially represents the digital output signal.

[0035] Switches 14 are used to connect the cell elements to V ref- or Vref+ The switch 14 is controlled according to the DAC code. The DAC code is typically provided by the output of the quantizer of the ADC. Figure 2 summarizes a typical switching sequence for a DAC such as Figure 1 depicted in. In the Figure 1 embodiment, the DAC has six codes represented by +5, +3, +1, -1, -3, and -5.

[0036] As can be seen in Figure 2 , for the DAC code of +5, the switches for the five cell elements 12 (pairs) have a control state of "1", such that each cell element is driven by V ref+ . For the DAC of +3, four of the five switches have a control state of "1", such that four cell elements are driven by V ref+ , while the switch for the fifth cell element has a control state of "0", such that the cell element associated with this switch is driven by V ref- . For the DAC code of +1, three switches have a control state of "1", while two switches have a control state of "0". For the DAC codes -1, -3, and -5, the control states of the switches are inverted with respect to the DAC codes +1, +3, and +5, respectively.

[0037] As can be seen in Figure 2 , in the last column of the table in, the offset error charge for each DAC code is the same, e.g., -5V os C u . This is because regardless of the control state of the switches, each reference capacitor is always connected to the active circuit. As a result, the thermal noise and power consumption of the reference capacitor are always factors in the operation of the device.

[0038] The present disclosure proposes a reference scaling technique that enables significant reduction of the thermal noise and power consumption of a delta-sigma modulator. In particular, the delta-sigma ADC according to the present disclosure is configured to have a 3-level (+1, 0, -1) switched-capacitor feedback DAC architecture, where each reference capacitor has the ability to be driven either by V ref- , or by V ref+ , or not connected to the active circuit.

[0039] In Figure 3 , an example implementation of the proposed reference scaling technique is shown, while the switching sequences for different DAC control codes are summarized in the table depicted in Figure 4 . As can be seen in Figure 3 , the DAC 30 includes a switched-capacitor network 32 having a plurality of cell element (reference capacitor) pairs 34. In Figure 3In the embodiment, there are five cell element pairs 34.

[0040] The switched capacitor network 32 includes a plurality of switches associated with each cell element, the plurality of switches being configured to electrically connect the cell elements so as to provide a reference voltage V ref- or V ref+ . For example, the first cell element includes switches d1n and d1p for connecting the cell element to V ref- and V ref+ respectively; the second cell element includes switches d2n and d2p for connecting the cell element to V ref- and V ref+ respectively; and so on.

[0041] Each cell element further includes a switch dxz for electrically disconnecting the cell element from the output circuit. For example, the first cell element includes switches d1z and the second cell element includes switches d2z and and so on. In Figure 3 the embodiment, the switch dxz is configured to connect the corresponding cell element to the common mode voltage V cm .

[0042] Figure 3 The cell elements have control states given by "1 / 0", "0 / 1", and "0 / 0", which are the control states of the switches dxn, dxp associated with the cell elements. The cell element with the control state "1 / 0" is connected to V ref+ , and generates a signal level of +1. Similarly, the cell element with the control state "0 / 1" is connected to V ref- , and generates a signal level of -1. On the other hand, when the element is in the "0 / 0" state, the element is not connected to the active circuit, and thus does not deliver signal charge and thermal noise charge to the circuit. This results in a significant reduction in the thermal noise contribution from the element.

[0043] Figure 4 is a table showing the control states of the cell element switches corresponding to the DAC codes +5, +3, +1, -1, -3, and -5. The offset error charge depends on the number of cell elements connected to the active circuit. Thus, for lower DAC code values, the offset error charge is reduced, as can be seen in the last column of the table in Figure 4 . For small signals, only a small number of cell elements are attached to the virtual ground, resulting in an effective reduction in thermal noise. This technique can reduce the power dissipation of the ADC by approximately 50%.

[0044] A key side effect of the three-stage cell-feedback DAC is the loss of the inherent linearity enjoyed by the two-stage system. This non-linearity causes varying degrees of performance degradation, and this non-linearity is discussed for two different cases, namely, an even number of quantization levels and an odd number of quantization levels.

[0045] If the feedback DAC input has an even number of quantization levels, such as Figure 3 as depicted in, then for small signals where only the DAC codes +1 and -1 are used, the system has good signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). As the signal becomes larger and thus triggers the use of more DAC codes, SNDR degradation occurs due to DAC non-linearity, but for applications where the SNDR requirement relaxes with increasing signal power (such as in MEMS microphones), this SNDR degradation is acceptable.

[0046] Figure 5 The cause of this degradation is shown by graphing the input and output mapping of a feedback DAC using reference scaling for an even number of quantization levels. Figure 6 The corresponding SNDR as a function of the input level is shown for each case in. In Figure 6 the ideal curve is shown as a dashed line, where the effective charge for DAC code n is given by (nC u ΔV ref ), where ΔV ref = V ref+ - V ref- . In the presence of an offset in the integrator ( Figure 3 the V in os ), the effective charge delivered by the feedback DAC becomes (nC u ΔV ref - |n|C u V os ), as shown by the non-linear mapping of the solid curve in Figure 5 . For a conventional DAC without reference scaling, the offset is signal-independent and thus only introduces a DC offset into the mapping and therefore does not cause damage to the SNDR.

[0047] As can be seen from Figure 5 , for this particular design with reference scaling in the case of an even number of quantization levels, for small input signals, the DAC and thus the ADC behave like a unity ADC. The inherent linearity of the unity DAC gives good performance at low signal levels. As the DAC input grows beyond the unity level, the slope change causes non-linearity and degrades the SNDR, as shown in Figure 6As shown. For certain applications (e.g., audio systems) where the SNDR requirement relaxes with increasing signal power, the non-linearity due to reference scaling in the feedback DAC input with an even number of quantization levels is acceptable.

[0048] Figure 7 An example implementation of reference scaling for an odd number of feedback DAC quantization levels is shown. In this embodiment, four unit element pairs 74 are used in the switched capacitor network 72 of the DAC 70. The switched capacitor network 72 is otherwise similar to Figure 3 the switched capacitor network of the ref+ embodiment. Switches dxn, dxp are used to connect the unit elements to V ref and V cm respectively, and switch dxz is configured to disconnect the unit elements from the active circuit by connecting the unit elements to the common mode voltage V

[0049] For different DAC codes, the corresponding switching sequences are summarized in the table shown in Figure 8 . To implement an odd number of quantization levels, the unit elements are according to the DAC codes +4, +2, 0, -2, and -4. The unit elements have a control state "1 / 0" to provide a +1 signal level to the output, and a control state "0 / 1" to provide a -1 signal level to the output.

[0050] Figure 9 An input and output mapping of a feedback DAC such as that depicted in Figure 7 using reference scaling for an odd number of quantization levels is shown. For the DAC code 0, all unit elements have a control state "0 / 0" and are thus disconnected from the active circuit. This results in no offset error voltage at the DAC code 0. As a result, the reference scaling together with the offset causes non-linearity at the zero crossing. As a result, the SNDR is affected at both small and large signals, which is illustrated in Figure 10 .

[0051] In summary, the presence of amplifier offset causes non-linearity in a reference scaled multi-bit DAC. An operational amplifier balancing technique is proposed below to address the non-linearity problem associated with reference scaling. But first, reference scaling techniques for a unity triangle integral modulator will be discussed.

[0052] Conventionally, a unity triangle integral ADC has only one quantizer whose output is either +1 or -1. In other words, the DAC either transfers charge proportional to +V ref or charge proportional to -V ref . To apply reference scaling, three-level feedback, i.e., [+1, 0, -1], is required.

[0053] To generate the third level, the following scheme is proposed. When the input signal is small, the output stream of the DSM has a high density of alternating +1 and -1 pairs, which conceptually makes the feedback signal null and is equivalent to the "0" state in a three-level design. Therefore, the idea is to design a finite impulse response (FIR) filter to detect the alternating +1 and -1 pairs from the output. When such an event is detected, the 1-bit DAC is disabled (i.e., not connected to the ADC input summing node), thus effectively implementing reference scaling.

[0054] Figure 11 An example implementation of this idea is shown. Figure 11 The delta-sigma modulator 100 includes: a summing node 102, a loop filter 104, a unity quantizer 106, and a feedback path 108 with an FIR filter 110. The summing node 102 receives an analog input signal and a feedback signal from the FIR filter 110, and outputs the summed signal to the loop filter 104. The loop filter 104 filters the summed analog signal according to a noise shaping function and outputs the filtered analog signal to the unity quantizer 106. The quantizer 106 quantizes the analog signal and outputs a bit stream with values +1 or -1.

[0055] Before the quantizer output is sent to the DAC, the FIR filter 110 processes the quantizer output according to the transfer function In the case of a small input signal, where the quantizer output has a high density of alternating +1 and -1 pairs, the filter output generates a high density of zeros, so a 0 value is inserted into the DAC code.

[0056] Reference Figure 12 The circuit implementation of the three-level reference scaling feedback [+1, 0, -1] is similar to Figure 7 which has a single pair of cell elements and has DAC codes +1, 0, and -1 provided in the output from the FIR filter. For example, the DAC code +1 will result in a control state "1 / 0" for driving the cell element with V ref+ and the DAC code -1 will result in a control state "0 / 1" for driving the cell element with V ref- The DAC code 0 will result in a control state "0 / 0" for the cell element, where the cell element is disconnected from the active circuit.

[0057] Adding the filter 110 in the feedback path 108 changes the noise transfer function of the original design. Therefore, a compensating feedback path 112 accessed at different points in the loop is introduced in the delta-sigma modulator 100. This is in Figure 11are illustrated as compensation feedback path 112 and compensation filter 114. The loop filter 104 is divided into a first integrator 116 and a second integrator 118. A summing node 120 receives the output of the first integrator 116 and the compensation feedback signal from the compensation filter 114. The second integrator 118 receives the output of the summing node 120, and the unity quantizer 106 receives the output of the second integrator 118.

[0058] The compensation feedback path 112 is connected to the loop filter 104 at the summing node 120 between the first integrator 116 and the second integrator 118. The transfer function of the compensation filter 114 depends on the transfer function of the loop filter 104. When the first integrator is a delay integrator with a transfer function of z -1 / (1 - z -1 ), the transfer function of the compensation filter 114 is given by . When the first integrator 116 is a non-delay integrator with a transfer function of 1 / (1 - z -1 ), the transfer function of the compensation filter 114 is given by 1 / 2. By using the compensation filter 114, the original noise transfer function is restored. Figure 13 A general block diagram for FIR feedback of a unity DSM is shown.

[0059] Similar to a multi-bit delta-sigma modulator with an odd number of quantization levels, the three-stage feedback DAC in the unity delta-sigma modulator causes non-linearity as shown in Figure 11 due to the input and output mapping of the feedback DAC for Figure 14 .

[0060] An operational amplifier balancing technique is proposed to solve the non-linearity caused by reference scaling. Figure 15 A conventional integrator in a discrete-time (DT) delta-sigma modulator is shown, which is driven according to two non-overlapping clock phases φ1 and φ2. The input charge is sampled in one clock phase ( Figure 15 φ1 in Figure 15 ), and the input charge is integrated in the next clock phase ( Figure 15 φ2 in Figure 15 ). This means that the power of the integrator is wasted during the signal sampling phase when the operational amplifier is idle and not performing any tasks.

[0061] To avoid this idle state of the operational amplifier, the sampling capacitor is split into two parts - an upper path 160 and a lower path 162, as shown in Figure 16As shown in the figure. At φ1, while the upper capacitor path 160 samples the input, the lower capacitor path 162 integrates the charge, and vice versa at φ2. Compared with a conventional architecture with a similar data rate, this system gives a 3 dB advantage in power. Moreover, compared with a conventional integrator, the signal is integrated at twice the frequency. This technique is called "double sampling" when used in a delta-sigma modulator.

[0062] The main drawback of the double-sampling delta-sigma modulator is the folding of high-frequency shaped noise due to the mismatch of the DAC capacitors in φ1 and φ2. The mismatch in the DAC capacitors in φ1 and φ2 modulates the input with a discrete cosine signal that is clocked at 2f s and has a frequency equal to f s (see reference Figure 16 ). Thus, the integrator output is the sum of the input and the modulated version of the input.

[0063] The sampling frequency of the double-sampling delta-sigma modulator is given by 2f s . The signal injected into the first integrator consists of two parts - the input signal and the feedback from the DAC. The input signal is typically low-frequency content band-limited by an anti-aliasing filter. Thus, its modulation component is in the frequency band around f s and is greatly attenuated by the subsequent digital low-pass filter, thus having little impact on performance. On the other hand, the feedback signal from the DAC has a large high-frequency quantization noise power at the frequency f s (i.e., half of the effective sampling frequency, which is 2f s for the double-sampling DSM). As a result, the quantization noise is down-converted to the baseband and increases the in-band noise power, thus greatly reducing the SNR.

[0064] To solve this problem, an "op-amp balancing" technique is proposed. The main difference in this technique is that during a sampling period, the DAC values are held at the same level in φ1 and φ2. Figure 17 Fig. shows a delta-sigma modulator 170 using an op-amp balanced integrator, where the output Y Q of the quantizer is down-sampled 172 (denoted by Y Q , Y OUT , Y FB ) before being fed back to the input node. A fictitious intermediate node Y IMG is inserted to assist in the analysis of the frequency-domain conversion between Y OUT and Y FB .

[0065] Figure 18 shows the frequency-domain responses at different nodes. To convert between different clock domains, first, Y with a noise-shaped spectrum (which has a peak at p) OUT is upsampled (174, Figure 17 ), for example, upsampled by a factor of 2 using zero insertion. In the frequency domain, this is equivalent to compressing the spectrum of Y OUT as shown by the spectrum at Y IMG . After upsampling 174, there is a hold filter (176, -1 ) with a hold filter function of 1 + z Figure 17 to repeat (or hold) the same DAC signal for φ1 and φ2. This filter effectively nulls the frequency content of the feedback signal at f s , thus immunizing the system from the degradation caused by the above-mentioned capacitor mismatch problem.

[0066] Figure 19 gives a time-domain perspective of this immunity. Due to the capacitor mismatch in φ1 and φ2, the output step sizes are different. Since only the samples of the quantizer at φ2 ( Figure 17 Y in Q ) are considered for generating the feedback signal, this difference in step sizes does not cause any in-band noise degradation.

[0067] The proposed operational amplifier balancing can reduce the power consumption of the delta-sigma ADC by 50%. Additionally, it solves the problem of DAC noise folding due to capacitor mismatch in conventional dual-sampled delta-sigma ADCs.

[0068] Low-frequency DC offset and 1 / f noise cannot be filtered out by a low-pass filter, and thus this noise will be passed through the filter together with the signal information. As Figure 20 shown, a method to minimize low-frequency noise in an ADC using a delta-sigma modulator is to chop the operational transconductance amplifier (OTA) and modulate its flicker noise outside the signal band. As Figure 20 depicted, the integrator 200 of the delta-sigma modulator can include an OTA 202, an input chopper 204, and an output chopper 206.

[0069] The chopping frequency of the chopper needs to be at least one order of magnitude away from the signal bandwidth to avoid the residual flicker noise from corrupting the signal bandwidth. Unfortunately, the quantization noise of the DSM has increased sharply at frequencies that are one order of magnitude away from the signal bandwidth, especially for high-order loop filter designs. Therefore, although chopper stabilization itself serves to minimize the low-frequency noise, there is still a possibility that the high-frequency quantization noise is down-converted to the baseband of the modulator, resulting in a severe degradation in SQNR and a reduction in the dynamic range of the converter.

[0070] If the OTA can be chopper-stabilized at a chopping frequency equal to the sampling frequency f s , this will avoid the quantization noise from being down-converted from high frequencies to the baseband, because the DAC noise transfer function has a null at the sampling frequency (see Figure 18 for Y OUT ). Conventional discrete-time delta-sigma modulators can only be chopped at a "maximum" rate of f s / 2. It is obvious to those of ordinary skill in the art that, according to the operational amplifier balancing of the present disclosure, chopping can be performed at the sampling frequency f s . Therefore, we can enjoy the benefits of chopping without worrying about quantization noise folding.

[0071] By using the proposed operational amplifier balancing and the f s chopping discussed above, the performance degradation due to DAC non-linearity in the reference scaling system in the presence of an offset voltage is effectively solved. The mechanism by which the combination of these two techniques eliminates the offset-induced DAC error will be explained in the following paragraphs.

[0072] Conceptually, the operational amplifier balancing applies the same code to φ1 and φ2, and chopping at the sampling frequency f s means that the DAC experiences offset errors of opposite polarities and the same magnitude for φ1 and φ2. Figure 21 shows the corresponding DAC mapping functions for each case. The resulting effect is the averaged waveform (dashed line), which is linear.

[0073] An explanation of this removal mechanism based on frequency analysis is presented for a deeper understanding. The error caused by DAC non-linearity is given by:

[0074] E os (Y out ) = V os |Y out |,

[0075] This error is modeled as an additional feedback path to the input, as shown in Figure 22As shown in. Note that this example is based on a multi-bit delta-sigma modulator that combines reference scaling, op-amp balancing, and a sampling frequency f s Chopping. The single-bit implementation is discussed below. The analysis described for the multi-bit implementation can be easily extended to the single-bit implementation.

[0076] Based on Figure 22 the model in Figure 23 illustrates the frequency response of the error term E os which shows a distorted noise-shaping spectrum with an increased noise floor at low frequencies that corrupts the frequency band of our interest. The inherent filter (1 + z -1 ) in the op-amp balancing scheme reshapes this noise and creates a null at f s (see E OS，FB ). The subsequent f s chopping (represented by the chop sequence S CH ) shifts this null to the baseband (see E OS，CH ). As a result, the error due to DAC non-linearity is attenuated at the baseband and becomes negligible.

[0077] The SNDR degradation when using independent reference-scaled DACs with an even and odd number of quantizer levels has been discussed above. Figure 24 Compare these performances with our implementation that combines reference scaling, op-amp balancing, and f s chopping. It is clear that the SNR degradation is fully recovered in the case of the proposed technique.

[0078] Figure 25 Shows the block diagram of a single-bit DS ADC using reference scaling, op-amp balancing, and f s chopping. A first-order FIR filter 0.5(1 + z -1 ) is applied in the feedback path to enable reference scaling (described in Section 1.3), while a compensation path is added to ensure the recovery of the loop filter design. Figure 26 The table depicted in summarizes the compensators for the delayed integrator and non-delayed integrator designs. It is important to note that while the FIR filter is clocked at f s , the compensator needs to be clocked at 2f s .

[0079] Given in Table 6 are Figure 25 the examples of signal transitions at Y OUT , Y FB and Y CMP assuming H 1The case of the non-delayed integrator in (z). In this example, several characteristics can be observed from the feedback signal Y FB and these characteristics are the result of our techniques, which are briefly recapitulated below.

[0080] FIR feedback generates DAC code 0 and control state "0 / 0", which results in no reference capacitor being attached to the active circuit, thus effectively reducing the thermal noise contribution on the feedback path.

[0081] The operational amplifier balancing scheme applies the same feedback code from φ1 to φ2 to make the delta-sigma modulator immune to the effect of capacitor mismatch between the sampling capacitors and enables s chopping.

[0082] The combination of operational amplifier balancing and s chopping further eliminates the DAC nonlinearity problem caused by the offset associated with the reference-scaled DAC.

[0083] Different from Y FB , Y CMP is not guaranteed to have the same code from φ1 to φ2 due to the compensator. This violation of the operational amplifier balancing scheme makes Y CMP suffer from the effect of offset-induced DAC nonlinearity. To avoid any performance degradation from this problem, the compensator function is implemented in the analog domain so that the DAC of the compensation path is directly controlled by Y OUT , which Y OUT is the two-level signal +1 and -1. Therefore, no reference scaling means no DAC nonlinearity problem. Since the noise from the compensation is noise-shaped by the first integrator, the contribution of this noise is inherently small in the DSM even without the help of reference scaling.

[0084] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, it should be considered illustrative rather than restrictive in nature. It is to be understood that only the preferred embodiments are presented and all changes, modifications and further applications falling within the spirit of the present disclosure are desired to be protected.

Claims

1. A delta-sigma analog-to-digital converter, comprising: A delta-sigma modulator, which comprises: A first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal; A loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal; A quantizer that quantizes the filtered analog signal and outputs a quantized output signal; A feedback path that connects the output of the quantizer to the input of the summing node; and A feedback DAC on the feedback path that receives the quantized output signal and converts the quantized output signal into a feedback signal, and the feedback signal is provided to the first summing node; and wherein the feedback DAC includes a switched-capacitor circuit, the switched-capacitor circuit includes a plurality of unit elements, and the switched-capacitor circuit is configured to selectively connect each corresponding unit element to different connection states depending on the DAC code of the quantized output signal, and the different connection states include: A first connection state, wherein the corresponding unit element is connected to provide a first signal to the output of the feedback DAC, and the first connection state corresponds to a first signal level; A second connection state, wherein the corresponding unit element is connected to provide a second signal to the output of the feedback DAC, and the second connection state corresponds to a second signal level; and A third connection state, wherein the corresponding unit element is disconnected from the output of the feedback DAC and connected to a common-mode voltage, and the third connection state corresponds to a third signal level.

2. The delta-sigma analog-to-digital converter according to claim 1, wherein the feedback DAC is a unity DAC and the quantizer is a unity quantizer.

3. The delta-sigma analog-to-digital converter according to claim 2, further comprising: A finite impulse response (FIR) filter that filters the quantized output signal before it reaches the feedback DAC, and the FIR filter is configured to output a filtered quantized output signal, wherein a portion of the quantized output signal that alternates between a first value and a second value at a predetermined rate is replaced by a signal portion having a third quantization value.

4. The delta-sigma analog-to-digital converter according to claim 3, further comprising: A compensation feedback path that connects the output of the quantizer to the loop filter; and A compensation filter on the compensation feedback path, wherein the loop filter has a noise transfer function, wherein the FIR filter changes the noise transfer function, and wherein the compensation filter compensates the FIR filter so that the noise transfer function is restored.

5. The delta-sigma analog-to-digital converter according to claim 4, wherein the loop filter comprises: A first integrator that receives the first summed analog signal; A second integrator that outputs the filtered analog signal; And a second summing node, wherein the second summing node has a first input that receives the output of the first integrator, a second input that is connected to the compensation feedback path, and an output that is connected to the input of the second integrator, wherein the first integrator receives the first summed analog signal and outputs a first integrated analog signal to the first input of the second summing node, wherein a compensation filter outputs a compensation signal to a second input of the second summing node; wherein the second summing node outputs a second summing analog signal, the second summing analog signal being the sum of the first integrated analog signal and the compensation signal, and wherein a second integrator integrates the second summing signal to form a filtered analog signal.

6. The delta-sigma analog-to-digital converter according to claim 3, wherein the FIR filter has a transfer function 7. A delta-sigma modulator, which comprises: a first clock phase signal and a second clock phase signal that are non-overlapping with respect to each other; a summing node that sums an analog input signal and a feedback signal; a loop filter that filters the first summing analog signal according to a noise shaping function and outputs a filtered analog signal, the loop filter comprising: a dual-sampling integrator that includes a first capacitor path and a second capacitor path, wherein during the first clock phase signal, the first capacitor path samples the analog input signal and the second capacitor path integrates the sample, and wherein during the second clock phase signal, the second capacitor path integrates the sample and the second capacitor path samples the analog input signal; a quantizer that quantizes the output of the dual-sampling integrator; a feedback path that connects the output of the quantizer to the summing node; and a hold filter on the feedback path, wherein the first capacitor path and the second capacitor path have a first sampling frequency, wherein the dual-sampling integrator has a second sampling frequency, the second sampling frequency being twice the first sampling frequency, wherein the output of the quantizer is downsampled by a predetermined factor to form a downsampled signal, the downsampled signal being output to the feedback path, wherein the downsampled signal is upsampled by the predetermined factor on the feedback path before the downsampled signal is fed to the hold filter, wherein the upsampled signal includes a DAC code, and wherein the hold filter holds the value of the DAC code of the upsampled signal at a constant level during each period of the first clock phase signal and the second clock phase signal to generate a feedback signal.

8. The delta-sigma modulator according to claim 7, wherein the hold filter function of the hold filter is 1 + z -1 .

9. The delta-sigma modulator according to claim 8, wherein the hold filter function renders the frequency content of the feedback signal null at the first sampling frequency.

10. The delta-sigma modulator according to claim 7, wherein the DAC code indicated by the upsampled signal is used to generate the feedback signal during only one of the periods of the first clock phase signal and the second clock phase signal.

11. The delta-sigma modulator according to claim 7, wherein the predetermined factor is two.

12. The delta-sigma modulator according to claim 7, wherein the dual-sampling integrator comprises: an operational transconductance amplifier (OTA), an input chopper circuit for chopping the input to the OTA, and an output chopper circuit for chopping the output of the OTA, wherein the input chopper circuit and the output chopper circuit have a chopping frequency, and wherein the chopping frequency corresponds to the first sampling frequency.

13. A delta-sigma analog-to-digital converter, which comprises: a first clock phase signal and a second clock phase signal that are non-overlapping with respect to each other; a delta-sigma modulator, which includes: A first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal; A loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal; A quantizer that quantizes the filtered analog signal and outputs a quantized output signal; A feedback path that connects the output of the quantizer to the input of the summing node; and A feedback DAC on the feedback path that receives the quantized output signal and converts the quantized output signal into a feedback signal, the feedback signal being provided to the first summing node; and wherein the feedback DAC includes a switched capacitor circuit, the switched capacitor circuit includes a plurality of unit elements, and the switched capacitor circuit is configured to selectively connect each corresponding unit element to different connection states depending on the DAC code of the quantized output signal, the different connection states including: A first connection state in which the corresponding unit element is connected to provide a first signal to the output of the feedback DAC, the first connection state corresponding to a first signal level; A second connection state in which the corresponding unit element is connected to provide a second signal to the output of the feedback DAC, the second connection state corresponding to a second signal level; and A third connection state in which the corresponding unit element is disconnected from the output of the feedback DAC, the third connection state corresponding to a third signal level, and wherein the loop filter includes a dual-sampling integrator having a first capacitor path and a second capacitor path, wherein during a first clock phase signal, the first capacitor path samples the analog input signal and the second capacitor path integrates the sample, and wherein during a second clock phase signal, the second capacitor path integrates the sample and the second capacitor path samples the analog input signal, wherein the quantizer quantizes the output of the dual-sampling integrator, wherein the feedback path includes a hold filter, wherein the first capacitor path and the second capacitor path have a first sampling frequency, wherein the dual-sampling integrator has a second sampling frequency that is twice the first sampling frequency, wherein the output of the quantizer is downsampled by a predetermined factor to form a downsampled signal, the downsampled signal being output to the feedback path, wherein the downsampled signal is upsampled by the predetermined factor on the feedback path before being fed to the hold filter, wherein the upsampled signal includes a DAC code, and wherein the hold filter holds the value of the DAC code of the upsampled signal at a constant level during each period of the first clock phase signal and the second clock phase signal to generate a feedback signal.

14. The delta-sigma analog-to-digital converter according to claim 13, wherein the switched capacitor circuit is configured to connect the corresponding unit element to a common-mode voltage in the third connection state.

15. The delta-sigma analog-to-digital converter according to claim 13, wherein the dual-sampling integrator comprises: An operational transconductance amplifier (OTA), an input chopper circuit for chopping an input to the OTA, and an output chopper circuit for chopping an output of the OTA, wherein the input chopper circuit and the output chopper circuit have a chopping frequency, and wherein the chopping frequency corresponds to a first sampling frequency.

16. The delta-sigma analog-to-digital converter according to claim 13, wherein the hold filter function of the hold filter is 1 + z -1 .

17. The delta-sigma analog-to-digital converter according to claim 16, wherein the hold filter function renders the frequency content of the feedback signal null at the first sampling frequency.

18. The delta-sigma analog-to-digital converter according to claim 13, wherein the feedback DAC is a unity DAC and the quantizer is a unity quantizer, and, further comprises: A finite impulse response (FIR) filter that filters the quantized output signal before it reaches the feedback DAC, the FIR filter being configured to output a filtered quantized output signal, wherein a portion of the quantized output signal that alternates between a first value and a second value at a predetermined rate is replaced by a signal portion having a third quantization value.

19. The delta-sigma analog-to-digital converter according to claim 18, further comprises: A compensation feedback path that connects the output of the quantizer to the loop filter; and A compensation filter on the compensation feedback path, wherein the loop filter has a noise transfer function, wherein the FIR filter modifies the noise transfer function, and wherein the compensation filter compensates the FIR filter such that the noise transfer function is restored.

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