A ramp voltage generator and a ramp voltage generating method

Abstract

The present invention relates to the field of integrated circuits, and discloses a ramp voltage generator and a method for generating a ramp voltage, including: the V A terminal of the active capacitor is connected to the voltage input terminal, the V B terminal of the active capacitor is grounded, and a first charging circuit for charging the active capacitor to a reference voltage is formed between the voltage input terminal and the active capacitor; the V A terminal of the active capacitor is sequentially connected to one end of an integrating capacitor for outputting a voltage and the positive input terminal of an operational amplifier AMP, the other end of the integrating capacitor is grounded, and the V B terminal of the active capacitor is sequentially connected to the output V p terminal of the operational amplifier AMP and the negative input terminal of the operational amplifier AMP, and a second charging circuit for distributing charges to the integrating capacitor is formed between the active capacitor and the operational amplifier AMP; a control signal generation circuit is configured to alternately turn on the first charging circuit and the second charging circuit to charge the integrating capacitor so that its voltage reaches a target voltage that meets the output user requirements. The present invention can generate a ramp voltage with high linearity.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a ramp voltage generator and a method for generating a ramp voltage. Background Art

[0002] Voltage ramp signals can be used in circuits that require linear voltage changes, usually as reference signals, slope compensators or voltage sweep generators. Ramp voltage generators can be used in display devices or signal conversion situations. They are usually composed of an integrator composed of an operational amplifier, which can perform mathematical operations of integration, that is, we can make the output voltage respond to the change of the input voltage over time. The principle is that the output voltage generated by the integrator composed of the operational amplifier is proportional to the integral of the input voltage.

[0003] The following is an explanation combining two amplifier integration circuits. Figure 1 is a commonly used operational amplifier integrator circuit, such as Figure 1 As shown, the feedback capacitor C starts to charge due to the influence of the input voltage, and its impedance X c The capacitor charges at a rate determined by the RC time constant of the RC series network, and negative feedback forces op amp A to produce an output voltage of -V out , the voltage V generated across the capacitor C is maintained at a virtual ground at the inverting input of the operational amplifier. c Slowly increases, causing the charging current I f decreases as the capacitor impedance increases. This causes X c / R in (R in The ratio of the feedback capacitor C to the input resistor R is now infinite, resulting in infinite gain. The result of this high gain is that the output of the amplifier goes into saturation. Figure 2 It is a circuit diagram of another integrator circuit. Figure 2 The integration circuit includes a high-gain operational amplifier A, a high-speed MOS switch, and an integration capacitor C. The reset signal Reset controls the MOS switch to determine the operating range of the ramp voltage. The slope of the ramp voltage is determined by the reference current and the capacitor. Figure 2 In the actual reset signal generating system of the integration circuit, the high-gain operational amplifier used is not an ideal device. When generating the reset signal Reset, affected by the production process, power supply, voltage and temperature, the linearity of the ramp voltage is not very good, and the output ramp voltage range is limited, making it difficult to achieve the required design accuracy in the application. Summary of the invention

[0004] An object of the present invention is to provide a ramp voltage generator and a method for generating a ramp voltage, wherein the ramp voltage generator and the method for generating a ramp voltage can generate a ramp voltage with high linearity.

[0005] In order to achieve the above object, the present invention provides a ramp voltage generator, which comprises: a switch group, an operational amplifier AMP, an active capacitor, an integral capacitor and a control signal generating circuit; wherein the V A terminal is connected to the voltage input terminal, the V B The terminal is grounded, and the voltage input terminal and the active capacitor form a first charging circuit for charging the active capacitor to a reference voltage; V A The end is connected to one end of the integrating capacitor for generating the output voltage and the positive input end of the operational amplifier AMP in sequence, the other end of the integrating capacitor is grounded, and the V B The end is connected to the output V of the op amp AMP p The active capacitor and the operational amplifier AMP form a second charging circuit for distributing charge to the integral capacitor; the control signal generating circuit is used to generate a control signal, wherein the control signal is configured to control the conduction or disconnection of the switch groups disposed in the first charging circuit and the second charging circuit, so that the first charging circuit and the second charging circuit are alternately turned on to charge the integral capacitor so that its voltage reaches the target voltage required by the output user;

[0006] The switch group includes: a first switch, a second switch, a third switch and a fourth switch; wherein the first switch is placed at the V A The second switch is placed between the V B The third switch is placed between the V A The fourth switch is placed between the V B The output V of the op amp p between the ends;

[0007] The control signal generating circuit includes: a clock circuit for generating a non-overlapping clock signal and a timing adjustment circuit for adjusting the timing of the non-overlapping clock signal; wherein the clock circuit receives a CLK clock signal and sends the non-overlapping clock signal to the first switch, the second switch and the timing adjustment circuit, and the timing adjustment circuit sends the non-overlapping clock signal after the timing is adjusted to the third switch and the fourth switch.

[0008] Preferably, at least one of the first switch, the second switch, the third switch and the fourth switch is composed of a PMOS transistor; or at least one of the first switch, the second switch, the third switch and the fourth switch is composed of an NMOS transistor.

[0009] Preferably, the voltage input terminal is configured to input a reference voltage, wherein the reference voltage is smaller than a target voltage required by an output user.

[0010] In addition, an integrated circuit is also provided, and the integrated circuit includes the above-mentioned ramp voltage generator.

[0011] In addition, a method for generating a ramp voltage is also provided, which uses the above-mentioned ramp voltage generator, and the method for generating a ramp voltage includes: in one integration cycle, controlling the switch group placed in the first charging circuit to be turned on and the switch group in the second charging circuit to be turned off, so that the voltage of the active capacitor reaches a reference voltage that reflects the voltage change rate required by the user, and based on the reference voltage, continuing to control the switch group placed in the first charging circuit to be turned off and the switch group in the second charging circuit to be turned on, so that all the charges on the active capacitor are charged to the integration capacitor; and repeating multiple integration cycles so that the voltage of the integration capacitor reaches the target voltage required by the output user, wherein the target voltage is greater than the reference voltage.

[0012] According to the above technical solution, the present invention uses a designed switch group to control the conduction or disconnection of the first charging circuit and the second charging circuit, wherein the active capacitor can store a reference voltage when the first charging circuit is turned on, and when the second charging circuit is turned on, the active capacitor can cooperate with the integration capacitor and the operational amplifier AMP to distribute the charge on the active capacitor to the integration capacitor, thereby making the voltage of the integration capacitor reach the target voltage required by the output user. The above control circuit solves the shortcomings of insufficient linearity and easy saturation of the output voltage of the traditional integration circuit, and can maintain good linearity within the target voltage range.

[0013] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0015] Figure 1 It is an integration circuit diagram of an operational amplifier in the prior art;

[0016] Figure 2 It is another integration circuit diagram of an operational amplifier in the prior art;

[0017] Figure 3 is a circuit diagram illustrating a ramp voltage generator of the present invention;

[0018] Figure 4 is a circuit diagram illustrating a specific implementation of a ramp voltage generator of the present invention;

[0019] Figure 5 is a timing diagram illustrating the control timing of the control signal of the switch group of the present invention;

[0020] Figure 6 is a simulated output waveform diagram of the ramp voltage of the present invention; and

[0021] Figure 7 is a flow chart illustrating a method for generating a ramp voltage according to the present invention. DETAILED DESCRIPTION

[0022] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0023] Figure 1-Figure 2 It is an operational amplifier integration circuit in the prior art, used to generate Figure 3 The present invention Figure 1 and Figure 2 The operational amplifier integration circuits in the above examples are quite different in terms of structure and control principle. Figure 3-Figure 6 The ramp voltage generator of the present invention is described in detail.

[0024] Figure 3 is a circuit diagram of a ramp voltage generator of the present invention, such as Figure 3 As shown, the ramp voltage generator includes: a switch group (the switch group includes 4 switches), an operational amplifier AMP, an active capacitor C0, an integrating capacitor C1 and a control signal generating circuit; the output signal of the control signal generating circuit is used to control the four switches S1, S2, S3 and S4. Among them, the V A The active capacitor C0 is connected to the voltage input terminal VR. B The voltage input terminal VR and the active capacitor C0 form a first charging circuit for charging the active capacitor C0 to a reference voltage; the V A The ends are connected to one end of the integrating capacitor C1 for generating the output voltage and the positive input end of the operational amplifier AMP in sequence, the other end of the integrating capacitor C1 is grounded, and the VB The end is connected to the output V of the op amp AMP p The active capacitor C0 and the operational amplifier AMP form a second charging circuit for distributing charge to the integral capacitor C1; the control signal generating circuit is used to generate a control signal, wherein the control signal is configured to control the conduction or disconnection of the switch group placed in the first charging circuit and the second charging circuit, so that the first charging circuit and the second charging circuit are alternately turned on to charge the integral capacitor so that its voltage reaches the target voltage required by the user. The voltage input terminal is configured to input a reference voltage, and the reference voltage is less than the target voltage VDD required by the output user.

[0025] Among them, Figure 3 As shown, the switch group includes: a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; wherein the first switch S1 is placed at V A The second switch S2 is placed between the V B The third switch S3 is placed between the V A The fourth switch S4 is placed between the V B The output V of the op amp p Between the ends.

[0026] More preferably, Figure 4 is a circuit diagram of another ramp voltage generator of the present invention, Figure 5 exist Figure 4 On the basis of the above, a control signal generating circuit and a switch group are added, wherein the first switch, the second switch, the third switch and the fourth switch are all composed of PMOS tubes and / or NMOS tubes. Figure 4 As shown, transistor M1 constitutes a first switch S1; transistors M2 and M3 constitute a second switch S2; transistors M4 and M5 constitute a third switch S3; transistors M6 and M7 constitute a fourth switch S4, and U0 is an operational amplifier AMP. The control signal generating circuit includes: a clock circuit for generating a non-overlapping clock signal and a timing adjustment circuit for adjusting the timing of the non-overlapping clock signal; the clock circuit receives a CLK clock signal and sends the non-overlapping clock signal to the first switch S1, the second switch S2 and the timing adjustment circuit, and the timing adjustment circuit sends the non-overlapping clock signal after the timing is adjusted to the third switch S3 and the fourth switch S4.

[0027] Figure 5is a timing diagram of the control signal generated by the control signal generating circuit. Figure 6 As shown, the first switch S1 and the second switch S2 can be opened synchronously at a high level, the third switch S3 and the fourth switch S4 can be opened synchronously at a high level, and S1 and S2 and S3 and S4 are opened alternately.

[0028] Figure 6 1 is a diagram showing the simulated output waveform of the ramp voltage of the present invention. Figure 7 As shown, the output voltage range of the ramp voltage generator can reach 0V~VDD, and its range can be adjusted by the input reference voltage VR. In addition, the circuit has good linearity within the output voltage range and is suitable for many occasions with high requirements on the output voltage range and linearity.

[0029] Figure 7 This invention is used to illustrate Figure 4 or Figure 5 A flow chart of a method for generating a ramp voltage of a ramp voltage generator. Figure 7 As shown, the method for generating the ramp voltage includes:

[0030] Step 1: In one integration cycle, execute:

[0031] The first stage: controlling the switch group in the first charging circuit to be turned on and the switch group in the second charging circuit to be turned off, so that the voltage of the active capacitor reaches a reference voltage reflecting the voltage change rate required by the user; and

[0032] The second stage: based on the reference voltage, the switch group in the first charging circuit is continuously controlled to be turned off and the switch group in the second charging circuit is turned on, so as to charge all the charges on the active capacitor to the integration capacitor.

[0033] Step 2, repeating a plurality of the integration cycles so that the voltage of the integration capacitor reaches a target voltage required by the user, wherein the target voltage is greater than the reference voltage.

[0034] Specifically, during the first stage of operation in Step 1, S1 and S2 are closed, S3 and S4 are open, and V A The potential at point V R , V B The potential at is GND (0V). At this time, the voltage of the active capacitor C0 is charged to V R ; In the second stage, S1 and S2 are disconnected, S3 and S4 are closed, and the potential at VB is V P , that is, V OUT The potential, V A The potential at point is (V OUT +VR ) is greater than V OUT At this time, the charge of the active capacitor C0 flows to the integrating capacitor C1.

[0035] In Step 2, S1 to S4 complete multiple cycles of charging and charge distribution under the control of the clock CLK. The terminal voltage V OUT , will gradually increase from the initial 0V and eventually reach (V OUT +V R ). In this process, the charge of the active capacitor C0 is fixed, the change process of the charging voltage of the integrating capacitor C1 is close to linear, and the output range can reach the full voltage range, that is, 0V~VDD.

[0036] In addition, the present invention also provides an integrated circuit, which includes Figure 3 , Figure 4 The ramp voltage generator.

[0037] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0038] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0039] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A ramp voltage generator, characterized in that: The ramp voltage generator includes: a switch group, an operational amplifier AMP, an active capacitor, an integral capacitor and a control signal generating circuit; Among them, the V of the active capacitor A terminal is connected to the voltage input terminal, the V B The terminal is grounded, and the voltage input terminal and the active capacitor form a first charging circuit for charging the active capacitor to a reference voltage; The active capacitor V A The ends are connected to one end of the integrating capacitor for output voltage and the positive input end of the operational amplifier AMP in sequence, the other end of the integrating capacitor is grounded, and the V B The end is connected to the output V of the op amp AMP p The active capacitor and the operational amplifier AMP form a second charging circuit for distributing charge to the integral capacitor; The control signal generating circuit is used to generate a control signal, wherein the control signal is configured to control the on or off of the switch groups disposed in the first charging circuit and the second charging circuit, so that the first charging circuit and the second charging circuit are alternately turned on to charge the integral capacitor so that the voltage of the integral capacitor reaches the target voltage required by the output user; The switch group includes: a first switch, a second switch, a third switch and a fourth switch; Wherein, the first switch is placed at V of the active capacitor A The second switch is placed between the V B The third switch is placed between the V A The fourth switch is placed between the V B The output V of the op amp p between the ends; The control signal generating circuit comprises: a clock circuit for generating a non-overlapping clock signal and a timing adjustment circuit for adjusting the timing of the non-overlapping clock signal; The clock circuit receives a CLK clock signal and sends the non-overlapping clock signal to the first switch, the second switch and the timing adjustment circuit. The timing adjustment circuit sends the non-overlapping clock signal after adjusting the timing to the third switch and the fourth switch.

2. The ramp voltage generator according to claim 1, characterized in that: At least one of the first switch, the second switch, the third switch and the fourth switch is composed of a PMOS tube; or At least one of the first switch, the second switch, the third switch and the fourth switch is composed of an NMOS transistor.

3. The ramp voltage generator according to claim 1, characterized in that: The voltage input terminal is configured to input a reference voltage, wherein the reference voltage is smaller than a target voltage required by an output user.

4. An integrated circuit, characterized in that: The integrated circuit comprises the ramp voltage generator according to any one of claims 1-3.

5. A method for generating a ramp voltage, characterized in that: The method for generating the ramp voltage uses the ramp voltage generator according to any one of claims 1 to 3, and the method for generating the ramp voltage includes: In one integration cycle, the switch group in the first charging circuit is controlled to be turned on and the switch group in the second charging circuit is controlled to be turned off, so that the voltage of the active capacitor reaches a reference voltage reflecting the voltage change rate required by the user, and the switch group in the first charging circuit is controlled to be turned off and the switch group in the second charging circuit is controlled to be turned on based on the reference voltage, so that all the charges on the active capacitor are charged to the integration capacitor; and Repeating a plurality of integration cycles allows the voltage of the integration capacitor to reach a target voltage required by an output user, wherein the target voltage is greater than the reference voltage.

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