System and method for error correction code architecture with priority task queue

Abstract

The present application provides a system, device and method with an error correction code (ECC) architecture that reduces decoding delay in error control. The device may include a control circuit that is configured to receive a status report that a decoding task using a first priority codeword has failed, determine that a higher priority is required for the next round of re-decoding the codeword, generate a NAND read task with a second priority higher than the first priority, and generate an ECC re-decoding task with the second priority.

Description

Technical Field

[0001] The present disclosure relates to an error correction code (ECC) architecture, and more particularly to an ECC architecture with multiple task queues for tasks of different priorities, and a method for reducing decoding delay in multi-level and multi-round error control schemes. Background Art

[0002] ECC has been widely used in data storage and communication systems to recover user data by a receiver or reader even when many errors are introduced during transmission or in memory due to data corruption (depending on the capabilities of the code used). As data storage and transmission technology advances, more data bits are stored and transmitted at higher bit error rates. Higher bit error rates typically result in multi-level decoding, multiple rounds of data reading, or both, and typically have larger decoding delays. Therefore, there is a need in the art for an ECC architecture that reduces delays in multi-level and multi-round error control schemes. Summary of the invention

[0003] The subject matter of the present disclosure relates to systems, methods, and apparatus for providing multiple task queues for an ECC architecture. An ECC architecture implementing the techniques described herein can reduce decoding delays in multi-level and multi-round error control schemes by assigning different priorities to tasks and selecting tasks to be executed based on the priorities. In some embodiments, tasks can be pushed into different queues associated with different priorities, and arbitration rules can be applied so that higher priority tasks can be selected to execute earlier than lower priority tasks. Therefore, in a multi-channel NAND storage system with a large number of queued unfinished tasks, decoding delays for error recovery can be reduced by upgrading the priority of a re-decoding task to be higher than any normal or lower priority task. Compared to the traditional method of mixing re-decoding tasks with primary decoding tasks, embodiments of the present disclosure provide a fast processing path for re-decoding tasks to reduce delays.

[0004] In an exemplary embodiment, a device is provided, which may include a control circuit configured to: receive a status report that a decoding task using a first priority to decode a codeword has failed; determine that a higher priority is required for the next round of re-decoding the codeword; generate a NAND read task with a second priority higher than the first priority; and generate an ECC re-decoding task with the second priority.

[0005] In another exemplary embodiment, a method is provided, the method comprising: receiving a status report that a decoding task using a first priority to decode a codeword has failed; determining that a higher priority is required for the next round of re-decoding the codeword; generating a NAND read task having a second priority higher than the first priority; and generating an ECC re-decoding task having the second priority.

[0006] The present invention may also include a non-transitory machine-readable medium having executable instructions, wherein when the executable instructions are executed by a hardware controller system, the hardware controller system is caused to: receive a status report that a decoding task using a first priority codeword has failed; determine that a higher priority is required for the next round of re-decoding the codeword; generate a NAND read task having a second priority higher than the first priority; and generate an ECC re-decoding task having the second priority. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A nonvolatile memory controller according to an embodiment of the present disclosure is schematically shown.

[0008] Figure 2A The ECC architecture in one embodiment of the present disclosure is schematically shown.

[0009] Figure 2B The ECC architecture in another embodiment of the present disclosure is schematically shown.

[0010] Figure 3 is a flowchart of an error control method according to an embodiment of the present disclosure.

[0011] Figure 4 is a flowchart of executing a NAND read task according to an embodiment of the present disclosure.

[0012] Figure 5 is a flowchart of performing an ECC decoding task according to an embodiment of the present disclosure.

[0013] Figure 6 is a flowchart of an error control method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Now, specific embodiments according to the present application will be described in detail with reference to the accompanying drawings. For consistency, the same elements in various figures are represented by the same reference numerals.

[0015] This specification provides apparatus, systems and methods that support any combination of various high-speed non-volatile memories (NVMs) and various NVMs. As used herein, a non-volatile memory device can be a computer storage device that can retain stored information after power failure and can read the stored information after power is restored (turned off and reopened). Non-volatile storage devices may include floppy disks, hard disk drives, tapes, optical disks, NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), Nano-RAM. In the specification, NAND flash memory can be used as an example of the proposed technology. However, other types of non-volatile storage devices can be used to implement these technologies according to various embodiments disclosed in this specification.

[0016] Figure 1 An exemplary non-volatile memory controller 100 according to one embodiment is schematically shown. The non-volatile memory controller 100 may include a first interface 110, a second interface 112, a controller unit (MCU) 102, and an ECC processor 104. The first interface 110 may be any existing or yet to be developed interface, which is configured to couple the non-volatile memory controller 100 to a system bus of a host computing system, and receive data from the host computing system and send data to the host computing system. In one embodiment, for example, the first interface 110 may be an advanced extensible interface (AXI). The second interface 112 may be any existing interface or yet to be developed interface, which is configured to couple the memory controller 110 to one or more non-volatile memory devices (NVMs). In one embodiment, the second interface 112 may be a multi-channel interface, which may be configured to transmit encoded data (e.g., ECC codewords) on multiple channels in parallel. For example, the second interface 112 may be an open NAND Flash interface (ONFI), which may support different protocols (e.g., non-volatile double data rate (NVDDR), NVDDR type 2 (NVDDR2), NVDDR type 3 (NVDDR3)), or may be a Toggle protocol and operate at different transfer speeds.

[0017] The MCU 102 may be a computer processor configured to execute executable instructions (e.g., software or firmware). In various embodiments, the MCU 102 may be a microprocessor, a microcontroller, a field programmable gate array (FPGA), or an application specific IC (ASIC). The ECC processor 104 may include one or more ECC encoders and one or more ECC decoders, wherein the one or more ECC encoders encode data into code words to be stored in the NVM, and the one or more ECC decoders decode the code words read from the NVM.

[0018] Figure 2A The ECC architecture 200A according to an embodiment of the present disclosure is schematically shown. The ECC architecture 200A may include an ECC state manager 202, a task distributor 204, a NAND state manager 206, an ECC decoder engine 208, a NAND interface controller 210, a plurality of ECC task queues 220.1 to 220.M, a plurality of ECC task state queues 222.1 to 222.L, a plurality of NAND task queues 224.1 to 224.O, and a plurality of NAND task state queues 226.1 to 226.P. The ECC decoder engine 208 may include an ECC decoding control 212, a plurality of ECC decoders 214.1 to 214.N, an input multiplexer 216, and an output multiplexer 218.

[0019] Each of the numbers L, M, O, P and N can represent a positive integer greater than 1. The numbers L, M, O, P can indicate the number of priorities in each type of queue (e.g., ECC task state queue, ECC task queue, NAND task queue and NAND task state queue). For example, in an embodiment where L is 2, there can be two ECC task state queues, each associated with different priorities (e.g., normal and high). In another embodiment where L is 3, there can be three ECC task state queues, each associated with different priorities (e.g., low, normal and high). In one embodiment, the numbers L, M, O, P can have the same value (e.g., having two priorities in all four types of queues, or having three priorities in all four types of queues). But in some embodiments, at least some of the numbers L, M, O, P can have values ​​different from other numbers. For example, there may be two priority ECC task queues 220.1 to 220.2 and two priority ECC task status queues 222.1 to 222.2, but three priority NAND task queues 224.1 to 224.3 and three priority NAND task status queues 226.1 to 226.3. In one embodiment, the various types of queues may be implemented in known or yet to be developed hardware queues, such as, but not limited to, circuit registers, shift registers.

[0020] The plurality of ECC decoders 214.1 to 214.N may be N decoders providing different decoding capabilities. In one embodiment, more powerful decoding may mean using one or more different decoders with more powerful decoding capabilities, or reusing the same decoder to decode again with additional soft information. Thus, in an error control scheme, a codeword that fails to be decoded by a first decoder may be tried again by a more powerful second decoder or by a first decoder with additional soft information read from the NVM.

[0021] The task distributor 204 may be configured to control the read operation. For example, when there is a read request to the ECC architecture 200A to read data from the NVM, the task distributor 204 may generate a NAND read task, determine the priority of the NAND read task (e.g., based on the priority of the read request), and push it into one of the plurality of NAND task queues 224.1 to 224.0 according to the priority of the NAND read task. In one embodiment, a task identifier (e.g., a task ID) may be assigned to the NAND read task.

[0022] The NAND interface controller 210 may receive NAND read tasks from the NAND task queues 224.1 to 224.0 and execute the tasks via an input 230 coupled to the NVM to read data from the NVM. One or more of a set of arbitration rules may be implemented (e.g., by the NAND interface controller 210) to select a NAND task for execution when multiple tasks may be available for selection. The set of arbitration rules may include round-robin, weighted round-robin, priority, or a combination thereof. For example, in a polling-based selection, a task may be selected one at a time from each of the plurality of NAND task queues 224.1 to 224.O in turn; for example, in a weighted polling-based selection, a task may be selected from each of the plurality of NAND task queues 224.1 to 224.O in turn, but each queue may be given a different weight (e.g., two tasks from a task queue associated with a higher priority and one task from a task queue associated with a lower priority in one round); in a priority-based selection, a task in a higher priority queue among the plurality of NAND task queues 224.1 to 224.O may be executed by the NAND interface controller 210 before all tasks in a lower priority task queue.

[0023] The order in which the NAND tasks are completed may not be guaranteed to be the same as the order in which the NAND tasks are started. In one embodiment, for example, priority-based arbitration may be implemented, wherein a first NAND read task in a high priority NAND task queue may be executed before a second NAND read task in a normal priority NAND task queue. The second NAND read task may be started by the NAND interface controller 210 later than the first NAND read task, but may be completed earlier. The NAND interface controller 210 may be configured to generate a task completion status report according to the priority of the NAND read task and send the task completion status report to one of the multiple NAND task status queues 226.1 and 226.P whenever a NAND read task has been completed and the NAND interface controller 210 has received data (e.g., one or more codewords). For example, in an embodiment where the number of NAND task status queues can match the number of NAND task queues (e.g., number O equals number P), when the second NAND read task is completed, the NAND interface controller 210 can send a status report to the normal priority NAND task status queue, and when the first NAND read task is completed, the NAND interface controller 210 can send a status report to the high priority NAND task status queue. In one embodiment, the task status report can include a task identifier associated with the task.

[0024] The NAND state manager 206 may be configured to monitor the NAND task status queues 226.1 to 226.P and report the completion of the NAND task to the task distributor 204. Once the NAND read task is completed, the data read from the NVM may be ready for decoding. The task distributor 204 may generate an ECC decoding task, determine the priority of the decoding task, and push the decoding task into one of the multiple ECC task queues 220.1 to 220.M based on the priority of the ECC decoding task. In one embodiment, the same task identifier associated with the NAND read task may be reused for the ECC decoding task, but this may be optional. The ECC decoding control 212 may receive the ECC decoding task from the multiple ECC task queues 220.1 to 220.M and select one of the multiple ECC decoders 214.1 to 214.N to perform the decoding operation. One or more of a set of arbitration rules may be implemented (e.g., by the ECC decoding control 212) to select an ECC decoding task to execute when there may be multiple tasks to choose from. The arbitration rules may include round robin, weighted round robin, priority, or a combination thereof, similar to those that may be implemented for selecting a NAND task for execution. A control signal may be generated by the ECC decode control 212 and sent to the input multiplexer 216 so that a codeword read from the NVM may be routed to a selected ECC decoder.

[0025] The selected ECC decoder may successfully decode the codeword or fail to decode the codeword. If the codeword is successfully decoded, the decoding task is successfully completed, and a decoding success signal can be generated by the ECC decoding control 212 and pushed into one of the ECC task status queues 222.1 to 222.L. At the same time, the ECC decoding control 212 can send a signal to the decoder output multiplexer 232 so that the decoded data can be output from the decoder engine 208. If the codeword is not successfully decoded, the decoding task has failed, and a decoding failure signal can be generated by the ECC decoding control 212 and pushed into one of the ECC task status queues 222.1 to 222.L.

[0026] In one embodiment, one decoder may take longer to complete a decoding task than another decoder, regardless of whether the decoding operation is successful or failed. For example, ECC decoder 214.1 may start a decoding operation for a first decoding task after ECC decoder 214.2 starts a decoding operation for a second decoding task, but ECC decoder 214.1 may complete its decoding operation earlier. If the first decoding task and the second decoding task have the same priority, the state signals of the first decoding task and the second decoding task may be queued in the same ECC task state queue, and the earlier state signal is located before the later state signal. If the first decoding task and the second decoding task have different priorities, the state signals for the first decoding task and the second decoding task may be queued in different ECC task state queues with corresponding priorities, respectively. In one embodiment, an error control scheme may increase (e.g., upgrade) the priority of a decoding failure signal so that the priority of the decoding state is higher than the priority of the decoding task itself. For example, when a normal priority decoding task is successfully decoded, a decoding success signal may be sent to a normal priority ECC task state queue, but when a normal priority decoding task cannot be successfully decoded, a decoding failure signal may be sent to a high priority ECC task state queue.

[0027] The ECC state manager 202 may be configured to monitor the ECC task status queues 222.1 to 222.L and report the completion of the ECC task to the task dispatcher 204. In an embodiment where a decode failure may be reported in an ECC task status queue having a high priority level, the ECC state manager 202 may receive a decode failure signal earlier than a decode success signal even though a decode success signal may have been generated by the ECC decode control 212 and sent earlier to an ECC task status queue of a low priority or normal priority.

[0028] In some embodiments, the ECC architecture 200A can implement a multi-level and multi-round error control scheme so that if a codeword is not successfully decoded in the first decoding attempt, a re-decoding task can be processed through a fast processing path. In one embodiment, for example, the decoding failure of the codeword can be reported by the ECC decoding control 212 to the high priority ECC task status queue 222 and notified to the ECC state manager 202. The task distributor 204 can be configured to generate a NAND re-read task with a high priority and send the re-read task to the high priority NAND task queue 224. The NAND interface controller 210 can be configured to report the status of the NAND re-read task to the high priority NAND task status queue 226. The task distributor 204 can be further configured to generate a re-decoding task of a codeword with a high priority and send the re-decoding task to the high priority ECC task queue 220. Normal priority and high priority are examples only. In one embodiment, there can be more than two priorities, and the re-decoding task can be upgraded to a priority higher than the decoding task in the previous decoding attempt. In addition, in one embodiment, the same task identifier can be used in multiple rounds of the decoding process. Therefore, the fast processing path can reduce the delay in the multi-level multi-round error control method. It should be noted that in various embodiments, different rules can be used to change the priority of the re-decoding task. For example, one rule may always increase the priority of the re-decoding task in each round until the highest priority is reached. Another rule may only increase the priority of the re-decoding task when necessary.

[0029] Figure 2B Schematically illustrates an ECC architecture 200B according to another embodiment of the present disclosure. Compared with the ECC architecture 200A, the ECC architecture 200B may include a NAND task status queue 226 and an ECC task status queue 222. Therefore, once any NAND read task completes its read operation and has acquired the data required by the read task from the NVM, the NAND interface controller 210 may push the task status into the same NAND task status queue 226. And once any ECC decoding / re-decoding task is completed (e.g., successful or failed), the ECC decoding control 221 may push the task status into the same ECC task status queue 222. Therefore, in an embodiment of the ECC architecture 200B, task status information will not be pushed into different status queues associated with different priorities, while NAND tasks and ECC decoding / re-decoding tasks may be pushed into different task queues associated with different priorities. In such an embodiment, the task status information may include a task identifier and a priority of the task, and the ECC status manager 202 and the NAND status manager 206 may give priority to the task status report of a task with a higher priority.

[0030] In some embodiments, various components of ECC architecture 200A and ECC architecture 200B can be implemented with hardware circuit modules. For example, ECC state manager 202, task distributor 204, NAND state manager 206 can be implemented with FPGA, ASIC or a combination of FPGA and ASIC. In addition, NAND read tasks, ECC decoding or re-decoding tasks can be generated by hardware. In some other embodiments, at least some components of ECC architecture 200A and ECC architecture 200B can be implemented by a computer processor that executes executable instructions. For example, in one embodiment, any one or all of ECC state manager 202, task distributor 204, and NAND state manager 206 can be implemented by MCU102 executing executable instructions of software or firmware. In addition, NAND read tasks, ECC decoding or re-decoding tasks can be generated by a processor that executes executable instructions. In one embodiment, ECC state manager 202, task distributor 204, NAND state manager 206, ECC decoding control 212, NAND interface controller 210 and MCU102 can be collectively referred to as control circuits.

[0031] Figure 3 3 is a flowchart of an error control method 300 according to an embodiment of the present disclosure. In box 302, a status report identifying that a decoding task has failed may be received. For example, a decoding task with a first priority performed by one of a plurality of ECC decoders 214.1 to 214.N may fail to decode the codeword, and the ECC decoding control 212 may be configured to push the failure status that the decoding task has failed into the ECC task status queue. In box 304, it may be determined whether a higher priority is required to re-decode the codeword. For example, when a codeword fails in a decoding task, the task distributor 204 may be configured to determine that a retry task may require a re-decoding task with an upgraded priority. In box 306, a NAND read task with a second priority higher than the first priority may be generated. For example, the task distributor 204 may generate a NAND read task with an upgraded priority. In one embodiment, the NAND read task may attempt to read more information about the codeword, for example, additional information for soft decision decoding. In box 308, the NAND read task may be pushed into a NAND task queue associated with the second priority. The plurality of NAND task queues 224.1 to 224.O may be associated with different priorities, so that the generated NAND read tasks may be stored in a task queue associated with an upgraded priority.

[0032] In box 310, the NAND read tasks may be prioritized based on the second priority. For example, tasks in multiple NAND task queues 224.1 to 224.0 may be selected for execution by the NAND interface controller 210 based on an arbitration rule (e.g., a priority-based selection or a weighted round-robin selection), and tasks with higher priorities may be selected and started earlier than tasks with lower priorities. In box 312, an ECC re-decoding task with a second priority may be generated. In box 314, the ECC re-decoding task may be pushed into an ECC task queue associated with the second priority. For example, once the NAND read task has been completed by the NAND interface controller 210 and the data read from the NVM may be ready for further processing, a task status report may be sent to the task status queue. The NAND state manager 206 may report a status update for the NAND read task to the task distributor 204, and the task distributor 204 may generate an ECC re-decoding task with an upgraded higher priority.

[0033] In block 316, the ECC re-decoding tasks may be prioritized based on higher priorities. For example, the ECC re-decoding tasks may be sent to an ECC task queue with a correspondingly higher priority and may be selected for execution by the ECC decoding control 212 according to an arbitration rule (e.g., a priority-based selection or a weighted round-robin selection), so that a higher priority task may be selected and started earlier than a lower priority task. In one embodiment, the re-decoding task may be assigned to a decoder that failed in a first decoding attempt for a more powerful retry. In another embodiment, the re-decoding task may be assigned to another decoder that may be more powerful than the decoder that failed in the first decoding attempt.

[0034] Figure 4 4 is a flowchart of a method 400 for performing a NAND read task according to an embodiment of the present disclosure. In box 402, it can be determined whether there is a read request. For example, the read request can come from a host coupled to a NAND storage system, or be generated within the NAND storage system (e.g., for garbage collection). In one embodiment, a priority can be assigned to the read request based on whether it comes from a host or is generated in the NAND storage system. In box 404, a NAND read task can be generated, and a specific priority can be assigned to the NAND read task. In box 406, the NAND read task can be pushed into a NAND task queue based on the priority. In box 408, a NAND read task can be selected based on an arbitration rule and sent to a NAND interface controller for execution. The arbitration rule can be polling, weighted polling, priority, or a combination thereof.

[0035] Figure 5 5 is a flowchart of a method 500 for performing an ECC decoding task according to an embodiment of the present disclosure. In box 502, it can be determined that the NAND interface controller has read a codeword from the NVM. For example, when the NAND interface controller 210 has completed the NAND read task, the status report can be pushed into the NAND task status queue 226, and the task distributor 204 can obtain the NAND task completion status from the NAND state manager 206. In box 504, an ECC decoding task can be generated and assigned a priority. In one embodiment, the ECC decoding task can reuse the task identifier assigned to the NAND read task that reads the codeword from the NVM. In addition, the priority can also be the same priority as the read task. In box 506, the ECC decoding task can be pushed into the ECC task queue based on the priority. In box 508, the ECC decoding task can be selected based on the arbitration rule and sent to the ECC decoding control for execution. The arbitration rule can be polling, weighted polling, priority, or a combination thereof. In one embodiment, the ECC decoding control 212 may select an ECC decoder from among the plurality of ECC decoders 214 . 1 to 214 .N to decode the codeword based on the decoding capability requirement.

[0036] Figure 6 6 is a flowchart of an error control method 600 according to another embodiment of the present disclosure. In box 602, a status report indicating that a decoding task has failed may be received. For example, a decoding task with a first priority performed by one of a plurality of ECC decoders 214.1 to 214.N may not be able to decode the codeword, and the ECC decoding control 212 may be configured to push the failure status that the decoding task has failed to the ECC task status queue. In box 604, it may be determined whether a higher priority is needed to re-decode the codeword. For example, when a codeword fails in a decoding task, the task distributor 204 may be configured to determine that a retry task may require a re-decoding task with an upgraded priority. In box 606, a NAND read task with a second priority higher than the first priority may be generated. For example, the task distributor 204 may generate a NAND read task with an upgraded priority. In one embodiment, the NAND read task may attempt to read more information about the codeword, for example, additional information for soft decision decoding.

[0037] In an embodiment implementing multiple NAND task queues 224.1 to 224.0, NAND read tasks to be pushed into a NAND task queue associated with a second priority level and the NAND read tasks may be prioritized based on the second priority level.

[0038] In block 608, an ECC re-decode task with a second priority may be generated. In one embodiment implementing ECC task queues 220.1 through 220.M, the ECC re-decode task may be pushed into an ECC task queue associated with the second priority and may be prioritized based on the higher priority.

[0039] In various embodiments, each of methods 300, 400, 500, and 600 may have one or more parts, or all, implemented using hardware (e.g., a field programmable gate array (FPGA) or an application specific IC (ASIC)), firmware, a computer processor executing software instructions, or any suitable combination.

[0040] Embodiments of the present disclosure may include multiple ECC decoders 1 to decoders N providing different decoding capabilities, where N is an integer greater than 1. In one embodiment, a more powerful decoding scheme may mean using a different decoder or reusing the same decoder with additional soft information. Therefore, in an error control scheme, a codeword that a decoder fails to decode may have one or more rounds of re-decoding process. The re-decoding tasks can be generated by hardware or software. The arbitration scheme for selecting the execution task can be polling, weighted polling priority, or a combination thereof. Moreover, different rules can be used to change the priority of the re-decoding task. For example, the priority of the re-decoding task can always be increased each round until the highest priority is reached, or, if necessary, the priority of the re-decoding task may only be increased.

[0041] In an exemplary embodiment, a device is provided, which may include a control circuit configured to: receive a status report that a decoding task with a first priority for decoding a codeword has failed; determine that a higher priority is required for the next round of re-decoding the codeword; generate a NAND read task with a second priority higher than the first priority; and generate an ECC re-decoding task with the second priority.

[0042] In one embodiment, the apparatus may further include a plurality of NAND task queues associated with different priorities and a plurality of error correction code (ECC) task queues associated with different priorities. The control circuit may be further configured to: push the NAND read task into one of the plurality of NAND task queues associated with the second priority; prioritize the NAND read task based on the second priority; push the ECC re-decoding task into one of the plurality of ECC task queues associated with the second priority; and prioritize the ECC re-decoding task based on the second priority.

[0043] In one embodiment, the apparatus further comprises a plurality of ECC decoders, wherein the control circuit is further configured to select an ECC decoder from the plurality of ECC decoders to decode the codeword.

[0044] In one embodiment, the plurality of ECC decoders include at least a first decoder and a second decoder, the second decoder being more powerful than the first decoder, and the control circuit is further configured to select the first decoder for the decoding task and the second decoder for the ECC re-decoding task.

[0045] In one embodiment, the apparatus further comprises an ECC task status queue, wherein the control circuit is further configured to generate a failure status report when the decoding task fails, and push the failure status report to the ECC task status queue.

[0046] In one embodiment, the device also includes: multiple ECC task status queues associated with different priorities, wherein the control circuit is further configured to: when the decoding task fails, generate a failure status report, and push the failure status report to one of the multiple ECC task status queues associated with the second priority.

[0047] In one embodiment, prioritizing the NAND read tasks and prioritizing the ECC re-decode tasks include applying an arbitration rule of one of weighted round-robin or priority.

[0048] In one embodiment, the apparatus may further include an ECC state manager configured to monitor the ECC task state, a NAND state manager configured to monitor the NAND task state, and a task distributor coupled to the ECC state manager and the NAND state manager and configured to generate NAND tasks and ECC decoding and re-decoding tasks.

[0049] In one embodiment, each of the NAND tasks and each of the ECC decoding and re-decoding tasks has a priority, respectively, and the NAND tasks and the ECC decoding and re-decoding tasks are pushed into a plurality of NAND task queues and a plurality of ECC task queues based on their respective priorities.

[0050] In one embodiment, the control circuit may include a computer processor configured to execute the following software instructions: monitor ECC task status; monitor NAND task status, and generate NAND tasks and ECC decode and re-decode tasks.

[0051] In one embodiment, each of the NAND tasks and each of the ECC decoding and re-decoding tasks has a priority, respectively, and the NAND tasks and the ECC decoding and re-decoding tasks are pushed into a plurality of NAND task queues and a plurality of ECC task queues based on their respective priorities.

[0052] In another exemplary embodiment, a method is provided, the method comprising: receiving a status report that a decoding task using a first priority to decode a codeword has failed; determining that a higher priority is required for the next round of re-decoding the codeword; generating a NAND read task having a second priority higher than the first priority; and generating an ECC re-decoding task having the second priority.

[0053] In one embodiment, the method may further include: pushing the NAND read task into a NAND task queue associated with the second priority; prioritizing the NAND read task based on the second priority; pushing the ECC re-decoding task into an ECC task queue associated with the second priority; and prioritizing the ECC re-decoding task based on the second priority.

[0054] In one embodiment, the method further comprises: selecting an ECC decoder from a plurality of ECC decoders to decode the codeword.

[0055] In one embodiment, the decoding task is performed using a first ECC decoder and the re-decoding task is performed using a second decoder, and the second decoder is more powerful than the first decoder.

[0056] The method further includes: when the decoding task fails, generating a failure status report, and pushing the failure status report into an ECC task status queue.

[0057] In one embodiment, the method further comprises: generating a failure status report when the decoding task fails, and pushing the failure status report into a queue associated with the second priority in the multiple ECC task status queues, each of the multiple ECC task status queues being associated with a different priority. The multiple ECC task status queues may be associated with different priorities, respectively.

[0058] In one embodiment, the method further comprises: applying an arbitration rule of one of weighted round-robin or priority to prioritize the NAND read task and the ECC re-decode task.

[0059] In one embodiment, the method may further include monitoring the ECC task status; monitoring the NAND task status, and generating a NAND task and an ECC decoding and re-decoding task based on the collected NAND task status or the ECC task status.

[0060] In one embodiment, each of the NAND tasks and each of the ECC decoding and re-decoding tasks has a priority, respectively, and the NAND tasks and the ECC decoding and re-decoding tasks are pushed into a plurality of NAND task queues and a plurality of ECC task queues based on their respective priorities.

[0061] The present invention may also include a non-transitory machine-readable medium having executable instructions, which, when executed by a hardware controller system, may cause the hardware controller system to perform the following operations: receive a status report that a decoding task using a first priority codeword has failed; determine that a higher priority is required for the next round of re-decoding the codeword; generate a NAND read task having a second priority higher than the first priority; and generate an ECC re-decoding task having the second priority.

[0062] In one embodiment, when the executable instructions are executed by the hardware controller system, they may also cause the hardware controller system to perform the following operations: push the NAND read task into one of the multiple NAND task queues associated with the second priority; prioritize the NAND read task based on the second priority; push the ECC re-decoding task into one of the multiple ECC task queues associated with the second priority; and prioritize the ECC re-decoding task based on the second priority.

[0063] In one embodiment, the executable instructions, when executed by the hardware controller system, may also cause the hardware controller system to apply an arbitration rule, which may be one of weighted round-robin or priority, to prioritize NAND read tasks and ECC re-decode tasks.

[0064] Any disclosed methods and operations may be implemented as computer executable instructions (e.g., software codes for the operations described herein) stored on one or more computer-readable storage media (e.g., non-transitory computer-readable media, such as one or more optical disk media, volatile storage components (e.g., DRAM or SRAM), or non-volatile storage components (e.g., SSD hard disks)) and executed on a device controller (e.g., firmware executed by an ASIC). Any computer executable instructions for implementing the disclosed technology and any data created and used during the implementation of the disclosed embodiments may be stored on one or more computer-readable media (e.g., non-transitory computer-readable media).

[0065] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

Claims

1. A device for decoding, comprising: Multiple NAND task queues associated with different priorities; One or more NAND task status queues; Multiple ECC task queues associated with different priorities; Control circuit, including: An ECC status manager configured to monitor an ECC task status; A NAND status manager configured to monitor NAND task status, and a task distributor coupled to the ECC status manager and the NAND status manager and configured to: receiving, via the ECC status manager, a status report that a decoding task using a first priority decoding codeword has failed; Determine that the next round of re-decoding of the codeword requires a higher priority; generating a NAND read task having a second priority level higher than the first priority level; Pushing the NAND read task into one of the plurality of NAND task queues associated with the second priority level; receiving, via the NAND status manager, a NAND read completion status report of completion of the NAND read task of the second priority level; generating an ECC re-decoding task having a second priority level higher than the first priority level; Pushing the ECC re-decoding task into one of the plurality of ECC task queues associated with the second priority level; A NAND interface controller, wherein the one or more NAND task status queues are coupled between the NAND status manager and the NAND interface controller, and the NAND interface controller is configured to: generate a NAND read completion status report when a NAND read task with the second priority is read completed, and for the NAND status report with the second priority, push the NAND read completion status report into one of the one or more NAND task status queues.

2. The device according to claim 1, characterized in that Further comprising a plurality of ECC decoders, wherein the control circuit is further configured to select an ECC decoder from the plurality of ECC decoders to decode the codeword.

3. The device according to claim 2, characterized in that The plurality of ECC decoders include at least a first decoder and a second decoder, the second decoder being more powerful than the first decoder, and the control circuit is further configured to select the first decoder for the decoding task and the second decoder for the ECC re-decoding task.

4. The device according to claim 1, characterized in that Further comprising an ECC task status queue, wherein the control circuit is further configured to generate a failure status report when the decoding task fails, and push the failure status report into the ECC task status queue.

5. The device according to claim 1, characterized in that Also includes: Multiple ECC task status queues associated with different priorities, wherein the control circuit is further configured to: when the decoding task fails, generate a failure status report, and push the failure status report into a queue associated with the second priority among the multiple ECC task queues.

6. The device according to claim 1, characterized in that Prioritizing the NAND read tasks and prioritizing the ECC re-decode tasks include applying an arbitration rule of one of weighted round-robin or priority.

7. The device according to claim 1, characterized in that Each of the NAND tasks and each of the ECC decoding and re-decoding tasks has a priority, respectively, and the NAND tasks and the ECC decoding and re-decoding tasks are pushed into a plurality of NAND task queues and a plurality of ECC task queues based on their respective priorities.

8. The device according to claim 1, characterized in that The control circuit includes a computer processor configured to execute software instructions to: Monitor ECC task status; Monitor NAND task status, and Generates NAND tasks as well as ECC decode and re-decode tasks.

9. The device according to claim 8, characterized in that Each of the NAND tasks and each of the ECC decoding and re-decoding tasks has a priority, respectively, and the NAND tasks and the ECC decoding and re-decoding tasks are pushed into a plurality of NAND task queues and a plurality of ECC task queues based on their respective priorities.

10. A decoding method, comprising: receiving, in the task dispatcher via the ECC status manager, a status report that a decoding task using a first priority decoding codeword has failed; Determining by the task allocator that the next round of re-decoding of the codeword requires a higher priority; generating, by the task allocator, a NAND read task having a second priority level higher than the first priority level; Pushing the NAND read task into one of the plurality of NAND task queues associated with the second priority level by the task distributor; When the NAND read task with the second priority level is read and a NAND read completion status report is generated, the NAND read completion status report is pushed into one of the one or more NAND task status queues coupled between the NAND status manager and the NAND interface controller; receiving, by the task distributor via the NAND status manager, a NAND read completion status report of completion of the NAND read task of the second priority level; generating, by the task allocator, an ECC re-decoding task having a second priority level higher than the first priority level; as well as The ECC re-decoding task is pushed into one of the multiple ECC task queues associated with the second priority level by the task distributor.

11. The method according to claim 10, characterized in that Also includes: An ECC decoder is selected from a plurality of ECC decoders to decode the codeword.

12. The method according to claim 10, characterized in that The decoding task is performed using a first ECC decoder, and the re-decoding task is performed using a second decoder, and the second decoder is more powerful than the first decoder.

13. The method according to claim 10, characterized in that Also includes: When the decoding task fails, a failure status report is generated and the failure status report is pushed into the ECC task status queue.

14. The method according to claim 10, characterized in that Also includes: When the decoding task fails, a failure status report is generated and pushed into one of the multiple ECC task queues associated with the second priority level, each of the multiple ECC task status queues being associated with a different priority level.

15. The method according to claim 10, characterized in that Also includes: An arbitration rule of one of weighted round-robin or priority is applied to prioritize the NAND read task and the ECC re-decode task.

16. The method according to claim 10, characterized in that Each of the NAND tasks and each of the ECC decoding and re-decoding tasks has a priority, respectively, and the NAND tasks and the ECC decoding and re-decoding tasks are pushed into a plurality of NAND task queues and a plurality of ECC task queues based on their respective priorities.

17. A non-transitory machine-readable medium having executable instructions, characterized in that: When the executable instructions are executed by the hardware controller system, the hardware controller system performs the following operations: receiving, in the task dispatcher via the ECC status manager, a status report that a decoding task using a first priority decoding codeword has failed; Determining by the task allocator that the next round of re-decoding of the codeword requires a higher priority; generating, by the task allocator, a NAND read task having a second priority level higher than the first priority level; Pushing the NAND read task into one of the plurality of NAND task queues associated with the second priority level by the task distributor; When the NAND read task with the second priority level is read and a NAND read completion status report is generated, the NAND read completion status report is pushed into one of the one or more NAND task status queues coupled between the NAND status manager and the NAND interface controller; receiving, by the task distributor via the NAND status manager, a NAND read completion status report of completion of the NAND read task of the second priority level; generating, by the task allocator, an ECC re-decoding task having a second priority level higher than the first priority level; as well as The ECC re-decoding task is pushed into one of the multiple ECC task queues associated with the second priority level by the task distributor.

18. The non-transitory machine-readable medium of claim 17, wherein: When the executable instructions are executed by the hardware controller system, the hardware controller system is further caused to apply an arbitration rule of one of weighted round-robin or priority to prioritize the NAND read task and the ECC re-decode task.

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