Electronic device including a photodiode

Abstract

An electronic device including a photodiode is provided. The photodiode includes a semiconductor region coupled to a node to which a first voltage is applied and at least one semiconductor wall. The at least one semiconductor wall extends at least along the height of the photodiode and partially surrounds the semiconductor region.

Description

Technical Field

[0001] The present disclosure generally relates to electronic devices including at least one photodiode. Background Art

[0002] Photodiodes are semiconductor components each including a PN junction. Photodiodes have the ability to detect radiation in the optical domain and convert it into an electrical signal.

[0003] Image sensors are electronic devices that each include a plurality of photodiodes. The photodiodes enable the device to obtain an image of a scene at a given time. The image is formed by an array of pixels, and the information of each pixel is obtained by one or more photodiodes. For example, this information usually corresponds to the number of electrons obtained by the photodiode at a given time, which is converted by the image sensor into a color level (red, green or blue) or into a grayscale level.

[0004] However, electrons formed after the time corresponding to the image may cause modifications in the image obtained by the sensor. Summary of the invention

[0005] One embodiment overcomes all or part of the disadvantages of known devices including photodiodes.

[0006] One embodiment provides an electronic device including a photodiode, the photodiode including a region coupled to a node to which a first voltage is applied, the region being partially surrounded by at least one semiconductor wall extending at least along a height of the photodiode.

[0007] According to one embodiment, the photodiode is formed in a semiconductor substrate and the one or more walls extend along the entire height of the semiconductor substrate.

[0008] According to one embodiment, the one or more walls are coupled to a node to which the second voltage is applied.

[0009] According to one embodiment, at least one of the one or more walls is U-shaped.

[0010] According to one embodiment, the region is located in a convex area delimited by at least one of the one or more U-shaped walls.

[0011] According to one embodiment, the device comprises two walls, each wall being U-shaped.

[0012] According to one embodiment, the convex area delimited by each of the two walls extends in the direction of the other wall.

[0013] According to one embodiment, the device comprises at least one wall having a cuboid shape.

[0014] According to one embodiment, the region is separated from the one or more walls by an insulating trench.

[0015] According to one embodiment, an apparatus comprises a transistor that couples, via its source and its drain, the cathode of the photodiode to a node to which a positive voltage is applied.

[0016] According to one embodiment, an apparatus includes a storage element coupled to a cathode of a photodiode.

[0017] According to one embodiment, the storage element is an electron collecting region.

[0018] According to one embodiment, an apparatus includes at least one connection pad disposed on a photodiode coupled to a node to which a positive voltage is applied.

[0019] Another embodiment provides a method of using an electronic device such as described above, the method comprising a first step during which a second voltage is a negative voltage and a second step during which the second voltage is a positive voltage.

[0020] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 schematically illustrates an electronic device including a photodiode;

[0022] Figure 2 The top view schematically shows the Figure 1 An embodiment of a photodiode as a portion of an electronic device;

[0023] Figure 3A It is along Figure 2 A cross-sectional view of plane AA, and Figure 3B It is along Figure 2 A cross-sectional view of plane BB; and

[0024] Figure 4 A further embodiment of an electronic device comprising a photodiode is schematically shown in a top view. DETAILED DESCRIPTION

[0025] In different drawings, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structure, size and material properties.

[0026] For clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail.

[0027] Throughout this disclosure, the term "connected" is used to designate a direct electrical connection between circuit elements with no intervening elements other than conductors, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more intervening elements.

[0028] In the following description, when referring to terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative positions (such as terms "above", "below", "upper", "lower", etc.), or when referring to terms defining directions (such as terms "horizontal", "vertical", etc.), unless otherwise specified, it refers to the orientation of the drawing.

[0029] The terms "approximately," "approximately," "substantially," and "about" are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0030] Figure 1 Schematically shown is an electronic device 100 comprising a photodiode 102. The device 100 is, for example, part of an image sensor comprising a plurality of photodiodes. For example, the device 100 may be repeated for each photodiode of the image sensor.

[0031] The photodiode 102 is coupled (preferably connected) between the node 104 and a node to which a first reference voltage (e.g., ground) is applied. More precisely, the cathode of the photodiode 102 is coupled (preferably connected) to the node 104, and the anode of the photodiode 102 is coupled (preferably connected) to the node to which the first reference voltage is applied.

[0032] The device 100 further comprises a switch 106, preferably a transistor, coupled between the node 104 and a node to which a second reference voltage (eg, a positive supply voltage Vdd) is applied. The voltage Vdd is, for example, greater than 1V.

[0033] The transistor 106 is connected, for example, by its drain to a node to which a voltage Vdd is applied, and by its source to the node 104. The gate of the transistor 106 is coupled (preferably connected) to a node to which a control voltage VC is applied.

[0034] The node 104 is further coupled (preferably connected) to a storage element 108MEM.

[0035] The storage element 108 is preferably an electron collecting region, for example a region made of a semiconductor material, which is capable of holding electrons formed by the photodiode 102. The device 100 may include one or more electron collecting regions 108.

[0036] In some embodiments, the method of using the device 100 includes at least two steps, which will be described for a single device 100. In the case where the image sensor includes multiple devices 100, each device 100 implements the method of using. Preferably, multiple devices 100 implement each step of the method simultaneously. Therefore, the information provided by each pixel 102 represents the same scene at the same time.

[0037] During a first step, an image of the scene is captured. More specifically, at a given time, light originating from the scene causes the formation of electrons in the photodiode 102. The number of electrons provides, for example, information about the pixel of the image to be obtained. During this first step, the electrons are transferred to one or more electron collection regions, which form, for example, the storage element 108. Then, the photodiode 102 can, for example, be covered.

[0038] The method may comprise a second step during which the number of electrons in the storage element is read by an adaptation circuit (not shown).

[0039] However, for example, if the photodiode is not covered, or if the photodiode is partially covered, light can continue to reach the photodiode. Then, electrons continue to form and are in danger of being transferred to the electronic storage area. At this time, the number of electrons and the information representing the image will be modified, and the information will no longer correspond to the image of the scene at the selected time. Then during the second step, switch 106 is turned on to couple node 104 to the node to which voltage Vdd is applied. Then, electrons are attracted to the node to which voltage Vdd is applied and away from storage element 108.

[0040] As a variation, in the case where the image sensor includes a plurality of devices 100, some parts of the device 100 may be common to the plurality of devices 100. For example, the switch 106 may be common to the plurality of devices 100, and the charges or electrons generated or formed by the plurality of devices 100 may be collectively stored in the storage element 108. In such an embodiment, the switch 106 may be selectively operated to transfer the stored charges from the storage element 108 to a node to which the voltage Vdd is applied.

[0041] Figure 2 One embodiment of a portion of an electronic device 100 including a photodiode 102 is schematically shown in top view. Figure 2 The cross-sectional view of plane AA ( Figure 3A ) and along Figure 2 The cross section of plane BB Figure 3B ( Figure 3B ).

[0042] The photodiode 102 comprises a PN junction in a semiconductor substrate. The photodiode 102 comprises, for example, a P-type semiconductor layer 200 covered with an N-type semiconductor layer 202. The layers 200 and 202 are made of silicon, for example. The layer 202 thus forms the source of the transistor 106 coupled to the cathode of the photodiode.

[0043] The device 100 comprises two contact pads 204, for example located on the upper surface of the photodiode 102. The pads 204 are located on the upper surface of the semiconductor layer 202, for example.

[0044] The contact pad 204 is, for example, coupled (preferably connected) to a node to which a control voltage is applied. For example, both pads are coupled to the same node to which the same control voltage is applied via a switch. The control voltage can cause electrons to move to the electron collection region. The control voltage is, for example, a positive voltage having a value equal to the power supply voltage Vdd.

[0045] The electron collection region is, for example, a semiconductor region adjacent to the photodiode 102. Each contact pad 204 is preferably opposite to a contact interface between the photodiode 102 and one of the electron collection regions. In addition to the contact interface, the photodiode 102 and the collection region are separated, for example, by an insulating wall or a semiconductor wall (not shown) that receives a negative voltage. As a variant, multiple pads 204 can be opposite to the same contact interface between the photodiode 102 and one of the electron collection regions.

[0046] exist Figure 2 3 , the device comprises two pads 204 , and thus, for example, two electron collecting regions. More generally, a device may comprise at least one pad 204 , and thus, at least one electron collecting region.

[0047] During the first step described previously, a positive voltage VP (e.g., a power supply voltage Vdd) is delivered to at least one of the pads 204 to attract electrons toward the pad 204 and thus toward the corresponding electron collection region. In the case where there are multiple pads 204 and multiple electron collection regions, the pads 204 receive the positive voltage in sequence, for example, alternately, so that electrons are partially stored in each electron collection region. This enables sampling of information obtained by the photodiode 102.

[0048] The connection pads 204 are, for example, surface elements, i.e., they are in contact with the surface of the photodiode 102, for example only with the upper surface of the semiconductor layer 202. For example, the connection pads 204 are in contact with the photodiode 102 only via a flat surface. For example, the contact pads 204 are semiconductor plates or layers made of, for example, metal, arranged on the photodiode 102.

[0049] The device 100 further comprises a semiconductor region 208 located in the photodiode 102. The region 208 is, for example, located in the semiconductor layer 202. In this example, the region 208 has the same doping type as the layer 202, for example N-type doping. The region 208 is, for example, more heavily doped than the semiconductor layer 202. The region 208 extends, for example, from the upper surface of the photodiode 102 (i.e., for example from the upper surface of the layer 202) into the semiconductor layer 202. The region 208 preferably does not extend along the entire height of the semiconductor layer 202.

[0050] Region 208 is coupled (preferably connected) to a node to which power supply voltage Vdd is applied. Region 208 forms the drain of transistor 106 ( Figure 1 ).

[0051] The device 100 also includes two semiconductor walls 210 ( Figure 2 3 ). More generally, the device 100 includes at least one semiconductor wall 210 partially surrounding the region 208. The wall 210 is, for example, made of an intrinsic semiconductor. The wall 210 is, for example, made of silicon. The wall 210 extends at least along the entire height of the photodiode (i.e., along the height of the layer 200 and the layer 202). Preferably, the wall 210 extends along the entire height of the substrate in which the photodiode 102 is formed.

[0052] In a top view, the wall 201a has a U-shape. Therefore, the wall 210a has a U-shaped cross-section in a plane parallel to the upper surface of the layer 202. The wall 210a includes two first branches that are substantially parallel to each other and are coupled by a second branch that is substantially perpendicular to the two first branches.

[0053] In a top view, the wall 210b also has a U-shape. Therefore, the wall 210b has a U-shaped cross-section in a plane parallel to the upper surface of the layer 202. The wall 210b includes two first branches that are substantially parallel to each other and are coupled by a second branch that is substantially perpendicular to the two first branches.

[0054] Preferably, the first branch of wall 210b is shorter than the first branch of wall 210a. Furthermore, the length of the second branch of wall 210a is substantially equal to the length of the second branch of wall 210b.

[0055] The first branch of each wall 210a and 210b has, for example, substantially the same width. Similarly, the second branch of each wall 210a and 210b has, for example, the same width. In addition, the first and second branches of the same wall have, for example, substantially the same width. The common width is, for example, in the range of 100 nm to 500 nm.

[0056] Walls 210a and 210b are located in front of each other. More specifically, the first branch of wall 210a is in line with the first branch of wall 210b. Preferably, the inner area of ​​wall 210a is at the surface of the inner area of ​​wall 210b, that is, the first branches of walls 210a and 210b are located between the second branches of walls 210a and 210b. In other words, the convex area defined by the U-shape of each of the two walls (i.e., the area located between the first branches) extends in the direction of the other wall 210.

[0057] The walls 210 a and 210 b are spaced apart from each other, ie they do not contact each other. The walls 210 a and 210 b are thus separated from each other by a portion of the semiconductor layers 200 and 202 .

[0058] The semiconductor region 208 is located inside the U-shape of the wall 210a, ie between the two first branches of the wall 210a. In other words, the region 208 is located in the convex region defined by the U-shape. Therefore, the region 208 is partially surrounded by the walls 210a and 201b.

[0059] The space between the ends of the first branches of walls 210 a and 210 b may allow passage of electrons in layers 200 and 202 to reach semiconductor region 208 .

[0060] However, the length of the first branch is preferably sufficient so that the first branch is located between the region 208 and the pad 204. In addition, the wall 210 is located between the region 208 and the electron collection region.

[0061] Wall 210 forms the gate of transistor 106 ( Figure 1 ). Wall 210 is coupled (preferably connected) to a node to which a control voltage VC is applied.

[0062] The region 208 is separated from the wall 210a by an insulating trench 212. The region 208 is preferably separated from the wall 210a only by the insulating trench 212. Thus, preferably no portion of the semiconductor layer 202 is present between the region 208 and the wall 210a.

[0063] The insulation trench 212 extends, for example, from the upper surface of the semiconductor layer 202 into the semiconductor layer 202. The insulation trench 212 is at least as deep as the region 208. The insulation trench 212 is preferably shallower than the wall 210.

[0064] During the aforementioned first step, the control voltage VC is a negative voltage, for example, less than or equal to -1 V. The contact pad 204 continuously or alternately receives the positive voltage VP. Therefore, the electrons formed in the photodiode 102 are attracted to the electron collection region.

[0065] During the second step, the control voltage VC is a positive voltage, for example, equal to the power supply voltage Vdd. In addition, the voltage VP is a negative voltage, for example, less than or equal to -0.5V. Therefore, the electrons are first attracted by the wall 210 and then by the semiconductor region 208. For this purpose, the electrons pass through the space between the walls 210a and 210b. The electrons are not attracted into the electron storage region and the number of stored electrons is not modified.

[0066] The interface between the wall 210 and the photodiode forms a volume. In practice, the wall 210 is located in the photodiode 102. Several surfaces (sides) of the wall 210 are in contact with the photodiode 102. In addition, the wall 210 is in contact with the inner part of the photodiode 102. This has the advantage of attracting electrons located in the lower part of the photodiode. In practice, it may have been chosen to form a semiconductor pad having a shape similar to that of the pad 204 and located on the upper surface of the photodiode 102. However, the electrons located in the lower part of the photodiode will have the risk of not being attracted by the wall 210 and of being attracted into the storage element.

[0067] As a variant, the wall 210b may not comprise a first branch. The wall 210b thus has the shape of a rectangular parallelepiped.

[0068] As a variant, the device 100 may include a single semiconductor wall surrounding the region 208, except for an opening, for example, on one side of the pad 204. For example, this wall corresponds to the wall 210, bringing into contact a plurality of first branches that are furthest from the pad 204 to form a single branch extending from one second branch to another second branch. However, there is a separation of the other first branches.

[0069] Figure 4 Another example of an electronic device 400 is schematically shown in a top view. The electronic device 400 includes a photodiode 102, which is similar to Figure 2 and the photodiode of the embodiment of FIG3. Figure 4 The cross-sectional view of plane BB is similar to that of FIG. Figure 3B The device 400 has Figure 1 The structure of the device 100 described in .

[0070] As mentioned above, the photodiode 102 includes a PN junction in a semiconductor substrate. The photodiode includes, for example, a P-type semiconductor layer 200 covered with an N-type semiconductor layer 202. The layers 200 and 202 are made of silicon, for example. The layer 202 also forms the source of the transistor 106 in contact with the cathode of the photodiode 102.

[0071] The device 400 comprises two contact pads 204, for example located on the upper surface of the photodiode 102. The pads 204 are located on the upper surface of the semiconductor layer 202, for example.

[0072] The contact pad 204 is, for example, coupled (preferably connected) to a node to which a control voltage is applied. For example, both pads are coupled to the same node to which the same control voltage is applied via a switch. The control voltage can cause electrons to move to the electron collection region. The control voltage is, for example, a positive voltage having a value equal to the power supply voltage.

[0073] The electron collection region is, for example, a semiconductor region adjacent to the photodiode 102. Each contact pad 204 is preferably opposite to a contact interface between the photodiode 102 and one of the electron collection regions. In addition to the contact interface, the photodiode 102 and the collection region are separated, for example, by an insulating wall or a semiconductor wall (not shown) that receives a negative voltage. As a variant, multiple pads 204 can be opposite to the same contact interface between the photodiode 102 and one electron collection region.

[0074] exist Figure 4 In the example, as in Figure 2 As in the example of Figure 3, Figure 2 Similar to the device 100 in Figure 3, the device 400 includes two pads 204, and thus, for example, two electron collecting regions. More generally, the device 400 may include at least one pad 204, and thus, at least one electron collecting region.

[0075] Figure 4 The device 400 is implemented before combining Figure 1 Describe the steps.

[0076] During the aforementioned first step, a positive voltage VP (e.g., a power supply voltage Vdd) is delivered to at least one of the pads 204 to attract electrons toward the pad 204 and thus toward the corresponding electron collection region. In the case where there are multiple pads 204, these pads receive positive voltages, for example, alternately, so that electrons are partially stored in each of the electron collection regions. This enables sampling of information obtained by the photodiode 102.

[0077] The connection pads 204 are, for example, surface elements, i.e., they are in contact with the surface of the photodiode 102, for example only with the upper surface of the semiconductor layer 202. For example, the connection pads 204 are in contact with the photodiode 102 only via a flat surface. For example, the contact pads 204 are semiconductor plates or layers made of, for example, metal, arranged on the photodiode 102.

[0078] The device 400 further comprises a semiconductor region 208 located in the photodiode 102. The region 208 is, for example, located in the semiconductor layer 202. In this example, the region 208 has the same doping type as the layer 202, for example, N-type doping. The region 208 is, for example, more heavily doped than the semiconductor layer 202. For example, the region 208 extends from the upper surface of the photodiode 102 (i.e., for example, from the upper surface of the layer 202) in the semiconductor layer 202. The region 208 preferably does not extend along the entire height of the semiconductor layer 202.

[0079] Region 208 is coupled (preferably connected) to a node to which power supply voltage Vdd is applied. Region 208 forms the drain of transistor 106 ( Figure 1 ).

[0080] Similar to the device 100, the device 400 includes a semiconductor wall 410. The device 400 includes two semiconductor walls 410 ( Figure 4 410a and 410b in FIG. 4 ). Wall 410 is made of, for example, an intrinsic semiconductor. Wall 210 is made of, for example, silicon. Wall 410 extends at least along the entire height of the photodiode (i.e., along the height of layers 200 and 202). Preferably, wall 410 extends along the entire height of the substrate in which the photodiode 102 is formed.

[0081] Unlike wall 210, Figure 4 Each of the walls 410 of the example has a substantially rectangular parallelepiped shape. Wall 410a and wall 410b are parallel to each other. For example, wall 410a and wall 410b have Figure 2 and the shapes and positions of the second branches of the wall 210a and the wall 210b of the embodiment of FIG. 3 .

[0082] The wall 410 a and the wall 410 b are spaced apart from each other, ie, they do not contact each other. Therefore, the wall 410 a and the wall 410 b are separated from each other by the region of the semiconductor layers 200 and 202 .

[0083] The semiconductor region 208 in the region of the semiconductor layer 202 is located between the wall 410a and the wall 410b. The region 208 is thus partially surrounded by the wall 410a and the wall 410b.

[0084] The space between the wall 410 a and the wall 410 b may allow passage of electrons in the layers 200 and 202 to reach the semiconductor region 208 .

[0085] Wall 410 forms the gate of transistor 106 ( Figure 1 ). Wall 410 is coupled (preferably connected) to a node to which a control voltage VC is applied.

[0086] The region 208 is separated from the wall 410a by an insulating trench 412. The region 208 is preferably separated from the wall 410a only by the insulating trench 412. Thus, preferably no portion of the semiconductor layer 202 is present between the region 208 and the wall 410a.

[0087] The insulation trench 412 extends, for example, from the upper surface of the semiconductor layer 202 into the semiconductor layer 202. The insulation trench 412 is at least as deep as the region 208. The insulation trench 212 is preferably shallower than the wall 410.

[0088] During the aforementioned first step, the control voltage VC is a negative voltage, for example, less than or equal to -1 V. The contact pad 204 continuously or alternately receives the positive voltage VP. Therefore, the electrons formed in the photodiode 102 are attracted to the electron collection region.

[0089] During the second step, the control voltage VC is a positive voltage, for example, equal to the supply voltage Vdd. In addition, the voltage VP is no longer supplied to the contact pad 204. Therefore, the electrons are first attracted by the wall 410 and then by the semiconductor region 208. For this purpose, the electrons pass between the wall 410a and the wall 410b. The electrons are not attracted into the electron storage region and the number of stored electrons is not modified.

[0090] The interface between the wall 410 and the photodiode forms a volume. In practice, the wall 410 is located in the photodiode 102. Several surfaces (sides) of the wall 410 are in contact with the photodiode 102. In addition, the wall 410 is in contact with the inner part of the photodiode 102. This has the advantage of attracting electrons located in the lower part of the photodiode. In practice, it may have been chosen to form a semiconductor pad having a shape similar to that of the pad 204 and located on the upper surface of the photodiode 102. However, the electrons located in the lower part of the photodiode will have the risk of not being attracted by the wall 210 and of being attracted into the storage element.

[0091] As a variant, the semiconductor wall may have a different shape by partially surrounding the semiconductor region 208. For example, the device 400 comprises a single wall 410a and no wall 410b.

[0092] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the described embodiments may be capable of operating in an equivalent manner for holes rather than electrons.

[0093] Furthermore, the photodiode may be different than described. For example, the photodiode may include a vertical PN junction, rather than a horizontal PN junction as in the described embodiments.

[0094] Furthermore, the doping types of the different elements described may be reversed.

[0095] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0096] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the disclosure.Accordingly, the foregoing description is by way of example only and is not intended to be limiting.

[0097] The various embodiments described above can be combined to provide further embodiments.

[0098] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic device, comprising: A photodiode, the photodiode comprising: a semiconductor region coupled to a node to which a first voltage is applied; and and a first semiconductor wall and a second semiconductor wall, the first semiconductor wall and the second semiconductor wall extending at least along a height of the photodiode, the first semiconductor wall and the second semiconductor wall partially surrounding the semiconductor region, wherein each of the first semiconductor wall and the second semiconductor wall is U-shaped, and the first semiconductor wall and the second semiconductor wall are spaced apart from each other. 2 . The device of claim 1 , comprising a semiconductor substrate, wherein the photodiode is formed in the semiconductor substrate, and the first semiconductor wall and the second semiconductor wall extend along the entire height of the semiconductor substrate. 3 . The device of claim 1 , wherein at least one of the first semiconductor wall and the second semiconductor wall is coupled to a node to which a second voltage is applied. 4 . The device of claim 1 , wherein the semiconductor region is located in a convex region defined by at least one of the first and second semiconductor walls that are U-shaped. 5 . The device of claim 1 , wherein each of the first and second semiconducting walls defines a respective convex region, and the convex regions extend toward each other. 6 . The device of claim 1 , comprising an insulating trench, wherein the semiconductor region is separated from the first semiconductor wall and the second semiconductor wall by the insulating trench.

7. The apparatus of claim 1, comprising a transistor having a source terminal and a drain terminal coupled between a cathode of the photodiode and the node to which the first voltage is applied.

8. The apparatus of claim 7, comprising a storage element coupled to the cathode of the photodiode.

9. The device of claim 8, wherein the storage element is an electron collecting region.

10. The apparatus of claim 1, comprising at least one connection pad on the photodiode and coupled to a node to which a positive voltage is applied.

11. A method comprising: applying a first voltage to a semiconductor region of a photodiode, the first voltage being a positive voltage, the photodiode comprising a first semiconductor wall and a second semiconductor wall, the first semiconductor wall and the second semiconductor wall extending at least along a height of the photodiode, the first semiconductor wall and the second semiconductor wall partially surrounding the semiconductor region, wherein each of the first semiconductor wall and the second semiconductor wall is U-shaped, and the first semiconductor wall and the second semiconductor wall are spaced apart from each other; applying a second voltage to the first semiconductor wall and the second semiconductor wall, wherein the second voltage is a negative voltage; as well as After applying the second voltage, a third voltage is applied to the first semiconductor wall and the second semiconductor wall, the third voltage being a positive voltage. The method according to claim 11 , wherein the second voltage is equal to or less than −1V. The method according to claim 11 , wherein the second voltage is applied simultaneously with the application of the first voltage. The method of claim 13 , wherein the first voltage is a power supply voltage.

15. An apparatus comprising: Photodiodes, including: a semiconductor region coupled to a node to which a first voltage is applied; a first semiconductor wall partially surrounding the semiconductor region, the first semiconductor wall having a first segment extending along a first direction and having a pair of second segments extending from opposite ends of the first segment along a second direction transverse to the first direction; and a second semiconductor wall having a third segment extending along the first direction and having a pair of fourth segments extending from opposite ends of the third segment along the second direction, wherein the fourth segment of the second semiconductor wall is spaced apart from the second segment of the first semiconductor wall and faces the second segment of the first semiconductor wall.

16. The apparatus of claim 15, further comprising a transistor electrically coupled between a cathode of the photodiode and the node to which the first voltage is applied.

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