SPAD type photoelectric detector

Abstract

The present invention relates to an SPAD-type photodetector, the SPAD-type photodetector comprising: an SPAD-type photodiode comprising, in a semiconductor substrate: a first doped region of a first conductivity type and a second doped region of a second conductivity type opposite to the first conductivity type to form a PN junction; and a quenching transistor including a channel of the second conductivity type in the substrate, a gate electrically isolated from the substrate by a dielectric layer, and a third doped region of the first conductivity type flush with an upper surface of the substrate. A dielectric layer is interposed between the gate and the first doped region, and a channel is defined by the first doped region and the third doped region.

Description

Technical Field

[0001] The field of the invention is a photodetector comprising at least one avalanche photodiode for detecting a single photon, also called a Single Photon Avalanche Diode (SPAD). The invention also relates to a photodetector comprising an array of SPAD photodiodes. Background Art

[0002] A SPAD photodiode is an extremely sensitive detector capable of detecting single photons. A SPAD photodiode is essentially made up of a PN junction in a semiconductor layer that is reverse polarized at a voltage greater than its avalanche threshold (also called breakdown voltage). This generates a very strong electric field inside the SPAD. The photogenerated carriers are then accelerated by the electric field at a sufficient speed to trigger the impact ionization phenomenon or avalanche phenomenon. As a result, a single photon is able to generate a measurable electrical signal within a very short response time.

[0003] Once a signal is detected, the avalanche must be interrupted and the SPAD photodiode recharged. To this end, a quenching circuit is usually used to control the avalanche phenomenon. The quenching circuit can be passive or active. Active circuits enable better avalanche control, but are bulkier than passive circuits.

[0004] The simplest quenching circuit consists of a resistor connected in series with the SPAD photodiode. During an avalanche, the current through the resistor increases rapidly, thereby strengthening the potential difference at the resistor terminals by applying Ohm's law, mechanically reducing the potential difference at the SPAD photodiode terminals. If the resistor has sufficient resistance, the electric field within the SPAD photodiode decreases until the avalanche is quenched. The SPAD photodiode then gradually recovers its initial polarization.

[0005] The resistor may be, for example, a 10 μm long weakly doped silicon rod arranged on the edge of the SPAD photodiode. Thus, the quenching circuit occupies a large surface area compared to the size of the SPAD photodiode, which is particularly detrimental in the case of a photodetector comprising an array of SPAD photodiodes. Furthermore, such a circuit does not allow for a precise control of the avalanche phenomenon.

[0006] In order to reduce the surface area of ​​the quenching circuit and improve avalanche control, resistors can be replaced by transistors. Patent application JP 2022-148028 proposes such a solution. Figure 8 of the document shows a pixel of a photodetector including a SPAD photodiode. The SPAD photodiode includes a PN junction in a substrate that defines an avalanche region. The avalanche region is located at a non-zero distance from the upper surface of the substrate. The pixel also includes a PMOS transistor to quench the avalanche and recharge the SPAD photodiode. Different types of doped wells isolate the PMOS transistor from the photodiode cathode. The drain of the PMOS transistor is connected to the photodiode cathode through a metal interconnect (Figures 8 and 10). The channel of the PMOS transistor extends along a plane parallel to the upper surface of the substrate.

[0007] Therefore, in this embodiment of the prior art, the quenching circuit occupies a considerable surface area, particularly due to the presence of the doped well and the arrangement of the channel of the PMOS transistor.Therefore, it is desirable to further reduce the surface area of ​​the quenching circuit. Summary of the invention

[0008] The object of the present invention is to at least partially remedy the disadvantages of the prior art, and more specifically to provide a photodetector comprising a SPAD type photodiode and a quenching circuit which is smaller in size than in the prior art.

[0009] To this end, the subject of the present invention is a photodetector comprising a SPAD type photodiode and a quenching transistor. The SPAD type photodiode comprises a first doped region of a first conductivity type in a semiconductor substrate and a second doped region of a second conductivity type opposite to the first conductivity type to form a PN junction. The quenching transistor comprises in the substrate: a channel of the second conductivity type; a gate electrically isolated from the substrate by a dielectric layer; and a third doped region of the first conductivity type and flush with the upper surface of the substrate. The photodetector is such that the dielectric layer is inserted between the gate and the first doped region, and the channel is defined by the first doped region and the third doped region.

[0010] Some preferred but non-limiting aspects of the photodetector are as follows.

[0011] The gate may extend in the substrate from an upper surface of the substrate, and the first doped region of the photodiode may be separated from the upper surface by a non-zero distance.

[0012] The photodiode may further include a fourth doped region of the second conductivity type, the fourth doped region being flush with the upper surface of the substrate.

[0013] The substrate may include a first doping layer and a second doping layer both of the second conductivity type, such that the doping atom concentration of the second doping layer is different from that of the first doping layer, the second doping region may extend in the first doping layer, and the channel may extend in the second doping layer.

[0014] The substrate may also include an upper doped layer of the second conductivity type, the doping atom concentration of the upper doped layer being strictly less than the doping atom concentration of the second doped layer, the upper doped layer being arranged so that the second doped layer can be inserted between the first doped layer and the upper doped layer, and the fourth doping region can extend in the upper doped layer.

[0015] The third doping region may include a second doping region and a first doping region of the first conductivity type, the photodetector may enable a doping atom concentration of the first doping region to be strictly greater than a doping atom concentration of the second doping region, and the first doping region may be included in the second doping region.

[0016] The dielectric layer and the first doped region 201 may define a plane substantially parallel to the upper surface, and the first doped region and the gate may extend on both sides of the plane.

[0017] The PN junction may be ellipsoidal in shape.

[0018] The gate may fill the groove of the substrate, and the first doped region may surround the groove.

[0019] The recess may include a shoulder, and the first doped region may conform to the shoulder.

[0020] The channel may face a portion of the dielectric layer having a thickness between 7 nm and 20 nm.

[0021] The quenching transistor may belong to a quenching circuit configured to apply a fixed polarization voltage V to the gate. G .

[0022] The first conductivity type may be N type, and the second conductivity type may be P type.

[0023] The photodetector may also include a readout circuit electrically connected to the anode of the photodiode.

[0024] The photodetector may be a back-illuminated photodiode.

[0025] The invention also relates to a method for manufacturing such a photodetector, the method optionally comprising one or more preferred features.

[0026] The manufacturing method comprises the following steps: producing a groove in a substrate; covering the groove with a dielectric layer; and filling the groove with a doped polycrystalline semiconductor material of a first conductivity type to obtain a gate electrically isolated from the substrate by the dielectric layer.

[0027] Generating the groove may include: performing a first etching on a first cavity from an upper surface of the substrate, the first cavity having a bottom and sidewalls, covering the bottom and the sidewalls with a protective layer, removing the protective layer on a portion of the bottom of the first cavity while maintaining the protective layer on the sidewalls, and performing a second selective etching on a second cavity from the bottom of the first cavity relative to the protective layer.

[0028] The method may further include a step of performing vapor phase doping atom diffusion doping between the step of generating the groove and the step of covering the groove with a dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other aspects, objects, advantages and features of the present invention will become more apparent on reading the following detailed description of a preferred embodiment of the present application, given as a non-limiting example and made with reference to the accompanying drawings, in which:

[0030] Figure 1 is a schematic cross-sectional view of a photodetector including a planar SPAD photodiode according to a first embodiment;

[0031] Figure 2 is a top view of the photodetector according to the first embodiment or the second embodiment;

[0032] Figure 3 is a schematic cross-sectional view of a photodetector including a pin-type SPAD photodiode according to a second embodiment;

[0033] Figure 4 is a circuit diagram of an electronic circuit including a SPAD photodiode according to the first embodiment or the second embodiment;

[0034] Figure 5 is a dynamic simulation of the triggering and stopping of the avalanche phenomenon in the photodetector according to the second embodiment. DETAILED DESCRIPTION

[0035] In the drawings and the rest of the specification, the same reference numerals represent the same or similar elements. In addition, the various elements are not shown to scale to improve the clarity of the drawings. In addition, different embodiments and modifications are not mutually exclusive and can be combined together. Unless otherwise specified, the terms "substantially", "about", "approximately" refer to within a range of 10%, preferably within a range of 5%. In addition, unless otherwise specified, the terms "contained between ... and ... " and similar expressions mean including boundaries.

[0036] "Based on" means that the material is a compound formed from at least the same elements as the semiconductor compound of interest.

[0037] Throughout the specification, when comparing the doping atom concentrations of two regions or two zones, the average concentrations in these regions are compared. Thus, when it is said that the doping atom concentration of region A is greater than the doping atom concentration of region B, this means that the average doping atom concentration within the volume of region A is greater than the average doping atom concentration within the volume of region B.

[0038] The present invention relates to a photodetector and a method for manufacturing such a photodetector. The photodetector comprises a SPAD type photodiode and a quenching transistor, the quenching transistor being used to quench the avalanche phenomenon in the SPAD photodiode. The transistor is of NMOS type or PMOS type. A co-doped region of a semiconductor substrate forms a cathode (respectively, an anode) of the SPAD photodiode and a source (respectively, a drain) of an NMOS (respectively, a PMOS) transistor. As a result, the surface area occupied by the SPAD photodiode and transistor components is reduced.

[0039] The co-doped region of the substrate may be buried, i.e., the co-doped region of the substrate is located at a non-zero distance from the upper surface of the substrate. In this case, the doped region flush with the upper surface of the substrate defines together with the co-doped region a transistor channel, which extends along a substantially vertical axis of the upper surface. Such a transistor is referred to as a vertical channel transistor. This arrangement enables a further reduction in the surface area occupied by the assembly consisting of the SPAD photodiode and the transistor.

[0040] The invention is particularly advantageous for photodetectors comprising an array of pixels extending in a detection plane, since the invention enables the size of the pixels to be reduced.

[0041] Particular embodiments will be described with reference to a photodetector comprising a SPAD type photodiode and a vertical channel transistor having a common substrate doping region. However, these embodiments may be applicable to avalanche photodiodes comprising any type, such as avalanche photodiodes having separate charging and / or acceleration and / or multiplication regions.

[0042] Figure 1 A photodetector 10 according to a first embodiment is schematically shown. The photodetector 10 comprises an array of pixels extending in a detection plane. For the sake of clarity and in order not to overcomplicate the drawing, the pixels are arranged along Figure 2 The cross section AA observation Figure 1 Half of a pixel is shown. Figure 2 The entire top view of the same pixel is schematically shown.

[0043] The photodetector 10 includes a photodiode 200 , a quenching transistor 100 , and an isolation trench 305 in a substrate 300 .

[0044] The substrate 300 includes an upper surface 300a and a lower surface 300b that are substantially flat and parallel to the detection plane. The substrate 300 is based on a semiconductor material and is P-doped here. The photodetector 10 includes a stack of insulating layers and conductive layers (not shown) (referred to as an interconnect stack), in which metal lines and contacts electrically connected to the photodiode 200 and the quenching transistor 100 may be formed. When the interconnect stack is arranged on one side of the illumination surface of the substrate, the photodetector 10 is referred to as a front side illumination (FSI) photodetector. When the interconnect stack is arranged on the side opposite to the illumination surface of the substrate, the photodetector 10 is referred to as a back side illumination (BSI) photodetector. The photodetector 10 of the first embodiment may be a BSI photodetector having an interconnect stack, which is arranged on one side of the upper surface 300a.

[0045] Herein and hereinafter in the specification, orthogonal three-dimensional direct marking (X, Y, Z) is defined, wherein the X-axis and the Y-axis form a plane parallel to the upper surface 300a of the substrate 300, the X-axis being oriented here parallel to the axis of the pixel array, and wherein the Z-axis is oriented substantially orthogonal to the upper surface 300a of the substrate 300 and is oriented from the lower surface 300b to the upper surface 300a. hereinafter in the specification, the terms "vertical" and "vertically" are understood to refer to an orientation substantially parallel to the Z-axis, and the terms "horizontal" and "horizontally" are understood to refer to an orientation substantially parallel to the plane (X, Y). Furthermore, the terms "lower" and "upper" are understood to refer to an increasing positioning when moving away from the substrate 300 in the +Z direction.

[0046] The photodiode 200 includes a first doped region 201 of a first conductivity type and a second doped region 202 of a second conductivity type opposite to the first conductivity type to produce a PN junction. The second doped region 202 surrounds the first doped region 201 in a half space defined by a plane substantially parallel to the upper surface 300a. In this example, the first doped region 201 is N-type and thus forms the cathode of the photodiode 200. Therefore, the second doped region 202 is P-type.

[0047] Preferably, the first doped region 201 and the second doped region 202 are ellipsoidal, or hemispherical in a half space, similar to a PN junction. This makes it possible to maximize the volume of the region of the substrate 300 in which photons can trigger an avalanche while minimizing the photodiode 200. This also makes it possible to limit untimely avalanches.

[0048] The photodiode 200 further comprises a fourth doped region 203 of the second conductivity type flush with the upper surface 300a of the substrate 300. The fourth doped region 203 occupies the peripheral area of ​​the pixel. The fourth doped region is here P-doped and defines the anode of the photodiode 200.

[0049] The quenching transistor 100 comprises a channel 102 in the substrate inserted between a first doped region 201 and a third doped region 103, the third doped region being of the first conductivity type and flush with the upper surface 300a of the substrate 300. The channel 102 has the same conductivity type as the substrate 300, thus being p-doped in this example. By the doping type chosen here, the third doped region 103 defines the drain of the transistor and the first doped region 201, i.e. the source of the transistor.

[0050] As shown here, the third doping region 103 can have a ring shape. The third doping region advantageously includes a first doping region 103a, and the doping atom concentration of the first doping region is strictly greater than the doping atom concentration of the second doping region 103b. The first doping region 103a is included in the second doping region 103b, that is, the second doping region 103b surrounds the first doping region 103a in a plane parallel to the upper surface 300a. The second doping region 103b is inserted between the first doping region 103a and the fourth doping region 203, so the electric field is reduced near the upper surface 300a, and untimely avalanches in this region can be avoided.

[0051] The quenching transistor 100 further comprises a gate 105 electrically isolated from the substrate by a dielectric layer 104. The gate 105 is flush with the upper surface 300a of the substrate 300, and in this example the gate has a substantially cylindrical shape with an axis parallel to the Z axis. The dielectric layer 104 together with the first doped region 201 defines a separation plane substantially parallel to the upper surface 300a of the substrate 300, i.e., there is an interface included in the plane between the dielectric layer 104 and the substantially flat first doped region 201. The first doped region 201 and the gate 105 extend mainly on both sides of the separation plane. In addition, along the direction of the separation plane, the size of the first doped region 201 is strictly greater than the size of the dielectric layer 104. The separation plane is, for example, the same as the plane defining the half space.

[0052] The dielectric layer 104 has a portion 104a facing the channel 102, hereinafter referred to as the gate oxide 104a. The gate 105 can be metallic or based on a semiconductor material. In the latter case, the gate is doped with a first conductivity type or a second conductivity type, in which case the gate 105 is of the first conductivity type. The gate may include a first doped region 105a flush with the upper surface 300a of the substrate 300. The portion not included in the first doped region 105a forms a second doped region 105b of the gate 105. The first doped region 105a and the second doped region 105b are of the same conductivity type, which may be the first conductivity type or the second conductivity type, in which case it is N-type. The gate oxide 104a of the channel 102 faces the second doped region 105b. In addition, the doping atom concentration of the first doped region 105a may be strictly greater than the doping atom concentration of the second doped region 105b.

[0053] The third doped region 103, the gate 105, the first doped region 201 and the second doped region 202 occupy the central area of ​​the pixel. A metal contact is arranged to contact the gate 105, the third doped region 103 and the fourth doped region 203, optionally through a passivation layer not shown to contact the gate 105, the third doped region 103 and the fourth doped region 203. The doping atom concentrations of the first doped region 103a of the drain 103, the first doped region 105a of the gate 105 and the anode 203 are selected to reduce the contact resistance.

[0054] Advantageously, the substrate 300 comprises a first doped layer 301 in contact with a second doped layer 302, both of which are of the second conductivity type. The second doped region 202 extends in the first doped layer 301, and the channel 102 extends in the second doped layer 302. The doping atom concentration of the second doped layer 302 may be different from (e.g., strictly less than) the doping atom concentration of the first doped layer 301. Thus, the resistivity of the channel 102 and the electric field in the photodiode 200 may be optimized independently of each other. Even more advantageously, the doping atom concentration of the first doped layer 301 gradually changes along the Z axis to attract photogenerated charges toward the second doped region 202.

[0055] In addition, advantageously, the substrate 300 comprises an upper doped layer 303 of the second conductivity type, in which the third doped region 103, the first doped region 103a and the second doped region 103b (when they exist) and the fourth doped region 203 extend. The upper layer 303 is weakly doped. For example, the doping atom concentration of the upper layer is strictly less than the doping atom concentration of the second doped layer 302. This makes it possible to reduce the electric field near the upper surface 300a, thereby avoiding any untimely avalanche that may occur in this area.

[0056] In this example, the first doped layer 301 and the second doped layer 302 are made of P-doped silicon. The doping atomic concentration of layer 301 is between 10 15 atoms / cm 3 Up to 10 18 atoms / cm 3 For example, 9×10 16 atoms / cm 3 The concentration of doping atoms in the second doping layer 302 is between 10 15 atoms / cm 3 Up to 10 18 atoms / cm 3 For example, 4×10 16 atoms / cm 3 The concentration of doping atoms in the upper doping layer 303 is between 10 14 atoms / cm 3 Up to 10 17 atoms / cm 3 Between, for example, equal to 10 15 atoms / cm 3 .

[0057] The thickness of the first doping layer 301 is, for example, between 1 μm and 15 μm. The thickness of the second doping layer 302 is between 500 nm and 5 μm, preferably between 1 μm and 4 μm. The thickness of the upper doping layer 303 is between 100 nm and 500 nm.

[0058] The concentration of doping atoms in the fourth doping region 203 is between 10 17 atoms / cm 3 Up to 5×10 20 atoms / cm 3 The concentration of doping atoms in the first doping region 201 is between 10 17 atoms / cm 3 Up to 5×10 20 atoms / cm 3 The concentration of doping atoms in the second doping region 202 is between 10 16 atoms / cm 3 Up to 10 20 atoms / cm 3 The concentration of doping atoms in the first doping region 103a is between 10 17 atoms / cm 3 Up to 5×10 20 atoms / cm 3 The concentration of doping atoms in 103b is between 10 16 atoms / cm 3 Up to 10 19 atoms / cm3 between.

[0059] The first doping region 105a and the second doping region 105b are made of polysilicon. The doping atomic concentration of the second doping region 105b is between 10 17 Up to 5×10 20 The concentration of doping atoms in the first doping region 105a is between 10 17 atoms / cm 3 Up to 5×10 20 atoms / cm 3 between.

[0060] The gate 105 has a cross section perpendicular to the Z axis, the diameter of which is between 100 nm and 1 μm, for example, equal to 600 nm. The thickness of the gate oxide 104a measured in a direction parallel to the upper surface 300a of the substrate 300 is between 2 nm and 100 nm, preferably between 2 nm and 20 nm, for example, equal to 7 nm. The length of the channel 102 measured in a direction parallel to the Z axis is between 500 nm and 5 μm, preferably between 1 μm and 4 μm, for example, equal to 1 μm.

[0061] The first doping layer 301 , the second doping layer 302 and the upper doping layer 303 are, for example, in-situ doped epitaxial layers.

[0062] The pixels are laterally separated from each other by isolation trenches or walls 305 extending vertically through the substrate 300, for example, along the entire thickness of the first doped layer 301. The isolation trenches 305 are, for example, capacitive isolation trenches, for example, of the capacitive deep trench isolation (CDTI) type, each isolation trench comprising a core or central wall made of a conductive material (e.g., doped polysilicon) and a side coating made of an electrically insulating material (e.g., silicon oxide). Alternatively, the isolation trenches 305 are isolation trenches completely filled with a dielectric material (e.g., silicon oxide), for example, deep trench isolation (DTI) type trenches. The isolation trenches 305 are, for example, formed from the upper surface 300a of the substrate 300.

[0063] Figure 3 A photodetector 20 according to a second embodiment is schematically shown. Figure 1 The same reasons for the disclosure, along Figure 2 The cross section AA observation Figure 3 Half of a pixel is shown. Figure 2This is also a schematic top view of a pixel of the second embodiment considered as a whole. Only the differences with respect to the first embodiment will be described here. The photodetector 20 of the second embodiment may be a BSI detector of an interconnect stack, the interconnect stack being arranged on the upper surface 300a of the substrate 300.

[0064] The substrate 300 accommodates a non-through groove. The first doped region 201 surrounds the groove in the lower part, that is, the groove has a bottom and a sidewall, and the first doped region 201 covers the lower part of the bottom and the sidewall. The groove extends in depth in the substrate 300, typically along a depth of several microns (e.g., between 5μm and 25μm). The groove is coated with a dielectric layer 104 and filled with a gate 105. Therefore, the gate 105 extends from the upper surface 300a of the substrate 300 to the bottom of the groove.

[0065] When the gate 105 is based on a semiconductor material, the gate may include a first doping region 105a of a first conductivity type or a second conductivity type (here, the first conductivity type), and the first doping region is flush with the upper surface 300a of the substrate 300. The portion not included in the first doping region 105a may include one or more different doping regions of the first conductivity type. For example, the gate oxide 104a may face the second doping region 105b. The first doping region 201 may face the second doping region 105b and / or the third doping region 105c not shown. The doping atom concentrations of the doping regions 105a, 105b, and 105c may be different, for example, the doping atom concentration of the first doping region 105a may be strictly greater than the doping atom concentration of the second doping region 105b (when the second doping region exists). The third doping region 105c may be a dielectric.

[0066] The groove may include a shoulder, that is, near a plane parallel to the upper surface 300a, the area of ​​the cross section of the groove parallel to the upper surface 300a increases rapidly in the direction +Z. In this case, the area of ​​the cross section of the first doped region 201 in the plane is strictly greater than the maximum area of ​​the cross section of the groove parallel to the upper surface 300a near the plane. Preferably, the first doped region 201 is in contact with the shoulder.

[0067] As shown here, the first doped region 201 and the second doped region 202 may be located on a doped lower layer 304 of the first conductivity type or the second conductivity type. The doped lower layer 304 has a lower doping atom concentration than the first doped region 201 and the second doped region 202. The second doped region 202 extends laterally from the first doped region 201 to the isolation trench 305.

[0068] Figure 4is an electrical diagram of an electronic circuit including the photodiode 200 according to the first embodiment or the second embodiment in the case where the first conductivity type is the N type and the second conductivity type is the P type.

[0069] The electronic circuit further includes a power supply circuit 401 , a quenching circuit 402 and a reading circuit 403 .

[0070] The quenching circuit 402 includes the quenching transistor 100 according to the first embodiment or the second embodiment. The quenching circuit is configured to G Applied to the gate 105 of the quenching transistor 100. Potential V G Here, it is a fixed potential. Alternatively, the potential V G can be variable, for example, following the drain current i of the quenching transistor 100 D In this case, the quenching circuit 402 can apply the first potential V within a few nanoseconds. G and the second potential V G , for a first potential, the channel of the quenching transistor 100 is opened during the avalanche, and for a second potential, the channel of the quenching transistor 100 is closed once the avalanche stops.

[0071] The power supply circuit 401 is configured to provide a fixed potential V D is applied to the drain of the quenching transistor 100. For its part, the source of the quenching transistor 100 is electrically connected to the cathode of the photodiode 200, which is consistent with the explanations given in conjunction with the first and second embodiments. The anode of the photodiode 200 is electrically connected to the potential source V A .

[0072] The reading circuit 403 is electrically connected to the anode of the photodiode 200. The reading circuit is intended to measure and / or detect the signal emitted by the photodiode 200 after the avalanche phenomenon is triggered. The reading circuit may comprise, for example, a capacitor or an inverter connected in series with a resistor.

[0073] For example, the anode of the photodiode 200 is electrically connected to ground; therefore, the potential V A Equal to 0V. Potential V G is fixed and is between 18.0V and 18.2V, for example, equal to 18.2V. Potential V D Greater than the breakdown voltage of the photodiode 200 , such as a breakdown voltage greater than 2V, such as equal to 18.6V.

[0074] Alternatively, the gate 105 of the quenching transistor 100 may be connected to ground so that V G Equal to 0V. Potential V D = -0.4V, potential V A Equal to -18.6V.

[0075] In the absence of photons, the quenching transistor 100 is locked. The cathode of the photodiode 200 and the source of the quenching transistor 100 (corresponding to the first doped region 201) are at V D Approaching potential V S The gate 105 is in the same voltage as V S Approaching potential V G , for example V G With V S The voltage difference is close to the threshold voltage of the quenching transistor 100, so the resistance of the channel 102 has a high value R i Then the potential difference V S -V A A strong internal electric field is generated within the photodiode 200. When an incident photon generates an electron-hole pair in the absorption region of the photodiode 200, the electron is accelerated by the internal electric field until it reaches a speed sufficient to trigger an avalanche phenomenon. As a result, the electron generates many other electrons, which are collected by the first doped region 201, thereby generating a drain current i D The resistance R of the channel 102 i High, potential V S Rapidly decreases. Therefore, the potential difference V S -V A decreases; the potential difference drops below the breakdown voltage and the avalanche stops. Then, V S The decrease in R causes the resistance of the channel 102 to decrease until the resistance of the channel reaches a low value R for recharging the photodiode 200. a , so that before triggering the avalanche, the potential V S and the resistance gradually increases to recover its initial value.

[0076] Using simulation tools known to those skilled in the art, such as Synopsys' TCAD Sentaurus simulator, the settings of the quenching transistor 100 can be adjusted to set a high value R of the resistance of the channel 102 i and low value R a , and thus control the avalanche in the photodiode 200. For example, the thickness of the gate oxide 104a, the length of the channel 102, and the doping atomic concentration of the channel 102 and the gate 105 can be adjusted.

[0077] Figure 5 is a dynamic simulation of the triggering and stopping of the avalanche phenomenon in the photodetector according to the second embodiment. Here, the configuration of the NMOS type quenching transistor 100 is selected to quench the avalanche in the photodiode 200. In particular, the thickness of the gate oxide 104a is equal to 7nm, the length of the channel 102 is equal to 1μm, the doping atomic concentration of the channel 102 is equal to 4×10 16 atoms / cm3 , and the doping atomic concentration of gate 105 is equal to 2×10 20 atoms / cm 3 .

[0078] Here, the drain current i in amperes is shown. D According to the change of time in nanoseconds (ns). The scale used is semi-logarithmic on the ordinate axis. For a gate potential V equal to 18.0 V G , curve A is obtained, for a potential V equal to 18.1V G Curve B is obtained, for a potential V equal to 18.2 V G Curve C is obtained, for a potential V equal to 18.3 V G Curve D is obtained. Curves A, B, and C show the quenching of the avalanche and the recharging of the photodiode 200. On curve D, the drain current i D There are a series of peaks, including quenching the channel 102 of the transistor 100, before settling at a high threshold (eg, a high threshold at which avalanche is sustained).

[0079] A manufacturing method which may be suitable for manufacturing the photodetector according to the first embodiment will now be described.

[0080] During a first step, the planar photodiode 200 is produced in a first doped epitaxial layer 301 using conventional method steps of the semiconductor industry, so that the first doped region 201 is flush with the upper surface of the first doped layer 301. In patent application FR3121282 A1 (cf. Figure 3 An example of such a sequence of method steps is disclosed in Figures 1 to 9 . The first doped layer 301 is based on P-doped silicon during epitaxial growth.

[0081] During a second step, a second doped layer 302 is epitaxially grown on the upper surface of the first doped layer 301. The second doped layer 302 is based on P-doped silicon during the epitaxial growth.

[0082] During a third step, an upper doped layer 303 is epitaxially grown on the face of the second doped layer 302 opposite to the first doped layer 301 to produce a stack of substrate 300. The stack comprises the first doped layer 301 and the second doped layer 302 as well as the upper doped layer 303. The substrate 300 has an upper surface 300a belonging to the upper doped layer 303. The upper doped layer 303 is based on P-doped silicon during epitaxial growth.

[0083] During the fourth step, a cylindrical groove, for example, is etched from the upper surface 300a of the substrate 300 to pass through the upper doped layer 303 and the second doped layer 302. The groove has a bottom substantially parallel to the upper surface 300a and a sidewall substantially perpendicular to the bottom. The bottom is in contact with the first doped region 201 and is completely included in the first doped region.

[0084] During a fifth step, a dielectric layer 104 is deposited in the groove in a uniform manner, for example by CVD or LPCVD, to cover the bottom and sidewalls of the groove. Alternatively, thermal oxidation can be used. On the sidewalls of the groove, the thickness of the dielectric layer 104 is between 2 nm and 100 nm, preferably between 2 nm and 20 nm, for example equal to 7 nm.

[0085] During a sixth step, the recess is filled with N-type doped polysilicon to produce the gate 105 of the quenching transistor 100 , wherein the source comprises the first doped region 201 .

[0086] During a seventh step, an isolation trench 305 is produced through the upper doped layer 303 , the second doped layer 302 and the first doped layer 301 .

[0087] The seventh step comprises implanting doping atoms to produce the first doping region 105a of the gate 105, the first doping region 103a and the second doping region 103b for producing the drain of the quenching transistor 100, and the fourth doping region 203 for producing the anode of the photodiode 200, all of which are flush with the upper surface 300a.

[0088] A manufacturing method which may be suitable for manufacturing the photodetector according to the second embodiment will now be described.

[0089] During a first step, a stack of three silicon layers is epitaxially grown. The stack comprises, in the following order, a first doped layer 301P, a second doped layer 302P, the concentration of doping atoms of the second doped layer being strictly less than that of the first doped layer 301, and an upper doped layer 303, the concentration of doping atoms of the upper doped layer being strictly less than that of the second doped layer 302. These three layers are based on silicon.

[0090] During the second step, a first cavity, for example cylindrical, is etched from the upper surface 300a of the stack to pass through at least a portion of the upper doped layer 303 and the second doped layer 302. The first cavity has a bottom substantially parallel to the upper surface 300a and sidewalls substantially perpendicular to the bottom.

[0091] During the third step, a protective layer is deposited in the first cavity in a consistent manner, for example by CVD or LPCVD, to cover the bottom and sidewalls of the first cavity. Alternatively, thermal oxidation may be used. The thickness of the protective layer is between 5 nm and 50 nm.

[0092] During a fourth step, a through opening is etched in the protection layer to reach the bottom of the first cavity while maintaining a non-zero thickness of the protection layer on the sidewalls of the first cavity.

[0093] The fifth step comprises selectively etching the first doped layer 301 with respect to the protective layer to obtain a second cavity in the first doped layer 301. The second cavity extends in depth in a portion of the first doped layer 301, typically along a depth of several microns (e.g., between 5 μm and 25 μm). The second cavity has a bottom substantially parallel to the upper surface 300a and a sidewall substantially perpendicular to the bottom. The first cavity and the second cavity form a groove comprising the stacked substrate 300.

[0094] The sixth step comprises vapour diffusion doping with doping atoms (for example phosphorus or arsenic) to obtain a first doped region 201 of N type surrounding the second cavity and preferably the lower part of the first cavity. The first doped region 201 is intended to be the cathode of the photodiode 200 .

[0095] During the seventh step, a dielectric coating is deposited in the first cavity and the second cavity in a consistent manner, for example by CVD or LPCVD, to cover the bottom and walls of the first cavity and the second cavity. Alternatively, thermal oxidation can be used to obtain the dielectric coating. The protective layer can be removed before this step. After this step, the groove is coated with a dielectric layer 104, and if the protective layer is a dielectric and is not removed, the dielectric layer includes a protective layer and a dielectric coating. Otherwise, the dielectric layer 104 is a dielectric coating. After this step, the dielectric layer 104 has a portion 104a facing the second doped layer 302, and the thickness of the portion is between 2nm and 100nm, preferably between 2nm and 20nm, for example, equal to 7nm.

[0096] During an eighth step, the recess is filled with N-type doped polysilicon to produce the gate 105 of the quenching transistor 100 , wherein the source comprises the first doped region 201 .

[0097] During a ninth step, an isolation trench 305 is produced through the upper doped layer 303 , the first doped layer 301 and the second doped layer 302 .

[0098] The tenth step includes implanting dopant atoms to produce the first doped region 105a of the gate 105, the first doped region 103a and the second doped region 103b for producing the drain of the quenching transistor 100, and the fourth doped region 203 for producing the anode of the photodiode 200, all of which are flush with the upper surface 300a.

[0099] A specific embodiment has just been described. Various modifications and variations will become apparent to those skilled in the art. In particular, all doping types may be varied. For N-type doping in silicon, phosphorus, arsenic, antimony or bismuth may be used, for example. For P-type doping in silicon, boron, aluminum, gallium or bismuth may be used, for example.

Claims

1. A photodetector (10, 20), comprising: A SPAD type photodiode (200), comprising a first doping region (201) of a first conductivity type and a second doping region (202) of a second conductivity type opposite to the first conductivity type in a semiconductor substrate (300) to form a PN junction; as well as A quenching transistor (100), comprising: in the substrate (300), a channel (102), the channel being of the second conductivity type; a gate (105), the gate being electrically isolated from the substrate (300) by a dielectric layer (104); and a third doped region (103), the third doped region being of the second conductivity type and being flush with the upper surface (300a) of the substrate (300); It is characterized in that The dielectric layer (104) is inserted between the gate (105) and the first doped region (201), The channel (102) is defined by the first doped region (201) and the third doped region (103).

2. The photodetector (10, 20) according to claim 1, wherein: The gate (105) extends from an upper surface (300a) of the substrate (300) in the substrate (300), and the first doped region (201) of the photodiode (200) is separated from the upper surface (300a) by a non-zero distance.

3. The photodetector (10, 20) according to claim 2, wherein: The photodiode (200) further comprises a fourth doped region (203) of the second conductivity type, wherein the fourth doped region is flush with the upper surface (300a) of the substrate (300).

4. The photodetector (10, 20) according to claim 2 or 3, wherein: The substrate (300) comprises a first doping layer (301) and a second doping layer (302), both of which are of the second conductivity type, such that the doping atom concentration of the second doping layer (302) is different from the doping atom concentration of the first doping layer (301), the second doping region (202) extends in the first doping layer (301), and the channel (102) extends in the second doping layer (302).

5. The photodetector (10, 20) according to claim 3 and 4, wherein: The substrate (300) further comprises an upper doped layer (303) of the second conductivity type, the doping atom concentration of the upper doped layer being strictly less than the doping atom concentration of the second doped layer (302), the upper doped layer being arranged such that the second doped layer (302) is inserted between the first doped layer (301) and the upper doped layer (303), and the fourth doped region (203) extends in the upper doped layer (303).

6. The photodetector (10, 20) according to claim 5, wherein: The third doping region (103) includes a second doping region (103b) of the first conductivity type and a first doping region (103a), and the photodetector is capable of making the doping atom concentration of the first doping region (103a) strictly greater than the doping atom concentration of the second doping region (103b), and the first doping region is contained in the second doping region (103b).

7. The photodetector (10) according to any one of claims 2 to 6, wherein: The dielectric layer (104) and the first doped region (201) define a plane substantially parallel to the upper surface (300a), and the first doped region (201) and the gate (105) extend on both sides of the plane.

8. The photodetector (10) according to claim 7, wherein: The PN junction is in an ellipsoidal shape.

9. The photodetector (20) according to any one of claims 2 to 6, wherein: The gate (105) fills a groove of the substrate (300), and the first doped region (201) surrounds the groove.

10. The photodetector (20) according to claim 9, wherein: The groove includes a shoulder, and the first doped region (201) fits the shoulder.

11. The photodetector (10, 20) according to any one of the preceding claims, wherein The channel (102) faces a portion (104a) of the dielectric layer (104) having a thickness between 7 nm and 20 nm.

12. The photodetector (10, 20) according to any one of the preceding claims, wherein: The quenching transistor (100) belongs to a quenching circuit (402) configured to apply a fixed polarization voltage V to the gate (105). G .

13. A photodetector according to any one of the preceding claims, wherein: The first conductivity type is N type, and the second conductivity type is P type.

14. The photodetector according to the preceding claim, further comprising a read-out circuit (403) electrically connected to the anode of the photodiode (200).

15. A back-illuminated photodetector (10, 20) according to any one of the preceding claims.

16. A method for manufacturing a photodetector according to any one of claims 1 to 15, the method comprising the steps of: creating a groove in the substrate (300), covering the groove with a dielectric layer (104), and The recess is filled with a doped polycrystalline material of a first conductivity type to obtain a gate (105) electrically isolated from the substrate (300) by the dielectric layer (104).

17. The manufacturing method according to claim 16, wherein: Generating the groove comprises: A first cavity is first etched from the upper surface (300a) of the substrate (300), wherein the first cavity has a bottom and a sidewall, Covering the bottom and the side walls with a protective layer, removing the protective layer on a portion of the bottom of the first cavity while maintaining the protective layer on the sidewalls, and performing a second selective etching on the second cavity from the bottom of the first cavity relative to the protective layer, The method further comprises: A step of gas phase doping atom diffusion doping is performed between the step of producing the groove and the step of covering the groove with the dielectric layer (104).

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