Semiconductor device including capacitor and method of manufacturing semiconductor device

Abstract

A semiconductor device including a capacitor and a method for manufacturing the semiconductor device are provided. The semiconductor device may include a capacitor, the capacitor including: a lower electrode; an upper electrode on the lower electrode; and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region contacting the dielectric layer, the doped region of the lower electrode being configured to increase the capacitance of the capacitor.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0037315 filed on March 29, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a capacitor. Background Art

[0003] The capacitor may include two electrodes and a dielectric layer between the two electrodes. The capacitance may be proportional to the area of ​​the capacitor and the dielectric constant of the dielectric layer. As the integration level of the semiconductor device increases, the area of ​​the capacitor in the semiconductor device decreases, and the capacitance of the capacitor also decreases. Therefore, forming a dielectric layer with a higher dielectric constant may help maintain the capacitance of the capacitor. Summary of the invention

[0004] The inventive concept provides a semiconductor device including a capacitor having high capacitance by providing a dielectric layer having a high dielectric constant.

[0005] According to some embodiments of the inventive concept, a semiconductor device may include a capacitor, the capacitor including: a lower electrode; an upper electrode on the lower electrode; and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region contacting the dielectric layer, and the doped region of the lower electrode is configured to increase the capacitance of the capacitor.

[0006] According to some embodiments of the inventive concept, a semiconductor device may include a capacitor, the capacitor including: a lower electrode; an upper electrode on the lower electrode; and a dielectric layer extending between the lower electrode and the upper electrode and extending on an upper surface and sidewalls of the lower electrode. The lower electrode may include an undoped region and a doped region, the doped region of the lower electrode may extend between the undoped region of the lower electrode and the upper surface of the lower electrode, and may extend between the undoped region of the lower electrode and the sidewalls of the lower electrode.

[0007] According to some embodiments of the inventive concept, a semiconductor device may include a capacitor, the capacitor including: a lower electrode; an upper electrode on the lower electrode; and a dielectric layer extending between the lower electrode and the upper electrode and extending on an upper surface and a sidewall of the lower electrode. The lower electrode may include an undoped region and a doped region, the doped region of the lower electrode may include a first portion extending between the undoped region of the lower electrode and the sidewall of the lower electrode and a second portion extending between the undoped region of the lower electrode and the lower surface of the lower electrode or between the undoped region of the lower electrode and the upper surface of the lower electrode.

[0008] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device may include forming a capacitor by performing an operation including the following steps: forming a lower electrode; forming a doped region in a surface portion of the lower electrode; forming a dielectric layer on the doped region; and forming an upper electrode on the dielectric layer.

[0009] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device may include forming a capacitor by performing an operation including the following steps: forming a molding layer; forming a hole extending through the molding layer; forming a first lower electrode layer in the hole; forming a source layer on the first lower electrode layer; moving dopants from the source layer to the first lower electrode layer; removing the source layer; forming a second lower electrode layer on the first lower electrode layer; removing the molding layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

[0010] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device may include forming a capacitor by performing an operation including the following steps: forming a molding layer; forming a hole extending through the molding layer; forming a source layer in the hole; forming a lower electrode on the source layer; forming a doped region in the lower electrode by moving dopants from the source layer to the lower electrode; removing the molding layer; removing at least a portion of the source layer; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.

[0011] According to some embodiments of the inventive concept, a semiconductor device may include a first capacitor, the first capacitor including: a lower electrode including a doped region, the doped region including a dopant including a chemical element; an upper electrode on the lower electrode; and a dielectric layer between the lower electrode and the upper electrode. The doped region of the lower electrode may contact the dielectric layer, a first capacitance of the first capacitor may be greater than a second capacitance of a second capacitor, wherein the second capacitor is the same as the first capacitor except that the second capacitor does not include the chemical element therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0014] Figure 2A is a cross-sectional view illustrating a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0015] Figure 2B yes Figure 2A An enlarged view of region A;

[0016] Figure 2Cyes Figure 2A An enlarged view of region A;

[0017] Figure 2D yes Figure 2A An enlarged view of region A;

[0018] Figure 3 is a cross-sectional view illustrating a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0019] Figure 4 is a cross-sectional view illustrating a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0020] FIG. 5A to FIG. 5E is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0021] FIG. 6A to FIG. 6J is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0022] 7A to 7J is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0023] FIG. 8A to FIG. 8J is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0024] Fig. 9 is a circuit diagram illustrating a semiconductor device including a capacitor according to some embodiments of the inventive concept;

[0025] Fig. 10A is a plan view showing a semiconductor device including a capacitor according to some embodiments of the inventive concept; and

[0026] Fig. 10B is along Fig. 10A A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0027] Figure 1 is a cross-sectional view illustrating a semiconductor device 100 including a capacitor according to some embodiments of the inventive concept.

[0028] Reference Figure 1 , the semiconductor device 100 including a capacitor according to some embodiments of the inventive concept may include a lower structure LS and a capacitor CA1 on the lower structure LS.

[0029] The lower structure LS may include, for example, a substrate. The lower structure LS may include, for example, a substrate on which a transistor is formed.

[0030] The capacitor CA1 may include a lower electrode 120, a dielectric layer 130 on the lower electrode 120, and an upper electrode 140 on the dielectric layer 130. That is, the capacitor CA1 may include the lower electrode 120, the upper electrode 140 facing the lower electrode 120, and the dielectric layer 130 therebetween.

[0031] The lower electrode 120 may include silicon, metal, metal compound, or a combination thereof. However, the inventive concept is not limited thereto. Figure 1 , the lower electrode 120 is shown as being flat. However, the shape of the lower electrode 120 is not limited thereto. In some embodiments, the lower electrode 120 may include a metal nitride, such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN) or molybdenum nitride (MoN). However, the inventive concept is not limited thereto. The lower electrode 120 may include a doped region 120a in contact with the dielectric layer 130. The doped region 120a may be the upper portion of the lower electrode 120. The doped region 120a of the lower electrode 120 may also include a dopant. The dopant may be, for example, niobium (Nb), vanadium (V), chromium (Cr), tantalum (Ta), molybdenum (Mo), tungsten (W), cobalt (Co), rhodium (Rh), iridium (Ir) or a combination of the above metals. However, the inventive concept is not limited thereto. In some embodiments, the doping concentration in the doped region 120a of the lower electrode 120 may decrease as the distance from the dielectric layer 130 increases. That is, the doping concentration in the doping region 120a of the lower electrode 120 may be the maximum (e.g., the highest) on the upper surface of the lower electrode 120 or adjacent to the upper surface of the lower electrode 120, and may decrease as the distance from the upper surface of the lower electrode 120 increases. In some embodiments, the thickness of the doping region 120a may be greater than 0 nm and not more than about 10 nm, for example, greater than 0 nm and not more than about 5 nm or greater than 0 nm and not more than about 2 nm. However, the inventive concept is not limited thereto. It will be understood that the term "doping concentration" may be interchangeable with "dopant concentration". It will also be understood that the "distance from element A" (or similar expressions) used herein may refer to the shortest distance from element A.

[0032] In some embodiments, the lower electrode 120 may further include a non-doped region 120b. The non-doped region 120b of the lower electrode 120 may not substantially include the dopant of the doped region 120a. For example, the non-doped region 120b of the lower electrode 120 may have a dopant concentration not exceeding 1% of the maximum dopant concentration of the doped region 120a of the lower electrode 120. For example, when the doping concentration in the lower electrode 120 decreases with increasing distance from the dielectric layer 130, the non-doped region 120b of the lower electrode 120 may have a dopant concentration not exceeding 1% of the doping concentration on the upper surface of the doped region 120a of the lower electrode 120 or adjacent to the upper surface of the doped region 120a of the lower electrode 120. For example, the lower electrode 120 may include: a first portion including a first surface (e.g., an upper surface) and having a first dopant concentration; and a second portion including a second surface (e.g., a lower surface) and having a second dopant concentration, and the second dopant concentration may be equal to or less than 1% of the first dopant concentration.

[0033] It will be understood that a "non-doped region" may refer to a region to which a dopant is not intentionally added, and may also be referred to as an "undoped region". It will also be understood that a portion of a non-doped region may be substantially free of the same chemical element as the dopant of a doped region, and may have a dopant concentration equal to or less than 1% of the highest dopant concentration of a doped region. In addition, it will be understood that a portion of a non-doped region may include chemical elements that originate from a doped region (e.g., diffused from a doped region).

[0034] The dielectric layer 130 may include, for example, a metal oxide. The dielectric layer 130 may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ) or a combination thereof. However, the inventive concept is not limited thereto.

[0035] The upper electrode 140 may include silicon, metal, metal compound, or a combination thereof. However, the inventive concept is not limited thereto. Figure 1 , the upper electrode 140 is shown to be flat. However, the shape of the upper electrode 140 is not limited thereto. In some embodiments, the upper electrode 140 may include a metal nitride such as TiN, WN, TaN, or MoN. However, the inventive concept is not limited thereto.

[0036] The capacitance of the capacitor CA1 may be greater than the capacitance of a capacitor in which the lower electrode 120 does not include the doped region 120a. For example, the dielectric layer 130 may have a dielectric constant greater than the dielectric constant of a dielectric layer under which the lower electrode 120 not including the doped region 120a is formed. This may be because the doped region 120a of the lower electrode 120 affects the crystalline phase of the dielectric layer 130 formed on the lower electrode 120. For example, this is because the doped region 120a of the lower electrode 120 affects the crystalline phase ratio in the dielectric layer 130 formed on the lower electrode 120.

[0037] In some embodiments, the doped region 120a of the lower electrode 120 may increase the capacitance of the capacitor CA1. The doped region 120a of the lower electrode 120 may increase the dielectric constant of the dielectric layer 130, thereby increasing the capacitance of the capacitor CA1. The doped region 120a of the lower electrode 120 may change the crystal phase ratio of the dielectric layer 130, thereby increasing the capacitance of the capacitor CA1.

[0038] It will be understood that the capacitance of capacitor CA1 can be greater than the capacitance of a second capacitor, which is the same as capacitor CA1 except that the second capacitor does not include a dopant (e.g., a chemical element) in its lower electrode. The second capacitor may include a lower electrode, a dielectric layer, and an upper electrode, each of the lower electrode, the dielectric layer, and the upper electrode including the same material as the material of the corresponding element of capacitor CA1 and having the same thickness as the thickness of the corresponding element of capacitor CA1. For example, the upper electrode of capacitor CA1 and the upper electrode of the second capacitor may include the same material and may have the same thickness. In some embodiments, the dielectric layer of capacitor CA1 may have a dielectric constant greater than the dielectric constant of the dielectric layer of the second capacitor. In some embodiments, the dielectric layer of capacitor CA1 may have a crystalline phase ratio different from the crystalline phase ratio of the dielectric layer of the second capacitor. For example, the first sample includes a lower electrode including Nb-doped TiN and a dielectric layer formed on the lower electrode including HfO 2 The second sample (reference) includes a lower electrode including TiN not doped with Nb and a dielectric layer including HfO formed on the lower electrode. 2 of the dielectric layer. That is, the lower electrode of the first sample includes a doped region, while the lower electrode of the second sample (reference) does not include the doped region. In this case, the dielectric layer of the first sample can be formed to have a crystallographic phase ratio that is different from the crystallographic phase ratio of the dielectric layer of the second sample. For example, the ratio of the tetragonal phase to the monoclinic phase of the dielectric layer of the first sample can be greater than the ratio of the tetragonal phase to the monoclinic phase of the dielectric layer of the second sample. Due to this difference in the crystallographic phase ratio, the dielectric layer of the first sample can have a dielectric constant greater than the dielectric constant of the dielectric layer of the second sample (reference).

[0039] As described above, the capacitor CA1 according to some embodiments of the inventive concept includes the doping region 120 a of the lower electrode 120 , and thus, the dielectric layer 130 having a larger dielectric constant may be obtained, and a larger capacitance may be obtained.

[0040] Figure 2A is a cross-sectional view illustrating a semiconductor device 200 including a capacitor according to some embodiments of the inventive concept. Figure 2B , Figure 2C and Figure 2D All are based on some embodiments of the invention concept Figure 2A Magnified view of area A.

[0041] Reference Figure 2A , a semiconductor device 200 including a capacitor according to some embodiments of the inventive concept may include a lower structure LS and a capacitor CA2 on the lower structure LS.

[0042] Capacitor CA2 may include a lower electrode 220, a dielectric layer 230 extending on (e.g., covering) an upper surface and sidewalls of the lower electrode 220, and an upper electrode 240 extending on (e.g., covering) the dielectric layer 230. It will be understood that "element A covers a surface of element B" (or similar expressions) means that element A is on the surface of element B, but does not necessarily mean that element A completely covers the surface of element B.

[0043] exist Figure 2A , the lower electrode 220 is shown as a cylindrical shape. However, the shape of the lower electrode 220 is not limited thereto. The lower electrode 220 may include a doped region 220a and a non-doped region 220b. The doped region 220a of the lower electrode 220 may be between the non-doped region 220b of the lower electrode 220 and the upper surface of the lower electrode 220 and between the non-doped region 220b of the lower electrode 220 and the sidewall of the lower electrode 220. In some embodiments, the doping concentration in the doped region 220a of the lower electrode 220 may decrease as the distance from the upper surface and the sidewall of the lower electrode 220 increases. That is, the doping concentration in the doped region 220a of the lower electrode 220 may be the largest on the upper surface and the sidewall of the lower electrode 220. In some embodiments, as Figure 2A As shown in FIG. 2 , the upper surface and sidewalls of the lower electrode 220 contact the dielectric layer 230 .

[0044] The capacitance of the capacitor CA2 may be greater than the capacitance of a capacitor in which the lower electrode 220 does not include the doped region 220a. For example, the dielectric layer 230 may have a dielectric constant greater than the dielectric constant of a dielectric layer under which the lower electrode 220 not including the doped region 220a is formed. This is because the doped region 220a of the lower electrode 220 affects the crystalline phase of the dielectric layer 230 formed on the lower electrode 220. For example, this is because the doped region 220a of the lower electrode 220 affects the crystalline phase ratio in the dielectric layer 230 formed on the lower electrode 220.

[0045] In some embodiments, the capacitor CA2 may further include at least one of the support layers 250a and 250b contacting the sidewall of the lower electrode 220. Figure 2A , capacitor CA2 is shown as including two support layers 250a and 250b. However, capacitor CA2 may include only one support layer or two or more support layers. Support layers 250a and 250b may support (e.g., structurally support) lower electrode 220. Support layers 250a and 250b may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto.

[0046] Reference Figure 2B In some embodiments, both the doped region 220a and the non-doped region 220b may contact the support layer 250a. Figure 2C In some embodiments, the doped region 220a contacts the support layer 250a, while the non-doped region 220b may not contact the support layer 250a. Figure 2D In some embodiments, the doped region 220 a does not contact the support layer 250 a , while the non-doped region 220 b may contact the support layer 250 a .

[0047] Figure 3 is a cross-sectional view illustrating a semiconductor device 300 including a capacitor according to some embodiments of the inventive concept.

[0048] Reference Figure 3 , a semiconductor device 300 including a capacitor according to some embodiments of the inventive concept may include a lower structure LS and a capacitor CA3 on the lower structure LS.

[0049] The capacitor CA3 may include a lower electrode 320 , a dielectric layer 330 covering an upper surface and sidewalls of the lower electrode 320 , and an upper electrode 340 covering the dielectric layer 330 .

[0050] The lower electrode 320 may include a doped region 320a and a non-doped region 320b. The doped region 320a of the lower electrode 320 may be between the non-doped region 320b of the lower electrode 320 and the sidewall of the lower electrode 320, and between the non-doped region 320b of the lower electrode 320 and the lower surface of the lower electrode 320. In some embodiments, the doping concentration in the doped region 320a of the lower electrode 320 may increase as the distance from the sidewall and the lower surface of the lower electrode 320 increases. That is, the doping concentration in the doped region 320a may be maximum at the interface between the adjacent doped region 320a and the non-doped region 320b.

[0051] The capacitance of the capacitor CA3 may be greater than the capacitance of a capacitor in which the lower electrode 320 does not include the doped region 320a. For example, the dielectric layer 330 may have a dielectric constant greater than the dielectric constant of a dielectric layer under which the lower electrode 320 not including the doped region 320a is formed. This is because the doped region 320a of the lower electrode 320 affects the crystalline phase of the dielectric layer 330 formed on the lower electrode 320. For example, this is because the doped region 320a of the lower electrode 320 affects the crystalline phase ratio in the dielectric layer 330 formed on the lower electrode 320.

[0052] In some embodiments, the capacitor CA3 may further include at least one of support layers 350a and 350b contacting the sidewall of the lower electrode 320. The support layers 350a and 350b contact the doped region 320a of the lower electrode 320 and may not contact the undoped region 320b of the lower electrode 320.

[0053] Figure 4 is a cross-sectional view illustrating a semiconductor device 400 including a capacitor according to some embodiments of the inventive concept.

[0054] Reference Figure 4 , a semiconductor device 400 including a capacitor according to some embodiments of the inventive concept may include a lower structure LS and a capacitor CA4 on the lower structure LS.

[0055] The capacitor CA4 may include a lower electrode 420 , a dielectric layer 430 covering an upper surface and sidewalls of the lower electrode 420 , and an upper electrode 440 covering the dielectric layer 430 .

[0056] The lower electrode 420 may include a doped region 420a and a non-doped region 420b. The doped region 420a of the lower electrode 420 may be between the non-doped region 420b of the lower electrode 420 and the sidewall of the lower electrode 420 and between the non-doped region 420b of the lower electrode 420 and the lower surface of the lower electrode. In some embodiments, the doping concentration in the doped region 420a of the lower electrode 420 may decrease as the distance from the sidewall and the lower surface of the lower electrode 420 increases. That is, the doping concentration in the doped region 420a may be the largest at the sidewall and the lower surface adjacent to the lower electrode 420.

[0057] The capacitance of the capacitor CA4 may be greater than the capacitance of a capacitor in which the lower electrode 420 does not include the doped region 420a. For example, the dielectric layer 430 may have a dielectric constant greater than the dielectric constant of a dielectric layer under which the lower electrode 420 not including the doped region 420a is formed. This is because the doped region 420a of the lower electrode 420 affects the crystalline phase of the dielectric layer 430 formed on the lower electrode 420. For example, this is because the doped region 420a of the lower electrode 420 affects the crystalline phase ratio in the dielectric layer 430 formed on the lower electrode 420.

[0058] In some embodiments, the capacitor CA4 may further include a first residual layer 460a contacting the lower surface of the lower electrode 420. The first residual layer 460a may include the same chemical element as the dopant of the doping region 420a of the lower electrode 420. The first residual layer 460a may include, for example, niobium nitride (NbN), vanadium nitride (VN), chromium nitride (CrN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten nitride (WN), cobalt nitride (CoN), rhodium nitride (RhN), iridium nitride (IrN), or a combination thereof.

[0059] In some embodiments, the capacitor CA4 may further include at least one of the supporting layers 450a and 450b supporting the lower electrode 420. In addition, the capacitor CA4 may further include a second residual layer 460b located between the sidewall of the lower electrode 420 and the supporting layers 450a and 450b. The second residual layer 460b may include the same chemical element as the dopant of the doping region 420a of the lower electrode 420. The second residual layer 460b may include, for example, NbN, VN, CrN, TaN, MoN, WN, CoN, RhN, IrN, or a combination thereof.

[0060] FIG. 5A to FIG. 5E is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept.

[0061] Reference Figure 5A, the lower electrode 120 may be formed on the lower structure LS. For example, to form the lower electrode 120, sputtering, evaporation, atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof may be used.

[0062] Reference Figure 5B , a source layer 160' may be formed on the lower electrode 120. To form the source layer 160', sputtering, evaporation, ALD, CVD, or a combination thereof may be used. The source layer 160' may include a dopant. For example, the source layer 160' may include, for example, NbN, VN, CrN, TaN, MoN, WN, CoN, RhN, IrN, or a combination thereof. However, the inventive concept is not limited thereto.

[0063] Reference Figure 5C , the doping region 120a can be formed in the surface portion of the lower electrode 120 by moving the dopant in the source layer 160' into the lower electrode 120. For example, the dopant in the source layer 160' can be diffused into the lower electrode 120 by increasing the temperature of the lower electrode 120 and the source layer 160'. 3 ) gas, nitrogen (N 2 The lower electrode 120 and the source layer 160' may be thermally treated in an argon (AR) gas, an argon (AR) gas, or a combination thereof. The lower electrode 120 and the source layer 160' may be thermally treated at a temperature of about 200°C to about 800°C (e.g., about 400°C to about 600°C).

[0064] Reference Figure 5C and Figure 5D , after forming the doping region 120a of the lower electrode 120, the source layer 160' may be removed. To remove the source layer 160', for example, dry etching or wet etching may be used.

[0065] Reference Figure 5E , a dielectric layer 130 is formed on the doped region 120a of the lower electrode 120. The dielectric layer 130 may be formed by, for example, ALD. The doped region 120a of the lower electrode 120 may affect the crystalline phase of the dielectric layer 130. Therefore, the dielectric layer 130 formed on the doped region 120a of the lower electrode 120 may have a higher dielectric constant than the dielectric layer in the case where the lower electrode 120 does not include the doped region 120a.

[0066] Return to reference Figure 1 , an upper electrode 140 may be formed on the dielectric layer 130. To form the upper electrode 140, sputtering, evaporation, ALD, CVD, or a combination thereof may be used.

[0067] Figure 1The semiconductor device 100 shown in FIG. 1 may be completely formed through the above-described processes. The capacitor CA1 included in the semiconductor device 100 may have the dielectric layer 130 having a larger dielectric constant, and thus may have a larger capacitance by including the doped region 120 a of the lower electrode 120 .

[0068] FIG. 6A to FIG. 6J is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept.

[0069] Reference Fig. 6A , a first mold layer MD1, a first supporting layer 250a, a second mold layer MD2, and a second supporting layer 250b are sequentially formed on the lower structure LS. The first mold layer MD1 and the second mold layer MD2 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto. The first supporting layer 250a and the second supporting layer 250b may include a material having an etching selectivity relative to the first mold layer MD1 and the second mold layer MD2. For example, the first mold layer MD1 and the second mold layer MD2 may include silicon oxide, and the first supporting layer 250a and the second supporting layer 250b may include silicon nitride. The first mold layer MD1 and the second mold layer MD2 may be formed by spin coating, sputtering, evaporation, CVD, or a combination thereof. The first supporting layer 250a and the second supporting layer 250b may be formed by sputtering, evaporation, CVD, ALD, or a combination thereof.

[0070] Reference Figure 6B A hole H may be formed through the first mold layer MD1, the first supporting layer 250a, the second mold layer MD2, and the second supporting layer 250b, and the hole H exposes the lower structure LS. For example, the second supporting layer 250b, the second mold layer MD2, the first supporting layer 250a, and the first mold layer MD1 may be sequentially etched by forming a mask pattern defining the hole H on the second supporting layer 250b and using the mask pattern as an etching mask.

[0071] Reference Figure 6C , a lower electrode 220 may be formed in the hole H. The lower electrode 220 may be formed to fill the hole H and cover the second supporting layer 250 b. In some embodiments, the lower electrode 220 may conformally cover the side surface and the bottom of the hole H without completely filling the hole H.

[0072] Reference Fig.6D , the lower electrode 220 on the second support layer 250b is removed by using etch-back or polishing. Therefore, only the lower electrode 220 in the hole H may remain.

[0073] Reference Fig.6D and Fig. 6E, the second supporting layer 250b may be patterned. The second supporting layer 250b may be etched by forming a mask pattern on the second supporting layer 250b and using the mask pattern as an etching mask. The patterned second supporting layer 250b may expose a portion of the second mold layer MD2. Next, the second mold layer MD2 may be removed. By removing the second mold layer MD2, an empty space ES may be formed between the first supporting layer 250a and the second supporting layer 250b. The sidewall on the upper portion of the lower electrode 220 and the upper surface of the first supporting layer 250a may be exposed in the empty space ES.

[0074] Reference Fig. 6E and Fig. 6F , the first supporting layer 250a may be patterned by etching the first supporting layer 250a using the mask pattern or the second supporting layer 250b as an etching mask. The patterned first supporting layer 250a may expose a portion of the first mold layer MD1. Next, the first mold layer MD1 may be removed. By removing the first mold layer MD1, an empty space ES may be formed between the lower structure LS and the first supporting layer 250a. The sidewall of the lower electrode 220 and the upper surface of the lower structure LS may be exposed in the empty space ES.

[0075] Reference Figure 6G , a source layer 260' may be formed on the upper surface and sidewalls of the lower electrode 220. The source layer 260' may also cover the upper surface of the lower structure LS, the upper and lower surfaces of the first support layer 250a, and the upper and lower surfaces of the second support layer 250b.

[0076] Reference Figure 6H , a doping region 220a may be formed on the surface of the lower electrode 220 by moving the dopant in the source layer 260' into the lower electrode 220. For example, the dopant in the source layer 260' may be diffused into the lower electrode 220 by increasing the temperature of the lower electrode 220 and the source layer 260'.

[0077] Reference Figure 6H and Fig.6I , after forming the doping region 220 a of the lower electrode 220 , the source layer 260 ′ may be removed.

[0078] Reference Figure 6J, a dielectric layer 230 may be formed on the upper surface and sidewalls of the lower electrode 220. The dielectric layer 230 may also cover the upper surface of the lower structure LS, the upper and lower surfaces of the first supporting layer 250a, and the upper and lower surfaces of the second supporting layer 250b. The doped region 220a of the lower electrode 220 may affect the crystalline phase of the dielectric layer 230. Therefore, the dielectric layer 230 formed on the doped region 220a of the lower electrode 220 may have a higher dielectric constant than the dielectric constant of the dielectric layer in the case where the lower electrode 220 does not include the doped region 220a.

[0079] Return to reference Figure 2A , an upper electrode 240 may be formed on the dielectric layer 230 . Figure 2A The semiconductor device 200 shown in FIG. 1 may be completely formed through the above-described processes. The capacitor CA2 included in the semiconductor device 200 may include the dielectric layer 230 having a large dielectric constant, and thus may have a large capacitance by including the doped region 220 a of the lower electrode 220 .

[0080] 7A to 7J is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept.

[0081] Reference Fig. 7A , a first molded layer MD1, a first supporting layer 350a, a second molded layer MD2 and a second supporting layer 350b are sequentially formed on the lower structure LS.

[0082] Reference Figure 7B , a hole H may be formed through the first mold layer MD1 , the first supporting layer 350 a , the second mold layer MD2 , and the second supporting layer 350 b , the hole H exposing the lower structure LS.

[0083] Reference Figure 7C , a first lower electrode layer 321 may be formed in the hole H. The first lower electrode layer 321 may conformally cover the side surface and the bottom of the hole H without completely filling the hole H. The first lower electrode layer 321 may also cover the second supporting layer 350 b.

[0084] Reference Fig.7D , a source layer 360' may be formed on the first lower electrode layer 321. Then, the dopant in the source layer 360' may move into the first lower electrode layer 321. For example, the dopant in the source layer 360' may be diffused into the first lower electrode layer 321 by increasing the temperatures of the source layer 360' and the first lower electrode layer 321.

[0085] Reference Fig.7D and Fig. 7E After the dopants in the source layer 360 ′ are moved into the first lower electrode layer 321 , the source layer 360 ′ may be removed.

[0086] Reference Figure 7F , a second lower electrode layer 322 may be formed on the first lower electrode layer 321. The second lower electrode layer 322 may include the same material as that of the first lower electrode layer 321.

[0087] Reference Figure 7F and Figure 7G , the portions of the first lower electrode layer 321 and the second lower electrode layer 322 covering the second supporting layer 350b may be removed. For example, etching back or polishing may be used. Thus, the lower electrode 320 may be completely formed. The remaining portion of the first lower electrode layer 321 may be referred to as the doped region 320a of the lower electrode 320, and the remaining portion of the second lower electrode layer 322 may be referred to as the non-doped region 320b of the lower electrode 320.

[0088] Reference Figure 7G and Figure 7H , the second supporting layer 350b may be patterned. The second supporting layer 350b may be etched by forming a mask pattern on the second supporting layer 350b and using the mask pattern as an etching mask. The patterned second supporting layer 350b may expose a portion of the second mold layer MD2. Next, the second mold layer MD2 may be removed. By removing the second mold layer MD2, an empty space ES may be formed between the first supporting layer 350a and the second supporting layer 350b. The sidewall on the upper portion of the lower electrode 320 and the upper surface of the first supporting layer 350a may be exposed in the empty space ES.

[0089] Reference Figure 7H and Fig.7I , the first supporting layer 350a may be patterned by etching the first supporting layer 350a using the mask pattern or the second supporting layer 350b as an etching mask. The patterned first supporting layer 350a may expose a portion of the first mold layer MD1. Next, the first mold layer MD1 may be removed. By removing the first mold layer MD1, an empty space ES may be formed between the lower structure LS and the first supporting layer 350a. The sidewall of the lower portion of the lower electrode 320 and the upper surface of the lower structure LS may be exposed in the empty space ES.

[0090] Reference Figure 7J, a dielectric layer 330 may be formed on the upper surface and sidewalls of the lower electrode 320. The dielectric layer 330 may also cover the upper surface of the lower structure LS, the upper and lower surfaces of the first supporting layer 350a, and the upper and lower surfaces of the second supporting layer 350b. The doped region 320a of the lower electrode 320 may affect the crystalline phase of the dielectric layer 330. Therefore, the dielectric layer 330 formed on the doped region 320a of the lower electrode 320 may have a higher dielectric constant than the dielectric constant of the dielectric layer in the case where the lower electrode 320 does not include the doped region 320a.

[0091] Return to reference Figure 3 , an upper electrode 340 may be formed on the dielectric layer 330 . Figure 3 The semiconductor device 300 shown in FIG. 3 may be completely formed through the above-described processes. The capacitor CA3 included in the semiconductor device 300 may include a dielectric layer 330 having a large dielectric constant, and thus may have a large capacitance by including the doped region 320 a of the lower electrode 320 .

[0092] FIG. 8A to FIG. 8J is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to some embodiments of the inventive concept.

[0093] Reference Fig. 8A , a first molded layer MD1, a first supporting layer 450a, a second molded layer MD2 and a second supporting layer 450b are sequentially formed on the lower structure LS.

[0094] Reference Figure 8B , a hole H may be formed through the first mold layer MD1 , the first supporting layer 450 a , the second mold layer MD2 , and the second supporting layer 450 b , the hole H exposing the lower structure LS.

[0095] Reference Figure 8C , a source layer 460 ′ may be formed in the hole H. The source layer 460 ′ may conformally cover the side surface and the bottom of the hole H without completely filling the hole H. The source layer 460 ′ may also cover the second supporting layer 450 b.

[0096] Reference Fig.8D , a lower electrode 420 may be formed on the source layer 460 ′.

[0097] Reference Fig. 8E , a doping region 420a may be formed on the surface of the lower electrode 420 by moving the dopant in the source layer 460' into the lower electrode 420. For example, the dopant in the source layer 460' may be diffused into the lower electrode 420 by increasing the temperature of the source layer 460' and the lower electrode 420.

[0098] Reference Fig.8F, the source layer 460' and the portion of the lower electrode 420 covering the second supporting layer 450b may be removed. For example, etch-back or polishing may be used.

[0099] Reference Fig.8F and Figure 8G , the second supporting layer 450b may be patterned. The second supporting layer 450b may be etched by forming a mask pattern on the second supporting layer 450b and using the mask pattern as an etching mask. The patterned second supporting layer 450b may expose a portion of the second mold layer MD2. Next, the second mold layer MD2 may be removed. By removing the second mold layer MD2, an empty space ES may be formed between the first supporting layer 450a and the second supporting layer 450b. A portion of the source layer 460' and the upper surface of the first supporting layer 450a may be exposed in the empty space ES.

[0100] Reference Figure 8G and Figure 8H , the first supporting layer 450a may be patterned by etching the first supporting layer 450a using the mask pattern or the second supporting layer 450b as an etching mask. The patterned first supporting layer 450a may expose a portion of the first mold layer MD1. Next, the first mold layer MD1 may be removed. By removing the first mold layer MD1, an empty space ES may be formed between the lower structure LS and the first supporting layer 450a. A portion of the source layer 460' and the upper surface of the lower structure LS may be exposed in the empty space ES.

[0101] Reference Figure 8H and Fig.8I , at least a portion of the source layer 460' may be removed. The remaining portion of the source layer 460' may remain as a first residual layer 460a and a second residual layer 460b. Figure 8G The process of removing the second mold layer MD2 shown in Figure 8H In the process of removing the first mold layer MD1 shown in FIG. 4 , at least a portion of the source layer 460 ′ is removed together with the first mold layer MD1 and the second mold layer MD2 .

[0102] Reference Figure 8J , a dielectric layer 430 may be formed on the upper surface and sidewalls of the lower electrode 420. The dielectric layer 430 may also cover the upper surface of the lower structure LS, the upper and lower surfaces of the first supporting layer 450a, and the upper and lower surfaces of the second supporting layer 450b. The doped region 420a of the lower electrode 420 may affect the crystalline phase of the dielectric layer 430. Therefore, the dielectric layer 430 formed on the doped region 420a of the lower electrode 420 may have a higher dielectric constant than the dielectric constant of the dielectric layer in the case where the lower electrode 420 does not include the doped region 420a.

[0103] Return to reference Figure 4 , an upper electrode 440 may be formed on the dielectric layer 430 . Figure 4 The semiconductor device 400 shown in FIG. 4 may be completely formed through the above-described processes. The capacitor CA4 included in the semiconductor device 400 may include a dielectric layer 430 having a large dielectric constant, and thus may have a large capacitance by including the doped region 420 a of the lower electrode 420 .

[0104] Fig. 9 is a circuit diagram illustrating a semiconductor device including a capacitor according to some embodiments of the inventive concept.

[0105] Reference Fig. 9 , the memory cell MC may be connected between the word line WL and the bit line BL. The memory cell MC may include a transistor TR and a capacitor CA. The memory cell MC may store data of 0 or 1 according to the presence of charge stored in the capacitor CA. The drain of the transistor TR may be connected to the bit line BL, the source of the transistor TR may be connected to the capacitor CA, and the gate of the transistor TR may be connected to the word line WL. The transistor TR may be configured to control a current flowing out of the capacitor CA and a current flowing to the capacitor CA. The capacitor CA may be Figures 1 to 4 One of the capacitors CA1 to CA4 shown in FIG.

[0106] Fig. 10A is a plan view illustrating a semiconductor device 1000 including a capacitor according to some embodiments of the inventive concept. Fig. 10B is along Fig. 10A A cross-sectional view taken along line II'.

[0107] Reference Fig. 10A and Fig. 10B In some embodiments, the semiconductor device 1000 may be a memory device such as a dynamic random access memory (DRAM). However, the inventive concept is not limited thereto. The semiconductor device 1000 may include a lower structure LS and a capacitor CA on the lower structure LS. Fig. 10B The capacitor CA is shown with Figure 2A The capacitor CA2 shown in FIG. 1 is the same as the capacitor CA2 shown in FIG. However, the capacitor CA may be Figures 1 to 4 The lower structure LS may include transistors, word lines WL, and bit lines BL.

[0108] An isolation layer 1020 defining a plurality of active regions ACT may be provided in the substrate 1010. The substrate 1010 may include a semiconductor material, such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or Si-Ge. The group III-V semiconductor material may include, for example, GaAs, InP, GaP, InAs, InSb, or InGaAs. The group II-VI semiconductor material may include, for example, ZnTe or CdS. The substrate 1010 may include a bulk wafer or an epitaxial layer. The isolation layer 1020 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto. In a plane, each active region ACT may have the form of an island having a major axis in a third direction D3.

[0109] A plurality of word lines WL may intersect with the active area ACT. A plurality of word lines WL may extend in the first direction D1. A plurality of word lines WL may be buried in the substrate 1010. Each word line WL may include a conductive material. Each word line WL may include, for example, polysilicon, a metal, a metal nitride, or a combination thereof. However, the inventive concept is not limited thereto. A gate insulating layer 1030 may be located between the word line WL and the active area ACT. The gate insulating layer 1030 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto. A word line capping layer 1040 may be located on the word line WL. The upper surface of the word line capping layer 1040 may be coplanar with the upper surface of the substrate 1010. The word line capping layer 1040 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto.

[0110] The first source / drain region SD1 may be located in the center of each active region ACT, and a pair of second source / drain regions SD2 may be located at both ends of each active region ACT. The first source / drain region SD1 may be between a pair of word lines WL, and the pair of second source / drain regions SD2 may be separated from each other by a pair of word lines WL.

[0111] The first interlayer insulating layer 1050 may be located on the substrate 1010. The first interlayer insulating layer 1050 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto.

[0112] A plurality of bit lines BL may be located on the first interlayer insulating layer 1050. Each of the plurality of bit lines BL may extend in the second direction D2. Each bit line BL may include, for example, polysilicon, metal, metal nitride, metal-semiconductor mixture, or a combination thereof. However, the inventive concept is not limited thereto. The bit line BL may be connected to the first source / drain region SD1 through a bit line contact BLC passing through the first interlayer insulating layer 1050. The bit line contact BLC may include, for example, polysilicon, metal, metal nitride, metal-semiconductor mixture, or a combination thereof. However, the inventive concept is not limited thereto. The bit line capping layer 1070 may be located on the bit line BL. The bit line capping layer 1070 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto.

[0113] The second interlayer insulating layer 1060 may be disposed on the first interlayer insulating layer 1050. The second interlayer insulating layer 1060 may cover the bit line BL and the bit line capping layer 1070. The second interlayer insulating layer 1060 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the inventive concept is not limited thereto.

[0114] The capacitor CA may be positioned on the second interlayer insulating layer 1060. The capacitor CA may be connected to the second source / drain region SD2 through a capacitor contact CC passing through the second interlayer insulating layer 1060 and the first interlayer insulating layer 1050.

[0115] While the inventive concepts have been particularly shown and described with reference to example embodiments of the inventive concepts, it will be understood that various changes in form and details may be made therein without departing from the spirit of the inventive concepts and the scope of the appended claims.

Claims

1. A semiconductor device, comprising a capacitor, wherein the capacitor comprises: Lower electrode; an upper electrode, on the lower electrode; as well as a dielectric layer extending between the lower electrode and the upper electrode, wherein the lower electrode includes a doped region contacting the dielectric layer, and The doped region of the lower electrode is configured to increase the capacitance of the capacitor. The doped region of the lower electrode is configured to increase the dielectric constant of the dielectric layer.

2. The semiconductor device according to claim 1, wherein The doped region of the lower electrode is configured to change a crystalline phase ratio of the dielectric layer.

3. The semiconductor device according to claim 1, wherein The doped region of the bottom electrode includes a niobium dopant.

4. The semiconductor device according to claim 1, wherein The dopant concentration in the doped region of the lower electrode decreases as the distance from the dielectric layer increases.

5. The semiconductor device according to claim 1, in, The doped region of the lower electrode includes a first surface contacting the dielectric layer, and the lower electrode also includes a second surface opposite to the first surface, and The lower electrode includes: a first portion including a first surface and having a first dopant concentration; and a second portion including a second surface and having a second dopant concentration, and the second dopant concentration is equal to or less than 1% of the first dopant concentration.

6. A semiconductor device, comprising a capacitor, wherein the capacitor comprises: Lower electrode; an upper electrode, on the lower electrode; as well as a dielectric layer extending between the lower electrode and the upper electrode and extending on an upper surface and sidewalls of the lower electrode, The lower electrode includes an undoped region and a doped region, and wherein the doped region of the lower electrode extends between the undoped region of the lower electrode and the upper surface of the lower electrode, and extends between the undoped region of the lower electrode and the sidewall of the lower electrode, The doped region of the lower electrode is configured to increase the dielectric constant of the dielectric layer.

7. The semiconductor device according to claim 6, wherein: The dopant concentration in the doping region of the lower electrode decreases with increasing first distance from the upper surface of the lower electrode and second distance from the sidewall of the lower electrode.

8. The semiconductor device according to claim 6, further comprising a support layer contacting a side wall of the lower electrode, in, The supporting layer contacts the doped region and the undoped region of the lower electrode.

9. The semiconductor device according to claim 6, further comprising a support layer contacting a side wall of the lower electrode, in, The supporting layer contacts the doped region of the lower electrode and does not contact the undoped region of the lower electrode.

10. The semiconductor device according to claim 6, further comprising a support layer contacting a side wall of the lower electrode, in, The support layer contacts the undoped region of the lower electrode and does not contact the doped region of the lower electrode.

11. A semiconductor device, comprising a capacitor, wherein the capacitor comprises: Lower electrode; an upper electrode, on the lower electrode; as well as a dielectric layer extending between the lower electrode and the upper electrode and extending on an upper surface and sidewalls of the lower electrode, The lower electrode includes an undoped region and a doped region, and The doped region of the lower electrode includes a first portion extending between the undoped region of the lower electrode and the sidewall of the lower electrode and a second portion extending between the undoped region of the lower electrode and the lower surface of the lower electrode. The doped region of the lower electrode is configured to increase the dielectric constant of the dielectric layer.

12. The semiconductor device according to claim 11, wherein The dopant concentration in the doping region of the lower electrode decreases with increasing first distance from the sidewall of the lower electrode and decreases with increasing second distance from the lower surface of the lower electrode.

13. The semiconductor device according to claim 11, in, The dopant concentration in the doping region of the lower electrode increases with increasing first distance from the sidewall of the lower electrode and second distance from the lower surface of the lower electrode.

14. The semiconductor device according to claim 11, further comprising a support layer contacting a side wall of the lower electrode, in, The supporting layer contacts the doped region of the lower electrode and does not contact the undoped region of the lower electrode. 15 . The semiconductor device according to claim 11 , further comprising a first residual layer contacting a lower surface of the lower electrode.

16. The semiconductor device according to claim 15, wherein: Dopants of the first residual layer and the doping region of the lower electrode include the same chemical element.

17. The semiconductor device according to claim 16, wherein: The first residual layer includes niobium nitride.

18. The semiconductor device according to claim 11, further comprising: a support layer configured to support the lower electrode; as well as A second residual layer is between the side wall of the lower electrode and the supporting layer.

19. The semiconductor device according to claim 18, wherein: The dopant of the second residual layer and the doping region of the lower electrode includes the same chemical element.

20. The semiconductor device according to claim 19, wherein The second residual layer includes niobium nitride.

21. A method of manufacturing a semiconductor device, the method comprising forming a capacitor by performing an operation comprising the steps of: forming a lower electrode; forming a doped region in a surface portion of the lower electrode; forming a dielectric layer on the doped region; and forming an upper electrode on the dielectric layer, The doped region is configured to increase the dielectric constant of the dielectric layer.

22. The method according to claim 21, wherein: The steps of forming the doped region include: forming a source layer on the lower electrode; causing dopants to move from the source layer into the lower electrode; and Remove the source layer.

23. The method according to claim 22, wherein: The step of moving the dopant from the source layer into the lower electrode includes increasing the temperature of the source layer and the lower electrode.

24. The method according to claim 22, wherein: The source layer includes niobium nitride.

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