A method for forming a semiconductor device

Abstract

According to one aspect of the inventive concept, there is provided a method for forming a semiconductor device comprising vertical channel field effect transistor (FET) devices, the method comprising: forming a plurality of semiconductor structures projecting vertically from a lower source / drain semiconductor layer of a substrate, the semiconductor structures being arranged in an array having a plurality of rows and columns; etching metal line trenches parallel to the rows at least between a subset of the rows; forming metal lines in the metal line trenches to contact the lower source / drain layer; forming gate structures surrounding channel portions of the semiconductor structures located above the lower source / drain layer; and forming upper source / drain metal contacts on upper source / drain portions of the semiconductor structures located above the channel portions.

Description

TECHNICAL FIELD

[0001] The present inventive concept relates to a method for forming a semiconductor device. BACKGROUND

[0002] To provide circuit designs that are more power efficient and area efficient, new transistor devices are being developed. One type of non-planar field effect transistor (FET) device is a vertical channel FET device.

[0003] A vertical channel FET device (also referred to as a VFET device) includes a vertical nanowire or nanosheet FET (vertical NWFET or NSFET) having a channel portion at least partially, or preferably completely, surrounding a vertically oriented nanowire or nanosheet semiconductor structure.

[0004] Due to its vertically oriented channel structure, the gate length of a VFET device is influenced by the line width, rather than the vertical dimension or thickness of the gate electrode. Secondly, the source and drain portions of a vertical transistor device are vertically displaced from one another. For these reasons, VFET devices are implemented in dense and area efficient arrays.

[0005] To form functional circuits, it is necessary to contact the source / drain of the devices. However, due to the vertically oriented channel structure and the vertical displacement of the source and drain, contacting the lower source (or, as the case can be, drain) can be more challenging than contacting a horizontal channel device. Typically, for VFETs, the contact relies on providing a metal via connection that is dispersed in the VFET array for contacting each source / drain. To allow for a low resistance connection, the via needs to have a certain minimum cross section, which can be challenging to accommodate in a dense array. SUMMARY

[0006] It is an object of the present inventive concept to provide a method that allows for a low resistance lower source / drain connection even in a dense VFET array. Other and alternative objects can become apparent from the following.

[0007] According to one aspect of the present inventive concept, there is provided a method for forming a semiconductor device comprising vertical channel field effect transistor (FET) devices, the method comprising:

[0008] forming a plurality of semiconductor structures on a substrate protruding vertically from a lower source / drain semiconductor layer of the substrate, the semiconductor structures being arranged in an array having a plurality of rows and columns;

[0009] etching metal line trenches parallel to the rows at least between a subset of the rows;

[0010] forming metal lines in the metal line trenches to contact the lower source / drain layer;

[0011] forming a gate structure surrounding a channel portion of the semiconductor structure overlying the lower source / drain layer; and

[0012] forming an upper source / drain metal contact on an upper source / drain portion of the semiconductor structure overlying the channel portion.

[0013] According to the inventive method, the lower source / drain of the VFETs in the array can be contacted by horizontally extending metal lines that pass through the VFET array, parallel to and between rows of the array. Each metal line can be formed in a metal line trench etched in the substrate.

[0014] The resistance of the source / drain connection can be adjusted accordingly via the vertical dimension (i.e. height) of the metal line. That is, a higher line height increases the cross-sectional area of the metal line, thereby reducing the resistance.

[0015] Another advantage is that VFETs arranged along the same row can be connected with the same metal line. Furthermore, VFETs arranged along a pair of adjacent rows can be connected with a common metal line formed therebetween. This further supports the goal of allowing the use of an area-efficient VFET array as compared to providing multiple individual vertical vias along each row. Each metal line trench can advantageously extend across multiple columns of the array.

[0016] It can be appreciated that the metal lines can be connected to back-end-of-line (BEOL) interconnect structures of the line at several selected locations, e.g. at the edges or outer sides of the array, accordingly.

[0017] Accordingly, a vertical channel FET device refers to a device comprising a semiconductor structure comprising an upper source / drain portion and a lower source / drain portion and a channel portion in between and vertically extending therebetween, and further comprising a gate structure vertically extending along the channel portion. The gate structure can at least partially surround the channel portion. In particular, the gate structure can encircle the channel portion, in other words, form a gate-all-around (GAA) structure. The lower source / drain portion and the upper source / drain portion and the channel portion intersect a common vertical plane. The channel portion is adapted to conduct vertically oriented charge carriers between the source / drain (in use of the device).

[0018] As used herein, the term "vertical" denotes a direction or orientation (e.g., surface, dimension, or other feature) that is parallel to the normal of the substrate (i.e., the main extension plane or its main / superior surface). At the same time, the term "horizontal" refers to a direction or orientation that is parallel to the substrate (i.e., the main extension plane or its main surface) or, equivalently, transverse to the vertical direction. At the same time, terms such as "above", "upper", "top" and "below", "lower", "bottom" refer to relative positions as viewed along the vertical direction, and thus do not imply absolute orientation of the substrate or device.

[0019] According to the inventive method, the semiconductor structures are arranged in an array having a plurality of (horizontal) rows and (horizontal) columns. In other words, the method comprises forming an array of rows and columns of semiconductor structures. Each semiconductor structure can be arranged at the intersection of a row and a column of the array, respectively.

[0020] The rows can extend along the substrate in a first horizontal direction (i.e., the "row direction"). The columns can extend along the substrate in a second horizontal direction (i.e., the "column direction"). The row direction and the column direction can be transverse to each other. The rows can be equally spaced apart as viewed from the column direction. The columns can be equally spaced apart as viewed from the row direction.

[0021] The metal line trenches can be formed between each row of the array, or only between a subset (i.e., an exact subset) of the rows of the array. Each metal line trench can be formed between a respective pair of adjacent rows. For example, a first metal line trench can be formed between a first pair of adjacent rows, and a second metal line trench can be formed between a second pair of adjacent rows, etc.

[0022] The method can further comprise forming an insulating spacer layer on the semiconductor structure sidewalls along the at least one subset of rows prior to forming the metal lines.

[0023] The insulating spacer can be formed on the sidewalls of the semiconductor structures arranged along the at least one subset of rows, respectively.

[0024] The spacer layer on the semiconductor structure sidewalls can enable at least a minimum amount of electrical isolation between the metal lines and the semiconductor structures (e.g., including base portions of the semiconductor structures).

[0025] Another advantage is that the height of the metal lines can be increased, thereby exceeding the depth of the metal line trenches, without risk of short-circuiting between the semiconductor structure (particularly, base portions thereof) sidewalls and the metal lines.

[0026] The spacer layer can be formed preferably prior to forming the metal line trenches. Thereby, the spacer layer can mask the sidewalls prior to formation of the metal line trenches. Thus, the sidewalls of the semiconductor structures can be masked from the processing steps used during formation of the metal line trenches, e.g., etching of the semiconductor material of the lower source / drain layers.

[0027] The method can further comprise:

[0028] forming a cover layer embedding the semiconductor structures and covering the lower source / drain layer; and

[0029] forming a trench in the cover layer, the trench extending through the cover layer between the at least one subset of rows;

[0030] wherein the metal line trenches are formed by etching the lower source / drain layer via the trench in the cover layer.

[0031] Thus, the cover layer can mask the portion of the lower source / drain layer between any rows for which a metal line trench is not to be formed during the metal line trench formation. The cover layer can also cover the portion of the lower source / drain layer extending between semiconductor structures of the same row during the metal line trench formation. The cover layer can be an insulating layer, e.g. an oxide layer or a dielectric layer. Thus, the cover layer can still serve as an insulating layer in subsequent processing steps and in the final device.

[0032] The trench can be formed in the cover layer to expose sidewalls of the semiconductor structures arranged along the at least one row, wherein the method can further comprise forming an insulating spacer layer on the sidewalls of the semiconductor structures exposed in the cover layer trench.

[0033] In line with the above discussion, the spacer layer can thus provide electrical isolation between the metal lines and the exposed semiconductor structure sidewalls. Thereby, the spacer layer can also mask the sidewalls during the (semiconductor material) etching of the metal line trenches.

[0034] Alternatively, the method can further comprise, prior to forming the cover layer, depositing a conformal layer covering the semiconductor structures and the lower source / drain layer. The trench in the cover layer is formed by etching the cover layer relative to the conformal layer after forming the cover layer. That is, by depositing a conformal layer of a material different from the material of the cover layer allows forming the trench in the cover layer without exposing the sidewalls of the semiconductor structures. The conformal layer formed on the lower source / drain layer can be removed prior to or after forming the cover layer by a conformal anisotropic etch. The conformal layer is thus removed selectively from the lower source / drain layer and remains as a spacer layer on the sidewalls of the semiconductor structures. At least, the conformal layer on the lower source / drain layer can be removed prior to etching the metal line trenches.

[0035] The metal lines can be formed with a height greater than the depth of the metal line trenches. Thus, the electrical resistance of the metal lines can be reduced. This is preferably combined with forming an insulating spacer layer on the semiconductor structure sidewalls to reduce the risk of short circuits.

[0036] Forming the metal line can include depositing metal line material in the metal line trench, and etching back the deposited metal line material to a level below the channel portion. Thus, an upper surface of the metal line can be etched back to a level below the channel portion. Thus, vertical space can be created to form a gate structure along the channel portion.

[0037] The method can further include covering the metal line with an insulating layer, wherein the gate structure can be formed on the insulating layer. Thus, the metal line and the gate structure can be electrically insulated from each other.

[0038] Each upper source / drain contact can be formed on at least two semiconductor structure source / drain portions of two consecutive rows. This can result in a multi-channel VFET device. That is, the channels of the consecutive rows of semiconductor structures can be connected between a common metal line (formed in contact with the lower source / drain layer portions) and a common upper source / drain metal contact.

[0039] Each upper source / drain metal contact can extend on and across at least one of the metal lines. Thus, the metal lines can be provided in the vicinity of the base of the consecutive semiconductor structures. This can reduce the series resistance of each multi-channel VFET device.

[0040] The method can further include, before or after forming the metal lines (and the metal line trenches), forming trenches in the lower source / drain layer between the plurality of rows of the array, filling the trenches with an insulating material, thereby dividing the lower source / drain layer into a plurality of lower source / drain layer portions, wherein at least one metal line trench and metal line are formed on each lower source / drain layer portion. Thus, individual "islands" of lower source / drain layer portions (also referred to in the art as "bottom electrode regions") can be defined. By contacting each lower source / drain layer portion with at least one metal line, the lower source / drain of the VFET of each "island" can be reached via a lower resistance contact. It can be preferred to form these insulating filled trenches to extend completely through the lower source / drain layer and to the underlying substrate layer. This can improve the degree or electrical isolation between the lower source / drain layer portions.

[0041] In particular, the metal line trenches and metal lines are formed between each row of semiconductor structures supported by each lower source / drain portion. Each lower source / drain portion can accordingly be reached in a parallel fashion by more than one metal line. This allows for a further reduction of the device series resistance.

[0042] The etching of the metal line trench can include etching the lower source / drain layer, wherein the metal line is formed in the metal line trench of the lower source / drain layer. For example, the etching of the lower source / drain layer can extend only partially through the lower source / drain layer.

[0043] The etching of the metal line trench can further comprise:

[0044] etching through the lower source / drain layer and into the underlying substrate layer, thereby forming an upper trench portion in the lower source / drain layer and a lower trench portion in the underlying substrate layer; and

[0045] performing a lateral etch-back of the lower trench portion sidewall to form a widened lower trench portion,

[0046] wherein a metal line is formed at least in the widened lower trench portion.

[0047] Thereby, an even wider metal line can be embedded in the substrate. The metal line can be formed to contact the lower source / drain layer at least from the lower side.

[0048] If the underlying substrate layer and the lower source / drain layer are formed of different semiconductor materials, for example, Si 1-x Ge x the underlying substrate layer is formed of Si 1-y Ge y and the lower source / drain layer is formed of Si1-xGex, and 0≤x≤1 and 0≤y≤1 and x≠y, the lateral etch-back can be facilitated.

[0049] The method can further comprise cutting the metal line along its longitudinal direction, thereby forming two separate parallel metal line portions in the widened lower trench portion. Thereby, two electrically separated metal lines can be formed in each metal line trench. This can be advantageous if separate access to the lower source / drain of VFETs in adjacent rows is desired.

[0050] According to another aspect of the inventive concept, there is provided a semiconductor device, comprising:

[0051] a substrate;

[0052] a plurality of VFET devices, comprising:

[0053] a plurality of semiconductor structures protruding from a lower source / drain semiconductor layer on the substrate, the semiconductor structures being arranged in an array having a plurality of rows and columns;

[0054] a gate structure surrounding a channel portion of the semiconductor structures above the lower source / drain layer; and

[0055] an upper source / drain metal contact on an upper source / drain portion of the semiconductor structures above the channel portion;

[0056] a metal line trench formed in the lower source / drain semiconductor layer and extending parallel to the rows between at least a subset of the rows;

[0057] A metal line disposed in the metal line trench, the metal line contacting the lower source / drain layer.

[0058] The above details and advantages discussed in connection with the method aspects and embodiments thereof apply correspondingly to the further apparatus aspects, and vice versa, so reference is made thereto. BRIEF DESCRIPTION OF DRAWINGS

[0059] The above and other objects, features and advantages of the present application will be better understood through the following description taken in

[0060] Figures 1 to 12 A method for forming a semiconductor device is shown.

[0061] Figures 13 to 18 Another method for forming a semiconductor device is shown.

[0062] Figures 19 to 22 Another method for forming a semiconductor device is shown. DETAILED DESCRIPTION

[0063] Reference is now made to the drawings to explain a semiconductor device including a VFET device and a method for forming a semiconductor device. Unless otherwise specified, the drawings show a substrate 100 including an array (or at least a portion of an array) of vertical semiconductor structures of VFETs in perspective view. Unless otherwise specified, the plane extending through the illustrated portion of the substrate 100 is common to all of the drawings. It will be appreciated that the substrate 100 can generally exhibit greater lateral / horizontal extension than shown, beyond the illustrated portion. It should also be noted that the relative dimensions of the illustrated structures (e.g., relative thicknesses of layers) are merely schematic for the sake of clarity and can differ from physical structures.

[0064] Figure 1 A starting substrate 100 for processing is shown. The substrate 100 can be a semiconductor substrate, i.e., a substrate that includes at least one semiconductor layer. The substrate 100 can be a single-layer semiconductor substrate, e.g., a single-layer semiconductor substrate formed from a bulk substrate. However, the substrate 100 can also be a multi-layer substrate, e.g., a multi-layer structure formed from a semiconductor layer epitaxially grown on a bulk substrate, or a semiconductor-on-insulator (SOI) substrate. For example, the substrate 100 can include a silicon (Si), germanium (Ge), or silicon-germanium (SiGe) layer.

[0065] As Figure 1 Further shown is the formation of a plurality of semiconductor structures 110 on the substrate 100. The semiconductor structures 110 protrude vertically from the lower source / drain semiconductor layer 102 of the substrate 100.

[0066] Figure 1 The particular semiconductor structure 110 shown can be formed by patterning the epitaxial lower, middle, and upper semiconductor layers such that each semiconductor structure 110 includes a lower or base portion 112, a middle portion 114, and an upper portion 116. The lower and upper portions 112, 116 of the pillar 110 can be used to form the lower source / drain and upper source / drain of the final VFET, respectively, and can therefore be referred to hereinafter as the lower source / drain portion 112 and the upper source / drain portion 116, respectively. Similarly, the middle layer portion 114 can be used to house the channel of the final VFET, and can therefore be referred to hereinafter as the channel portion 114. Thus, the channel portion 114 is disposed intermediate the source / drain portions 112, 116, and extends vertically therebetween. In other words, the source / drain portions 112, 116 are located at vertically opposite ends of the channel portion 114. The present approach is applicable to junctionless devices as well as reverse-mode devices, and the pillars 110 can be doped accordingly. For example, each layer 112, 114, 116 can be formed by ALD, physical vapor deposition (PVD), or metal-organic vapor phase epitaxy (MOVPE). Exemplary layer stacks include a SiGe / Si / SiGe layer stack, a SiGe / Ge / SiGe layer stack, or a SiGe / SiGe / SiGe layer stack, in which the Ge content of the middle layer differs from the upper and lower layers. It is noted, however, that the semiconductor structures can also be patterned in layer stacks including more or fewer layers, or even in a single epitaxial semiconductor layer.

[0067] The lower source / drain layer 102 can be heavily doped with the conductivity type, depending on the type of VFET device to be formed (i.e., p-type or n-type). The lower source / drain layer 102 can be formed from another epitaxial semiconductor layer that is separate from the one or more layers that define the semiconductor structure 110. However, the lower source / drain layer 102 can also be formed from a thickness portion of the lower layer of the layer stack, for example, from a thickness portion of the lower layer of the layer stack that remains after the semiconductor structure 110 (e.g., a lower SiGe layer) is patterned. In any case, the lower source / drain layer 112 and the lower source / drain portion 112 and 116 that protrude therefrom can together define the lower source / drain or lower source / drain region of the VFET to be formed.

[0068] Formation of the semiconductor structures 110 can be performed in a continuous manner, e.g., by patterning (e.g., using photolithography or etching) one or more epitaxial semiconductor layers formed on the substrate 100. For example, patterning of the semiconductor structures 110 can include defining a patterning mask, e.g., a hard mask (e.g., of Si3N4, spin-on carbon, or a carbon-based patterning film), on the one or more epitaxial semiconductor layers, and etching the one or more epitaxial semiconductor layers while using the patterning mask as an etching mask. As Figure 1 As shown, mask portions of the patterning mask can remain on top of the patterned channel structures as caps 120.

[0069] As shown, the first semiconductor structures 110 can be formed as vertically oriented "nanoplates," i.e., having an oval-shaped, rectangular cross-sectional shape. However, the first semiconductor structures 110 can also be formed as vertically oriented "nanowires," i.e., having a square or circular cross-sectional shape. For ease of reading, the semiconductor structures 110 will be referred to as "pillars" hereinafter.

[0070] As Figure 1 shown, the pillars 110 are formed in an array 104 having a plurality of rows Rl, R2, R3, R4 and columns Cl, C2, C3. The rows Rl-R4 extend parallel to a row direction R. The columns extend parallel to a column direction C. The rows Rl-R4 can be equally spaced along the column direction C. The columns Cl-C3 can be equally spaced along the row direction C. Each pillar 110 is disposed at a respective intersection of a row and a column. Note that Figure 1 Only a small portion of the array 104 can be depicted, which can typically include hundreds or thousands of rows and columns of pillars 110.

[0071] In Figure 2 , the pillars 110 are embedded in a capping layer 122. The capping layer 122 can be formed of a typical insulating material (e.g., SiO2) or another conventional low-k dielectric, for example. The capping layer 122 can be formed by depositing an insulating material (e.g., by CVD), followed by back-etching and / or polishing to reduce the thickness of the capping layer 122, thereby exposing the upper surfaces of the pillars 110 (or, as in the case shown, to expose the caps 120 formed thereon).

[0072] A mask 124 has been formed over the insulating layer 122, defining openings over and between a subset of the rows (e.g., rows Rl and R2 and R3 and R4, etc.). The openings define the locations of metal line trenches to be formed in the lower source / drain layer 102 between the rows. The mask can be of a conventional type, e.g., a resist-based mask patterned using photolithography.

[0073] In Figure 3In this process, trench 126 is formed in capping layer 126, extending through capping layer 122 between row subsets. Trench 126 can be formed by etching capping layer 126 via openings defined in mask 124. Trench 126 can be etched using any conventional etching process suitable for etching dielectric materials, preferably dry etching. After trench 126 is formed, mask 124 can be removed. Trench 126 exposes the lower source / drain layer 102 between row subsets. Figure 3 As shown, the width of each groove 126 allows the sidewalls of the column 110 arranged along the groove 126 to be exposed.

[0074] exist Figure 4 An insulating spacer layer 128 is formed to cover the sidewalls of the pillars 110 exposed in the trench 126 of the capping layer 122. As shown, the spacer layer 128 can be deposited as a conformal layer covering the sidewalls of the trench 126. The spacer 128 can also cover the surface portion of the lower source / drain layer 102 exposed at the bottom of the trench 126 and the upper surface of the capping layer 122. The spacer layer 128 can be an oxide layer or a nitride layer, such as SiO2 or SiN formed by ALD.

[0075] exist Figure 5 In this process, a portion of the spacer layer 128 deposited in the horizontally oriented surface is removed, thereby leaving a portion of the spacer layer 128 forming insulating sidewall spacers 128 on the sidewalls of the trench 126, and thus covering the sidewalls of the pillars 110 previously exposed in the trench 126. This can be achieved by vertical anisotropic etching of the initially deposited spacer layer 128, such as a short dry etching step. Thus, at the bottom of the trench 126, the upper surface portion 102a of the lower source / drain layer 102 is exposed.

[0076] exist Figure 6In the process, metal line trenches 130 are etched between subsets of rows R1 and R2, and R3 and R4, etc. Each metal line trench 130 is correspondingly parallel to a corresponding pair of adjacent rows and extends between the corresponding pair of adjacent rows. The metal line trenches 130 are formed by etching into the lower source / drain layer 102 via trenches 126 in the capping layer 122. Any conventional wet or dry etching process suitable for semiconductor etching can be used, such as etching processes that allow etching of Si or SiGe (including but not limited to SF6 or CF4 containing etchant). During etching, sidewall spacers 128 can mask the sidewalls of pillars 110 facing the trenches 126, thus counteracting the etching of pillars 110. As shown, the etching can partially extend through the lower source / drain layer 102 such that a portion of the thickness of the lower source / drain layer 102 remains under each trench 130. However, the etching can also extend completely through the lower source / drain layer 102, for example, stopping at the interface between the lower source / drain layer 102 and the semiconductor layer below the substrate 100.

[0077] exist Figure 7 In this configuration, a metal line 132 is formed within a metal line trench 130. Therefore, the metal line 132 can be formed to make physical and electrical contact with the lower source / drain layer 102. As shown, the metal line 132 can be formed with a vertical dimension or height greater than the depth of the metal line trench 130. Therefore, the metal line 132 can vertically overlap with the base portion / lower source / drain portion 112 of the pillar 110. In this case, sidewall spacers 128 can form an isolation between the sidewalls of the lower source / drain portion 112 and the metal line 132. The metal line 132 can be formed by depositing a metal line material (e.g., Al, Cu, W, or Ru) in the metal line trench 130 and etching the deposited metal line material back to the channel portion 114 below the pillar 110. Any conventional metal etching process can be used, which allows selective etching of the metal relative to, for example, the material forming the sidewall spacers 128 and the capping layer 122.

[0078] exist Figure 8 In this process, the metal wire 122 is covered with an insulating material, thereby closing the trenches 126 in the capping layer 122. For example, the same insulating material used to form the initial deposited capping layer 122 can be deposited to fill the trenches 126. The deposited insulating material can be polished (e.g., by CMP) and optionally etched back to form thin film pillars 110 and expose the capping layer 122 of the capping 120.

[0079] It should be noted that if the capping layer 122 is formed of a material of a type not desired by the final device (e.g., an organic spin coating, etc.), the capping layer 122 can be peeled off first and then redeposited as a new capping layer 122 of a suitable insulating material (e.g., SiO2 or another low-k dielectric).

[0080] In Figure 9 which the trenches 133 have been formed in the lower source / drain layer 102 between the plurality of rows of the array 104. The trenches 133 can be formed by first etching trenches at desired locations in the overlayer 122, and then etching the trenches 133 by etching through the trenches in the overlayer 122. Similar etching processes used to form the metal line trenches 130 can be employed. The trenches 133 are then filled with insulating material, preferably the same material as the overlayer 122. The lower source / drain layer 102 has thus been divided into a plurality of lower source / drain layer portions 102a. The trenches 133 filled with insulating material can be referred to as a shallow-trench-insulation (STI) structure. The trenches 133 preferably extend completely through the lower source / drain layer 102, and into the underlying substrate 100, to ensure reliable isolation between the lower source / drain layer portions 102a. As shown, the trenches 133 are formed with a periodicity of every two rows of the array 104. Thus, one metal line trench 130 and metal line 132 are formed for each lower source / drain layer portion 102a. However, this represents only one example, and it is equally possible for the trenches 133 to be formed with a lower periodicity (e.g., every three rows, every four rows, etc.).

[0081] As Figure 9 It is further shown that the overlayer 122 has been etched back so that the channel portions 114 and the upper source / drain portions 116 of the pillars 110 are exposed. Any sidewall spacer portions 128 can also be removed from the channel portions 114 and the upper source / drain portions 116 of the pillars 100 in the same or a subsequent etching step.

[0082] In Figure 10In the diagram, a gate structure 134 has been formed to surround the channel portion 114 of 110. As shown, the gate structure 134 is preferably formed to completely surround the channel portion 114 in the circumferential direction. The gate structure 134 can be formed as an elongated gate structure line extending along column C-C3 of array 104 and across the rows of array 104. The gate structure 134 can include a conventional gate structure, which includes, for example, a gate electrode and a gate dielectric layer formed by one or more gate conductors. The gate dielectric material includes, for example, HfO2, ZrO2, Al2O3, or other high-k dielectric materials. The gate dielectric layer can be deposited as a conformal thin film by any conventional deposition process such as ALD. The gate conductor includes, for example, a p-type effective work function metal (EWF) metal (e.g., TiN, TaN, TiTaN), or an n-type EWF metal (e.g., Al, TiAl, TiC, or TiAlC), or a composite layer (e.g., TiN / TiAl or TiN / TaN / TiAl). The gate conductor also includes a filler metal, such as W, Al, Co, Ni, Ru, or an alloy of two or more of these materials. The gate conductor can be deposited using any conventional deposition process such as ALD, CVD, or PVD.

[0083] The gate structure 134 can be formed by depositing a gate stack and then patterning the deposited gate stack to form a gate structure 134 with the desired horizontal dimensions. However, an alternative metal gate (RMG) process can also be used, in which a dummy gate (e.g., comprising polysilicon) can be formed first and then replaced by a final gate stack (as is known in the art itself).

[0084] After the gate structure 134 is formed, the gate structure can be covered by an insulating layer 136. The insulating layer 136 can advantageously be formed of the same material as the capping layer 122, such that the capping layer 122 and the insulating layer 136 together define a common insulating layer 138. Etching back and / or polishing can be performed to planarize the insulating layer 138.

[0085] exist Figure 11 In this process, an etching mask 140 is formed on the insulating layer 138. The etching mask 140 defines an opening that will be used to define the upper source / drain contacts of the VFET device. The etching mask 140 can be of a conventional type, for example, using a photolithographically patterned resist-based mask.

[0086] exist Figure 12 In this process, the source / drain contact or “top electrode” 142 is formed by etching down through the etching mask 140 to the upper source / drain portion 116 and filling the resulting trench with contact metal (e.g., Al, Co, Ni, W or Ru).

[0087] As shown, each upper source / drain metal contact 142 can be formed on a pair of upper source / drain portions 116 belonging to columns 100 opposite each other in adjacent rows. Thus, each source / drain metal contact 142 can be formed on and extend across a respective metal line 132 between adjacent rows.

[0088] However, other designs of source / drain metal contacts 142 are possible. For example, upper source / drain metal contacts 142 can be formed so as to contact only the upper source / drain portions 116 of a single column 110, or more than two columns 110.

[0089] Optionally, prior to depositing the contact metal, a doped semiconductor material can be epitaxially grown on the upper source / drain portions 116 to form an enlarged upper source / drain portion to improve electrical contact with the source / drain contact structure 142.

[0090] Subsequently, BEOL processing etc. can be performed in a manner known per se in the art. Therein, the metal lines 132 can be connected to BEOL interconnect structures, e.g. at the edges or outside of the array 104, by suitable locations of vertical vias.

[0091] Figures 13 to 18 A variant of a method for forming a semiconductor device comprising a VFET device is shown. Figures 13 to 18 A planar cross-section of a portion of the array 104 across a plurality of rows R1-R3 etc. is shown taken along the column direction. Unless otherwise stated, the same reference numerals as in Figures 1 to 12 The same reference numerals in Figures 13-18 denote the same elements.

[0092] The method is generally performed in the same manner as described above until the stage of forming the metal line trenches 130. Figure 13 Columns 110 after formation of trenches 126 in the cover layer 122 are shown. In contrast to the method described above, trenches 126 have been formed between each row of the array 104 and are thus not visible in the cross-sectional view. A conformal insulating layer 228 is formed to cover the upper surface portions of the lower source / drain layer 102 exposed in the trenches 126 and the columns 110. The conformal insulating layer 228 can be formed in a corresponding manner as the spacer layer 128. However, according to a variant, the layer 228 can be formed prior to the cover layer 112 and the trenches 126. Subsequently, the cover layer 122 can be deposited, wherein the trenches 126 can be formed by selective etching of the cover layer 122 with respect to the conformal layer 228. For example, the spacer layer 228 can be formed as a SiN layer, wherein the SiO2 cover layer 122 can be selectively etched with respect to the conformal layer 228.

[0093] InFigure 14 In this process, the conformal layer 228 opens at the bottom of the trench 126, and the remainder of the conformal layer 228 is formed on the sidewalls of the (trench 126 and) pillar 110 to form a sidewall spacer layer 228 thereon. Subsequently, metal wire trenches 130 and metal wires have been formed between each row of pillars 110.

[0094] Figure 15 An optional insulating barrier liner 150 (if desired) is shown deposited on the metal wire 132 to prevent material contamination of the metal wire 132.

[0095] exist Figure 16 In this process, a mask layer 160 is formed above pillars 110 and metal lines 132. A plurality of trench openings 162 are formed in the mask layer 160, each trench opening being formed above a corresponding metal line 132 between a pair of rows. For example, the mask layer 160 can be a spin-on layer or a layer stack, such as spin-on carbon (SOC) and spin-on glass (SOG). The trench openings 162 can be formed using conventional photolithography and etching.

[0096] exist Figure 17 In the process, the metal lines 132 below the trench opening 162 have been removed during metal etching. Subsequently, the semiconductor material below the lower source / drain layer 102 is etched to form a trench 164, which divides the lower source / drain layer 102 into separate lower source / drain layer portions 102a. The mask layer 160 can then be removed. If an optional barrier liner 150 has been formed, it can be first opened by a short oxidation or dielectric etching step, thereby exposing the corresponding metal lines 132.

[0097] exist Figure 18 In this process, trench 164 is filled with an insulating layer 222, which also embeds pillars 222. Subsequently, the method described above can be used to form the gate structure and source / drain contacts as described above.

[0098] Figures 19 to 22 Another variation of a method for forming a semiconductor device containing a VFET is shown. Figures 19 to 22 This shows a planar cross-section of a portion of an array 104, taken along the column direction and spanning multiple rows R1-R3, etc. Unless otherwise stated, Figures 1 to 12 The same reference numerals as in 19-22 denote the same elements.

[0099] This method is usually carried out in the same manner as described above, but with the difference that metal wire trenches 130 and metal wires 132 are formed. Figure 19The pillars 110 after the formation of the capping layer 122 are shown. Trenches 126 are formed between the multiple rows of the array 104.

[0100] Furthermore, the metal lines 130 are formed by etching through the lower source / drain layer 102 and into the underlying substrate 100, thereby forming an upper trench portion 130a in the lower source / drain layer 102 and a lower trench portion 130b in the underlying substrate 100. Subsequently, a lateral etch-back of the lower trench portion sidewalls can be performed to form a widened lower trench portion 130b (shown schematically by the arrow in the lower trench portion 130b). The initial etching of the lower source / drain layer 102 and the substrate 100 can be achieved in the same manner as described above, e.g., by a conventional wet or dry etching process to allow etching of semiconductor materials such as SiGe and Si. The lateral etch-back can include isotropically etching the substrate 100 to selectively etch into the lower source / drain layer 102. For example, if the lower source / drain layer 102 is formed of SiGe and the etch- thickness portion of the substrate 100 is formed of Si, an etch contrast between the lower source / drain layer 102 and the substrate 100 can be provided. As described above, the spacer layer 128 can mask the sidewalls of the pillars 110 during the metal line trench 130 etching.

[0101] In Figure 20 the metal lines 132 are formed in the widened lower trench portions 130b. As shown, each metal line 132 contacts the lower side of the source / drain layer 102.

[0102] Figure 21 and Figure 22 how a cut is formed in each metal line 132, the cut extending in the longitudinal direction of the metal line (i.e., the row direction R), thereby forming two separate parallel metal line portions 132a, 132b in each widened lower trench portion 130b. In Figure 21 the mask 172 defining a trench-shaped opening 174 has been formed, each trench-shaped opening exposing an upper surface of a longitudinal portion of each metal line 132. For example, the mask layer 172 can be a spin-on layer or a layer stack, e.g., spin-on carbon (SOC) and spin-on glass (SOG). Conventional photolithography and etching can be used to form the trench openings 174. In Figure 22 the metal lines 132 are cut by performing a metal etch through the trench openings 174. Subsequently, the method can be performed to cover the metal line portions 132a, 132b with an insulating material and further to form a gate structure and to form an upper source / drain contact, as described above.

[0103] In the foregoing, the inventive concept has been described mainly with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the application, which is defined by the appended claims.

Claims

1. A method of forming a semiconductor device, said semiconductor device comprising a vertical channel field-effect transistor device, said method comprising: Multiple semiconductor structures are formed on a substrate, protruding vertically from the lower source / drain layer of the substrate, and the semiconductor structures are arranged in an array with multiple rows and multiple columns. A capping layer is formed that at least partially encapsulates the semiconductor structure and at least partially covers the lower source / drain layer; A trench is formed in the overlay layer, the trench extending through the overlay layer between at least one subset of rows; Etching metal line trenches between at least one subset of rows, wherein etching the metal line trenches includes etching the source / drain layer through trenches in the capping layer. Metal wires are formed in metal wire trenches, which contact the lower source / drain layers; Forming a gate structure that at least partially surrounds the semiconductor structure channel portion located above the lower source / drain layer; and Upper source / drain metal contacts are formed on the upper source / drain portions of the semiconductor structure located above the channel portion.

2. The method of claim 1, further comprising: Before forming the metal lines, an insulating spacer layer is formed on the sidewall of the semiconductor structure along at least one subset of rows.

3. The method as described in claim 2, wherein, A spacer layer is formed before the metal wire trench is formed.

4. The method of claim 1, wherein, The trenches in the capping layer expose the sidewalls of the semiconductor structure disposed along the at least one subset of rows, and the method further includes forming an insulating spacer layer on the sidewalls of the semiconductor structure exposed in the capping layer trenches.

5. The method of claim 1, further comprising: Before forming the capping layer, a conformal layer is deposited that at least partially covers the semiconductor structure and the lower source / drain layer, and The process of forming trenches in the capping layer after its formation includes selectively etching the capping layer relative to the conformal layer.

6. The method of claim 1, wherein, The metal wire is formed at a height greater than the depth of the metal wire trench.

7. The method of claim 1, wherein, Forming a metal wire includes depositing metal wire material in a metal wire trench and etching the deposited metal wire material back to a level below the channel portion.

8. The method of claim 1, further comprising: The metal wire is at least partially covered by an insulating layer, wherein the gate structure is formed on the insulating layer.

9. The method of claim 1, wherein, Each upper source / drain metal contact is formed on the upper source / drain portion of at least two consecutive rows of semiconductor structures.

10. The method of claim 9, wherein, Each source / drain metal contact is on at least one metal line and extends across it.

11. The method of claim 1, wherein before or after forming the metal wire, the method further comprises: Trenches are formed in the lower source / drain layer between multiple rows of the array, and the trenches formed between the multiple rows are filled with insulating material, thereby dividing the lower source / drain layer into multiple lower source / drain layer portions, wherein at least one metal line trench and a metal line are formed in each lower source / drain layer portion.

12. The method of claim 11, wherein, Metal trenches and metal lines are formed between rows of a semiconductor structure supported by each lower source / drain portion.

13. The method of claim 1, wherein, Etched metal wire trenches include: The etching penetrates the lower source / drain layer and extends into the underlying substrate, thereby forming an upper trench portion in the lower source / drain layer and a lower trench portion in the substrate; and Lateral back etching is performed on the sidewalls of the lower trench section to form a wider lower trench section compared to the upper trench step. Metal wires are formed, at least in the widened lower trench section.

14. The method of claim 13, further comprising: Each metal wire is cut along its longitudinal direction, thereby forming two metal wire sections in each widened lower trench section.

15. The method of claim 13, wherein, The metal line contacts the lower side of the source / drain layer.

16. The method of claim 14, wherein, The two metal wire sections are parallel to each other and separate.

17. The method of claim 1, wherein, The metal wire grooves are parallel to the rows.

18. The method of claim 1, further comprising a subsequent step of connecting the metal wire to the wire.

19. The method of claim 1, wherein, Vertical channel field-effect transistor devices arranged along a pair of adjacent rows are connected to a common metal line formed therebetween.

20. A method of forming a semiconductor device, said semiconductor device comprising a vertical channel field-effect transistor device, said method comprising: Multiple semiconductor structures are formed on a substrate, protruding vertically from the lower source / drain layer of the substrate, and the semiconductor structures are arranged in an array with multiple rows and multiple columns. Etch the metal wire trenches between at least one row subset; Metal wires are formed in metal wire trenches, which contact the lower source / drain layers; A gate structure is formed that at least partially surrounds the semiconductor structure channel portion located above the lower source / drain layer; and Upper source / drain metal contacts are formed on the upper source / drain portions of the semiconductor structure located above the channel portion, wherein each upper source / drain metal contact is formed on the upper source / drain portions of at least two consecutive rows of the semiconductor structure.

21. A method of forming a semiconductor device, said semiconductor device comprising a vertical channel field-effect transistor device, said method comprising: Multiple semiconductor structures are formed on a substrate, protruding vertically from the lower source / drain layer of the substrate, and the semiconductor structures are arranged in an array with multiple rows and multiple columns. Etch the metal wire trenches between at least one row subset; Before or after the formation of metal lines, trenches are formed in the lower source / drain layer between multiple rows of the array; The trenches formed between multiple rows are filled with insulating material, thereby dividing the lower source / drain layer into multiple lower source / drain layer portions, wherein at least one metal wire trench and a metal wire are formed in each lower source / drain layer portion; Forming a gate structure that at least partially surrounds the semiconductor structure channel portion located above the lower source / drain layer; and Upper source / drain metal contacts are formed on the upper source / drain portion of the semiconductor structure located above the channel portion.

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