Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a stack structure disposed on a lower structure, an insulating structure disposed on the stack structure, and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure and having a side surface opposite to the stack structure and the insulating structure. The stack structure includes interlayer insulating layers and gate layers alternately stacked, and the insulating structure includes a lower insulating layer, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present application relate to semiconductor devices, and more particularly, to three-dimensional semiconductor devices. BACKGROUND

[0002] To improve price competitiveness of electronic products, demand for increasing integration density of semiconductor devices has increased. To increase integration density of semiconductor devices, semiconductor devices in which memory cells are arranged three-dimensionally have been proposed instead of semiconductor devices including memory cells arranged two-dimensionally. SUMMARY

[0003] Example embodiments of the present application provide semiconductor devices having increased integration density.

[0004] Provided herein is a semiconductor device including a stack structure, a lower structure in which the stack structure is disposed on the lower structure, an insulating structure disposed on the stack structure, and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure, wherein the vertical structure includes a side surface opposite to a side surface of the stack structure and opposite to a side surface of the insulating structure, wherein at least a portion of the stack structure includes a plurality of interlayer insulating layers and a plurality of gate layers, wherein the plurality of interlayer insulating layers and the plurality of gate layers are alternately stacked, wherein the insulating structure includes a lower insulating layer, an intermediate insulating layer, and an upper insulating layer, wherein the intermediate insulating layer is disposed on the lower insulating layer, wherein the upper insulating layer is disposed on the intermediate insulating layer, and wherein the intermediate insulating layer exhibits an etching selectivity.

[0005] In some embodiments of the semiconductor device, a material of the intermediate insulating layer is different from a material of the lower insulating layer and a material of the upper insulating layer, the intermediate insulating layer includes a dopant, wherein the dopant includes an element of Group VA of the Periodic Table of Elements, and wherein the intermediate insulating layer exhibits an etching selectivity with respect to the upper insulating layer.

[0006] Also provided in some embodiments is an optional semiconductor device including a stack structure, a lower structure in which the stack structure is disposed on the lower structure, an insulating structure disposed on the stack structure, a vertical structure extending in a direction perpendicular to an upper surface of the lower structure, wherein the vertical structure penetrates the stack structure and penetrates the insulating structure, a cap insulating layer, wherein the cap insulating layer is disposed on the insulating structure and on the vertical structure, and a separation structure, wherein the separation structure extends in a direction perpendicular to the upper surface of the lower structure, and wherein the separation structure penetrates the stack structure, penetrates the insulating structure, and penetrates the cap insulating layer, the insulating structure includes a lower insulating layer, an intermediate insulating layer, and an upper insulating layer, the intermediate insulating layer is disposed on the lower insulating layer, the upper insulating layer is disposed on the intermediate insulating layer, and the intermediate insulating layer exhibits an etching selectivity.

[0007] In some embodiments of the optional semiconductor device, at least a portion of the stack structure includes a plurality of gate layers and a plurality of interlayer insulating layers, wherein the plurality of interlayer insulating layers and the plurality of gate layers are alternately stacked, the material of the intermediate insulating layer is different from the material of the lower insulating layer, the material of the upper insulating layer, and the material of the interlayer insulating layer, the intermediate insulating layer includes a dopant, wherein the dopant includes a Group VA element of the Periodic Table of Elements, and wherein the intermediate insulating layer exhibits an etch selectivity with respect to the upper insulating layer.

[0008] In some embodiments, yet another semiconductor device is also provided, including: a stack structure; a lower structure, wherein the stack structure is disposed on the lower structure; an insulating structure disposed on the stack structure; a vertical structure extending in a direction perpendicular to an upper surface of the lower structure, wherein the vertical structure penetrates the stack structure and penetrates the insulating structure; a cap insulating layer, wherein the cap insulating layer is disposed on the insulating structure and on the vertical structure; and a contact plug, wherein the contact plug penetrates the cap insulating layer and penetrates the insulating structure, the insulating structure includes a lower insulating layer, an intermediate insulating layer, and an upper insulating layer, the intermediate insulating layer is disposed on the lower insulating layer, wherein the upper insulating layer is disposed on the intermediate insulating layer, the intermediate insulating layer exhibits an etch selectivity. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and further aspects, features and advantages of the present application will be understood more readily by reference to the following detailed description taken in connection with the following drawings:

[0010] Figure 1 is a block diagram illustrating a semiconductor device according to an example embodiment of the present application;

[0011] Figure 2 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the present application;

[0012] Figure 3 is a cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment of the present application;

[0013] Figure 4 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the present application;

[0014] Figure 5 is a cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment of the present application;

[0015] Figure 6 is a perspective view illustrating an example of a portion of a semiconductor device according to an example embodiment of the present application;

[0016] Figure 7is a cross-sectional view showing an example of a semiconductor device according to an example embodiment of the present application and a graph showing an example of a doping profile of a portion of the cross-sectional view;

[0017] Figure 8 is an enlarged view showing an example of a portion of a semiconductor device according to an example embodiment of the present application;

[0018] Figure 9 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application and a graph showing an example of a doping profile of a portion of the cross-sectional view;

[0019] Figure 10 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application and a graph showing an example of a doping profile of a portion of the cross-sectional view;

[0020] Figure 11 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application and a graph showing an example of a doping profile of a portion of the cross-sectional view;

[0021] Figures 12A-12F is a cross-sectional view showing various modified examples of a portion of a semiconductor device according to an example embodiment of the present application;

[0022] Figure 13 is a plan view showing a semiconductor device according to an example embodiment of the present application;

[0023] Figures 14A-14D is a cross-sectional view showing an example of a semiconductor device.

[0024] Figure 15 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application;

[0025] Figure 16 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application;

[0026] Figure 17 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application;

[0027] Figure 18A is a perspective view showing a modified example of a semiconductor device according to an example embodiment of the present application;

[0028] Figure 18B is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application;

[0029] Figure 19 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present application;

[0030] Figures 20A-26B is a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment of the present application;

[0031] Figure 27 is a cross-sectional view showing a modified example of a method of manufacturing a semiconductor device according to an example embodiment of the present application;

[0032] Figure 28 and Figure 29 is a cross-sectional view showing a modified example of a method of manufacturing a semiconductor device according to an example embodiment of the present application; and

[0033] Figure 30 is a cross-sectional view showing a modified example of a method of manufacturing a semiconductor device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0034] Hereinafter, example embodiments of the present application will be described with reference to the accompanying drawings.

[0035] An example of a semiconductor device will be described with reference to Figure 1 . Figure 1 is a block diagram showing a semiconductor device according to an example embodiment.

[0036] Referring to Figure 1 , the semiconductor device 10 can include a memory cell array region 20 in which a cell string S including an upper transistor UT controlled by a string selection line SSL, a lower transistor LT controlled by a ground selection line GSL, and a memory cell MC disposed between the upper transistor UT and the lower transistor LT and controlled by a word line WL are provided, and a peripheral circuit region 40 in which a peripheral circuit for storing information in the memory cell MC or for reading out information stored in the memory cell MC, such as a row decoder 42, a page buffer 44, an input / output (I / O) buffer 45, a control logic 46, a voltage generator 47, and the like, are provided.

[0037] An example of a semiconductor device will be described with reference to Figure 2 . Figure 2 is a cross-sectional view showing an example of a semiconductor device according to an example embodiment.

[0038] Referring to Figure 2In one example embodiment, the semiconductor device 10a can include a memory cell array region 20 and a peripheral circuit region 40a disposed adjacent to the memory cell array region 20. The peripheral circuit region 40a can include a peripheral transistor PT included in a peripheral circuit. The peripheral transistor PT can include a peripheral gate PG and a peripheral source / drain PSD.

[0039] In one example, the semiconductor device 10a can include a connection region 25 adjacent to the memory cell array region 20. The connection region 25 can be referred to as a "contact region" or an "extension region".

[0040] In one example, the semiconductor device 10a can include a lower structure 50a, a stack structure 65 disposed on the lower structure 50a, and an insulating structure 24 disposed on the lower structure 50a and covering the stack structure 65. In one example embodiment, the lower structure 50a can be a semiconductor substrate. The memory cell array region 20 and the peripheral circuit region 40a can be disposed on the lower structure 50a. The stack structure 65 can be disposed in the memory cell array region 20 and can extend into the connection region 25.

[0041] In this example embodiment, the stack structure 65 can include a first region 65t and a second region 65s extending from the first region 65t and having a stepped form in the connection region 25. The second region 65s can have a stepped form descending from an upper surface of the first region 65t. The second region 65s can be disposed in the connection region 25.

[0042] In this example embodiment, the stepped form can include a form gradually descending with a certain height difference between steps, and can include different types of stepped forms. Hereinafter, the first region 65t of the stack structure 65 can be referred to as a "stack region", and the second region 65s of the stack structure 65 can be referred to as a "stepped region".

[0043] The insulating structure 24 can include a lower insulating layer 15, an intermediate insulating layer 18 disposed on the lower insulating layer 15, and an upper insulating layer 21 disposed on the intermediate insulating layer 18.

[0044] The material of the intermediate insulating layer 18 can be different from the material of the lower insulating layer 15 and the material of the upper insulating layer 21. The intermediate insulating layer 18 can be formed of a material having an etching selectivity different from the etching selectivity of the material of the lower insulating layer 15 and the etching selectivity of the material of the upper insulating layer 21.

[0045] In this example embodiment, the semiconductor device 10a can include a vertical structure VS provided over the lower structure 50a and penetrating the stacked structure 65 and the insulating structure 24. The vertical structure VS can have a side surface facing the stacked structure 65 and the insulating structure 24. The vertical structure VS can be provided in the memory cell array region 20 and can penetrate the stacked region 65t of the stacked structure 65 and the insulating structure 24 provided over the stacked region 65t.

[0046] In one example embodiment, the vertical structure VS can have an upper surface substantially coplanar with an upper surface of the insulating structure 24. The upper surface of the vertical structure VS and the upper surface of the insulating structure 24 can be located substantially at the same level.

[0047] The peripheral circuit region 40a can be provided adjacent to the memory cell array region 20, but example embodiments thereof are not limited thereto. In the following description, a modified example of the peripheral circuit region 40a will be described with reference to Figure 3 Figure 3 is a cross-sectional view illustrating a modified example of a semiconductor device according to one example embodiment.

[0048] In this modified example, with reference to Figure 3 , the semiconductor device 10b can include the memory cell array region 20 and the connection region 25 as in the foregoing example embodiment described with reference to Figure 2 , and can include a peripheral circuit region 40b provided under the memory cell array region 20 and the connection region 25.

[0049] In this example embodiment, the semiconductor device 10b can include a lower structure 50b. The lower structure 50b can include a first substrate 5 and a peripheral circuit region 40b provided over the first substrate 5. The first substrate 5 can be a semiconductor substrate. The peripheral circuit region 40b can include a peripheral transistor PT included in a peripheral circuit, including a peripheral gate PG and a peripheral source / drain PSD, and a peripheral insulating layer 41 covering the peripheral transistor PT.

[0050] In this example embodiment, the lower structure 50b can further include a second substrate 52 provided over the peripheral circuit region 40b and an intermediate insulating layer 54 provided over a side surface of the second substrate 52. The second substrate 52 can include a semiconductor material (e.g., polysilicon, etc.) and / or a conductive material (e.g., TiN, tungsten, etc.).

[0051] In one example embodiment, the semiconductor device 10b can include the stacked structure 65, the insulating structure 24, and the vertical structure VS as in the foregoing example embodiment described with reference to Figure 2 . With reference to Figure 2 and Figure 3 ​An example of the insulating structure 24 described will be described with reference to Figure 4 described. Figure 4 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment.

[0052] In an example embodiment, with reference to Figure 4 As in the example embodiment described with reference to Figure 2 and Figure 3 The stack structure 65 can include the stack region 65t and the step region 65s, and the insulating structure 24 provided on the stack structure 65 can include the lower insulating layer 15, the intermediate insulating layer 18, and the upper insulating layer 21 stacked in this order, as in the example embodiment described with reference to

[0053] In this example embodiment, the lower insulating layer 15 can include a first lower insulating layer 15a and a second lower insulating layer 15b. The first lower insulating layer 15a can be provided on the stack region 65t of the stack structure 65, and the second lower insulating layer 15b can be provided on the step region 65s of the stack structure 65.

[0054] In this example embodiment, the first lower insulating layer 15a can have an upper surface that is coplanar with an upper surface of the second lower insulating layer 15b.

[0055] In this example embodiment, the first lower insulating layer 15a can have a width substantially the same as a width of an upper surface of the stack region 65t. The first lower insulating layer 15a can be self-aligned with the stack region 65t.

[0056] In this example embodiment, the intermediate insulating layer 18 can be in contact with the first lower insulating layer 15a and the second lower insulating layer 15b.

[0057] With reference to Figure 2 and Figure 3 The vertical structure VS described with reference to can extend through the stack region 65t, the first lower insulating layer 15a, the intermediate insulating layer 18, and the upper insulating layer 21.

[0058] In the following description, a modified example of the second lower insulating layer 15b and the intermediate insulating layer 18 of the insulating structure 24 will be described with reference to Figure 5 described. Figure 5 is a cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment.

[0059] In this modified example, with reference to Figure 5 , a first lower insulating layer 15a and an intermediate insulating layer 18' stacked in this order can be provided on the stack region 65t of the stack structure 65. As described in the foregoing example embodiment, a second lower insulating layer 15b' can be provided on the step region 65s of the stack structure 65.

[0060] In this example embodiment, the first lower insulating layer 15a and the intermediate insulating layer 18' can have substantially the same width.

[0061] The upper insulating layer 21 can be provided on the intermediate insulating layer 18' and the second lower insulating layer 15b'. Thus, the insulating structure 24 including the lower insulating layer 15 including the first lower insulating layer 15a and the second lower insulating layer 15b', the intermediate insulating layer 18', and the upper insulating layer 21 can be provided on the stack structure 65.

[0062] In this example embodiment, the second lower insulating layer 15b' can have an upper surface that is coplanar with an upper surface of the intermediate insulating layer 18'.

[0063] The upper insulating layer 21 can be in contact with the second lower insulating layer 15b' and the intermediate insulating layer 18'.

[0064] In the following description, the example embodiments of the stack structure 65, the insulating structure 24, and the vertical structure VS provided in the memory cell array region 20 described in the foregoing example embodiments will be described with reference to Figure 6 the drawings. Figure 6 is a perspective view illustrating an example of a semiconductor device according to an example embodiment.

[0065] With reference to Figure 6 , the stack structure 165, the insulating structure 124, and the vertical structure VS can be provided on the lower structure 50. The lower structure 50 can be the lower structure 50a (in Figure 2 ) illustrated in the example in Figure 2 , or can be the lower structure 50b (in Figure 3 ) illustrated in the example in Figure 3 .

[0066] The stack structure 165 can include a plurality of interlayer insulating layers 102 and a plurality of gate layers 162 stacked alternately. The interlayer insulating layer 102 can be formed of an insulating material such as silicon oxide.

[0067] The plurality of gate layers 162 can include one or more lower gate layers 162L, a plurality of intermediate gate layers 162M provided on the one or more lower gate layers 162L, and one or more upper gate layers 162U provided on the plurality of intermediate gate layers 162M.

[0068] In this example embodiment, a plurality of lower gate layers 162L can be provided. For example, the plurality of lower gate layers 162L can include a first lower gate layer 162L1, a second lower gate layer 162L2, and a third lower gate layer 162L3 provided in this order from an upper surface of the lower structure 50 in a direction perpendicular to the upper surface of the lower structure 50.

[0069] In this example embodiment, multiple upper gate layers 162U may be provided. For example, the multiple upper gate layers 162U may include a first upper gate layer 162U1, a second upper gate layer 162U2, a third upper gate layer 162U3, and a fourth upper gate layer 162U4, which are sequentially arranged from the upper surface of the stacked structure 165 in a direction perpendicular to the upper surface of the lower structure 50.

[0070] The insulating structure 124 may include a lower insulating layer 115, an intermediate insulating layer 118, and an upper insulating layer 121 stacked sequentially. The insulating structure 124 can be coupled with... Figure 4 and Figure 5 The example shown illustrates the insulating structure 24 disposed in the memory cell array region 20 (in... Figure 4 and Figure 5 The two are basically the same. For example, the lower insulating layer 115, the middle insulating layer 118, and the upper insulating layer 121 of the insulating structure 124 can respectively correspond to the reference. Figure 4 and Figure 5 The described insulation structure 24 (in) Figure 4 and Figure 5 The first lower insulating layer 15a (in the middle) Figure 4 and Figure 5 (middle), intermediate insulating layers 18 and 18' (respectively in) Figure 4 and Figure 5 (middle) and upper insulating layer 21 (in) Figure 4 and Figure 5 (Middle). Therefore, as described above, the intermediate insulating layer 118 can be formed of a material different from the material of the lower insulating layer 115 and the upper insulating layer 121.

[0071] A hole 130 can be provided that sequentially penetrates the stacked structure 165 and the insulating structure 124. A vertical structure VS can be provided in the hole 130. The vertical structure VS can extend in a direction perpendicular to the upper surface of the lower structure 50 and can sequentially penetrate the stacked structure 165 and the insulating structure 124. The vertical structure VS can have a side surface opposite to the side surface of the stacked structure 165 and the side surface of the insulating structure 124. The vertical structure VS can have an upper surface that is substantially coplanar with the upper surface of the insulating structure 124.

[0072] The vertical structure VS may include a semiconductor pattern 140. The semiconductor pattern 140 may include a pad portion 140P located at a level higher than the stacked structure 165 (or the core pattern 142 described below), and a liner portion 140L extending from the edge region of the pad portion 140P in a direction perpendicular to the upper surface of the lower structure 50.

[0073] The semiconductor pattern 140 can include a channel region 140Lc and doped regions 140Ld and 140Pd. The channel region 140Lc can be constituted by a lower portion of the liner portion 140L of the semiconductor pattern 140. The doped regions 140Ld and 140Pd can include a first doped region 140Pd constituted by the pad portion 140P of the semiconductor pattern 140 and a second doped region 140Ld extending from the first doped region 140Pd into the liner portion 140L and constituted by an upper portion of the liner portion 140L.

[0074] In this example embodiment, the insulating structure 124 can be opposite to the doped regions 140Ld and 140Pd. A lower surface of the insulating structure 124 can be disposed at a higher level than the contact region 140J (see Figure 4 ) and the doped regions 140Ld and 140Pd.

[0075] The vertical structure VS can further include a core pattern 142 and a dielectric structure 138 surrounding an outer side surface of the semiconductor pattern 140. The semiconductor pattern 140 can surround a side surface of the core pattern 142 and can cover an upper surface of the core pattern 142. The semiconductor pattern 140 can surround a side surface of the core pattern 142 and can extend to a region between a lower surface of the core pattern 142 and the lower structure 50. The core pattern 142 can be formed of an insulating material such as silicon oxide. The liner portion 140L of the semiconductor pattern 140 can be disposed to surround a side surface of the core pattern 142, and the pad portion 140P of the semiconductor pattern 140 can be disposed on the core pattern 142.

[0076] In the following description, various examples of the stack structure 165, the insulating structure 124, and the vertical structure VS will be described with reference to Figure 5 , Figure 4 , Figure 5 , Figure 4 and Figure 5 . Figure 4 is a cross-sectional view showing an example of a semiconductor device according to an example embodiment and a graph showing an example of a doping distribution of a portion of the cross-sectional view. Figure 5 is an enlarged view showing the portion marked 'A' shown in Figure 4 . Figure 5 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment and a graph showing an example of a doping distribution of a portion of the cross-sectional view. Figure 4 is a cross-sectional view showing another modified example of a semiconductor device according to an example embodiment and a graph showing an example of a doping distribution of a portion of the cross-sectional view. Figure 5 is a cross-sectional view showing another modified example of a semiconductor device according to an example embodiment and a graph showing an example of a doping distribution of a portion of the cross-sectional view. Figure 4A cross-sectional view in FIG. 1A can show a cross-section taken from the reference Figure 5 A cross-section of an upper surface of the insulating structure 124 described with reference to Figure 4 A cross-section of an upper surface of the insulating structure 124 described with reference to Figure 5 Figure 4 Figure 5 A graph showing a doping profile of the insulating structure 124 described with reference to Figure 4 A graph showing a doping profile of the insulating structure 124 described with reference to

[0077] Examples of the stack structure 165, the insulating structure 124, and the vertical structure VS will be described with reference to Figure 5

[0078] With reference to Figure 8 , the stack structure 165, the insulating structure 124, and the vertical structure VS as in the example embodiment described with reference to Figure 8 may be provided. The stack structure 165 can include the plurality of gate layers 162 as described above. Each gate layer 162 can include the first material layer 158 and the second material layer 160. The first material layer 158 can cover an upper surface and a lower surface of the second material layer 160, and can extend to a region between a side surface of the second material layer 160 and a side surface of the vertical structure VS.

[0079] In this example embodiment, the first material layer 158 can be formed of a dielectric material such as aluminum oxide or the like, and the second material layer 160 can be formed of a conductive material including one or two or more of doped silicon, metal nitride (e.g., TiN or the like), and metal (e.g., W or the like).

[0080] In another example embodiment, the first material layer 158 can be formed of a conductive material such as metal nitride (e.g., TiN or the like) or the like, and the second material layer 160 can be formed of a conductive material such as metal (e.g., W or the like) or the like.

[0081] As described with reference to Figure 1 , the insulating structure 124 can include the lower insulating layer 115, the middle insulating layer 118, and the upper insulating layer 121 stacked in this order, and the vertical structure VS can include the semiconductor pattern 140 including the channel region 140Lc and the doped regions 140Ld and 140Pd. The doped regions 140Ld and 140Pd can include the first doped region 140Pd composed of the pad portion 140P of the semiconductor pattern 140 and the second doped region 140Ld composed of an upper portion of the liner portion 140L of the semiconductor pattern 140.

[0082] ​​​In this example embodiment, the contact region 140J between the second doped region 140Ld and the channel region 140Lc can be disposed at a level lower than the upper surface of the first upper gate layer 162U1, which is at its highest level within the gate layer 162. For example, the contact region 140J can be located at the level between the upper surface and the lower surface of the first upper gate layer 162U1.

[0083] The doped regions 140Ld and 140Pd and the insulating structure 124 may include a first element implanted from the upper surface 140S of the semiconductor pattern 140 and the upper surface 124S of the insulating structure 124 by an ion implantation process.

[0084] In this example embodiment, the first element in the insulating structure 124 may be doped with a Gaussian distribution or a distribution similar to a Gaussian distribution.

[0085] In this example embodiment, the doping distribution of the first element in the insulating structure 124 can have a maximum concentration at a first depth Rp, extending from the upper surface 140S of the semiconductor pattern 140 and the upper surface 124S of the insulating structure 124. The upper surface 140S of the semiconductor pattern 140 and the upper surface 124S of the insulating structure 124 can be coplanar with each other. The first depth Rp can be located between the upper and lower surfaces of the intermediate insulating layer 118. Therefore, the first element in the insulating structure 124 can have a maximum concentration in the intermediate insulating layer 118. The concentration of the first element in the insulating structure 124 can be higher in the intermediate insulating layer 118 than in the lower insulating layer 115 and the upper insulating layer 121.

[0086] In this example embodiment, the first element can be a Group VA element in the periodic table (e.g., phosphorus (P), arsenic (As), etc.). Therefore, the doped regions 140Ld and 140Pd can have N-type conductivity.

[0087] In this example embodiment, the insulating structure 124 can be compared with the reference. Figure 1 and Figure 1 The described insulating structure 24 is disposed in the memory cell array region 20 (in Figure 9 and Figure 10 The insulation structure 24 (in the middle) is basically the same, therefore, the insulation structure 24 (in Figure 9 and Figure 10 (in) may include the first element, and the insulating structure 24 (in) Figure 11 and Figure 11 The doping concentration of the first element in the middle layer can be adjusted in the intermediate insulating layers 18 and 18' (respectively in...). Figure 6 and Figures 12A-12F In the middle) the first lower insulating layer 15a (in Figures 12A-12F and Figure 12AThe middle insulating layer 118 can include a first element, and a doping concentration of the first element in the insulating structure 124 can be higher in the middle insulating layer 118 than in the lower insulating layer 115 and the upper insulating layer 121. Figure 12B The middle insulating layer 118 can include a first element, and a doping concentration of the first element in the insulating structure 124 can be higher in the middle insulating layer 118 than in the lower insulating layer 115 and the upper insulating layer 121. Figure 12C The middle insulating layer 118 can include a first element, and a doping concentration of the first element in the insulating structure 124 can be higher in the middle insulating layer 118 than in the lower insulating layer 115 and the upper insulating layer 121. The middle insulating layer 118 can include a first element, and a doping concentration of the first element in the insulating structure 124 can be higher in the middle insulating layer 118 than in the lower insulating layer 115 and the upper insulating layer 121.

[0088] In the following description, it can be understood that the middle insulating layer 118 can include a first element, and a doping concentration of the first element in the insulating structure 124 can be higher in the middle insulating layer 118 than in the lower insulating layer 115 and the upper insulating layer 121. Thus, although a description thereof is not provided, it can be understood that the insulating structure 124 or an insulating structure corresponding to the insulating structure 124 can have a concentration distribution of the first element described above.

[0089] In this example embodiment, the middle insulating layer 118 can be a middle insulating layer 118a configured to surround a boundary region between the pad portion 140P and the liner portion 140L of the semiconductor pattern 140. The middle insulating layer 118a can surround an upper surface of the core pattern 142. Thus, the middle insulating layer 118a can be disposed at the same level as a portion of the pad portion 140P and a portion of the liner portion 140L.

[0090] In the following description, an example of the dielectric structure 138 will be described with reference to Figure 12D .

[0091] With reference to Figure 12E , the dielectric structure 138 can include the first dielectric layer 132, the data storage layer 134, and the second dielectric layer 136. The data storage layer 134 can be disposed between the first dielectric layer 132 and the second dielectric layer 136. The first dielectric layer 132 can be disposed between the data storage layer 134 and the gate layer 162, and can extend to a region between the data storage layer 134 and the interlayer insulating layer 102. The second dielectric layer 136 can be disposed between the semiconductor pattern 140 and the data storage layer 134.

[0092] In this example embodiment, the data storage layer 134 can function as a data storage region of a storage cell of a NAND flash memory device. For example, a region of the data storage layer 134 opposite to a middle gate layer among the middle gate layers 162M that functions as a word line WL (in Figure 12F ) can be a "data storage region", and can be included in a storage cell MC (in Figure 13 ) illustrated in the example. Figures 14A-14D For example, the data storage layer 134 can be formed of a material that can trap electric charges, such as silicon nitride. The first dielectric layer 132 can be a blocking layer, and the second dielectric layer 136 can be a tunneling layer. The dielectric structure 138 can be referred to as a "gate dielectric".

[0093] In the following description, various modification examples of the level (height) of the pad portion 140P of the vertical structure VS and the intermediate insulating layer 118 of the insulating structure 124 will be described with reference to Figure 13 and Figures 14A-14D respectively.

[0094] In one modification example, with reference to Figure 13 , the intermediate insulating layer 118 of the insulating structure 124 can be located at a level higher than the liner portion 140L, and can be an intermediate insulating layer 118b surrounding a portion of the pad portion 140P. The thickness of the intermediate insulating layer 118b can be smaller than the thickness of the pad portion 140P.

[0095] In another modification example, with reference to Figure 14A , the intermediate insulating layer 118 of the insulating structure 124 can be located at a level lower than the pad portion 140P, and can be an intermediate insulating layer 118c surrounding a portion of the liner portion 140L.

[0096] In the following description, a modification example of the contact region 140J between the second doped region 140Ld and the channel region 140Lc will be described with reference to Figure 13 .

[0097] In this modification example, with reference to Figure 14B , the contact region 140J' between the second doped region 140Ld and the channel region 140Lc can be located at a level lower than the first upper gate layer 162U1 among the gate layers 162 that is located at the highest level. For example, the contact region 140J' between the second doped region 140Ld and the channel region 140Lc can be located at a level between the first upper gate layer 162U1 among the gate layers 162 that is located at the highest level and the second upper gate layer 162U2 among the gate layers 162 that is located at the second highest level.

[0098] Referring back to Figure 13 , in this example embodiment, the thickness 115ta of the lower insulating layer 115 can be greater than the thickness 118ta of the intermediate insulating layer 118, the thickness 121ta of the upper insulating layer 121, the thickness 102t of each interlayer insulating layer 102, and the thickness 162t of each gate layer 162. The thickness 121ta of the upper insulating layer 121 can be greater than the thickness 118ta of the intermediate insulating layer 118. The thickness 118ta of the intermediate insulating layer 118 can be greater than the thickness 102t of each interlayer insulating layer 102. The thickness 118ta of the intermediate insulating layer 118 can be the same as, or greater than, the thickness 162t of each gate layer 162.

[0099] In the following description, various modification examples of the thicknesses of the lower insulating layer 115, the intermediate insulating layer 118, and the upper insulating layer 121 of the insulating structure 124 will be described with reference to Figure 14C Description. Figure 13 is a cross-sectional view showing portions of the lower insulating layer 115, the intermediate insulating layer 118, and the upper insulating layer 121 of the insulating structure 124, portions of the first upper gate layer 162U1 and the second upper gate layer 162U2 of the stacked structure 165, and portions of the interlayer insulating layer 102 between the first upper gate layer 162U1 and the second upper gate layer 162U2.

[0100] In one modification example, with reference to Figure 14D , the thickness 115tb of the lower insulating layer 115, the thickness 118tb of the intermediate insulating layer 118, and the thickness 121tb of the upper insulating layer 121 can be substantially the same. The thickness 115tb of the lower insulating layer 115, the thickness 118tb of the intermediate insulating layer 118, and the thickness 121tb of the upper insulating layer 121 can be greater than the thickness 162t of each gate layer 162 and the thickness 102t of each interlayer insulating layer 102. In this example embodiment, the thickness 162t of each gate layer 162 can be greater than the thickness 102t of each interlayer insulating layer 102.

[0101] In another modification example, with reference to Figure 13 , the thickness 118tc of the intermediate insulating layer 118 can be less than the thickness 115tc of the lower insulating layer 115 and the thickness 121tc of the upper insulating layer 121. The thickness 115tc of the lower insulating layer 115 can be substantially the same as the thickness 121tc of the upper insulating layer 121.

[0102] In another modification example, with reference to Figure 13 , the thickness 118td of the intermediate insulating layer 118 can be greater than the thickness 115td of the lower insulating layer 115 and the thickness 121td of the upper insulating layer 121.

[0103] In another modification example, with reference to Figures 14A-14D , the thickness 121te of the upper insulating layer 121 can be greater than the thickness 118te of the intermediate insulating layer 118 and the thickness 115te of the lower insulating layer 115. The thickness 115te of the lower insulating layer 115 can be greater than the thickness 118te of the intermediate insulating layer 118.

[0104] In another modification example, with reference to Figure 2 , the thickness 121tf of the upper insulating layer 121 and the thickness 118tf of the intermediate insulating layer 118 can be substantially the same, and the thickness 115tf of the lower insulating layer 115 can be greater than the thickness 121tf of the upper insulating layer 121 and the thickness 118tf of the intermediate insulating layer 118.

[0105] In another modified example, refer to Figure 3 The thickness 121tg of the upper insulating layer 121 can be greater than the thickness 118tg of the middle insulating layer 118 and the thickness 115tg of the lower insulating layer 115, and the thickness 118tg of the middle insulating layer 118 and the thickness 115tg of the lower insulating layer 115 can be substantially the same.

[0106] In the following description, an example of a semiconductor device will be referred to. Figures 6-8 and Figures 6-8 Description. About Figure 4 and Figure 14A , Figure 14B This is a top view showing a semiconductor device 10c according to an example embodiment. Figure 1 It shows along Figure 1 A cross-sectional view of the area intercepted by line I-I' in the diagram. Figure 1 It shows along Figure 1 A cross-sectional view of the area intercepted by line II-II' in the diagram. Figure 13 It shows along Figure 13 A cross-sectional view of the area intercepted by line III-III' in the diagram. Figure 15 It shows along Figure 15 A cross-sectional view of the area intercepted by line IV-IV'.

[0107] Reference Figure 13 and Figure 15 The stacked structure 165, the insulating structure 124, and the vertical structure VS can be disposed on the lower structure 50. The lower structure 50 can be... Figure 13 The lower structure 50a shown in the example implementation can be, or may be Figures 14A-14D The lower structure 50b is shown in the example implementation.

[0108] The stacking structure 165 can be disposed in the storage cell array region 20 and can extend from the storage cell array region 20 to the connection region 25.

[0109] The stacked structure 165 may include alternately stacked interlayer insulating layers 102 and gate layers 162. The interlayer insulating layers 102 may be formed of silicon oxide.

[0110] In the storage cell array region 20, as in the reference Figure 16 As described in the foregoing example embodiments, gate layer 162 may include one or more lower gate layers 162L (e.g., 162L1, 162L2 and 162L3), a plurality of intermediate gate layers 162M and one or more upper gate layers 162U (e.g., 162U1, 162U2, 162U3 and 162U4).

[0111] In the connection region 25, the gate layer 162 can have a pad region 162P arranged in a stepped form. Thus, the stacked structure 165 can have a stepped form in the connection region 25.

[0112] In this example embodiment, the vertical structure VS can extend in a third direction D3 perpendicular to the upper surface of the lower structure 50 and can penetrate the stacked structure 165 and the insulating structure 124, and can include Figure 17 the semiconductor pattern 140 including the channel region 140Lc and the doped regions 140Ld and 140Pd, the core pattern 142, and the dielectric structure 138 shown in the example in

[0113] The insulating structure 124 can include a lower insulating layer 115, an intermediate insulating layer 118, and an upper insulating layer 121 stacked in this order. The lower insulating layer 115 can include a first lower insulating layer 115a and a second lower insulating layer 115b that can correspond to the first lower insulating layer 15a and the second lower insulating layer 15b shown in the example in Figure 16 In this example embodiment, the first lower insulating layer 115a can overlap and self-align with the first upper gate layer 162U1 (the uppermost gate layer among the gate layers 162), and the second lower insulating layer 115b can have an upper surface that is coplanar with the upper surface of the first lower insulating layer 115a and can be provided on the stacked structure 165 in the connection region 25.

[0114] In this example embodiment, the intermediate insulating layer 118 can be in contact with the first lower insulating layer 115a and the second lower insulating layer 115b.

[0115] In this example embodiment, an insulating pattern 127 (in

[0116] ) that penetrates the insulating structure 124 and penetrates one or more of the upper gate layers 162U1, 162U2, 162U3, and 162U4 can be provided. Figure 17 A plurality of vertical structures VS can be provided. Among the plurality of vertical structures VS, a vertical structure that penetrates or is in contact with the insulating pattern 127 can be a dummy vertical structure VSd (in

[0117] ), and the remaining vertical structures can be vertical structures VS of the memory cells. The dummy vertical structure VSd among the plurality of vertical structures VS can not constitute Figure 13 a memory cell MC (in Figure 16 ). Figure 17The remaining vertical structures can constitute Figure 18A The storage unit MC shown in the example in Figure 18B The storage unit MC shown in the example in

[0118] The first cap insulating layer 150 and the second cap insulating layer 178 that are stacked in this order can be provided on the insulating structure 124 and the vertical structure VS. The first cap insulating layer 150 and the second cap insulating layer 178 can be formed of silicon oxide.

[0119] The partition structure 175 that extends in a third direction D3 perpendicular to the upper surface of the lower structure 50 and penetrates the stacked structure 165, the insulating structure 124, and the first cap insulating layer 150 can be provided. Each partition structure 175 can include a partition core pattern 173 and a spacer layer 170 provided on a side surface of the partition core pattern 173. In one example embodiment, the spacer layer 170 can be formed of an insulating material such as silicon oxide, and the partition core pattern 173 can be formed of a conductive material such as doped silicon or a metal. In another example embodiment, the partition core pattern 173 can be formed of an insulating material.

[0120] The partition structure 175 can include first partition structures 175a and second partition structures 175b provided between the first partition structures 175a. The stacked structure 165 can be provided between the first partition structures 175a. As shown in Figure 18A Each first partition structure 175a can have a length obtained in a first direction D1 parallel to the upper surface of the lower structure 50 that is greater than a length of each second partition structure 175b obtained in the first direction D1. As shown in Figure 18B A portion of the second partition structure 175b can span the storage unit array region 20 and can extend into a portion of the connection region 25, and the insulating pattern 127 can be provided between the second partition structure 175b that spans the storage unit array region 20 and extends into a portion of the connection region 25 and the first partition structure 175a among the second partition structures 175b.

[0121] A bit line contact plug 187 that penetrates the first cap insulating layer 150 and the second cap insulating layer 178 and is electrically connected to the pad portion 140P of the vertical structure VS can be provided.

[0122] In the connection region 25, a gate contact plug 184 that penetrates the first cap insulating layer 150 and the second cap insulating layer 178 and the insulating structure 124 and is electrically connected to the pad region 162P of the gate layer 162 can be provided. A bit line 190 can be provided on the bit line contact plug 187, and a gate connection wiring 192 can be provided on the gate contact plug 184. The bit line 190 can extend in a second direction D2 parallel to the upper surface of the lower structure 50.

[0123] In the following description, a modified example of the insulating structure 124 will be described with reference to Figure 18A . Figure 18B is a cross-sectional view showing a region taken along the line IV-IV' in Figure 18B .

[0124] In this modified example, with reference to Figure 18B , the insulating structure 124 can include the lower insulating layer 115, the intermediate insulating layer 118', and the upper insulating layer 121. The lower insulating layer 115 can include a first lower insulating layer 115a and a second lower insulating layer 115b' having upper surfaces of different heights. The first lower insulating layer 115a can be provided on the stack structure 165 in the memory cell array region 20, and the intermediate insulating layer 118' can be self-aligned with the first lower insulating layer 115a. The second lower insulating layer 115b' can have an upper surface that is coplanar with an upper surface of the intermediate insulating layer 118'. The second lower insulating layer 115b' can be provided on the stack structure 165 in the connection region 25. The upper insulating layer 121 can be in contact with the second lower insulating layer 115b' and the intermediate insulating layer 118'.

[0125] Referring back to Figure 18B and Figure 18B , the separation structure 175 can be in contact with the intermediate insulating layer 118. However, example embodiments are not limited thereto, and the separation structure 175 can be spaced apart from the intermediate insulating layer 118. One or more example configurations in which the separation structure 175 and the intermediate insulating layer 118 can be spaced apart from each other will be described with reference to Figure 18B and Figure 18B .

[0126] Figure 6 and Figure 7 are cross-sectional views showing a region taken along the line I-I' in Figure 6 , illustrating one or more example configurations in which the separation structure 175 and the intermediate insulating layer 118 can be spaced apart from each other.

[0127] In a modified example, with reference to Figure 7 , the buffer layer 151 can be provided between the separation structure 175 and the intermediate insulating layer 118. The buffer layer 151 can be provided on the stack structure 165. The buffer layer 151 can be provided between the separation structure 175 and the intermediate insulating layer 118, can extend to a region between the separation structure 175 and the lower insulating layer 115, and can further extend to a region between the separation structure 175 and the upper insulating layer 121. In addition, the buffer layer 151 can further extend to a region between the separation structure 175 and the first cap insulating layer 150.

[0128] For example, the buffer layer 151 can be formed of an insulating material such as silicon oxide or silicon nitride.

[0129] In this example embodiment, the buffer layer 151 can overlap the stack structure 165.

[0130] The buffer layer 151 can prevent defects between the doped regions 140Ld and 140Pd of the vertical structures VS adjacent to each other, together with the intermediate insulating layer 118 of the insulating structure 124.

[0131] In another modified example, referring to Figure 8 , a separation structure 175 can be provided in a separation trench 153 that penetrates the stack structure 165, the insulating structure 124, and the first cap insulating layer 150. A buffer spacer layer 154 that covers the upper sidewall of the separation trench 153 can be provided. The buffer spacer layer 154 can be located at a higher level than the stack structure 165. For example, the buffer spacer layer 154 can be formed of an insulating material such as silicon oxide or silicon nitride. The buffer spacer layer 154 can prevent defects between the doped regions 140Ld and 140Pd of the vertical structures VS adjacent to each other, together with the intermediate insulating layer 118 of the insulating structure 124. The buffer spacer layer 154 can be referred to as a “buffer layer”.

[0132] A modified example of a semiconductor device will be described with reference to Figure 8 and Figure 7 . Figure 7 is a perspective view that shows a modified example of a portion of the semiconductor device described in the foregoing example embodiment, provided in the memory cell array region 20. Figure 6 is a cross-sectional view that shows a modified example of a portion of the semiconductor device described in the foregoing example embodiment, provided in the memory cell array region 20 and the connection region 25.

[0133] In this modified example, referring to Figure 7 and Figure 6 , a lower stack structure 265, a lower insulating structure 224, an upper stack structure 365, and an upper insulating structure 324 can be provided on the lower structure 50. The lower stack structure 265, the lower insulating structure 224, the upper stack structure 365, and the upper insulating structure 324 can be provided in the memory cell array region 20 (in Figure 7 ) and can extend into the connection region 25 (in Figure 18B ). The lower stack structure 265 can have a lower pad region 262P (in Figure 18B ) arranged in the connection region 25 (in Figure 18B ) in a stepped form, and the upper stack structure 365 can have an upper pad region 362P (in Figure 18B ) arranged in the connection region 25 (in Figure 18B ) in a stepped form.

[0134] Each of the lower stack structure 265 and the upper stack structure 365 can have a structure identical or similar to that of the stack structure 165 shown in the example of Figure 18B and Figure 18B . For example, the lower stack structure 265 can include the first interlayer insulating layers 202 and the first gate layers 262 alternately stacked, and the upper stack structure 365 can include the second interlayer insulating layers 302 and the second gate layers 362 alternately stacked.

[0135] The vertical structure VS' can be provided on the lower structure 50. The vertical structure VS' can include a lower vertical structure VS_L and an upper vertical structure VS_U provided on the lower vertical structure VS_L. The lower vertical structure VS_L can penetrate the lower stack structure 265 and the lower insulating structure 224. The upper vertical structure VS_U can penetrate the upper stack structure 365 and the upper insulating structure 324. Each of the lower vertical structure VS_L and the upper vertical structure VS_U can have a structure identical or similar to that of the vertical structure VS shown in the example of Figure 18B , Figure 18B and Figure 18B . For example, the lower vertical structure VS_L can include the lower core pattern 242, the lower semiconductor pattern 240, and the lower dielectric structure 238, and the upper vertical structure VS_U can include the upper core pattern 342, the upper semiconductor pattern 340, and the upper dielectric structure 338. In this example embodiment, each of the lower dielectric structure 238 and the upper dielectric structure 338 can have a structure substantially identical to that of the dielectric structure 138 described with reference to Figure 18B .

[0136] The lower core pattern 242 and the upper core pattern 342 can be formed of an insulating material (e.g., silicon oxide, etc.). The lower semiconductor pattern 240 can include a lower pad portion 240P provided on the lower core pattern 242 and a lower liner portion 240L extending from an edge region of the lower pad portion 240P in a direction perpendicular to the upper surface of the lower structure 50. The upper semiconductor pattern 340 can include an upper pad portion 340P provided on the upper core pattern 342 and an upper liner portion 340L extending from an edge region of the upper pad portion 340P in a direction perpendicular to the upper surface of the lower structure 50.

[0137] The lower semiconductor pattern 240 can further extend from the lower liner portion 240L to a region between a bottom surface of the lower core pattern 242 and the lower structure 50. The upper semiconductor pattern 340 can further extend from the upper liner portion 340L to a region between a bottom surface of the upper core pattern 342 and the lower vertical structure VS_L. The upper liner portion 340L of the upper semiconductor pattern 340 can be in contact with the lower pad portion 240P of the lower semiconductor pattern 240.

[0138] The lower semiconductor pattern 240 may include a lower channel region 240Lc and lower doped regions 240Ld and 240Pd, and the upper semiconductor pattern 340 may include an upper channel region 340Lc and upper doped regions 340Ld and 340Pd.

[0139] The lower channel region 240Lc may be formed by the lower portion of the lower substrate portion 240L of the lower semiconductor pattern 240, and the lower doped regions 240Ld and 240Pd may include a first lower doped region 240Pd formed by the lower pad portion 240P of the lower semiconductor pattern 240 and a second lower doped region 240Ld extending from the first lower doped region 240Pd into the lower substrate portion 240L and formed by the upper portion of the lower substrate portion 240L.

[0140] The upper channel region 340Lc may be formed by the lower portion of the upper substrate portion 340L of the upper semiconductor pattern 340, and the upper doped regions 340Ld and 340Pd may include a first upper doped region 340Pd formed by the upper pad portion 340P of the upper semiconductor pattern 340 and a second upper doped region 340Ld extending from the first upper doped region 340Pd into the upper substrate portion 340L and formed by the upper portion of the upper substrate portion 340L.

[0141] In this example embodiment, the upper doped regions 340Ld and 340Pd and the lower doped regions 240Ld and 240Pd can be compared with a reference. Figure 18A The described doped regions 140Ld and 140Pd (in) Figure 18B (The two are basically the same)

[0142] In this example embodiment, each of the lower insulating structure 224 and the upper insulating structure 324 may have the same characteristics as... Figure 18B and Figure 18B The example shown in the image illustrates the insulation structure 124 (in...). Figure 18B and Figure 18B The structure is the same as or similar to the structure in the middle. For example, the lower insulating structure 224 may include a lower insulating layer 215, an intermediate insulating layer 218 and an upper insulating layer 221 stacked in sequence, and the upper insulating structure 324 may include a lower insulating layer 315, an intermediate insulating layer 318 and an upper insulating layer 321 stacked in sequence. In this example embodiment, the lower insulating layer 215 of the lower insulating structure 224 may include the uppermost first gate layer 262 (in the first gate layer 262) Figure 18B The first lower insulating layer 215a aligned with the middle) Figure 18B (in the middle) and cover the pad area 262P (in Figure 18B The second lower insulating layer 215b (in) Figure 18B middle).

[0143] In this example embodiment, the lower insulating layers 315 can include a first lower insulating layer 315a (in Figure 18B ) aligned with the uppermost one of the second gate layers 362 (in Figure 18B ) and a second lower insulating layer 315b (in Figure 18B ) covering the remaining upper pad regions 362P except the uppermost one of the upper pad regions 362P (in Figure 19 ).

[0144] The first cap insulating layer 150 (in Figure 19 ) and the second cap insulating layer 178 (in Figure 13 ) stacked in this order can be provided on the upper insulating structure 324. Bit line contact plugs 187 (in Figure 13 ) penetrating the first cap insulating layer 150 and the second cap insulating layer 178 (in Figure 19 ) and electrically connected to the upper pad portions 340P (in Figure 13 ) of the upper vertical structures VS_U of the vertical structures VS' can be provided. Bit lines 190 (in Figures 14A-14D ) can be provided on the bit line contact plugs 187 (in Figure 13 ).

[0145] Gate contact plugs 184 can be provided in the connection regions 25 (in Figures 14A-14D ). Some of the gate contact plugs 184 can be provided on the upper pad regions 362P (in Figures 20A-26B ) and can extend upward and can penetrate the upper insulating structure 324 (in Figures 20A-26B ), the first cap insulating layer 150 and the second cap insulating layer 178 (in Figure 20A ). Other ones of the gate contact plugs 184 (in Figure 21A ) can be provided on the lower pad regions 262P (in Figure 22A ) and can extend upward and can penetrate the lower insulating structure 224 (in Figure 23A ), the upper insulating structure 324 (in Figure 24 ), the first cap insulating layer 150 and the second cap insulating layer 178 (in Figure 25A ). Gate connection wirings 192 (in Figure 26A ) can be provided on the gate contact plugs 184 (in Figure 13 ).

[0146] The upper insulating structure 324 including the intermediate insulating layers 318 and the lower insulating structure 224 including the intermediate insulating layers 218 can prevent electrical short-circuit, current leakage, etc. from occurring between the gate contact plugs 184.

[0147] In the following description, a modified example of the vertical structure VS and the separation structure 175 described in the foregoing example embodiment will be described with reference to Figure 20B described above. Figure 21B is a cross-sectional view showing a region taken along a line I-I' in Figure 22B .

[0148] In this modified example, the lower structure 50, the stack structure 165, the insulating structure 124, the first cap insulating layer 150, and the second cap insulating layer 178 described above can be provided. Figure 23B and Figure 25B Figure 26B and Figure 13 described above.

[0149] A base insulating layer 405 can be provided between the lower structure 50 and the stack structure 165, and a horizontal connection pattern 410 can be provided on the base insulating layer 405.

[0150] A vertical structure VS that penetrates the stack structure 165 and the insulating structure 124 can be provided on the lower structure 50. The vertical structure VS can include the core pattern 142, the semiconductor pattern 140, and the dielectric structure 138 described above. Figure 13 and Figure 20A As described in the foregoing example embodiment, the semiconductor pattern 140 can include a liner portion 140L that surrounds a side surface of the core pattern 142.

[0151] The horizontal connection pattern 410 can be provided under the stack structure 165, can penetrate the dielectric structure 138, and can be connected to the liner portion 140L. For example, the horizontal connection pattern 410 can be in contact with the liner portion 140L. In an example embodiment, the horizontal connection pattern 410 can include polysilicon having N-type conductivity.

[0152] A separation structure 175 that penetrates the stack structure 165, the insulating structure 124, and the first cap insulating layer 150 can be provided. Each separation structure 175 can include a separation core pattern 173 and a spacer layer 170 provided on a side surface of the separation core pattern 173.

[0153] A lower pattern 415 can be provided between the separation structure 175 and the lower structure 50. In an example embodiment, the lower pattern 415 can be an epitaxial semiconductor layer formed from the lower structure 50 by an epitaxial process. In another example embodiment, the lower pattern 415 can be formed of polysilicon. In an example embodiment, the lower pattern 415 can include silicon having N-type conductivity.

[0154] In the following description, an example of a method of manufacturing a semiconductor device will be described with reference to Figure 20B described above. Regarding Figure 13 , Figure 21A ​、 Figure 21B , Figure 21B , Figure 21B , Figure 21A , Figure 21A and Figure 13 are cross-sectional views showing regions taken along lines I-I' in Figure 22A , Figure 22B , Figure 13 , Figure 23A , Figure 23B and Figure 7 are cross-sectional views showing regions taken along lines IV-IV' in Figure 7 Figure 23A

[0155] Referring to Figure 23B , Figure 13 and Figure 24 , a molding structure 106 including alternately stacked interlayer insulating layers 102 and molding layers 104 can be formed on the lower structure 50. The interlayer insulating layers 102 can be formed of silicon oxide, and the molding layers 104 can be formed of a material having etching selectivity with respect to the interlayer insulating layers 102. For example, the molding layers 104 can be formed of a material having etching selectivity with respect to the interlayer insulating layers 102, which can not be limited to any particular material. For example, when the interlayer insulating layers 102 are formed of silicon oxide, the molding layers 104 can be formed of a material having etching selectivity with respect to the silicon oxide, such as silicon nitride, polysilicon, etc.

[0156] A first lower insulating layer 115a can be formed on the molding structure 106. The first lower insulating layer 115a can be formed of silicon oxide.

[0157] A staircase structure can be formed by patterning the first lower insulating layer 115a and the molding structure 106. Accordingly, the interlayer insulating layers 102 and the molding layers 104 of the molding structure 106 can be alternately stacked in the memory cell array region 20, and can be formed in the connection region 25 adjacent to the memory cell array region 20 in a staircase structure.

[0158] Referring to Figure 13 , Figure 25A and Figure 25B , a second lower insulating layer 115b having an upper surface coplanar with an upper surface of the first lower insulating layer 115a (in Figure 13 ) can be formed. For example, the second lower insulating layer 115b (in Figure 26A ​​The middle) can include forming an insulating layer on the lower structure 50 having the first lower insulating layer 115a and the molding structure 106, and planarizing the insulating layer until the upper surface of the first lower insulating layer 115a is exposed. The first lower insulating layer 115a and the second lower insulating layer 115b can be included in the lower insulating layer 115.

[0159] The middle insulating layer 118 and the upper insulating layer 121 stacked in sequence can be formed on the lower insulating layer 115. The lower insulating layer 115, the middle insulating layer 118, and the upper insulating layer 121 stacked in sequence can be included in the insulating structure 124.

[0160] In this example embodiment, for example, the upper insulating layer 121 can be formed of the same material as that of the lower insulating layer 115, such as silicon oxide.

[0161] In this example embodiment, the middle insulating layer 118 can be formed of a material different from those of the lower insulating layer 115 and the upper insulating layer 121 and the material of the interlayer insulating layer 102. For example, the middle insulating layer 118 can be formed of a material having etching selectivity with respect to the lower insulating layer 115 and the upper insulating layer 121. For example, the lower insulating layer 115 and the upper insulating layer 121 and the interlayer insulating layer 102 can be formed of silicon oxide, and the middle insulating layer 118 can be formed of silicon nitride. In an example embodiment, the material of the middle insulating layer 118 can not be limited to silicon nitride, and can be replaced with an insulating material having etching selectivity with respect to the lower insulating layer 115 and the upper insulating layer 121 and the interlayer insulating layer 102.

[0162] In this example embodiment, the middle insulating layer 118 can be formed of a material different from that of the molding layer 104. For example, when the molding layer 104 is formed of polysilicon or is formed as an amorphous carbon layer, the middle insulating layer 118 can be formed of silicon nitride. For example, when the molding layer 104 is formed of silicon nitride, the middle insulating layer 118 can be formed of an insulating material different from silicon nitride.

[0163] An insulating pattern 127 (in the Figure 26B middle) can be formed to penetrate the insulating structure 124 and a portion of the molding structure 106. Figure 25A The insulating pattern 127 (in the middle) can be formed of silicon oxide.

[0164] Referring to Figure 25B , Figure 26A and Figure 26A , a vertical structure VS penetrating the molding structure 106 and the insulating structure 124 can be formed on the lower structure 50.

[0165] In this example embodiment, forming the vertical structure VS can include forming the hole 130 that penetrates the mold structure 106 and the insulating structure 124, forming the dielectric structure 138 on the sidewall of the hole 130, forming the liner portion 140L on the inner wall of the hole 130 that covers the dielectric structure 138, forming the core pattern 142 that partially fills the hole 130 in which the liner portion 140L is formed, and forming the pad portion 140P on the core pattern 142 that is connected to the liner portion 140L. The liner portion 140L, the portion between the lower surface of the core pattern 142 and the lower structure 50, and the pad portion 140P can be formed as the semiconductor pattern 140. The semiconductor pattern 140 can be formed of polysilicon.

[0166] With reference to Figure 13 , Figures 14A-14D and Figure 27 , the ion implantation process 148 can be performed. By the ion implantation process 148, the pad portion 140P of the semiconductor pattern 140 can be formed as the first doped region 140Pd, and a portion of the liner portion 140L of the semiconductor pattern 140 can be formed as the second doped region 140Ld.

[0167] In an example embodiment, a portion of the second doped region 140Ld can be opposite to the side surface of at least the uppermost mold layer among the mold layers 104.

[0168] In an example embodiment, a lower end portion of the second doped region 140Ld can be located at a level higher than the bottom surface of the insulating pattern 127. The second doped region 140Ld can be located at a level higher than the second uppermost mold layer among the mold layers 104.

[0169] In an example embodiment, the first doped region 140Pd and the second doped region 140Ld and the insulating structure 124 can include a first element that is doped by the ion implantation process 148. The first element can be a Group VA element in the periodic table, such as phosphorus (P) or arsenic (As). The first doped region 140Pd and the second doped region 140Ld can have N-type conductivity. In an example embodiment, in the insulating structure 124, the doping profile of the first element can have a maximum concentration at a first depth Rp (in Figure 27 ) from the upper surface of the semiconductor pattern 140 and the upper surface of the insulating structure 124. The first depth Rp (in Figure 13 ) can be located between the upper surface and the lower surface of the intermediate insulating layer 118. Thus, the first element in the insulating structure 124 can have a maximum concentration in the intermediate insulating layer 118. The first element is doped by the ion implantation process 148 Figure 13 and Figure 27The material of the intermediate insulating layer 118 doped therein with the maximum concentration can have etching selectivity with respect to the molding layer 104.

[0170] Referring to Figure 21A and Figure 21B , a first cap insulating layer 150 can be formed on the insulating structure 124. Also, a separation trench 153 penetrating the first cap insulating layer 150, the insulating structure 124, and the molding structure 106 can be formed. The side surface of the interlayer insulating layer 102, the side surface of the molding layer 104, and the side surface of the insulating structure 124 can be exposed through the separation trench 153.

[0171] Referring to Figures 22A-26B , Figure 15 and Figure 15 , the empty space 156 can be formed by selectively removing the molding layer 104 using an etching process. The interlayer insulating layer 102, the lower insulating layer 115, the intermediate insulating layer 118, and the upper insulating layer 121 can be formed of a material having etching selectivity with respect to the molding layer 104, and thus, can be preserved while the molding layer 104 is removed.

[0172] Referring to Figure 28 , Figure 29 and Figure 28 , a gate layer 162 can be formed in the empty space 156 (in Figure 29 and Figure 13 ). The gate layer 162 can include one or more lower gate layers 162L (e.g., a plurality of lower gate layers 162L1, 162L2, and 162L3 in Figure 13 ) stacked in order, a plurality of intermediate gate layers 162M, and one or more upper gate layers 162U (e.g., a plurality of upper gate layers 162U1, 162U2, 162U3, and 162U4 in Figure 28 ). The gate layer 162 and the interlayer insulating layer 102 can be included in a stacked structure 165.

[0173] A partition structure 175 can be formed to fill the partition trench 153. Forming the partition structure 175 may include forming a spacer layer 170 on the sidewall of the partition trench 153 and forming a partition core pattern 173 to fill the partition trench 153. A second cover insulating layer 178 may be formed on the partition structure 175 and the first cover insulating layer 150. Contact holes 181 that sequentially penetrate the first cover insulating layer 150, the second cover insulating layer 178, and the insulating structure 124 may be formed in the connection region 25 by performing an etching process. Contact holes 181 may expose the gate layer 162. By forming the intermediate insulating layer 118 with a material different from the materials of the first cover insulating layer 150, the second cover insulating layer 178, the upper insulating layer 121, and the lower insulating layer 115, the intermediate insulating layer 118 can be prevented from changing to an etch-sensitive property because the intermediate insulating layer 118 is doped with a first element. Therefore, during the etching process used to form the contact holes 181, defects such as excessive reduction of the gap between the contact holes 181 or the contact holes 181 connecting to each other due to over-etching of the intermediate insulating layer 118 doped with the first element can be prevented.

[0174] Return to reference Figure 24 , Figure 24 A gate contact plug 184 can be formed to fill the contact hole 181. Furthermore, a bit line contact plug 187 can be formed to penetrate the first cover insulating layer 150 and the second cover insulating layer 178 and be electrically connected to the pad portion 140P of the vertical structure VS. Additionally, a bit line 190 can be formed on the bit line contact plug 187, and a gate connection wiring 192 can be formed on the gate contact plug 184.

[0175] In the following description, a modified example of a method for manufacturing a semiconductor device according to an exemplary embodiment will be referred to. Figure 13 describe. Figure 29 It shows along Figure 25A A cross-sectional view of the area intercepted by line IV-IV'.

[0176] Reference Figure 25B and Figure 25AThe molding structure 106 including the interlayer insulating layers 102 and the molding layers 104 alternately stacked can be formed on the lower structure 50, the first lower insulating layer 115a and the intermediate insulating layer 118' can be sequentially formed on the molding structure 106, and the intermediate insulating layer 118', the first lower insulating layer 115a and the molding structure 106 can be patterned, thereby forming a stepped structure. Accordingly, the interlayer insulating layers 102 and the molding layers 104 of the molding structure 106 can be alternately stacked in the memory cell array region 20 and can be formed in the stepped structure in the connection region 25 adjacent to the memory cell array region 20, and the first lower insulating layer 115a and the intermediate insulating layer 118' can be self-aligned. The second lower insulating layer 115b' having an upper surface coplanar with an upper surface of the intermediate insulating layer 118' can be formed. For example, forming the second lower insulating layer 115b' can include forming an insulating layer on the lower structure 50 having the first lower insulating layer 115a, the intermediate insulating layer 118' and the molding structure 106, and planarizing the insulating layer until an upper surface of the intermediate insulating layer 118' is exposed. The first lower insulating layer 115a and the second lower insulating layer 115b' can be included in the lower insulating layer 115. The upper insulating layer 121 shown in the example of Figure 25B and Figure 26A may be formed, and the processes described with reference to Figure 26B may be performed. Accordingly, a semiconductor device including the insulating structure 124 shown in the example of Figure 26A (in Figure 26B ) can be manufactured.

[0177] In the following description, a modified example of a method of manufacturing a semiconductor device will be described with reference to Figure 16 and ​ . ​ and ​ are cross-sectional views showing regions taken along the line I-I' in ​ .

[0178] With reference to ​ and ​ , the method can further include forming a buffer layer 151 isolating at least the intermediate insulating layer 118 of the insulating structure 124 before forming the separation trench 153 described with reference to ​ . For example, forming the buffer layer 151 can include forming an opening penetrating the first cap insulating layer 150, the upper insulating layer 121 and the intermediate insulating layer 118 in sequence and exposing the first lower insulating layer 115a after forming the first cap insulating layer 150 as in the example shown in ​ , and filling the opening with a buffer material layer. In an example embodiment, the buffer layer 151 can be formed of silicon oxide.

[0179] With reference to ​ and ​The separation trenches 153 can be formed to sequentially penetrate the buffer layers 151, the first lower insulating layers 115a, and the molding structure 106.

[0180] In this example embodiment, the buffer layers 151 can be formed at positions where the separation trenches 153 are formed, and each of the buffer layers 151 can have a width greater than a width of each of the separation trenches 153. The buffer layers 151 can be isolated from each other by the separation trenches 153, and the buffer layers 151 that are spaced apart and reserved by the separation trenches 153 can cover side surfaces of the intermediate insulating layers 118.

[0181] The molding layer 104 can be removed by an etching process as described with reference to ​ and ​ , and the empty spaces 156 (in ​ and ​ ) can be formed. During the removal of the molding layer 104 by the etching process, the buffer layers 151 can protect the intermediate insulating layers 118 from the etching process. When the buffer layers 151 are formed as described above, a material used to form the intermediate insulating layers 118 can not be limited to any particular material, and can vary. For example, the intermediate insulating layers 118 can be formed of silicon oxide or silicon nitride.

[0182] The gate layer 162, the separation structure 175, and the second cap insulating layer 178 described with reference to ​ and ​ can be sequentially formed by performing processes described with reference to ​ and ​ . Accordingly, the semiconductor device described with reference to ​ can be manufactured.

[0183] In the following description, another modified example of a method of manufacturing a semiconductor device will be described with reference to Figure 30 . Figure 30 is a cross-sectional view illustrating a region taken along a line I-I' in Figure 13 .

[0184] With reference to Figure 13 and Figure 30 , after the separation trenches 153 shown in the example in Figure 24 are formed, the buffer layer 154 can be formed to cover an upper region of the insulating structure 124 and to cover the side surfaces of the intermediate insulating layers 118 of the insulating structure 124 exposed by the separation trenches 153. The buffer layer 154 can be formed using a deposition process that has a poor step coverage characteristic. Accordingly, after the buffer layer 154 is formed, the side surfaces of the intermediate insulating layers 118 can be covered by the buffer layer 154, but the molding layer 104 can be exposed by the separation trenches 153.

[0185] The molding layer 104 can be removed by an etching process as described with reference toFigure 25A and Figure 25B The through-etching process removes the buffer layer 154 and can form an empty space 156 (in Figure 25A and Figure 25B During the removal of the molding layer 104 by the etching process, the buffer layer 154 can protect the middle insulating layer 118 from the etching process.

[0186] Referring to Figure 26A and Figure 26B The gate layer 162 described with reference to Figure 26A and Figure 26B may be formed by performing the processes described with reference to

[0187] In an example embodiment, after the gate layer 162 is formed, the buffer layer 154 can be removed, and the separation structure 175 and the second cap insulating layer 178 described with reference to Figure 26A and Figure 26B may be sequentially formed. Accordingly, the semiconductor device described with reference to Figure 13 and Figures 14A-14D may be manufactured.

[0188] In another example embodiment, after the gate layer 162 is formed, the separation structure 175 and the second cap insulating layer 178 described with reference to Figure 26A and Figure 26B may be sequentially formed while the portion of the buffer layer 154 located in the separation trench 153 is retained. Accordingly, the semiconductor device described with reference to Figure 17 may be manufactured.

[0189] In the foregoing example embodiments described with reference to Figures 1-30 , by providing the middle insulating layer 118 surrounding the doped regions 140Ld and 140Pd of the vertical structure VS, defects occurring between the vertical structures VS located at a higher level than the stack structure 165 can be prevented. For example, by the ion implantation process 148 (in Figure 23A and Figure 23B ) for forming the doped regions 140Ld and 140Pd of the vertical structure VS as described above, the insulating structure 124 can include a first element, and a first depth (Rp) at which the projected range or the first element has the highest concentration can be formed in the middle insulating layer 118 in the insulating structure 124. By configuring the insulating structure 124 to include the lower insulating layer 115, the middle insulating layer 118, and the upper insulating layer 121 stacked in sequence as described above, and by forming the middle insulating layer 118 using a material different from those of the lower insulating layer 115 and the upper insulating layer 121, defects that can occur during a semiconductor process can be prevented. For example, as in Figure 25A and Figure 25BAs in the foregoing example embodiment described, because the material of the intermediate insulating layer 118 doped with the first element by the ion implantation process 148 (in Figure 23A and Figure 23B , can have etching selectivity with respect to the mold layer 104, the intermediate insulating layer 118 doped with the first element by the ion implantation process 148 (in Figure 25A and Figure 25B , can remain without being etched or damaged during the formation of the empty space 156 (in Figure 23A and Figure 23B , by removing the mold layer 104. Thus, the insulating structure 124 including the intermediate insulating layer 118 can prevent defects from occurring between the doped regions 140Ld and 140Pd of the vertical structures VS adjacent to each other.

[0190] In the foregoing example embodiment, defects that can occur during an etching process for forming the contact holes 181 (in Figure 26A and Figure 26B , for forming the gate contact plugs 184 electrically connected to the gate layers 162 of the stack structures 165 can be prevented. For example, gaps between the gate contact plugs 184 can become narrow due to high density, and the intermediate insulating layer 118 doped with the first element by the ion implantation process 148 (in Figure 26A and 26B , can remain without being etched or damaged during the etching process for forming the contact holes 181 (in Figure 23A and Figure 23B , Thus, the insulating structure 124 including the intermediate insulating layer 118 can prevent defects such as electrical short, current leakage, etc. from occurring between the gate contact plugs 184 formed in the contact holes 181 (in Figure 26A and Figure 26B .

[0191] Thus, according to the foregoing example embodiment, a semiconductor device including stack structures and insulating structures stacked in sequence and vertical structures penetrating the stack structures and the insulating structures can be provided. The insulating structure can include a lower insulating layer, an intermediate insulating layer, and an upper insulating layer stacked in sequence. The intermediate insulating layer can prevent defects from occurring between portions of the vertical structures located at a higher level than the stack structures.

[0192] Although example embodiments have been shown and described above, it will be obvious to those skilled in the art that modifications and changes can be made without departing from the scope of the present application as defined by the appended claims.

[0193] This application claims priority to Korean Patent Application No. 10-2019-0037916, filed on April 1, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a stack structure; a lower structure, wherein the stack structure is disposed on the lower structure; an insulating structure disposed on the stack structure; a vertical structure extending in a direction perpendicular to an upper surface of the lower structure, wherein the vertical structure includes a side surface opposite to a side surface of the stack structure and opposite to a side surface of the insulating structure; and a contact plug on and contacting the vertical structure, wherein at least a portion of the stack structure includes a plurality of interlayer insulating layers and a plurality of gate layers, wherein the plurality of interlayer insulating layers and the plurality of gate layers are alternately stacked, wherein the insulating structure includes a lower insulating layer, an intermediate insulating layer, and an upper insulating layer, wherein the intermediate insulating layer is disposed on the lower insulating layer, wherein the upper insulating layer is disposed on the intermediate insulating layer, wherein a material of the intermediate insulating layer is different from a material of the lower insulating layer and a material of the upper insulating layer, wherein the intermediate insulating layer exhibits an etching selectivity with respect to the upper insulating layer and the lower insulating layer, wherein the vertical structure includes a core pattern, a channel region on a side surface of the core pattern, and a pad portion on the core pattern, and wherein the contact plug contacts the pad portion.

2. The semiconductor device of claim 1, wherein the intermediate insulating layer includes a dopant, and wherein the dopant includes an element of Group VA of the Periodic Table.

3. The semiconductor device of claim 1, wherein a thickness of the intermediate insulating layer is greater than a thickness of each of the plurality of interlayer insulating layers.

4. The semiconductor device of claim 1, wherein a thickness of the intermediate insulating layer is greater than a thickness of each of the plurality of gate layers.

5. The semiconductor device of claim 1, wherein the stack structure is disposed in a memory cell array region and at least partially extends into a connection region adjacent to the memory cell array region, wherein the plurality of gate layers includes a plurality of pad regions, wherein the plurality of pad regions are arranged in a staircase form in the connection region, wherein the lower insulating layer includes a first lower insulating layer and a second lower insulating layer, wherein the second lower insulating layer is disposed adjacent to the first lower insulating layer, wherein the plurality of gate layers includes an uppermost gate layer, wherein the first lower insulating layer overlaps the uppermost gate layer, and wherein the second lower insulating layer overlaps the pad region.

6. The semiconductor device of claim 5, wherein a thickness of the first lower insulating layer is greater than a thickness of each of the plurality of interlayer insulating layers.

7. The semiconductor device of claim 5, wherein a thickness of the first lower insulating layer is greater than a thickness of each of the plurality of gate layers.

8. The semiconductor device of claim 5, wherein the first lower insulating layer and the second lower insulating layer are disposed below the intermediate insulating layer.

9. The semiconductor device of claim 5, wherein the intermediate insulating layer is disposed between the first lower insulating layer and the upper insulating layer, and wherein the upper insulating layer is in contact with the second lower insulating layer. ​ 10. The semiconductor device of claim 1, wherein a side surface of the pad portion is opposite to the side surface of the insulating structure.

11. The semiconductor device of claim 10, wherein at least a portion of the pad portion is located at a same level as at least a portion of the intermediate insulating layer.

12. The semiconductor device of claim 10, wherein the intermediate insulating layer is located at a lower level than the pad portion.

13. The semiconductor device of claim 1, wherein the pad portion and the insulating structure comprise a first element that is doped, and wherein a doping concentration of the first element in the intermediate insulating layer is higher than a doping concentration of the first element in the upper insulating layer and the lower insulating layer.

14. A semiconductor device, comprising: a stack structure; a lower structure, wherein the stack structure is disposed on the lower structure; an insulating structure disposed on the stack structure; a vertical structure extending in a direction perpendicular to an upper surface of the lower structure, wherein the vertical structure penetrates the stack structure and penetrates the insulating structure; a cap insulating layer, wherein the cap insulating layer is disposed on the insulating structure and on the vertical structure; a partition structure, wherein the partition structure extends in the direction perpendicular to the upper surface of the lower structure, and wherein the partition structure penetrates the stack structure, penetrates the insulating structure, and penetrates the cap insulating layer; and a contact plug penetrating the cap insulating layer and contacting the vertical structure, wherein the insulating structure comprises a lower insulating layer, an intermediate insulating layer, and an upper insulating layer, wherein the intermediate insulating layer is disposed on the lower insulating layer, wherein the upper insulating layer is disposed on the intermediate insulating layer, wherein a material of the intermediate insulating layer is different from a material of the lower insulating layer and a material of the upper insulating layer, wherein the intermediate insulating layer exhibits an etch selectivity with respect to the upper insulating layer, and wherein the vertical structure comprises a core pattern, a trench region on a side surface of the core pattern, and a doped region on the core pattern.

15. The semiconductor device of claim 14, wherein at least a portion of the stack structure comprises a plurality of gate layers and a plurality of interlayer insulating layers, wherein the plurality of interlayer insulating layers and the plurality of gate layers are alternately stacked, wherein the material of the intermediate insulating layer is different from a material of the interlayer insulating layers, wherein the intermediate insulating layer comprises a dopant, and wherein the dopant comprises a Group VA element of the periodic table.

16. The semiconductor device of claim 15, wherein a thickness of each of the plurality of interlayer insulating layers is less than a thickness of the lower insulating layer and a thickness of the intermediate insulating layer.

17. The semiconductor device of claim 15, further comprising: a buffer layer disposed on the stack structure and between the partition structure and the intermediate insulating layer.

18. A semiconductor device, comprising: a stack structure; a lower structure, wherein the stack structure is disposed on the lower structure; an insulating structure disposed on the stack structure; ​ a vertical structure extending in a direction perpendicular to an upper surface of the lower structure, wherein the vertical structure penetrates the stack structure and penetrates the insulating structure; a cap insulating layer, wherein the cap insulating layer is disposed on the insulating structure and on the vertical structure; a gate contact plug, wherein the gate contact plug penetrates the cap insulating layer and penetrates the insulating structure; and a bit line contact plug penetrating the cap insulating layer and contacting the vertical structure, wherein the insulating structure comprises a lower insulating layer, an intermediate insulating layer, and an upper insulating layer, wherein the intermediate insulating layer is disposed on the lower insulating layer, wherein the upper insulating layer is disposed on the intermediate insulating layer, wherein a material of the intermediate insulating layer is different from a material of the lower insulating layer and a material of the upper insulating layer, wherein the intermediate insulating layer exhibits an etch selectivity with respect to the upper insulating layer and the lower insulating layer, and wherein the vertical structure comprises a core pattern, a channel region on a side surface of the core pattern, and a pad portion on the core pattern.

19. The semiconductor device of claim 18, wherein the stack structure comprises an interlayer insulating layer and a gate layer, wherein the gate contact plug is electrically connected to a pad region of the gate layer, wherein the intermediate insulating layer comprises a dopant, and wherein the dopant comprises a group VA element of the periodic table.

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