Display device comprising an electrostatic barrier line

Abstract

A display apparatus includes a substrate having a display area and a non-display area. A driver is disposed in the non-display area and includes a driver circuit having a transistor and a driver control line that transmits a control signal to the driver circuit. An electrostatic barrier line is disposed in the non-display area and encircles the display area. The electrostatic barrier line at least partially overlaps the driver.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, to display devices that include electrostatic discharge blocking lines. Background Technology

[0002] Organic light-emitting diode (OLED) display devices include display panels manufactured by forming light-emitting elements and circuit elements for driving the light-emitting elements on a substrate.

[0003] A display panel can primarily include the display area where a screen is formed, but specific areas of the display panel, specifically the edge areas, can be non-display areas where no image is displayed. These non-display areas are typically covered by the bezel of the display device, and therefore, the smaller the non-display area, the fewer bezels can exist in the display device. Driver circuits, signal lines, etc., can be located in the non-display area.

[0004] Display devices are typically integrated into various electronic devices (e.g., smartphones, tablet PCs, laptops, televisions, monitors, etc.). These display devices can achieve a large screen-to-body ratio by reducing the size of the non-display area.

[0005] In order to reduce the non-display area of ​​a display device, components located in the non-display area may be designed to have a smaller size or be omitted, which may degrade the reliability of the display device. Summary of the Invention

[0006] A display device according to an exemplary embodiment of the present disclosure includes a substrate having a display area and a non-display area. A driver is disposed in the non-display area and includes a driver circuit having transistors and a driver control line for transmitting control signals to the driver circuit. An electrostatic discharge (ESD) barrier line is disposed in the non-display area and surrounds the display area. The ESD barrier line overlaps with the driver.

[0007] The electrostatic blocking line can at least partially overlap with the driver circuitry.

[0008] The electrostatic discharge barrier line may at least partially overlap with the driver control line.

[0009] The display device may further include a dam disposed in a non-display area and at least partially surrounding the display area. The dam may at least partially overlap with an electrostatic barrier line.

[0010] The width of the electrostatic barrier line can be smaller than the width of the bottom surface of the dam body, and the dam body can completely cover the electrostatic barrier line.

[0011] The dam body may include a lower layer and an upper layer set on the lower layer, and the electrostatic blocking line may be set between the lower layer and the upper layer.

[0012] Static electricity blocking lines can be installed in the upper part of the dam body.

[0013] The width of the electrostatic barrier line can be greater than the width of the bottom surface of the dam body, and the dam body can cover a portion of the electrostatic barrier line.

[0014] The display device may further include a light-emitting element disposed in the display area. The light-emitting element may include a first electrode, an emitting layer disposed on the first electrode, and a second electrode disposed on the emitting layer. The second electrode may extend to the area where the dam is located, and thus may cover the upper part of the dam outside the display area.

[0015] The display device may further include an encapsulation layer that covers the display area and seals the light-emitting elements. The electrostatic discharge (ESD) barrier lines may include multiple ESD barrier lines extending parallel to each other. A portion of the multiple ESD barrier lines may be covered by the encapsulation layer, while another portion may not be covered.

[0016] The electrostatic discharge (ESD) barrier lines may include multiple ESD barrier lines extending parallel to each other. The display device may further include connecting lines that connect the multiple ESD barrier lines to each other. The connecting lines can transmit a common voltage to the multiple ESD barrier lines.

[0017] The display device may further include a mask support that is positioned further away from the display area than the dam in the non-display area, and the mask support may overlap at least partially with only one of a plurality of electrostatic blocking lines while surrounding the display area.

[0018] A display device according to an exemplary embodiment of the present invention includes a first substrate, the first substrate including a display area and a non-display area. A plurality of transistors are disposed on the first substrate. A first electrode is disposed on a first transistor in the display area among the plurality of transistors and is electrically connected to one electrode of the first transistor. An emitter layer is disposed on the first electrode. A second electrode is disposed on the emitter layer. A contact layer is disposed between one electrode of the first transistor and the first electrode, and electrically connects the one electrode of the first transistor to the first electrode by contact with them. An electrostatic discharge (ESD) barrier line is disposed in the non-display area at the same layer as the contact layer, and the ESD barrier line at least partially surrounds the display area.

[0019] The display device may further include a driver having driver circuitry and driver control lines, the driver circuitry including a second transistor among a plurality of transistors disposed in a non-display area, and the driver control lines transmitting control signals to the driver circuitry. Electrostatic discharge (ESD) blocking lines may at least partially overlap with the driver.

[0020] The display device may further include a dam body disposed in a non-display area, at least partially surrounding the display area, and at least partially overlapping an electrostatic barrier line.

[0021] The width of the electrostatic barrier line can be smaller than the width of the bottom surface of the dam body, and the dam body can completely cover the electrostatic barrier line.

[0022] The width of the electrostatic barrier line can be greater than the width of the bottom surface of the dam body, and the dam body can cover a portion of the electrostatic barrier line.

[0023] The second electrode can extend to the area where the dam body is located, and thus can cover the upper part of the dam body in the non-display area.

[0024] A display device according to an exemplary embodiment of the present invention includes a substrate having a display area and a non-display area. First to third electrostatic blocking lines are disposed in the non-display area and thus at least partially surround the display area. The first to third electrostatic blocking lines extend parallel to each other. A first dam is disposed in the non-display area, at least partially surrounding the display area and at least partially overlapping the first electrostatic blocking line. A second dam is disposed in the non-display area, at least partially surrounding the display area and at least partially overlapping the second electrostatic blocking line. A mask support is disposed in the non-display area, at least partially surrounding the display area and at least partially overlapping the third electrostatic blocking line. Connecting lines connect the first to third electrostatic blocking lines to each other and transmit a common voltage to the first to third electrostatic blocking lines.

[0025] The display device may further include a light-emitting element disposed in the display area. An encapsulation layer may cover the display area and seal the light-emitting element. A first and second electrostatic discharge (ESD) barrier line may be covered by the encapsulation layer, while a third ESD barrier line may not be covered by the encapsulation layer.

[0026] According to an exemplary embodiment of the present invention, circuits such as driver circuits disposed in the non-display area of ​​the display panel can be protected from electrostatic discharge while reducing the size of the non-display area. Attached Figure Description

[0027] A more complete understanding of this disclosure and its many accompanying aspects will be readily acquired and better understood by referring to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a top view illustrating a display device according to an exemplary embodiment of the present invention;

[0029] Figure 2 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0030] Figure 3 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0031] Figure 4 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0032] Figure 5 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0033] Figure 6 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0034] Figure 7 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0035] Figure 8 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0036] Figure 9 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0037] Figure 10 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0038] Figure 11 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0039] Figure 12 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0040] Figure 13 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0041] Figure 14 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0042] Figure 15 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0043] Figure 16 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment;

[0044] Figure 17 This is a schematic cross-sectional view illustrating a display device according to an exemplary embodiment of the present invention; and

[0045] Figure 18 This is an equivalent circuit diagram illustrating a pixel in a display device according to an exemplary embodiment of the present invention. Detailed Implementation

[0046] In the following detailed description, exemplary embodiments of the invention have been shown and described for illustrative purposes. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit and scope of the invention.

[0047] Therefore, the accompanying drawings and description should be considered as illustrations of one or more specific exemplary embodiments of the invention, and should not be construed as depicting all embodiments of the invention or as limiting the invention. Throughout the specification and drawings, the same reference numerals may refer to the same elements.

[0048] For clarity, the dimensions and thicknesses of various elements shown in the figures may be exaggerated, such as the thickness of layers, regions, etc.

[0049] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element or there may be an intermediate element present.

[0050] In addition, unless explicitly stated otherwise, the word “including” and variations such as “comprising” or “having” will be understood to imply inclusion of the stated element but not exclusion of any other element, and the use of the phrase “consisting of” will be understood to imply exclusive inclusion of the stated element without any other element.

[0051] In the accompanying drawings, the symbol x represents a first direction, the symbol y represents a second direction perpendicular to the first direction, and the symbol z represents a third direction perpendicular to both the first and second directions. Therefore, the symbols x, y, and z are understood as Cartesian coordinates; however, the structure shown can be rotated in any way from where it is shown.

[0052] In the following description, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 This is a top view illustrating a display device according to an exemplary embodiment of the present invention.

[0054] refer to Figure 1 The display device 1 includes a display panel 10, which includes a display area DA and a non-display area NA. From a plan view, the display area DA and the non-display area NA can occupy different areas. Figure 1 In the diagram, the inner side of the dashed quadrilateral used to separate the display area DA from the non-display area NA corresponds to the display area DA, and the outer side of the dashed quadrilateral corresponds to the non-display area NA.

[0055] In the display panel 10, the display area DA corresponds to the screen displaying the image. Circuits and / or signal lines that generate and / or transmit various signals applied to the display area DA can be disposed in a non-display area NA at the periphery of the display area DA. The non-display area NA can at least partially surround the display area DA. For example, the non-display area NA can surround the display area DA on one side, two sides, three sides, or all four sides.

[0056] The display panel 10 includes multiple pixels (PX), multiple gate lines (also called scan lines), multiple data lines, and drive voltage lines. Each pixel (PX) is connected to the gate lines, data lines, and drive voltage lines. Each pixel (PX) can receive gate signals (also called scan signals), data signals, and drive voltages from the signal lines. Each pixel (PX) may include a light-emitting element. The light-emitting element may be, for example, an organic light-emitting element. In the display area DA, signal lines such as sensing lines, light-emitting control signal lines, and / or other signal lines may be further provided.

[0057] A touch sensor layer can be set in the display area DA to sense user touch (e.g., touch that makes contact with the display device) or non-touch (e.g., touch that brings an object close to the display device).

[0058] exist Figure 1 The example shows a quadrilateral-shaped display area DA, but the display area DA can have various shapes such as polygons, circles, ellipses, etc., or can have any shape such as a polygonal shape with rounded corners.

[0059] The non-display area NA of the display panel 10 may include pad portions PP, which include pads for receiving signals from the outside of the display panel 10. The pad portions PP may be disposed along the edge of the display panel 10. For example, the pad portions PP may extend along one edge of the display panel 10 in a first direction x. The display device 1 may include a flexible printed circuit board bonded to the pad portions PP. The pads of the flexible printed circuit board may be electrically connected to the pads of the pad portions PP. Depending on the size of the display panel 10, the display panel 10 may include a plurality of pad portions PP spaced apart from each other at predetermined intervals in the first direction x, and each pad portion PP may be bonded to a flexible printed circuit board. Figure 1 The example shows that the pad portion PP is provided at the lower end of the display panel 10, but the pad portion PP may be provided at the upper end of the display panel 10 or at both the lower and upper ends of the display panel 10.

[0060] Display device 1 includes a driving unit disposed in a non-display area NA of display panel 10. The driving unit can generate and / or process various signals for driving display panel 10. The driving unit may include: a data driver that applies data signals to data lines, a gate driver GD that applies gate signals to gate lines, and a signal controller that controls the data driver and the gate driver GD.

[0061] The display panel 10 may include a first substrate 110, which includes a display area DA and a non-display area NA. A gate driver GD may be integrated with the non-display area NA of the first substrate 110. The gate driver GD may be disposed on two opposite sides of the display area DA or on one side of the display area DA. A data driver may be provided in the form of an IC chip and may be disposed in a flexible printed circuit board connected to a pad portion PP or in the non-display area NA of the display panel 10. A signal controller may be provided in the form of an IC chip and may be disposed in a printed circuit board bonded to a flexible printed circuit board. The data driver and the signal controller may each be provided in the form of an integrated circuit (IC).

[0062] A gate driver GD, located in the non-display area NA, is connected to the gate line and applies a gate signal to the pixel PX. The gate driver GD can be integrated with the non-display area NA. The gate driver GD receives a vertical start signal, a clock signal, and a low-voltage driver control signal corresponding to the gate cutoff signal from a signal controller, generates a gate signal (e.g., a gate on-voltage and a gate off-voltage), and applies the gate signal to the gate line. The gate driver GD includes driver circuitry (also called a shift resistor) that generates and outputs the gate signal using the driver control signal. The driver circuitry includes stages connected to each other in a correlated manner. Additionally, the gate driver GD includes driver control signal lines that transmit the driver control signal to these stages. These stages are connected one-to-one to the gate line, allowing the gate signal to be sequentially output to the gate line for each frame.

[0063] Each stage includes a transistor and at least one capacitor. Some of the driver control signals can be provided from units other than the signal controller.

[0064] The display panel 10 includes an encapsulation layer EN that completely covers the display area DA. The encapsulation layer EN seals the display area DA (specifically, its light-emitting elements) to prevent moisture or oxygen from penetrating into the display panel 10, specifically into the display area DA. The edge of the encapsulation layer EN may be positioned between the edge of the display panel 10 and the display area DA.

[0065] The non-display area NA may include an electrostatic discharge (ESD) barrier line EP, which protects the driver circuitry of the non-display area NA or the pixels PX in the display area DA from electrostatic discharge. The ESD barrier line EP may be arranged in a closed loop around the display area DA in the non-display area NA. The ESD barrier line EP may be formed from at least one layer of a multilayer conductive material included in the display panel 10. Multiple ESD barrier lines EP may be provided. The ESD barrier line EP may be maintained at ground voltage or common voltage.

[0066] As in Figure 1 As exemplarily shown, the electrostatic discharge (ESD) barrier lines EP may include a first ESD barrier line EP1, a second ESD barrier line EP2, and a third ESD barrier line EP3 that extend parallel to each other and are concentric with each other. When the first ESD barrier line EP1, the second ESD barrier line EP2, and the third ESD barrier line EP3 are arranged sequentially in order of their distance from the display area DA, the first ESD barrier line EP1 and the second ESD barrier line EP2 are covered by the encapsulation layer EN, and the third ESD barrier line EP3 may not be covered by the encapsulation layer EN. The first to third ESD barrier lines EP1, EP2, and EP3 may each at least partially overlap with the gate driver GD.

[0067] The first to third electrostatic blocking lines EP1, EP2, and EP3 may extend primarily in the first direction x at the upper and lower edges of the display panel 10, and primarily in the second direction y at the left and right edges of the display panel 10. The first to third electrostatic blocking lines EP1, EP2, and EP3 may be connected to each other via connecting lines EPL disposed on at least one edge of the display panel 10. For example, in Figure 1 As exemplarily illustrated, the connecting line EPL can connect the first to third electrostatic blocking lines EP1, EP2, and EP3 at the upper edge of the display panel 10. Depending on the exemplary embodiment, the connecting line EPL can connect the first to third electrostatic blocking lines EP1, EP2, and EP3 at the lower edge of the display panel 10, or it can connect the first to third electrostatic blocking lines EP1, EP2, and EP3 at the left edge and / or right edge of the display panel 10.

[0068] In the following text, reference will be made to Figures 2 to 4 as well as Figure 1 An exemplary embodiment of the cross-sectional structure of the display panel 10 will be described in detail below.

[0069] Figure 2 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 3 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 4 This shows the section intercepted along line BB'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 2 and Figure 3 The cross-sectional structure of the non-display area NA at the upper edge of the display panel 10 is shown. Figure 4 The diagram shows a cross-sectional view of a portion of the display area DA and the non-display area NA at the left edge of the display panel 10. The outer perimeter of the right edge of the display panel 10 is approximately symmetrical with respect to the outer perimeter of the left edge of the display panel 10.

[0070] First, the gate driver GD includes a driver circuit DC and a driver control line DS disposed adjacent to each other in the non-display area NA. The driver circuit DC may include a transistor TRd. The driver circuit DC is disposed in the driver circuit region DCR, and the driver control line DS is disposed in the driver control line region DSR. The driver circuit region DCR and the driver control line region DSR extend in a second direction y between the edge of the display panel 10 and the display area DA, respectively. The driver circuit region DCR may be positioned closer to the display area DA than the driver control line region DSR. The driver control line DS is electrically connected to the driver circuit DC and can transmit vertical start signals, clock signals, low voltages of a specific level, etc., to the driver circuit DC. At least one of the driver control lines DS may be disposed in the driver circuit region DCR, or may be disposed between the driver circuit region DCR and the display area DA.

[0071] In the cross-sectional view, the display panel 10 includes a first substrate 110, and a plurality of layers, wiring, and components formed on the first substrate 110. The display panel 10 may include a second substrate 210, which is bonded to the first substrate 110 by a sealant 300. A plurality of pixels PX are disposed in the display area DA of the display panel 10, and each pixel PX includes a transistor, a capacitor, and a light-emitting element. However, in Figure 4 The image shows a transistor TRp and a light-emitting element LD connected to it. Additionally, the driver circuit DC for the non-display area NA includes transistors and capacitors, but... Figure 4 The image shows several transistors, TRd.

[0072] The first substrate 110 can be a rigid substrate formed of glass, quartz, ceramic, etc. Alternatively, the first substrate 110 can be a flexible substrate formed of a polymer such as polyimide.

[0073] A buffer layer 120 is disposed on a first substrate 110, a first insulating layer 140 is disposed on the buffer layer 120, and a second insulating layer 160 may be disposed on the first insulating layer 140.

[0074] A light-shielding layer LB can be disposed between the first substrate 110 and the buffer layer 120. The light-shielding layer LB prevents the semiconductor layer Ap from being degraded by preventing external light from reaching the semiconductor layer Ap of the transistor TRp. Current leakage of the transistor TRp (specifically, the driving transistor whose current characteristics are important in an organic light-emitting diode display) can be controlled. The light-shielding layer LB can comprise a material that does not transmit light of a specific wavelength or wavelength range to be blocked, and can be formed, for example, from a conductive material such as a metal or metal alloy. Therefore, the light-shielding layer LB can function as an electrode receiving a specific voltage in the display panel 10. In this case, the rate of change of current in the saturation region of the voltage-current characteristic diagram of the transistor TRp is reduced, thereby improving its functional characteristics as a driving transistor. The light-shielding layer LB can be electrically connected to another transistor (e.g., a switching transistor) or a signal line (e.g., a driving voltage line), or it can be in a floating state. The light-shielding layer LB can be disposed below the transistor TRd of the driver circuit DC.

[0075] The buffer layer 120 disposed on the light-shielding layer LB can prevent impurities from being dispersed from the first substrate 110 into the semiconductor layers Ap and Ad during the formation of the semiconductor layers Ap and Ad, and can reduce the stress applied to the first substrate 110. The buffer layer 120 may include an inorganic insulating material such as silicon oxide or silicon nitride.

[0076] Semiconductor layers Ap and Ad of transistors TRp and TRd can be disposed between buffer layer 120 and first insulating layer 140. Semiconductor layers Ap and Ad can include a channel region, a source region, and a drain region that at least partially overlap with gate electrodes Gp and Gd. The source and drain regions are doped and disposed on opposite sides of the channel region. Semiconductor layers Ap and Ad can include polycrystalline silicon, amorphous silicon, or oxide semiconductor.

[0077] The first insulating layer 140 disposed on the semiconductor layers Ap and Ad may include an inorganic insulating layer such as silicon oxide or silicon nitride. The first insulating layer 140 may be referred to as a gate insulating layer.

[0078] The gate conductors of the gate electrodes Gp and Gd of transistors TRp and TRd, including the gate line, driver control line DS, and transistors TRp and TRd, can be disposed between the first insulating layer 140 and the second insulating layer 160. The gate conductors can include metals or metal alloys such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti), or can be a multilayer of titanium (Ti) / molybdenum (Mo). The driver control line DS can be located on the same layer as the gate conductor. In this specification, "the same layer" or "forming the same layer" means that the constituent elements are formed from the same material in the same process. For example, the driver control line DS can be formed from the same material as the gate conductor through the same process and through the same one or more steps.

[0079] The second insulating layer 160 disposed on the first insulating layer 140 and the gate conductor may comprise an inorganic insulating material such as silicon oxide or silicon nitride. The second insulating layer 160 may also be referred to as an interlayer insulating layer.

[0080] The data conductors, including the data lines, drive voltage lines, common voltage lines VC, and the source electrodes Sp and Sd and drain electrodes Dp and Dd of transistors TRp and TRd, can be disposed on the second insulating layer 160.

[0081] The source electrodes Sp and Sd, and the drain electrodes Dp and Dd, can be connected to the source and drain regions of the semiconductor layers Ap and Ad through contact holes formed in the first insulating layer 140 and the second insulating layer 160. One of the source electrode Sp and the drain electrode Dp can be connected to the light-shielding layer LB through contact holes formed in the buffer layer 120, the first insulating layer 140, and the second insulating layer 160.

[0082] The common voltage line VC can transmit a power supply voltage with a predetermined level, which can be applied to the light-emitting element LD or driver circuit DC of the pixel PX. For example, the common voltage line VC can transmit a common voltage ELVSS or a ground voltage. One end of the common voltage line VC can be electrically connected to the pad portion PP. The common voltage line VC can surround the display area DA, or it can be formed into a rod shape extending along the edge of the display panel 10 in the first direction x and the second direction y.

[0083] The data conductor may include metals such as copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), or alloys of one or more of these metals. The data conductor may be multilayered, for example, titanium / copper (Ti / Cu), titanium / aluminum (Ti / Al), titanium / copper / titanium (Ti / Cu / Ti), titanium / aluminum / titanium (Ti / Al / Ti), or molybdenum / aluminum / titanium (Mo / Al / Ti). At least a portion of the common voltage line VC may be formed on the same layer as the data conductor; for example, it may be formed from the same material as the data conductor using the same process. The common voltage line VC may be formed on the same layer as the data conductor.

[0084] The gate electrode Gp, source electrode Sp, and drain electrode Dp, together with the semiconductor layer Ap, form the transistor TRp. The gate electrode Gd, source electrode Sd, and drain electrode Dd, together with the semiconductor layer Ad, form the transistor TRd. Figure 4 In the structure shown, the drain electrode Dp is connected to the light-shielding layer LB through contact holes formed in the buffer layer 120, the first insulating layer 140, and the second insulating layer 160. In transistors TRp and TRd, the gate electrodes Gp and Gd are located above the semiconductor layers Ap and Ad, but the structure of the transistor is not limited to this and can be modified in various ways.

[0085] A third insulating layer 181, comprising an inorganic insulating material such as silicon nitride or silicon oxide, may be disposed on the second insulating layer 160 and the data conductor. The third insulating layer 181, as an inorganic insulating layer, may also be referred to as a passivation layer. Depending on the exemplary embodiment, the third insulating layer 181 may be omitted.

[0086] The first to third electrostatic discharge (ESD) barriers EP1, EP2, and EP3, along with the contact layer CT, can be disposed on the third insulating layer 181. The first to third ESD barriers EP1, EP2, and EP3 and the contact layer CT can be the same layer. For example, the first to third ESD barriers EP1, EP2, and EP3, along with the contact layer CT, can be formed from the same material using the same process. For example, the first to third ESD barriers EP1, EP2, and EP3, along with the contact layer CT, can be formed from a transparent conductive oxide such as ITO or IZO. Alternatively, the contact layer CT can be formed from the same material using the same process as one layer of the pads in the pad portion PP.

[0087] In the left and right edges of the display panel 10, a first electrostatic blocking line EP1 and a second electrostatic blocking line EP2 may be disposed in the driver circuit region DCR, and a third electrostatic blocking line EP3 may be disposed in the driver control line region DSR. In some exemplary embodiments of the present invention, the first to third electrostatic blocking lines EP1, EP2 and EP3 may be disposed in the driver control line region DSR.

[0088] The first to third electrostatic blocking lines EP1, EP2, and EP3 can extend parallel to each other primarily in the first direction x at the upper and lower edges of the display panel 10. For example... Figure 3 As exemplarily shown, the connecting line EPL is located in the same layer as the first to third electrostatic barrier lines EP1, EP2, and EP3 and the contact layer CT. The connecting line EPL extends primarily in the second direction y from the contact layer CT above the common voltage line VC to the third electrostatic barrier line EP3. Therefore, the first to third electrostatic barrier lines EP1, EP2, and EP3 are connected to each other via the connecting line EPL and are electrically connected to the common voltage line VC, and thus can receive the common voltage ELVSS. The connecting line EPL can transmit the common voltage ELVSS to the first to third electrostatic barrier lines EP1, EP2, and EP3.

[0089] The contact layer CT can be connected to the common voltage line VC and the drain electrode Dp of the transistor TRp through contact holes formed in the third insulating layer 181. The contact layer CT can protect the common voltage line VC and the drain electrode Dp of the transistor TRp during the process of forming the first electrode E1 of the light-emitting element LD. Depending on the exemplary embodiment, the contact layer CT can be omitted.

[0090] A fourth insulating layer 182, comprising an organic insulating material, may be disposed on the third insulating layer 181 and the contact layer CT. For example, the fourth insulating layer 182 may be an organic insulating layer, which may include polyimide, acrylic polymers, siloxane polymers, etc. The fourth insulating layer 182 may also be referred to as a planarization layer. The fourth insulating layer 182 may cover at least a portion of the driver circuit DC.

[0091] The first electrode E1 of the light-emitting element LD can be disposed on the fourth insulating layer 182. The first electrode E1 is connected to the contact layer CT through a contact hole formed in the fourth insulating layer 182, and can be electrically connected to the drain electrode Dp through the contact layer CT. The first electrode E1 may include metals or metal alloys such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum-neodymium (AlNd), aluminum-nickel-lanthanum (AlNiLa), etc. The first electrode E1 may include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). The first electrode E1 may be a multilayer of ITO / silver (Ag) / ITO, ITO / aluminum (Al), etc.

[0092] A fifth insulating layer 360 having an opening that at least partially overlaps with the first electrode E1 may be disposed on the fourth insulating layer 182. The opening of the fifth insulating layer 360 may define each pixel region, and the fifth insulating layer 360 may also be referred to as a pixel defining layer. The fifth insulating layer 360 may be an organic insulating layer comprising an organic insulating material.

[0093] An emitter layer EL is disposed on the first electrode E1. The emitter layer EL is disposed in the pixel region defined by the opening of the fifth insulating layer 360.

[0094] The second electrode E2 is disposed on the emitting layer EL. The second electrode E2 can cover the entire display area DA. The second electrode E2 extends into the non-display area NA and thus can contact the contact layer CT, which is connected to the common voltage line VC. Therefore, the second electrode E2 can be subjected to the common voltage ELVSS. The second electrode E2 can be formed of a thin metal layer with a low work function, such as calcium (Ca), barium (Ba), magnesium (Mg), and aluminum (Al), and thus can be transparent. As used herein, the phrase "low work function metal" can refer to any metal having a work function within the range of said metals, or a metal having a work function lower than that of any said metal. The second electrode E2 can include a transparent conductive material such as ITO, IZO, etc.

[0095] The second electrode E2 can extend to the driver circuit region DCR in the non-display area NA, and thus can form a shielding layer SL that at least partially overlaps with the driver circuit DC. For example, the shielding layer SL overlapping with the driver circuit DC can be formed in the same layer as the second electrode E2. The first electrostatic blocking line EP1 and the second electrostatic blocking line EP2 can at least partially overlap with the second electrode E2 (e.g., the shielding layer SL). The third electrostatic blocking line EP3 may not overlap with the second electrode E2. Because the shielding layer SL is connected to the second electrode E2, a common voltage ELVSS can be applied to the shielding layer SL.

[0096] When static electricity is introduced, the transistor TRd forming the driver circuit DC may be damaged because the transistor TRd is susceptible to static electricity. The shielding layer SL can shield the driver circuit DC to prevent it from being damaged by static electricity during the manufacturing process of the display device 1 or during handling of the display device 1. The shielding layer SL can cover at least a portion, almost all of the driver circuit DC, or the entire driver circuit DC. When the driver circuit DC is provided, the shielding layer SL can extend primarily in the second direction y.

[0097] The first electrode E1, the emitting layer EL, and the second electrode E2 of each pixel PX form a light-emitting element LD, such as an organic light-emitting diode (OLED). The first electrode E1 can be the anode of the OLED, and the second electrode E2 can be the cathode. The first electrode E1 can be referred to as the pixel electrode, and the second electrode E2 can be referred to as the common electrode. The light-emitting element LD can be configured to emit blue or white light. Alternatively, the light-emitting element LD can be configured to emit three primary colors of light, such as red, green, and blue light.

[0098] A capping layer 371 is disposed on the second electrode E2, and a functional layer 372 may be disposed on the capping layer 371. The capping layer 371 can be used to improve light efficiency by adjusting the refractive index. The functional layer 372 can prevent damage to the underlying layer of the encapsulation layer EN during its formation and also increases light efficiency. The capping layer 371 may include an inorganic insulating material, and the functional layer 372 may include a material such as lithium fluoride. Compared to the second electrode E2, the capping layer 371 may extend further from the display area DA to the non-display area NA, allowing it to contact the third insulating layer 181 in the non-display area NA. The functional layer 372 may extend from the display area DA to the non-display area NA in the same way as the second electrode E2, but may extend less than the second electrode E2 or to the same extent as the capping layer 371. Depending on the exemplary embodiment, the capping layer 371 and the functional layer 372 may cover a portion of the shielding layer SL.

[0099] The encapsulation layer EN can be disposed on the cover layer 371 and the functional layer 372. The encapsulation layer EN can prevent external moisture or oxygen from penetrating by encapsulating the light-emitting element LD. The encapsulation layer EN can cover the entire display area DA. The edge of the encapsulation layer EN can be disposed in the non-display area NA. The distance between the edge of the encapsulation layer EN and the display area DA can be greater than the distance between the driver circuit area DCR and the display area DA.

[0100] The encapsulation layer EN may include one or more inorganic layers and one or more organic layers. For example, in... Figures 2 to 4As exemplarily shown, the encapsulation layer EN can be a thin-film encapsulation layer comprising a first inorganic layer 391, an organic layer 392, and a second inorganic layer 393. In the encapsulation layer EN, the first inorganic layer 391 and the second inorganic layer 393 prevent moisture penetration, and the organic layer 392 serves to planarize the surface of the encapsulation layer EN (specifically, the surface of the second inorganic layer 393 in the display area DA). The first inorganic layer 391 and the second inorganic layer 393 may each comprise an inorganic insulating material such as silicon oxide or silicon nitride. The organic layer 392 may comprise an organic material such as acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, or perylene resins.

[0101] The first inorganic layer 391 and the second inorganic layer 393 are each wider than the organic layer 392. The first inorganic layer 391 and the second inorganic layer 393 can contact each other at the periphery of the edge of the encapsulation layer EN. The edges of the first inorganic layer 391 and the second inorganic layer 393 can substantially correspond to each other. The first inorganic layer 391 can contact the cover layer 371 at the periphery of the encapsulation layer EN. Therefore, the third insulating layer 181, the cover layer 371, the first inorganic layer 391 and the second inorganic layer 393 are sequentially stacked on the periphery of the encapsulation layer EN, thereby achieving contact between the inorganic layers. As described, the first inorganic layer 391 and the second inorganic layer 393 are formed to be wider, thereby achieving contact between the inorganic layers, and therefore, moisture or oxygen can be more firmly prevented from penetrating through the sides of the display area DA, or the penetration path of moisture or oxygen can be made longer and more complex to delay the penetration of moisture or oxygen.

[0102] Dams DM1 and DM2 can be disposed in the non-display area NA. Dams DM1 and DM2 prevent the loss of organic materials, such as monomers, during the formation of the organic layer 392 of the encapsulation layer EN, and therefore, the edges of the organic layer 392 of the encapsulation layer EN can be disposed inside the dams DM1 and DM2, for example, between the dams DM1 and DM2 and the display area DA. The first inorganic layer 391 and the second inorganic layer 393 of the encapsulation layer EN can extend above the dams DM1 and DM2, so that they can cover the dams DM1 and DM2. In this case, the contact area between the first inorganic layer 391 and the second inorganic layer 393 is increased, thereby increasing the adhesion between the first inorganic layer 391 and the second inorganic layer 393.

[0103] Dams DM1 and DM2 at least partially overlap with the gate driver GD in the region where the gate driver GD is located. When dams DM1 and DM2 are formed as described above, the increase in the non-display area NA can be prevented. Therefore, the width of the non-display area NA can be reduced, or more wiring or components can be formed in the non-display area NA, and design margin can be increased. For example, compared to the case where dams DM1 and DM2 are formed between the gate driver GD and the display area DA, or at the outer edge of the gate driver GD, the width of the non-display area NA can be reduced to a greater extent. Therefore, the screen ratio of the display device 1 can be increased. (As in...) Figure 4 As exemplarily illustrated, dam bodies DM1 and DM2 may be located in the driver circuit region DCR. Depending on the exemplary embodiment, dam bodies DM1 and DM2 may be located in the driver control line region DSR, or may be located in both the driver circuit region DCR and the driver control line region DSR.

[0104] The dams DM1 and DM2 may include a first dam DM1 positioned closer to the display area DA, and a second dam DM2 positioned further away from the display area DA. The first dam DM1 may at least partially overlap with a first electrostatic blocking line EP1, and the second dam DM2 may at least partially overlap with a second electrostatic blocking line EP2. For example, the first dam DM1 may at least partially surround the display area DA along the first electrostatic blocking line EP1, and the second dam DM2 may at least partially surround the display area DA along the second electrostatic blocking line EP2.

[0105] The width of the first electrostatic barrier line EP1 can be smaller than the width of the bottom surface of the first dam body DM1. The width of the second electrostatic barrier line EP2 can be smaller than the width of the bottom surface of the second dam body DM2. By completely covering the first electrostatic barrier line EP1, the first dam body DM1 can directly contact not only the top surface of the first electrostatic barrier line EP1, but also its side surface. The bottom surface of the first dam body DM1 can directly contact the first electrostatic barrier line EP1 and the third insulating layer 181. By completely covering the second electrostatic barrier line EP2, the second dam body DM2 can directly contact not only the top surface of the second electrostatic barrier line EP2, but also its side surface. The bottom surface of the second dam body DM2 can directly contact the second electrostatic barrier line EP2 and the third insulating layer 181.

[0106] Dam bodies DM1 and DM2 can be formed as at least one layer. Dam bodies DM1 and DM2 can be formed using an insulating layer formed in the display area DA. For example, when dam bodies DM1 and DM2 are formed as a single layer, they can be formed from a layer identical to the fourth insulating layer 182 or the fifth insulating layer 360. (As in...) Figure 2 and Figure 3 As exemplarily shown, when the dam bodies DM1 and DM2 are formed as multiple layers, the first layers L11 and L21 forming the lower layers can be formed from the same layers as the fourth insulating layer 182, and the second layers L12 and L22 forming the upper layers can be formed from the same layers as the fifth insulating layer 360.

[0107] Even when the first dam DM1 or its lower layer L11 is formed on the same layer as the fourth insulating layer 182, the first dam DM1 is still separately disposed from the fourth insulating layer 182. When the first dam DM1 is adhered to or formed continuously with the fourth insulating layer 182, a space for accommodating the organic material that forms the organic layer 392 of the encapsulation layer EN cannot be formed before the first dam DM1.

[0108] Even when both the first dam body DM1 and the second dam body DM2 are formed as multiple layers, the second dam body DM2 can be formed to be higher than the first dam body DM1. For example, when forming the fifth insulating layer 360 and the upper layers L12 and L22, the upper layer L22 of the second dam body DM2 can be formed to be higher than the upper layer L12 of the first dam body DM1 by using a halftone mask. According to an exemplary embodiment of this disclosure, the first dam body DM1 and the second dam body DM2 can have approximately equal heights.

[0109] The second electrode E2 of the light-emitting element LD extends to the area where the dams DM1 and DM2 are located, such that the second electrode E2 of the light-emitting element LD can at least partially cover the upper part of the dams DM1 and DM2 in the non-display area NA. The second electrode E2 can contact the upper surface and side surface of the upper layers L12 and L22 of the dams DM1 and DM2, and can contact the side surface of the lower layers L11 and L21 of the dams DM1 and DM2.

[0110] The mask support MS can be disposed in the non-display area NA. The first inorganic layer 391 and the second inorganic layer 393 of the emitter layer EL, the second electrode E2, the capping layer 371, the functional layer 372, and the encapsulation layer EN can be formed by deposition using a metal mask, in which the regions where the corresponding layers are formed are exposed. The mask support MS supports the metal mask. The distance between the mask support MS and the display area DA can be greater than the distance between the dams DM1 and DM2 and the display area DA. The mask support MS can be formed in the same layer as the fourth insulating layer 182 or in the same layer as the fifth insulating layer 360.

[0111] The mask support MS can at least partially overlap with the third electrostatic barrier line EP3. For example, the mask support MS can at least partially surround the display area DA along the third electrostatic barrier line EP3. The width of the third electrostatic barrier line EP3 can be smaller than the width of the bottom surface of the mask support MS. By completely covering the third electrostatic barrier line EP3, the mask support MS can directly contact not only the top surface of the third electrostatic barrier line EP3, but also its side surfaces. The bottom surface of the mask support MS can directly contact the third electrostatic barrier line EP3 and the third insulating layer 181.

[0112] A second substrate 210, bonded to the first substrate 110 by a seal 300 disposed along the edge of the display panel 10, is disposed on the encapsulation layer EN. In the area where the pad portion PP is located, for example at the lower end of the display panel 10, the second substrate 210 may be shorter than the first substrate 110, so that the pad portion PP is exposed to the outside in order to bond the printed circuit film.

[0113] The seal 300 is formed to completely surround the display area DA. The seal 300 bonds the first substrate 110 to the second substrate 210 and prevents impurities such as moisture and oxygen from penetrating between the first substrate 110 and the second substrate 210. Therefore, the display area DA can be hermetically sealed by the combination of the first substrate 110, the second substrate 210, and the seal 300 between them. A sealing material is applied to the first substrate 110 and / or the second substrate 210, with the first substrate 110 and the second substrate 210 placed face-to-face, the sealing material positioned between the first substrate 110 and the second substrate 210. The seal 300 is then formed by irradiating the area coated with the sealing material using a laser beam. The applied sealing material can be a frit, such as a glass frit. When the sealing material is irradiated with a laser beam and then heated, the sealing material melts and thus adheres to the first substrate 110 and the second substrate 210 like an adhesive. The sealing material, which is thus bonded to the first substrate 110 and the second substrate 210, is then cured, thereby forming a hermetically sealed seal 300 between the first substrate 110 and the second substrate 210. As described above, the display area DA is also sealed by the encapsulation layer EN, and therefore the display area DA can be double-sealed.

[0114] The seal 300 may overlap with at least a portion of the gate driver GD, specifically with the driver control line region DSR. As described, when the seal 300 at least partially overlaps with the driver control line region DSR, the area of ​​the non-display regions NA on the left and right sides of the display region DA can be reduced, thereby reducing the width of the left and right bezels of the display device 1.

[0115] The second substrate 210 can be formed of a transparent and rigid material such as glass, quartz, or ceramic. The second substrate 210 can be spaced apart from the encapsulation layer EN by a predetermined distance.

[0116] The light-shielding member 220 and color filters 230R, 230G, and 230B can be disposed on the surface of the second substrate 210 facing the first substrate 110. Color filters 230R, 230G, and 230B can respectively include a red color filter 230R, a green color filter 230G, and a blue color filter 230B. A capping layer can be disposed on the color filters 230R, 230G, and 230B.

[0117] The light-shielding member 220 is formed in a region that substantially excludes the pixel region (e.g., the region overlapping with the emission layer EL), and the light-shielding member 220 prevents light transmission in regions other than the pixel region. The light-shielding member 220 can be disposed between the red color filter 230R and the green color filter 230G, between the green color filter 230G and the blue color filter 230B, and between the blue color filter 230B and the red color filter 230R. The light-shielding member 220 can divide the region in which the red color filter 230R, the green color filter 230G, and the blue color filter 230B are disposed.

[0118] When the light-emitting element (LD) is configured to emit blue light, the red filter 230R converts blue light to red light, the green filter 230G converts blue light to green light, and the blue filter 230B directly transmits blue light. Therefore, the red filter 230R and the green filter 230G can be referred to as color conversion layers, while the blue filter 230B can be referred to as a transmission layer. The red filter 230R may include quantum dots and / or phosphors for converting blue light to red light. The green filter 230G may include quantum dots and / or phosphors for converting blue light to green light. The blue filter 230B may include a light-transmitting resin and may further include dyes or pigments. A blue light cutoff filter (e.g., a yellow filter) that transmits wavelengths other than the blue wavelength band and blocks the blue wavelength band can be disposed between the red filter 230R and the second substrate 210, and between the green filter 230G and the second substrate 210.

[0119] A touch sensor layer, including touch electrodes for sensing touch (e.g., contact touch or non-contact touch), may be disposed on the second substrate 210, and a polarization layer may be disposed on the second substrate 210 to reduce the reflection of external light.

[0120] In the following text, reference will be made to Figures 5 to 7 as well as Figure 1 An exemplary embodiment of the cross-sectional structure of the display panel will be described below. The above will be the primary description. Figures 1 to 4Differences between exemplary embodiments. Where detailed descriptions of elements are omitted, it may be assumed that those elements are at least similar to corresponding elements described elsewhere in this disclosure.

[0121] Figure 5 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 6 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 7 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment.

[0122] The first to third electrostatic barrier lines EP1, EP2, and EP3 may not be located in the same layer as the contact layer CT, but may be located in the same layer as the first electrode E1 of the light-emitting element LD. For example, the first to third electrostatic barrier lines EP1, EP2, and EP3 may be formed from the same material using the same process as the first electrode E1 of the light-emitting element LD.

[0123] A first electrostatic barrier line EP1 can be disposed between the lower layer L11 and the upper layer L12 of the first dam body DM1, and a second electrostatic barrier line EP2 can be disposed between the lower layer L21 and the upper layer L22 of the second dam body DM2. The width of the first electrostatic barrier line EP1 can be smaller than the width of the bottom surface of the upper layer L12. By completely covering the first electrostatic barrier line EP1, the upper layer L12 of the first dam body DM1 can directly contact not only the top surface of the first electrostatic barrier line EP1, but also its side surface. The width of the second electrostatic barrier line EP2 can be smaller than the width of the bottom surface of the upper layer L22 of the second dam body DM2. The upper layer L22 of the second dam body DM2 completely covers the second electrostatic barrier line EP2, so that the upper layer L22 can directly contact not only the upper surface of the second electrostatic barrier line EP2, but also its side surface.

[0124] The mask support MS is formed on the same layer as the fifth insulating layer 360 and can completely cover the third electrostatic blocking line EP3, which is located on the same layer as the first electrode E1 of the light-emitting element LD.

[0125] The connecting line EPL can extend from the contact layer CT on the common voltage line VC to the third electrostatic barrier line EP3. The first electrostatic barrier line EP1 and the second electrostatic barrier line EP2 can be connected to the connecting line EPL through contact holes formed in the lower layer L11 of the first dam body DM1 and contact holes formed in the lower layer L21 of the second dam body DM2, respectively.

[0126] Excluding this difference, refer to Figures 1 to 4Features of the exemplary embodiments described can be applied to the reference Figures 5 to 7 The exemplary embodiments described herein, and therefore, refer to Figures 1 to 4 Redundant features of the exemplary embodiments described will not be described, and should be assumed to be at least similar to the features of corresponding elements described elsewhere in this specification.

[0127] In the following text, reference will be made to Figures 8 to 10 as well as Figure 1 An exemplary embodiment of the cross-sectional structure of the display panel 10 will be described herein. The description will primarily focus on... Figures 1 to 4 The differences between the described contents should be taken into account, and it should be assumed that any element not described in detail is at least similar to the corresponding element described elsewhere in this specification.

[0128] Figure 8 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 9 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 10 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment.

[0129] The first to third electrostatic barrier lines EP1, EP2, and EP3 may not be located in the same layer as the contact layer CT, but may be located in the same layer as the second electrode E2 of the light-emitting element LD. For example, the first to third electrostatic barrier lines EP1, EP2, and EP3 may be formed from the same material using the same process as the second electrode E2 of the light-emitting element LD.

[0130] The second electrode E2 of the light-emitting element LD is not directly connected to any of the first to third electrostatic blocking lines EP1, EP2, and EP3, and is connected to the connecting member CM. The connecting member CM is disposed on the fourth insulating layer 182 and can be electrically connected to the common voltage line VC through the contact layer CT. For this purpose, the third insulating layer 181 and the fourth insulating layer 182, which overlap with the common voltage line VC, can be partially removed. Since the connecting member CM is connected to the common voltage line VC, the second electrode E2 can be electrically connected to the common voltage line VC through the connecting member CM. The connecting member CM can be located on the same layer as the first electrode E1 of the light-emitting element LD.

[0131] The first electrostatic barrier line EP1 can be disposed above the first dam body DM1. The first electrostatic barrier line EP1 can be disposed above the upper layer L12 of the first dam body DM1. For example, the first electrostatic barrier line EP1 can contact the top surface of the upper layer L12 of the first dam body DM1.

[0132] The second electrostatic barrier line EP2 can be positioned above the second dam body DM2. The second electrostatic barrier line EP2 can be positioned above the upper layer L22 of the second dam body DM2. For example, the second electrostatic barrier line EP2 can contact the upper surface of the upper layer L22 of the second dam body DM2.

[0133] The third electrostatic barrier line EP3 can be disposed above the mask support MS. The mask support MS can be formed on the same layer as the fourth insulating layer 182 or the fifth insulating layer 360.

[0134] The connecting line EPL can extend from the contact layer CT on the common voltage line VC to the third electrostatic barrier line EP3. The first electrostatic barrier line EP1 and the second electrostatic barrier line EP2 can be connected to the connecting line EPL respectively through contact holes formed in the lower layer L11 and upper layer L12 of the first dam DM1 and the lower layer L21 and upper layer L22 of the second dam DM2. The third electrostatic barrier line EP3 can be connected to the connecting line EPL through contact holes formed in the mask support MS.

[0135] In the region where the gate driver GD is located, the shielding layer SL can be disposed between the third insulating layer 181 and the fourth insulating layer 182. The shielding layer SL can be disposed between the third insulating layer 181 and the dam bodies DM1 and DM2, and can receive the common voltage ELVSS by contacting the contact layer CT on the common voltage line VC. The shielding layer SL can be located on the same layer as the contact layer CT.

[0136] Excluding this difference, refer to Figures 1 to 4 Features of the exemplary embodiments described can be applied to the reference Figures 8 to 10 The exemplary embodiments described herein, and therefore, refer to Figures 1 to 4 Redundant features of the exemplary embodiments described will not be described, and it should be assumed that those undescribed elements are at least similar to their counterparts described elsewhere in this specification.

[0137] In the following text, we will combine Figures 11 to 13 as well as Figure 1 The exemplary embodiments of the present invention will be described using the cross-sectional structure of the display panel shown herein. The description here will primarily focus on... Figures 1 to 4 The differences between the described contents.

[0138] Figure 11 This shows the section intercepted along line A-A'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 12 This shows the section intercepted along line A”-A”'. Figure 1 A schematic cross-sectional view of an exemplary embodiment. Figure 13 This shows the section intercepted along line B-B'. Figure 1A schematic cross-sectional view of an exemplary embodiment.

[0139] The width of the first electrostatic blocking line EP1 is greater than the width of the bottom surface of the first dam DM1, the width of the second electrostatic blocking line EP2 is greater than the width of the bottom surface of the second dam DM2, and the width of the third electrostatic blocking line EP3 is greater than the width of the bottom surface of the mask support MS. For example, the first dam DM1 partially covers the first electrostatic blocking line EP1, the second dam DM2 partially covers the second electrostatic blocking line EP2, and the mask support MS partially covers the third electrostatic blocking line EP3. For example, the first dam DM1 covers approximately 80% of the top surface of the first electrostatic blocking line EP1, the second dam DM2 covers approximately 80% of the top surface of the second electrostatic blocking line EP2, and the mask support MS covers approximately 80% of the top surface of the third electrostatic blocking line EP3.

[0140] Since the width of the first electrostatic blocking line EP1 is greater than the width of the bottom surface of the first dam DM1, the second electrode E2 of the light-emitting element LD covering the first dam DM1 can contact the first electrostatic blocking line EP1. Similarly, since the width of the second electrostatic blocking line EP2 is greater than the width of the bottom surface of the second dam DM2, the second electrode E2 of the light-emitting element LD covering the second dam DM2 can contact the second electrostatic blocking line EP2.

[0141] Excluding this difference, refer to Figures 1 to 4 Features of the exemplary embodiments described can be applied to the reference Figures 11 to 13 The exemplary embodiments described herein, and therefore, refer to Figures 1 to 4 Redundant features of the exemplary embodiments described will not be described, and it should be assumed that those undescribed elements are at least similar to their counterparts described elsewhere in this specification.

[0142] In the example above, dams DM1 and DM2 are located in the driver circuit region DCR within the region where the gate driver GD is located, but dams DM1 and DM2 can also be located in the driver control line region DSR.

[0143] In the following text, reference will be made to Figures 14 to 16 This describes an exemplary embodiment in which dam bodies DM1 and DM2 are disposed in the driver control line region DSR within the region where the gate driver GD is located. The description here will primarily focus on... Figure 4 The differences between the described contents should be taken into account, and it should be assumed that any element not described in detail is at least similar to the corresponding element described elsewhere in this specification.

[0144] Figure 14 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment.

[0145] refer to Figure 14 The contact layer CT on the common voltage line VC and the connecting member CM connected thereto can be disposed on the fourth insulation layer 182.

[0146] A fourth insulating layer 182 is formed to cover at least a portion of the driver circuit DC, and a shielding layer SL overlapping the driver circuit DC can be disposed on the fourth insulating layer 182. The shielding layer SL can shield the driver circuit DC to prevent it from being damaged by electrostatic discharge during the manufacturing process of the display device 1 or during handling of the display device 1. The shielding layer SL can cover at least a portion, almost all of the driver circuit DC, or the entire driver circuit DC. When the driver circuit DC is disposed, the shielding layer SL can extend primarily in the second direction y. The shielding layer SL can be electrically and physically connected to the connecting member CM, and can be electrically connected to the common voltage line VC through the connecting member CM and the contact layer CT. The shielding layer SL and the connecting member CM, which is a conductive layer, can be located in the same layer as the first electrode E1. For example, the shielding layer SL and the connecting member CM can be formed from the same material using the same process as the first electrode E1.

[0147] The second electrode E2 is connected to the connecting member CM. Since the connecting member CM is electrically connected to the common voltage line VC, the second electrode E2 can be electrically connected to the common voltage line VC through the connecting member CM. Therefore, when the common voltage line VC transmits the common voltage ELVSS, the second electrode E2 can receive the common voltage ELVSS.

[0148] The capping layer 371 and the functional layer 372 may be generally formed on the shielding layer SL. The capping layer 371 and the functional layer 372 may cover a portion of the shielding layer SL, or they may completely cover the shielding layer SL. The bottom surface of the capping layer 371 may contact the top surface of the shielding layer SL.

[0149] Dam bodies DM1 and DM2 are located in the driver control line region DSR, but may not be located in the driver circuit region DCR. Additionally, the first to third electrostatic discharge blocking lines EP1, EP2, and EP3 are also located in the driver control line region DSR.

[0150] Excluding this difference, refer to Figures 1 to 4 Features of the exemplary embodiments described can be applied to the reference Figure 14 The exemplary embodiments described herein, and therefore, refer to Figures 1 to 4 Redundant features of the exemplary embodiments described will not be described, and it should be assumed that those undescribed elements are at least similar to their counterparts described elsewhere in this specification.

[0151] Figure 15 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment.

[0152] refer to Figure 15 ,and Figure 14 Unlike the exemplary embodiments, the display panel 10 may not include the connection member CM that electrically connects the second electrode E2 to the common voltage line VC, and the second electrode E2 may be connected to the common voltage line VC by directly contacting the contact layer CT on the common voltage line VC. Additionally, the shielding layer SL may be formed from an extension of the second electrode E2. For example, the shielding layer SL overlapping the driver circuit DC may be formed from the same material using the same process as the second electrode E2.

[0153] Excluding this difference, refer to Figures 1 to 4 Features of the exemplary embodiments described can be applied to the reference Figure 15 The exemplary embodiments described herein, and therefore, refer to Figures 1 to 4 Redundant features of the exemplary embodiments described will not be described, and it should be assumed that those undescribed elements are at least similar to their counterparts described elsewhere in this specification.

[0154] Figure 16 This shows the section intercepted along line B-B'. Figure 1 A schematic cross-sectional view of an exemplary embodiment.

[0155] refer to Figure 16 ,and Figure 14 Unlike the exemplary embodiment, the shielding layer SL, which may be formed on the same layer as the first electrode E1, can contact the contact layer CT on the common voltage line VC. Therefore, the shielding layer SL can receive the common voltage ELVSS through the contact layer CT. The display panel 10 does not include a connection member CM for electrically connecting the second electrode E2 to the common voltage line VC, and the second electrode E2 can be electrically connected to the common voltage line VC through the shielding layer SL and the contact layer CT.

[0156] Excluding this difference, refer to Figures 1 to 4 as well as Figure 14 Features of the exemplary embodiments described can be applied to the reference Figure 16 The exemplary embodiments described herein, and therefore, refer to Figures 1 to 4 as well as Figure 14 Redundant features of the exemplary embodiments described will not be described, and it should be assumed that those undescribed elements are at least similar to their counterparts described elsewhere in this specification.

[0157] In the following text, see references Figure 17The structure of the pads in the pad section of the display device 1 will be described with a focus on their layer relationship with the pixels disposed in the display area DA. To avoid excessive complexity in the description, the display area DA will only be shown from the first substrate 110 to the light-emitting element LD.

[0158] Figure 17 This is a schematic cross-sectional view illustrating a display device according to an exemplary embodiment of the present invention.

[0159] refer to Figure 17 A pad P is disposed within a pad portion PP. The pad P can be formed from multiple layers PL1, PL2, and PL3. For example, the pad P includes: a first layer PL1 formed from the same material using the same process as the gate electrode Gp of transistor TRp; a second layer PL2 formed from the same material using the same process as the source electrode Sp and drain electrode Dp of transistor TRp; and a third layer PL3 disposed on the second layer PL2. The three layers PL1, PL2, and PL3 are shown as layers used to form the pad P, but the pad P may include fewer or more than three layers.

[0160] The first layer PL1 can be connected to wiring disposed in the non-display area NA of the display panel 10, and a portion of the wiring can form the first layer PL1. The second layer PL2 can be connected to the first layer PL1 through contact holes formed in the second insulating layer 160, and the third layer PL3 can be connected to the second layer PL2 through contact holes formed in the third insulating layer 181. Therefore, signals input to the third layer PL3 can be transmitted to the wiring through the second layer PL2 and the first layer PL1.

[0161] Even when the second layer PL2, which serves as a data conductor, is formed from a single copper (Cu) layer or multiple layers (e.g., Ti / Cu), the second layer PL2 can be oxidized by exposure to the outside when the top layer is formed of copper (Cu). Therefore, a third layer PL3 can be formed on the second layer PL2 to prevent the second layer PL2 from being exposed, thereby preventing the second layer PL2 from oxidizing. The third layer PL3 can be formed from a transparent conductive oxide such as ITO, IZO, etc. In addition to transparent conductive oxides, the third layer PL3 can also be formed from a conductor with excellent oxidation resistance and corrosion resistance. The third layer PL3 is the top layer of the pad P, which is electrically connected to the pad, such as a flexible printed circuit film, through an anisotropic conductive layer, solder, etc., and can be referred to as a pad terminal. The third layer PL3 can be disposed between the third insulating layer 181 and the fourth insulating layer 182, and the fourth insulating layer 182 can cover the edge of the third layer PL3. According to an exemplary embodiment of this disclosure, any portion of the third layer PL3 may not be covered by the fourth insulating layer 182.

[0162] The aforementioned contact layer CT and connecting line EPL can be located in the same layer as the third layer PL3. For example, the contact layer CT and connecting line EPL can be formed from the same material using the same process as the third layer PL3. Additionally, refer to... Figures 2 to 4 The first to third electrostatic barrier lines EP1, EP2 and EP3 described can be located in the same layer as the third layer PL3.

[0163] Storage capacitors included in pixel PX (reference) Figure 18 In the transistor TRp, the first electrode C1 of the two electrodes C1 and C2 can be formed on the same layer as the gate electrode Gp of the transistor TRp. The second electrode C2, overlapping the first electrode C1, can be formed on the same layer as the source electrode Sp and drain electrode Dp of the transistor TRp. The first electrode C1 can be electrically connected to the gate electrode Gp, and the second electrode C2 can be electrically connected to the drain electrode Dp. However, unlike the exemplary embodiment described above, in... Figure 17 In this configuration, the first insulating layer 140 is not formed entirely, but only in the region overlapping with the gate conductor. This structure can be the result of patterning the first insulating layer 140 together with the patterned gate conductor.

[0164] In the following text, reference will be made to Figure 18 To describe the pixels according to an exemplary embodiment of the present invention.

[0165] Figure 18 This is an equivalent circuit diagram illustrating a pixel in a display device according to an exemplary embodiment of the present invention.

[0166] refer to Figure 18 Pixel PX includes multiple transistors T1, T2, and T3, a storage capacitor SC, and a light-emitting element LD. Pixel PX is connected to multiple signal lines DL, GL, CL, SSL, DVL, and VC. Figure 18 The diagram shows a structure with three transistors and one capacitor, but the number of transistors and capacitors can be varied. Six signal lines are connected to pixel PX, but the type and number of signal lines can also be changed.

[0167] Signal lines DL, GL, CL, SSL, DVL, and VC may include a data line DL, a gate line GL, a sense control line CL, a sense line SSL, a drive voltage line DVL, and a common voltage line VC. The gate line GL transmits the gate signal GW to the second transistor T2. The data line DL transmits the data signal DT, the drive voltage line DVL transmits the drive voltage ELVDD, and the common voltage line VC transmits the common voltage ELVSS. The sense control line CL transmits the sense signal SS, and the sense line SSL can be connected to the sensing unit.

[0168] Transistors T1, T2, and T3 include a first transistor T1 as a driving transistor, a second transistor T2 as a switching transistor, and a third transistor T3 as a sensing transistor. Transistors T1, T2, and T3 are three-terminal devices, comprising gate electrodes G1, G2, and G3, source electrodes S1, S2, and S3, and drain electrodes D1, D2, and D3. The source and drain electrodes are not fixed, and of the three terminals of the transistor, one of the two terminals other than the gate electrode can be referred to as the source electrode, and the other can be referred to as the drain electrode.

[0169] The gate electrode G1 of the first transistor T1 is connected to the first electrode C1 of the storage capacitor SC and the drain electrode D2 of the second transistor T2. The source electrode S1 of the first transistor T1 is connected to the drive voltage line DVL. The drain electrode D1 of the first transistor T1 is connected to the anode of the light-emitting element LD. Additionally, the drain electrode D1 of the first transistor T1 is connected to the source electrode S3 of the third transistor T3. The first transistor T1 can supply the light-emitting element LD with a drive current I corresponding to the magnitude of the data signal DT transmitted through the second transistor T2. D And it can emit with a driving current I D The size of the light corresponds to its brightness. Therefore, by adjusting the amount of current flowing through the first transistor T1 according to its size, various gray levels can be displayed. Drive current I D It can be related to the gate-source voltage V GS Relatedly, the gate-source voltage V GS This is the voltage between the gate electrode G1 and the source electrode S1 of the first transistor T1. For example, as the V of the first transistor T1... GS Increase, drive current I D It can be added. Since the light-shielding layer LB, which can overlap with the semiconductor layer of the first transistor T1, is connected to the drain electrode D1 of the first transistor T1, the characteristics of the first transistor T1, such as output saturation characteristics, can be improved.

[0170] The gate electrode G2 of the second transistor T2 is connected to the gate line GL, the source electrode S2 of the second transistor T2 is connected to the data line DL, and the drain electrode D2 of the second transistor T2 is connected to the gate electrode G1 of the first transistor T1 and the first electrode C1 of the storage capacitor SC. The second transistor T2 is turned on according to the gate signal GW transmitted through the gate line GL, and can perform a switching operation to transmit the data signal DT transmitted through the data line DL to the gate electrode G1 of the first transistor T1 and the first electrode C1 of the storage capacitor SC.

[0171] The gate electrode G3 of the third transistor T3 is connected to the sensing control line CL. The source electrode S3 of the third transistor T3 is connected to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting element LD. The drain electrode D3 of the third transistor T3 is connected to the sensing line SSL. The third transistor T3 is a transistor used to sense characteristics such as the threshold voltage of the first transistor T1, which causes a degradation in the display quality of the third transistor T3. The third transistor T3 is turned on according to the sensing signal SS transmitted through the sensing control line CL to electrically connect the first transistor T1 to the sensing line SSL. The sensing unit connected to the sensing line SSL can sense the characteristic information of the first transistor T1 during the sensing period. A data signal that is compensated by reflecting the characteristic information sensed by the third transistor T3 during the sensing period can be generated, so that the characteristic deviation of the first transistor T1, which may not be the same for each pixel PX, can be compensated from the outside.

[0172] The first electrode C1 of the storage capacitor SC is connected to the gate electrode G1 of the first transistor T1 and the drain electrode D2 of the second transistor T2. The second electrode C2 of the storage capacitor SC is connected to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting element LD. The storage capacitor SC holds the charged data signal DT, enabling the light-emitting element LD to emit light continuously during the emission period. The cathode of the light-emitting element LD can be connected to the common voltage line VC that transmits the common voltage ELVSS.

[0173] Although exemplary embodiments of the invention have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to the disclosed embodiments. Rather, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of this disclosure.

Claims

1. A display device comprising: a substrate including a display region and a non-display region at least partially surrounding the display region; a driver provided in the non-display region and including a driver circuit having a transistor and a driver control line transmitting a control signal to the driver circuit; an electrostatic blocking line provided in the non-display region in a closed loop form surrounding the display region; and a dam provided in the non-display region and surrounding the display region, and at least partially overlapping the electrostatic blocking line, wherein the electrostatic blocking line at least partially overlaps the driver. The electrostatic blocking line at least partially overlaps the driver circuit.

2. The display device of claim 1, wherein, The electrostatic blocking line at least partially overlaps the driver control line.

3. The display device of claim 1, wherein, A width of the electrostatic blocking line is smaller than a width of a bottom surface of the dam, and the dam completely covers the electrostatic blocking line.

4. The display device of claim 1, wherein, The dam includes a lower layer and an upper layer provided on the lower layer, and 5. The display device of claim 1, wherein, wherein the electrostatic blocking line is provided between the lower layer and the upper layer. The electrostatic blocking line is provided in an upper portion of the dam.

6. The display device of claim 1, wherein, A width of the electrostatic blocking line is greater than a width of a bottom surface of the dam, and the dam covers a portion of the electrostatic blocking line.

7. The display device of claim 1, wherein, 8. The display device according to claim 1, further comprising: a light emitting element provided in the display region and including a first electrode, an emission layer provided on the first electrode, and a second electrode provided on the emission layer, wherein the second electrode extends to a region where the dam is located, and covers an upper portion of the dam in the non-display region.

9. The display device according to claim 8, further comprising: an encapsulation layer covering the display region, and sealing the light emitting element; wherein the electrostatic blocking line includes a plurality of electrostatic blocking lines extending in parallel to each other, and wherein at least a portion of at least one of the plurality of electrostatic blocking lines is covered by the encapsulation layer, and at least another portion of at least one of the plurality of electrostatic blocking lines is not covered by the encapsulation layer. The electrostatic blocking line includes a plurality of electrostatic blocking lines extending in parallel to each other, and 10. The display device of claim 1, wherein, wherein the display device further includes a connection line connecting the plurality of electrostatic blocking lines to each other, and transmitting a common voltage to the plurality of electrostatic blocking lines.

11. The display device according to claim 10, further comprising: a mask support, and a distance between the mask support and the display region is greater than a distance between the dam in the non-display region and the display region, and the mask support at least partially overlaps only one of the plurality of electrostatic blocking lines while surrounding the display region. ​

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