Switching converter

Abstract

This document describes a phase-shifted full-bridge (PSFB) switching converter. According to one embodiment, the switching converter includes a transistor full-bridge composed of a first half-bridge and a second half-bridge. The first half-bridge includes a first high-side transistor and a first low-side transistor, and the second half-bridge includes a second high-side transistor and a second low-side transistor. The switching converter includes a controller circuit configured to generate a first drive signal for the first high-side transistor, a second drive signal for the first low-side transistor, a third drive signal for the second high-side transistor, and a fourth drive signal for the second low-side transistor. The first drive signal and the second drive signal are periodic, have a cycle period and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period. Similarly, the third drive signal and the fourth drive signal are also periodic, have a cycle period and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period. The first and second drive signals are phase-shifted with respect to the third and fourth drive signals. In addition, the controller circuit is configured to generate the first drive signal such that the first high-side transistor is turned off when the third drive signal indicates turning on the second high-side transistor, and the controller circuit is configured to generate the second drive signal such that the first low-side transistor is turned off when the fourth drive signal indicates turning on the second low-side transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of switching converters, and more particularly to a so-called phase-shifted full-bridge (PSFB) converter. Background Art

[0002] PSFB converters can be used for DC-DC conversion in a variety of applications. The PSFB converter provides voltage conversion as well as current isolation from the input line voltage, since the converter topology includes a transformer. Like other resonant or quasi-resonant converters, the PSFB converter can be operated to perform so-called zero-voltage switching (ZVS) on the power transistors that switch the primary current through the transformer.

[0003] However, unlike other fully resonant topologies (LLC converter topology or dual active bridge (DAB) converter topology), the PSFB converter may incur losses due to circulating currents. These circulating currents do not contribute to power transfer from the primary side to the secondary side of the transformer and may therefore reduce efficiency. Especially in applications with a wide input and / or wide output voltage range, the circulating currents and associated losses can have a significant impact on the efficiency of power conversion. Summary of the Invention

[0004] A phase-shifted full-bridge (PSFB) switching converter is described herein. According to one embodiment, the switching converter includes a transistor full-bridge composed of a first half-bridge and a second half-bridge. The first half-bridge includes a first high-side transistor and a first low-side transistor, and the second half-bridge includes a second high-side transistor and a second low-side transistor. The switching converter includes a controller circuit configured to generate a first drive signal for the first high-side transistor, a second drive signal for the first low-side transistor, a third drive signal for the second high-side transistor, and a fourth drive signal for the second low-side transistor. The first drive signal and the second drive signal are periodic, have a cycle period and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period. Similarly, the third drive signal and the fourth drive signal are also periodic, have a cycle period and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period. The first and second drive signals are phase-shifted with respect to the third and fourth drive signals. In addition, the controller circuit is configured to generate the first drive signal such that the first high-side transistor is turned off when the third drive signal indicates turning on the second high-side transistor, and the controller circuit is configured to generate the second drive signal such that the first low-side transistor is turned off when the fourth drive signal indicates turning on the second low-side transistor.

[0005] In addition, a method for controlling a phase-shifted full-bridge switching converter is described herein. According to one embodiment, the method includes generating a first drive signal for a first high-side transistor of the switching converter, a second drive signal for a first low-side transistor, a third drive signal for a second high-side transistor, and a fourth drive signal for a second low-side transistor. The first drive signal and the second drive signal are periodic, have a cycle period and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period. Similarly, the third drive signal and the fourth drive signal are also periodic, have a cycle period and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period. Thus, the first and second drive signals are phase-shifted with respect to the third and fourth drive signals. In addition, the first drive signal is generated such that the first high-side transistor is turned off when the third drive signal indicates turning on the second high-side transistor, and the second drive signal is generated such that the first low-side transistor is turned off when the fourth drive signal indicates turning on the second low-side transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention can be better understood with reference to the following drawings and description. The components in the drawings are not necessarily drawn to scale; instead, emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, like reference numerals denote corresponding parts. In the figures:

[0007] Figure 1 An example of a PSFB converter is shown.

[0008] Figure 2 Shows an example of a general switching scheme for controlling the switching operation of a circuit of a PSFB converter in the case where the input voltage is quite low Figure 1 of the PSFB converter.

[0009] Figure 3 Shows how the phase of the switching signal changes in the Figure 2 scheme when the input voltage is high.

[0010] Figure 4 and Figure 5 Show an example of a modified switching scheme according to which, compared with the switching scheme of Figure 2 and Figure 3 the transistors in one half-bridge of the PSFB converter are turned off earlier.

[0011] Figure 6 is a circuit configured to generate switching signals according to the switching scheme of Figure 4 and Figure 5 of the PSFB converter. DETAILED DESCRIPTION

[0012] Figure 1An exemplary embodiment of a PSFB converter is shown. Thus, the PSFB converter includes four power electronic switches that form a full bridge on the primary side of the transformer. In this example, the power electronic switches are implemented as Figure 1 marked as M A , M B , M C and M D metal-oxide semiconductor field effect transistors (MOSFETs). However, other types of power electronic switches such as IGBTs can also be used. Each of the MOSFETs has an intrinsic reverse diode (body diode), which is marked as D A , D B , D C and D D .

[0013] Transistors M A and M B form the first half-bridge, and transistors M C and M D form the second half-bridge. Both half-bridges are connected between a first power supply terminal providing an input voltage V IN and a second power supply terminal GND1 connected to a reference potential (e.g., a ground terminal). The half-bridge output node N1 of the first half-bridge is connected to the first end of an inductor L P1 , and the inductor L P1 is the primary winding of the transformer. The half-bridge output node N2 of the second half-bridge is connected to the first end of another inductor L P2 . The second end of the inductor L P1 and the second end of another inductor L P2 are connected at a circuit node N3, which is also coupled to the first power supply terminal via a freewheeling diode D1 and to the second power supply terminal GND1 via a freewheeling diode D2.

[0014] An inductor L S1 serving as the secondary winding of the transformer is connected to a rectifier, which in this example is a bridge rectifier composed of diodes D R1 , D R2 , D R3 and D R4 . Note that other types of rectifiers can be used instead of the depicted bridge rectifier. In a specific embodiment, a synchronous bridge rectifier is used instead of a diode bridge rectifier. In the case where the secondary inductor has a center tap, two diodes (or transistors in the case of synchronous rectification) may be sufficient to rectify the secondary current i LS . Another inductor L Ois connected between an output node of a bridge rectifier and the output terminal OUT of the PSFB converter, where the other output node of the bridge rectifier is connected to the reference terminal GND2, and the reference terminal GND2 forms a ground terminal for circuit components on the secondary side of the transformer. Capacitor C O is connected between the output terminal OUT and the reference terminal GND2. Inductor L O and capacitor C O basically form a low-pass filter to reduce the ripple of the output voltage V OUT . The load resistor R O connected in parallel to the output capacitor C L is a placeholder for any load that can be connected to and powered by the PSFB converter.

[0015] The drive signals V GA , V GB , V GC and V GD (i.e., in this example, the gate voltages for driving the gates of transistors M A , M B , M C and M D ) can be generated using any known technique. Pulse width modulation is typically used to modulate the drive signals in order to regulate the output voltage V OUT . Suitable gate driver circuits for driving MOSFETs are already well known and will not be discussed further here. Figure 1 The shown switched converter topology allows all power electronic switches to be switched with zero voltage switching (ZVS), thus achieving relatively low switching losses and efficient power conversion.

[0016] Figure 2 includes a timing diagram showing the control signals for driving MOSFETs M A , M B , M C and M D , the resulting inductor currents i P1 and i P2 flowing through inductors L LP1 and i LP2 and the corresponding diode currents i D1 and i D2 (also known as the circulating current) flowing through freewheeling diodes D1 and D2. The depicted waveforms represent Figure 1 the PSFB converter at full load (nominal output voltage V OUTOperation at the specified maximum output current) and the minimum input voltage within the specified input voltage range (e.g., 350V). In this case, the circulating current on the primary side is at its minimum, and the converter efficiency is high. It can be at Figure 2 As seen in the bottom figure of, the circulating current i D1 , i D2 The spikes with a peak of approximately 6 amperes are very short (only a few nanoseconds).

[0017] For the case where the PSFB converter operates at full load and the nominal input voltage within the specified input voltage range (e.g., 400V), Figure 3 Includes the same waveform as Figure 2 . It can be seen that in this case, compared with the Figure 2 The case shown, the circulating current i D1 , i D2 Is higher, and the freewheeling diodes D1 and D2 are forward-biased for a much longer time. Compared with the Figure 2 The case shown, the efficiency is lower. The higher input voltage causes the output voltage controller circuit ( Figure 1 Not shown in) to set a phase shift φ between the rising edge of the drive signal V GA And the corresponding rising edge of the drive signal V GD . The same phase shift φ can be observed between the rising edge of the drive signal V GB And the corresponding rising edge of the drive signal V GC . In the embodiments described herein, all drive signals are periodic, with a cycle period T PWM , and are pulse-width modulated to have a duty cycle of 50% (T ON = T OFF = T PWM / 2). During operation, the controller circuit that generates the drive signals V GA , V GB , V GC And V GD Can control / adjust the phase shift φ to maintain the output voltage V OUT At the desired setpoint level. The drive signals of the transistors of the first half-bridge (i.e., V GA And V GB ) Have a time offset between each other equal to half of the cycle period T PWM (i.e., a 180° phase shift). This also applies to the drive signals of the transistors of the second half-bridge (i.e., V GC And V GD ). The phase shift φ corresponds to a time delay Δt (time offset) equal to T PWM ·φ / 360° (when φ is provided in degrees), where T PWM Is the duration of one switching cycle, and the switching frequency is TPWM -1 Note that during the entire operation of the switching converter, the PWM frequency T PWM -1 is not necessarily constant. In particular, when the voltage controller circuit reacts in response to, for example, a load change or an input voltage change, the phase shift φ will change and there may be one or more pulses with different cycle times T PWM . However, this behavior of the controller depends on the specific implementation of the controller and is part of the prior art PSFB control and is thus not discussed in detail here.

[0018] At Figure 3 in the example, at time t0, the transistor M A is turned off and the transistor M B is turned on. At this time, the transistor M C has been conducting and the transistor M D is cut off. After a short dead time, power transfer from the primary side to the secondary side of the transformer occurs between times t1 and t3 (power conversion phase). During this phase, the MOSFETs M B and M C are active (i.e., on), and the diode D2 conducts between times t1 and t2, while the diode current i D2 decreases between times t1 and t2 and reaches zero at time t2; during times t2 and t3, the diode current i D2 is zero. During this power conversion phase (i.e., from time t1 to t3), the secondary current i LS flows through the rectifier diode D R2 , the secondary winding L S1 of the transformer, and the rectifier diode D R3 .

[0019] At time t3, the MOSFET M C is turned off while the MOSFET M D is turned on (zero voltage switching operation). Subsequently, between times t3 and t4 (freewheeling phase), the freewheeling current i D2 flows along the current path from the diode D2 via the inductor L P2 to the MOSFET M B through the freewheeling diode D2. At the end of the freewheeling phase, at time t4, the MOSFET M B is turned off while the MOSFET M A is turned on (zero voltage switching operation).

[0020] After a short dead time after time t4, the next power conversion phase starts at time t5. During this phase, the MOSFET MA and M D is active (i.e., turned on), and diode D1 conducts between times t5 and t6, while the diode current i D1 decreases between times t5 and t6 and reaches zero at time t6; during times t6 and t7, the diode current i D1 is zero. During this power conversion stage (i.e., from time t5 to t7), the secondary current i LS flows through the rectifier diode D R1 , the secondary winding L of the transformer S1 and the rectifier diode D R4 .

[0021] At time t7, MOSFET M D turns off, while MOSFET M C turns on (zero-voltage switching operation). Subsequently, between times t7 and t8 (freewheeling stage), the freewheeling current i D2 flows through the freewheeling diode D1 along the current path from MOSFET M A via inductor L P2 to diode D1. At the end of the freewheeling stage, at time t8, MOSFET M A turns off, while MOSFET M B turns on (zero-voltage switching operation). It should be noted that in the stationary operation, times t8 and t0 actually represent the same situation, and the next cycle starts at time t8.

[0022] Note that the waveforms showing the gate voltages V GA , V GB , V GC , V GD are merely phase-shifted forms of each other, and they all have the same on-time T1, off-time T2, and switching period T PWM . As described above, the phase shift φ is adjusted to regulate the output voltage to match the desired set point. Thus, when (assuming all other conditions are the same) the input voltage V IN decreases, for example from 400V to 350V in this example, then the controller circuit will have to reduce the phase shift φ from the value shown in Figure 3 to almost zero, as is the case shown in Figure 2 . Similarly, when the output current increases or decreases, the controller circuit will have to increase or correspondingly reduce the phase shift φ to maintain the output voltage V OUT at the desired level. Note that the general concept of how to control a PSFB converter by adjusting the phase shift φ is well known and is thus not described in detail here.

[0023] In the following, a modified switching scheme for a PSFB converter will be described, which allows reducing the length of the freewheeling phase and the losses associated with freewheeling. Figure 4 including a timing diagram showing the drive signals for driving MOSFET M A 、M B 、M C and M D ,the inductor currents i P1 and i P2 generated through inductors L LP1 and L LP2 ,and the corresponding diode currents i D1 and i D2 (circulating current) flowing through freewheeling diodes D1 and D2. Figure 5 including the corresponding timing diagram showing the drive signals for driving MOSFET M A 、M B 、M C and M D ,the inductor currents i P1 and i P2 generated through inductors L LP1 and L LP2 ,and the corresponding voltage drops V B and V C across transistors M DSB and M DSC . Figure 5 The diagram of Figure 4 has a scaled (magnified) time axis and represents only a short time period of the diagram of Figure 4 and Figure 5 . The markers t0, t1, t2, t3, and t4 in

[0024] represent the same moments. Figure 4 and Figure 5 According to the switching scheme shown in B ,transistor M C is turned on at time t0. At this time, transistor M D is already conducting, and transistor M A is off. Different from the previous example of Figure 3 ,transistor M B is not turned off at the same time t0 when transistor M A is turned on. Instead, transistor M C is turned off earlier, that is, it is turned off together with the turn-on of transistor M B and MC is active (i.e., turned on), and diode D2 conducts between times t1 and t2, while the diode current i D2 decreases between times t1 and t2 and reaches zero at time t2; during times t2 and t3, the diode current i D2 is zero. During this power conversion stage (i.e., from time t1 to t3), the secondary current i LS flows through the rectifier diode D R2 , the secondary winding L of the transformer S1 and the rectifier diode D R3 .

[0025] At time t3, MOSFET M C turns off, while MOSFET M D turns on (zero voltage switching operation). Different from Figure 3 the previous example, transistor M B is also turned off at time t3 together with the turn-on of transistor M D in the other half-bridge of the PSFB converter (early turn-off of transistor M B , see Figure 6 ). Since MOSFET M B will now block the current path of the inductor current i LP1 (the primary current of the transformer), the current i LP1 flows through the body diode D A of MOSFET M A ; the output capacitance of MOSFET M A discharges accordingly. As a result, after time t3, the recycling current i D2 flowing through diode D2 immediately drops to zero. During most of the freewheeling stage between times t3 and t4, the diode current i D2 is almost zero. Due to the resonance of inductor L P1 and the output capacitance of MOSFET M A , the body diode D B of MOSFET M B becomes forward-biased. This corresponds to a short peak of the drain-source voltage V B of MOSFET M DSB , which appears immediately after time t3, as Figure 5 shown. After this peak, the diode current is proportional to the capacitance and inductance values and is therefore not exactly zero. At the end of the freewheeling stage, at time t4, MOSFET M A turns on, which is a hard commutation rather than ZVS operation because the body diode D B of MOSFET M B conducts during the switching operation.

[0026] After a short dead time after time t4, the next power conversion stage starts at time t5. During this stage, MOSFET M A and M D are active, and diode D1 conducts between times t5 and t6, while the diode current i D1 decreases between times t5 and t6 and reaches zero at time t6; during times t6 and t7, the diode current i D1 is zero. During this power conversion stage (i.e., from time t5 to t7), the secondary current i LS flows through rectifier diode D R4 , the secondary winding L S1 of the transformer, and rectifier diode D R1 .

[0027] At time t7, MOSFET M D turns off, while MOSFET M C turns on (zero voltage switching operation). Different from the Figure 3 previous example, transistor M A is also turned off at time t7 together with the turn-on of transistor M C in the other half-bridge of the PSFB converter (transistor M A is turned off in advance, see Figure 6 ). Because now MOSFET M A blocks the current path of inductor current i LP1 (the primary current of the transformer), the current i LP1 flows through the body diode D B of MOSFET M B ; the output capacitance of MOSFET M B discharges accordingly. As a result, after time t7, the recycle current i D1 flowing through diode D1 immediately drops to zero. During most of the freewheeling stage between times t7 and t8, the diode current i D1 is almost zero. Due to the resonance of inductor L P1 and the output capacitance of MOSFET M B , the body diode D A of MOSFET M A becomes forward-biased. At the end of the freewheeling stage, at time t8, MOSFET M B turns on, which is a hard commutation, rather than ZVS operation, because the body diode D A of MOSFET M A conducts during the switching operation.

[0028] In summary, during operation, a controller circuit that generates drive signals V GA , V GB , V GC and V GD can control / regulate the phase shift φ between the drive signals V GA and V GB for the first half-bridge and the drive signals V GC and V GD for the second half-bridge to maintain the output voltage V OUT at a desired set-point level. The drive signals for the transistors of the first half-bridge (i.e., V GA and V GB ) are in opposite phase to each other, i.e., have a time offset of T PWM / 2 or 180°. This also applies to the drive signals for the transistors of the second half-bridge (i.e., there is a time offset of T GA and V GC between the rising edges of V GB and V GD and a time offset of T PWM / 2 between the rising edges of V Figure 3 However, different from the previous example of GA , the first drive signal V GC is generated such that when the third drive signal V C indicates turning on the second high-side transistor M A in the second half-bridge, the first high-side transistor M A in the first half-bridge is turned off (early turn-off of transistor M GB Similarly, the second drive signal V GD is generated such that when the fourth drive signal V D indicates turning on the second low-side transistor M B in the second half-bridge, the first low-side transistor M B in the first half-bridge is turned off (early turn-off of transistor M

[0029] Note that although the transistors M Figure 3 and M A and M B of the first half-bridge are turned off earlier compared to the situation shown in PWM , the duration of the switching period T Figure 3 remains the same and is the same as the conventional switching scheme shown in A and M B of the first half-bridge is not affected by the above-mentioned early turn-off. However, the time offset of T GA and V GB between the rising edges of the drive signals V PWM / 2. However, the transistors MA and M B The early turn-off of changes the respective drive signals V GA 、V GB The duty cycle of. However, since the signals V GA and V GB The longer turn-off time in (compared with the conventional switching scheme shown in Figure 3 ) only affects the freewheeling stage and does not affect the power conversion stage, and thus has no effect on the regulation of the output voltage V OUT , and the output voltage V OUT Can still be adjusted by adjusting the phase shift φ, and the phase shift φ corresponds to T PWM ·φ / 360° time offset)

[0030] Figure 6 Shows a simple example of the controller circuit 1, which is configured to generate transistors M for forming a full-bridge (see Figure 1 ) of the FSFP converter A 、M B 、M C and M D Drive signals. In fact, the PSFB converter includes a full bridge composed of two half bridges, where, in the example described herein, M A Represents the high-side transistor of the first half bridge, M B Represents the low-side transistor of the first half bridge, M C Represents the high-side transistor of the second half bridge, and M D Represents the low-side transistor of the second half bridge. The switched converter includes a controller circuit, an example of which is shown in Figure 6 , and its function has been described above with reference to Figure 4 and Figure 5 . Generally, the controller circuit 1 is configured to generate a first drive signal V for the first high-side transistor M A 、a second drive signal V for the first low-side transistor M GA 、a third drive signal V for the second high-side transistor M B and a fourth drive signal V for the second low-side transistor M GB 、a fifth drive signal V for the second high-side transistor M C 、a sixth drive signal V for the second low-side transistor M GC and a seventh drive signal V for the second low-side transistor M D (also see GD Figure 1 Figure 1 ).

[0031] The first drive signal V GA and the second drive signal V GB Are periodic, with a cycle period T PWMand are pulse-width modulated (e.g., with a 50% duty cycle) and have a time offset equal to half of the period T with respect to each other PWM (see Figure 4 and Figure 5 , the rising edge of V GA has a time offset of T GB / 2 with respect to the corresponding rising edge of V PWM . Similarly, the third drive signal V GC and the fourth drive signal V GD are also periodic, with the same cycle period T PWM and are pulse-width modulated, and have a time offset of T PWM / 2 with respect to each other (see Figure 4 , the rising edge of V GC has a time offset of T GD / 2 with respect to the corresponding rising edge of V PWM ). The first drive signal and the second drive signal are phase-shifted with respect to the third drive signal and the fourth drive signal (see Figure 4 , phase shift φ). In addition, the controller circuit is configured to generate the first drive signal V GA such that when the third drive signal M C indicates turning on the second high-side transistor M C , the first high-side transistor M A is turned off (see Figure 4 , at time t7, the falling edge of V GA coincides with the rising edge of V GC ), and generates the second drive signal V GB such that when the fourth drive signal V GD indicates turning on the second low-side transistor M D , the first low-side transistor M B is turned off (see Figure 5 , at time t3, the falling edge of V GB coincides with the rising edge of V GD ).

[0032] Figure 6 The example of Figure 2 and Figure 3 further shows how the standard PSFB controller 10 that generates the switching signals A, B, C, and D for the transistors M A , M B , M C and M D respectively according to the general switching scheme shown in Figure 4 and Figure 5The novel switching scheme shown is used to generate switching signals. Accordingly, switching signals A and B are modified, and the modified signals A' and B' along with signals C and D are used, for example, to generate drive signals V, such as using a common gate driver circuit GA 、V GB 、V GC and V GD .

[0033] According to Figure 6 the example of, the PSFB controller provides logic signals A, B, C, and D, which are respectively provided to gate driver circuits 21, 22, 23, and 24, which provide corresponding gate voltages V GA 、V GB 、V GC and V GD (see also Figure 1 ). However, to implement Figure 4 the switching scheme of, the logic signals A and B are modified, and the modified logic signals A' and B' are provided to the gate drivers 21 and 22 for MOSFET M A and M B . The modified logic signals A' and B' are obtained according to the following formulas:

[0034] A' = A & (NOT C), (1)

[0035] B' = B & (NOT D). (2)

[0036] In Figure 6 the example of, the AND operation is implemented by AND gates 12 and 14, and the NOT operation is implemented by inverters 11 and 13. Accordingly, inverter 11 receives logic signal C, and AND gate 12 receives logic signal A and the output signal of inverter 11. Similarly, inverter 13 receives logic signal D, and AND gate 14 receives logic signal B and the output signal of inverter 13.

[0037] The modified logic signal A' indicates that MOSFET M A turns off "earlier" at this moment, and logic signal C indicates that MOSFET M C turns on. Similarly, the modified logic signal B' indicates that MOSFET M B turns off "earlier" at this moment, and logic signal D indicates that MOSFET M D turns on. As a result, as explained above with reference to Figure 4 and 5 , the time period during which the recirculation current flows through diode D1 or D2 is greatly shortened.

[0038] The specific example of Figure 6 is chosen because it clearly showsFigure 2 and Figure 3 the standard switching scheme of Figure 4 and Figure 5 the difference between the repaired switching scheme of

[0039] Although the present invention has been shown and described with respect to one or more embodiments, changes and / or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (units, components, devices, circuits, systems, etc.), unless otherwise specified, the terms used to describe such components (including references to "means") are intended to correspond to any component or structure that performs the specified function of the described component (e.g., is functionally equivalent), even if not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of the present invention shown herein.

Claims

1. A phase-shifted full-bridge switching converter, comprising: Transistor full bridge, which includes a first half bridge and a second half bridge, the first half bridge includes a first high-side transistor (M A ), and a first low-side transistor (M B ), the second half bridge includes a second high-side transistor (M C ), and a second low-side transistor (M D ); and A controller circuit configured to generate a first drive signal (V A ) for the first high-side transistor (M GA ), a second drive signal (V B ) for the first low-side transistor (M GB ), a third drive signal (V C ) for the second high-side transistor (M GC ), and a fourth drive signal (V D ) for the second low-side transistor (M GD ), Among them, the first driving signal (V GA ) and the second driving signal (V GB ) are periodic, have a cycle period (T PWM ) and are pulse-width modulated, and have a time offset equal to half of the cycle period (T PWM ) from each other. Among them, the third driving signal (V GC ) and the fourth driving signal (V GD ) are periodic, have a cycle period (T PWM ) and are pulse-width modulated, and have a time offset between each other equal to half of the cycle period (T PWM ), the first driving signal and the second driving signal (V GA , V GB ) are phase-shifted relative to the third driving signal and the fourth driving signal (V GC , V GD ), and Wherein, the controller circuit is configured to generate the first driving signal (V GA ) such that when the third driving signal (V GC ) indicates turning on the second high-side transistor (M C ), the first high-side transistor (M A ) is turned off, and the controller circuit is configured to generate the second driving signal (V GB ) such that when the fourth driving signal (V GD ) indicates turning on the second low-side transistor (M D ), the first low-side transistor (M B ) is turned off, Among them, the first high-side transistor (M A ) and the first low-side transistor (M B ) are connected at a first circuit node (N1), and the second high-side transistor (M C ) and the second low-side transistor (M D ) are connected at a second circuit node (N2); both the first half-bridge and the second half-bridge are connected between a first power supply node (V IN ) and a second power supply node (GND); wherein, the switching converter further comprises: Series circuit, which includes a first inductor (L P1 ) and a second inductor (L P2 ) connected at a third circuit node (N3); the series circuit is connected between the first circuit node (N1) and the second circuit node (N2); A first freewheeling diode (D1) coupled between the third circuit node (N3) and the first power supply node (V IN ), and a second freewheeling diode (D2) coupled between the third circuit node (N3) and the second power supply node (GND); and A transformer having a primary winding and a secondary winding (L S1 ), wherein the primary winding is the first inductor (L P1 ); and Rectifier (D R1 , D R2 , D R3 , D R4 ), which is coupled to the secondary winding (L S1 ) and is configured to rectify the secondary current flowing through the secondary winding.

2. The switching converter according to claim 1, wherein, The controller circuit is configured to generate the first drive signal (V GA ), the second drive signal (V GB ), the third drive signal (V GC ), and the fourth drive signal (V GD ) as pulse-width modulation signals with a duty cycle of 50%.

3. The switching converter according to claim 1 or 2, wherein, The phase shift determines the output voltage (V OUT ) of the switching converter.

4. The switching converter according to claim 3, wherein, The controller circuit is configured to set the phase shift depending on the output voltage (V OUT ) of the switching converter.

5. The switching converter according to claim 1, further comprising: Connected to the output node (OUT) and the rectifier (D R1 , D R2 , D R3 , D R4 ), the output filter (L O , C O ), the output filter (L O , C O ) is used to smooth the voltage provided by the rectifier (D R1 , D R2 , D R3 , D R4 ).

6. A method for controlling a phase-shifted full-bridge switching converter, the method comprising: Generate a first drive signal (V A ) for the first high-side transistor (M GA ) of the switching converter, a second drive signal (V B ) for the first low-side transistor (M GB ), a third drive signal (V C ) for the second high-side transistor (M GC ), and a fourth drive signal (V D ) for the second low-side transistor (M GD ), Among them, the first driving signal (V GA ) and the second driving signal (V GB ) are periodic, have a cycle period (T PWM ) and are pulse-width modulated, and have a time offset equal to half of the cycle period (T PWM ) between each other. Among them, the third driving signal (V GC ) and the fourth driving signal (V GD ) are periodic, have a cycle period (T PWM ) and are pulse-width modulated, and have a time offset equal to half of the cycle period (T PWM ) between each other. The first driving signal and the second driving signal (V GA , V GB ) are phase-shifted relative to the third driving signal and the fourth driving signal (V GC , V GD ); and Among them, the first driving signal (V GA ) is generated so that when the third driving signal (V GC ) indicates turning on the second high-side transistor (M C ), the first high-side transistor (M A ) is turned off, and the second driving signal (V GB ) is generated so that when the fourth driving signal (V GD ) indicates turning on the second low-side transistor (M D ), the first low-side transistor (M B ) is turned off. Among them, the first high-side transistor (M A ) and the first low-side transistor (M B ) are connected at a first circuit node (N1) to form a first half-bridge, and the second high-side transistor (M C ) and the second low-side transistor (M D ) are connected at a second circuit node (N2) to form a second half-bridge, wherein, the switching converter includes a transformer having a primary winding coupled between the first circuit node (N1) and the second circuit node (N2), and wherein, the method further comprises rectifying a current flowing through a secondary winding of the transformer.

7. The method according to claim 6, wherein, The first driving signal (V GA ) and the second driving signal (V GB ), and the third driving signal (V GC ) and the fourth driving signal (V GD ) are pulse-width modulated to have a duty cycle of 50%.

8. The method according to claim 6 or 7, further comprising: Set the phase shift in response to the output voltage (V OUT ) of the switching converter.

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