Conversion boost circuit for operational amplifiers

Abstract

This application relates to a boost converter circuit for an operational amplifier. A differential input stage of one circuit includes a first transistor (M1), a second transistor (M2), a third transistor (M3), and a fourth transistor (M4). The drains of the first transistor (M1) and the third transistor (M3) are coupled together at a first node (N1), and the drains of the second transistor (M2) and the fourth transistor (M4) are coupled together at a second node (N2). A first boost converter circuit (130) includes a fifth transistor (M10) and a first current mirror (M11, M12). The gate of the fifth transistor (M10) is coupled to the second node (N2). The source of the fifth transistor (M10) is coupled to the first node (N1). The first current mirror (M11, M12) is coupled to the fifth transistor (M10) and also to the second node (N2). A second boost converter circuit (140) includes a sixth transistor (M14) and a second current mirror (M15, M16). The gate of the sixth transistor (M14) is coupled to the first node (N1). The source of the sixth transistor (M14) is coupled to the second node (N2). The second current mirrors (M15, M16) are coupled to the sixth transistor (M14) and also to the first node (N1).

Description

Technical Field

[0001] This application relates to operational amplifiers. Background Technology

[0002] The "slew rate" of an operational amplifier is a measure of how quickly the amplifier can charge the capacitors connected to the amplifier's output node in response to a large change (increase or decrease) in the input signal to the amplifier. More broadly, the slew rate is a measure of the maximum rate of change of the amplifier's output voltage in response to a step change in the input.

[0003] One technique to increase the slew rate of an operational amplifier is to increase the bias current of its input stage. Unfortunately, increasing the input stage bias current leads to an increase in the amplifier's bandwidth, which in turn requires increasing the output stage compensation capacitor to improve circuit stability. However, increasing the compensation capacitor results in a decrease in the slew rate. Furthermore, increasing the input stage bias current of a folded gate-cathode operational amplifier requires a corresponding increase in the output stage current, which in turn increases the total input referred noise. Summary of the Invention

[0004] In one example, a circuit includes a differential input stage. The differential input stage includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The drains of the first transistor and the third transistor are coupled together at a first node, and the drains of the second transistor and the fourth transistor are coupled together at a second node. An output stage is also included, coupled to the input stage. A first conversion boost circuit and a second conversion boost circuit are also included. The first conversion boost circuit includes a fifth transistor and a first current mirror. The gate of the fifth transistor is coupled to the second node. The source of the fifth transistor is coupled to the first node. The first current mirror is coupled to the fifth transistor and to the second node. The second conversion boost circuit includes a sixth transistor and a second current mirror. The gate of the sixth transistor is coupled to the first node. The source of the sixth transistor is coupled to the second node. The second current mirror is coupled to the sixth transistor and to the first node. Attached Figure Description

[0005] To illustrate the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 The diagram illustrates a circuit (e.g., an operational amplifier) ​​that includes a boost converter to increase the circuit's slew rate.

[0007] Figure 2 Show example timing diagrams. Detailed Implementation

[0008] The operational amplifier described herein includes a differential input stage coupled to an output stage. The differential input stage includes a pair of boost converters—one configured to temporarily increase the current through a compensation capacitor when the voltage at the first input of the input stage is greater than the voltage at the second input of the input stage, and the other configured to temporarily increase the current through the compensation capacitor when the voltage at the second input is greater than the voltage at the first input. The boost converters are coupled to both the input and output stages of the operational amplifier. In addition to the current path through the differential input stage transistors, each boost converter also provides a current path to the compensation capacitor, thereby causing the charging or discharging current to / from the compensation capacitor to be greater than in the case without boost converters.

[0009] The boost converter circuit therefore increases the charging / discharging current of the compensation capacitor, resulting in a larger rate of change of voltage across the compensation capacitor. Since one terminal of the compensation capacitor is the output node of the operational amplifier, the output voltage from the operational amplifier can change at a faster rate, and thus the slew rate of the operational amplifier increases. An advantage of the disclosed boost converter circuit is that during steady-state operation (i.e., when the voltage to the operational amplifier input is approximately the same and does not undergo a step change), the boost converter circuit has little or no current flow. Therefore, the quiescent current of the operational amplifier is not increased due to the inclusion of the boost converter circuit.

[0010] Figure 1 An example of operational amplifier 100 is shown, which includes a complementary folded gate-cathode input stage 110, an output stage 120, and conversion boost circuits 130 and 140. Figure 1 The transistors in the example embodiments include metal-oxide-semiconductor field-effect transistors (MOSFETs), but other types of transistors (e.g., bipolar junction transistors) may be included in other example embodiments. Furthermore, although Figure 1 Each transistor in the examples is shown as an n-type MOSFET (NMOS) or a p-type MOSFET (PMOS), but in other examples, an NMOS device may be used instead of a PMOS device, and vice versa.

[0011] Input stage 110 includes a differential input stage and has a first input node 111 (VIN-) and a second input node 113 (VIN+). In this example, input stage 110 includes a pair of PMOS transistors M1 and M2, whose sources are connected to tail current source 15. The gates of input transistors M1 and M2 are connected to input nodes 111 and 113, respectively. The drain of input transistor M1 is connected to the drain of current source transistor M3 (NMOS) at node N1, and the source of M3 is connected to ground. The drain of input transistor M2 is connected to the drain of current source transistor M4 (NMOS) at node N2, and the source of M4 is connected to ground. The gates of M3 and M4 are biased at a positive voltage level (VB3). M3 and M4 are current source transistors and pass some or all of the tail current from tail current source 15 to ground. The gates of current source transistors M3 and M5 are connected to a common bias voltage.

[0012] The drains of current source transistors M3 and M4 are connected to the sources of NMOS gate-cathode transistors M5 and M6, respectively. The gates of gate-cathode transistors M5 and M6 are connected to the reference voltage VB1. The drain of gate-cathode transistor M5 is connected to the drain of PMOS transistor M7 and also to the gates of M7 and M8. The sources of M7 and M8 are connected to the supply voltage node VDD. M7 and M8 form a current mirror.

[0013] In this example, output stage 120 is implemented as a Class A output stage (a common-source amplifier with a resistor as a load), but it can be other types of output stages (e.g., Class AB output stage) in other examples. Output stage 120 includes a PMOS transistor M9, a resistor R1, and a compensation capacitor CC. The source of M9 is connected to the supply voltage node VDD. The gate of M9 is connected to terminal 121 of CC and to the drains of M6 and M8. The drain of M9 is connected to the opposite terminal 122 of CC and to the resistor R1, the opposite terminal of which is connected to the ground node. The voltage at terminal 122 of CC (which is also connected to the drain of M9 and the resistor R1) is the operational amplifier's output voltage (VOUT). In one embodiment, the output voltage VOUT is provided as VIN-voltage to input node 111. Thus, operational amplifier 100 operates in a closed-loop configuration.

[0014] Operational amplifier 100 also includes boost converter circuits 130 and 140. Each of boost converter circuits 130 and 140 is coupled to differential input stage 110 and output stage 120 at nodes N1 and N2, respectively, as shown. Boost converter circuits 130 and 140 have the same general circuit architecture. Boost converter circuit 130 includes a PMOS transistor M10, a current mirror 131, and a transistor M13. Current mirror 131 includes NMOS transistors M11 and M12. The source of M10 is connected to node N1, and the gate of M10 is connected to node N2 and to the drain of M12. The drain of M10 is connected to the drain of M11, to the gates of M11 and M12, and to the drain of M13. The sources of M11, M12, and M13 are connected to a ground node. The gate of M13 is connected to a bias voltage VB2.

[0015] The boost converter circuit 140 includes a PMOS transistor M14, a current mirror 141, and a transistor M17. The current mirror 141 includes NMOS transistors M15 and M16. The source of M14 is connected to node N2, and the gate of M14 is connected to node N1 and to the drain of M16. The drain of M14 is connected to the drain of M15, the gates of M15 and M16, and the drain of M17. The sources of M15, M16, and M17 are connected to a ground node. The gate of M17 is connected to a bias voltage VB2.

[0016] To aid in understanding the operation of the boost converter circuits 130 and 140, it is helpful to understand the operation of the operational amplifier 100 without the boost converter functionality of the boost converter circuits 130 and 140. If the VIN+ input voltage at input node 113 experiences a large positive jump relative to the VIN- input voltage at input node 111, then most or all of the tail current from the tail current source 15 will flow through M1 and into the drain of M3. When the current entering the current source transistor M3 is constant, the increase in the current through M1 will result in a decrease in the amount of current flowing through the gate-cathode transistor M5, and thus a corresponding decrease in the current flowing through M7 and the current mirror transistor M8. Since less current flows through M8, the voltage across the drain of M8 will decrease, which in turn makes it more difficult to drive M9 to turn on, thereby causing more current to flow through M9 and into R1. Due to the increased current flowing through R1, the voltage across R1 (which is the output voltage VOUT) decreases.

[0017] During steady-state operation, a relatively constant voltage difference is maintained across capacitor CC. During transition events, the voltage at terminal 121 of capacitor CC decreases, and the voltage at terminal 122 of capacitor CC increases, as described above. The voltage difference across capacitor CC causes the capacitor to discharge to the ground node through M6 and M4. M4 is a current source device, meaning its current is limited to a fixed level (the current of tail current source 15). Thus, the discharge current from capacitor CC is limited by tail current source 15. The rate of change of voltage across capacitor CC is therefore limited by tail current source 15. Terminal 122 (VOUT) of CC therefore has a transition rate limited by tail current source 15.

[0018] In addition to the current path from tail current source 15 through M3 or M4, the conversion boost circuits 130 and 140 also provide an additional discharge current path for capacitor CC. Figure 2 The diagram illustrates the timing of the operation of the boost converter 130 when VIN+ has a large positive transition relative to VIN-. Figure 2 The waveforms shown include VIN+ and VIN- voltages, and the current flowing through M10 (e.g., Figure 1 The current passing through M12 (as shown in the diagram) is I_M10. Figure 1 The current through M13 (as shown in the figure) and the current through M12 (such as Figure 1 (I_M13 shown in the diagram). For Class AB output stages, the boost converters 130 and 140 help improve the slew rate when charging and discharging the output capacitors. For Class A output stages, such as... Figure 1 The output stage shown in the diagram features a boost converter 130 that helps improve the slew rate of VOUT. For the Class A output stage, the boost converter 140 helps maintain symmetry in the event of leakage at the drains of the input transistors M1 and M2 and provides some, but not much, help in improving the slew rate of VOUT.

[0019] refer to Figure 1 and 2 When the gate-to-source voltage (Vgs) of M10 is greater than its threshold voltage (i.e., when the voltage at node N1 is greater than the voltage at node N2 (greater than at least the threshold voltage of M10)), the conversion boost circuit 130 actively forms a discharge current path for capacitor CC. This occurs during a conversion event, in which the VIN+ input voltage at input node 113 experiences a large positive jump relative to the VIN- input voltage at input node 111. This divergence between N1 and N2 occurs during... Figure 2 At position 202. Therefore, M10 is turned on to conduct current from M1 to the drain of M11. Figure 2The diagram shows that I_M10 increases at 210. As explained above, M11 and M12 form a current mirror. The channel width (W) to channel length (L) ratio of M12 is N times larger than the W / L ratio of M11. Therefore, the drain current through M12 will be N times larger than the current through M11. The drain current through M12 is at least partially the discharge current from capacitor CC through M6 to node N2 and from node N2 through M12 to ground. Figure 2 I_M12 increases at 220. Consequently, the discharge current from capacitor CC flows through both M4 (which is limited by the current from tail current source 15) and M12. Compared to the case without the conversion boost circuit 130, a larger discharge current therefore flows from CC due to the conversion boost circuit 130. The larger discharge current from capacitor CC results in a larger rate of change of voltage across capacitor CC with respect to time, and thus a larger rate of change of VOUT. Ultimately, VIN+ and VIN- converge again at 240 and the voltages at nodes N1 and N2 become equal (245), which again causes currents I_M10 and I_M12 to decrease, as shown at 250 and 255.

[0020] The gate and drain of M10 are connected to nodes N2 and N1, respectively. For the boost converter 140, the gate and drain of M14 are connected to nodes N1 and N2, respectively, meaning it has the opposite polarity to M10. Therefore, when VIN+ experiences a large positive transition relative to VIN-, M14 remains off while an additional current path for CC discharge is formed through the boost converter 130. Consequently, no current flows through the boost converter 140.

[0021] When VIN- experiences a large positive jump relative to the input voltage VIN+ at the input node, the operation of the boost converter 140 is largely similar to that described above. Therefore, VIN- becomes more positive than VIN+, the voltage at node N2 increases and the voltage at node N1 decreases, causing M14 to turn on. Current then flows from M2 to the drain of M15. M15 and M16 form a current mirror. The W / L ratio of M16 is N times larger than that of M15. Therefore, the drain current through M16 will be N times larger than the current through M15. The drain current through M16 includes the current flowing through M7, M5, and M16 and is used to charge capacitor CC. The current through M7 is mirrored through M8 to reach capacitor CC. Thus, the charging current to capacitor CC consists of a combination of the bias current through M3 and the current through M16. Compared to the case without the conversion boost circuit 140, due to the conversion boost circuit 140, a larger charging current therefore flows to CC. The larger charging current to capacitor CC produces a larger rate of change of voltage across CC with respect to time, and thus a larger slew rate of VOUT.

[0022] When charging current flows through the boost converter 140, no current flows through the boost converter 130 because the voltage at node N2 is greater than the voltage at node N1. Furthermore, during steady-state operation (i.e., VIN+ is approximately equal to VIN-), the voltage at node N1 is approximately equal to the voltage at node N2, and therefore Vgs of both M10 and M14 is insufficient to turn on either transistor. Therefore, during steady-state operation, no current flows through either the boost converter 130 or 140, and thus, the boost converters 130 and 140 do not contribute to the increase in quiescent current (exceeding the increase in bias current from tail current source 15).

[0023] Regarding the conversion boost circuit 130, as capacitor CC partially discharges through M12, eventually, the voltage at node N1 becomes equal to the voltage at node N2, and M10 is turned off. However, at this moment, since the capacitance on the drain of M11 remains charged to a voltage greater than 0V during the conversion boost phase, the voltage on the drain of M11 may be greater than zero. Since M11 will operate in the subthreshold region to make its gate voltage less than the threshold voltage of the transistor, the impedance will be higher at the drain of M11, resulting in a longer gate discharge time for M11. In this subthreshold region of M11, a small amount of current will flow through M11, and the drain voltage of M11 will slowly decay to zero (the decay time is partly a function of the capacitance within M11). Due to the current mirror formed by M11 and M12, current can also flow through M12, thereby forming an offset current between the input transistor pairs M1 and M2. To avoid this offset, M13 is included in the conversion boost circuit 130. M13 is biased on. In one example, M13 could be part of a current mirror, where another transistor in the current mirror is a current source device. This causes current to flow through M13 even when the voltage across M11 is greater than zero. M13 thus provides a current bypass path so that current flows to ground instead of through M11 and M12. Because current flows through M13 (as... Figure 2 (As shown at 260), therefore the drain voltage of M11 decays to zero very quickly. Transistor M17 functions similarly within the converter boost circuit 140.

[0024] In this description, the term "couple" (or "couples") means an indirect or direct connection. Therefore, if a first device is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices and connections. Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A circuit for operational amplification, comprising: A differential input stage includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the drains of the first transistor and the third transistor are coupled together at a first node, and the drains of the second transistor and the fourth transistor are coupled together at a second node. An output stage, which is coupled to the input stage; A first conversion boost circuit includes a fifth transistor and a first current mirror, wherein the gate of the fifth transistor is coupled to the second node, the source of the fifth transistor is coupled to the first node, and the first current mirror is coupled to the fifth transistor and coupled to the second node; The second conversion boost circuit includes a sixth transistor and a second current mirror. The gate of the sixth transistor is coupled to the first node, the source of the sixth transistor is coupled to the second node, and the second current mirror is coupled to the sixth transistor and to the first node. and A seventh transistor, the drain of which is coupled to the drain of the fifth transistor, and the source of which is coupled to a ground node.

2. The circuit of claim 1, further comprising an eighth transistor, the drain of the eighth transistor being coupled to the drain of the sixth transistor, and the source of the eighth transistor being coupled to a ground node.

3. The circuit according to claim 1, wherein: The first current mirror includes a first current mirror transistor and a second current mirror transistor. The gates of the first current mirror transistor and the second current mirror transistor are coupled together, and the sources of the first current mirror transistor and the second current mirror transistor are coupled together. The drain of the fifth transistor is coupled to the drain of the first current mirror transistor and the gate, and the drain of the second current mirror transistor is coupled to the gate of the fifth transistor and coupled to the second node.

4. The circuit according to claim 3, wherein: The second current mirror includes a third current mirror transistor and a fourth current mirror transistor. The gates of the third current mirror transistor and the fourth current mirror transistor are coupled together. The source of the third current mirror transistor and the fourth current mirror transistor are coupled together. The drain of the sixth transistor is coupled to the drain of the third current mirror transistor and the gate. The drain of the fourth current mirror transistor is coupled to the gate of the sixth transistor and coupled to the first node.

5. The circuit according to claim 1, wherein the output stage includes a Class A output stage.

6. A circuit for operational amplification, comprising: A differential input stage includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a first current terminal and a second current terminal. The second transistor has a third current terminal and a fourth current terminal. The third transistor has a fifth current terminal and a sixth current terminal. The fourth transistor has a seventh current terminal and an eighth current terminal. The second current terminal and the fifth current terminal are coupled together at a first node, and the fourth current terminal and the seventh current terminal are coupled together at a second node. A first conversion boost circuit includes a fifth transistor and a first current mirror. The fifth transistor has a first control input, a ninth current terminal and a tenth current terminal. The first control input is coupled to a second node, the ninth current terminal is coupled to the first node, and the first current mirror is coupled to the fifth transistor and coupled to the second node. The second conversion boost circuit includes a sixth transistor and a second current mirror. The sixth transistor has a second control input, an eleventh current terminal and a twelfth current terminal. The second control input is coupled to the first node, the eleventh current terminal is coupled to the second node, and the second current mirror is coupled to the sixth transistor and coupled to the first node. and A seventh transistor, one terminal of which is coupled to the tenth current terminal, and the other terminal of which is coupled to a ground node.

7. The circuit of claim 6, further comprising an eighth transistor having a thirteenth current terminal and a fourteenth current terminal, the thirteenth current terminal being coupled to the twelfth current terminal and the fourteenth current terminal being coupled to a ground node.

8. The circuit of claim 6, wherein the first current mirror comprises: The first current mirror transistor has a third control input and thirteenth and fourteenth current terminals. The second current mirror transistor has a fourth control input and a fifteenth and a sixteenth current terminal; The third control input is coupled to the fourth control input; The fourteenth current terminal is coupled together with the sixteenth current terminal; The tenth current terminal is coupled to the third control input and the fourth control input, and is also coupled to the thirteenth current terminal; and The fifteenth current terminal is coupled to the first control input and also to the second node.

9. The circuit of claim 8, wherein the second current mirror comprises: The third current mirror transistor has a fifth control input and a seventeenth and an eighteenth current terminal; The fourth current mirror transistor has a sixth control input, a nineteenth current terminal, and a twentieth current terminal. The fifth control input is coupled to the sixth control input; The eighteenth current terminal is coupled together with the twentieth current terminal; The twelfth current terminal is coupled to the fifth control input and the sixth control input, and is also coupled to the seventeenth current terminal; and The nineteenth current terminal is coupled to the second control input and also to the first node.

10. The circuit of claim 6, further comprising an output stage coupled to the differential input stage.

11. The circuit of claim 10, wherein the output stage includes a Class A or Class AB output stage.

12. The circuit of claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprise metal-oxide-semiconductor field-effect transistors.

13. A circuit for operational amplification, comprising: The differential input stage consists of a first node and a second node; An output stage, which is coupled to the input stage; A first conversion boost circuit is coupled at the first node and the second node to the differential input stage, coupled to the output stage, and coupled to a ground node, wherein, in response to a first non-zero voltage polarity between the first node and the second node, the first conversion boost circuit is configured to provide a first current path from the output stage to the ground node, wherein the first conversion boost circuit includes a first transistor, a second transistor, and a first current mirror, the second transistor being coupled between the first transistor and the ground node; and A second conversion boost circuit is coupled to the differential input stage, the output stage, and the ground node at the first and second nodes, wherein, in response to a second non-zero voltage polarity between the first and second nodes, the second conversion boost circuit is configured to provide a second current path from the output stage to the ground node, the second non-zero voltage polarity being opposite to the polarity of the first non-zero voltage polarity.

14. The circuit of claim 13, wherein the first transistor has a first control input, a first current terminal and a second current terminal, the first control input being coupled to the second node, the first current terminal being coupled to the first node, and the first current mirror being coupled to the first transistor and to the second node.

15. The circuit of claim 14, wherein the second transistor is configured to provide a current path from the first transistor to the ground node.

16. The circuit of claim 14, wherein the second conversion boost circuit includes a second transistor and a second current mirror, the second transistor having a second control input, a third current terminal and a fourth current terminal, the second control input being coupled to the first node, the third current terminal being coupled to the second node, and the second current mirror being coupled to the second transistor and coupled to the first node.

17. The circuit according to claim 16, wherein: The first conversion boost circuit includes a third transistor coupled between the first transistor and the ground node, the third transistor being configured to provide a current path from the third transistor to the ground node; and The second conversion boost circuit includes a fourth transistor coupled between the first transistor and the ground node, the fourth transistor being configured to provide a current path from the fourth transistor to the ground node.

18. The circuit of claim 14, wherein the output stage includes a capacitor, and the first current path and the second current path include the capacitor.

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