Memory controller, memory system and operation method thereof

Abstract

A memory controller, a memory system and an operation method thereof are provided. When a data write request for a first block is received, an erase programming interval (EPI) representing a time period elapsed after erasing the first block is determined. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operating condition selected from among a plurality of operating conditions. When the determined EPI is greater than the reference time, data is programmed to the first block based on a second operating condition selected from among the plurality of operating conditions.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0044478, filed on April 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a memory controller and a memory system, and more particularly, to a memory controller and a memory system providing improved threshold voltage distribution characteristics and related operating methods. Background Art

[0003] A memory system typically includes a memory controller and one or more memory devices, such as nonvolatile memory devices. Nonvolatile memory devices, such as flash memory devices, are widely used in cellular phones, digital cameras, personal digital assistants (PDAs), mobile computer devices, stationary computer devices, and other devices.

[0004] A flash memory device includes a plurality of blocks of memory cells, wherein each of the plurality of blocks includes a plurality of pages of memory cells. In the flash memory device, an erase program interval (EPI) of a block may correspond to a period of time that passes after an erase operation has been performed on the block until a program (PGM) operation of the block is to be performed. In view of the characteristics of some flash memory devices, in the case where the EPI is long, the threshold voltage distribution characteristics of the flash memory device may be degraded, and as a result, the reliability of the data may be degraded. Summary of the invention

[0005] The inventive concept provides a memory controller, a nonvolatile memory device, and a memory system, and related operations thereof, capable of reducing or preventing degradation of reliability of data despite a relatively long erase program interval (EPI).

[0006] According to one aspect of the inventive concept, a method for operating a memory system is provided, the memory system including a memory device having a plurality of blocks. When a data write request for a first block is received, an erase programming interval (EPI) representing a time period elapsed after erasing the first block may be determined. In response to the determined EPI being equal to or less than a reference time, data may be programmed to the first block based on a first operating condition selected from among a plurality of operating conditions, and in response to the determined EPI being greater than the reference time, data may be programmed to the first block based on a second operating condition selected from among the plurality of operating conditions.

[0007] According to another aspect of the inventive concept, a memory controller configured to control a memory device including multiple blocks may include: a host interface, configured to communicate with a host and receive a data write request and an address from the host; an erase programming interval (EPI) detector, configured to determine an EPI representing a time period elapsed after erasing a first block pointed to by a data write request in the multiple blocks of the memory device; and a control information generator, configured to output control information indicating an operating condition selected from among a plurality of operating conditions based on the determined EPI, so that data will be written to the first block according to the one operating condition.

[0008] According to another aspect of the inventive concept, a memory system includes a memory device having multiple blocks, wherein the memory device includes: a voltage generator configured to generate a programming voltage and a verification voltage for a write operation for the multiple blocks; and a control logic configured to: when a data write request for a first block is received, in response to an erase programming interval (EPI) representing a time period elapsed after erasing the first block, set a level of at least one of the programming voltage and the verification voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a memory system according to an embodiment;

[0011] Figure 2 yes Figure 1 A block diagram of an implementation example of a memory controller;

[0012] Figure 3 yes Figure 1 A block diagram of an implementation example of a memory device;

[0013] Figure 4 is a flowchart of a method of operating a memory system according to an example embodiment;

[0014] Figure 5 and Figure 6 is a conceptual diagram of an example of writing data to a block according to an example embodiment;

[0015] Figures 7 to 10 , Fig.11A and Fig. 11B is a diagram of an example of changing an operating condition according to an example embodiment;

[0016] Fig.12 is a flow chart of a read operation according to an example embodiment;

[0017] Fig.13is a block diagram of an example of writing data according to a modifiable embodiment;

[0018] Fig.14 and Fig.15 is a flow chart of a method of operating a memory controller according to an example embodiment;

[0019] Fig.16A and Fig. 16B is a block diagram of a memory system according to a modifiable embodiment;

[0020] Fig.17 is a block diagram of a memory system according to another modifiable embodiment;

[0021] Fig.18 is a block diagram of a memory system according to another modifiable embodiment;

[0022] Fig.19 and Fig. 20 is a flowchart of an operating method of a memory system according to a modifiable embodiment; and

[0023] Fig.21 is a block diagram of an example of a memory device in a solid state drive (SSD) system according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram of a memory system 10 according to an embodiment. Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200 , and the memory device 200 may include a memory cell array 210 , a voltage generator 220 , and a control logic 230 (a logic circuit for controlling internal operations of the memory device 200 ).

[0026] According to an embodiment, the memory device 200 may be a non-volatile memory device. In some embodiments, the memory system 10 may be implemented as an internal memory embedded in an electronic device, for example, the memory system 10 may be an embedded universal flash memory (UFS) memory device, an embedded multimedia card (eMMC), or a solid state drive (SSD). In some embodiments, the memory system 10 may be implemented as an external memory that can be removed from the electronic device, for example, the memory system 10 may be a UFS memory card, a compact flash memory (CF) card, a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, a memory stick, or an external solid state drive.

[0027] The memory controller 100 may control the memory device 200 and, for example, read data stored in the memory device 200 or write (or program) data to the memory device 200 in response to a read request / write request received from the host HOST. Specifically, the memory controller 100 may control a write operation, a read operation, and an erase operation of the memory device 200 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 200. In addition, data DATA to be written to the memory device 200 and data DATA read from the memory device 200 may be exchanged between the memory controller 100 and the memory device 200.

[0028] The memory cell array 210 may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. However, the embodiment is not limited thereto. For example, in some embodiments, the plurality of memory cells may be resistive memory cells (such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM)).

[0029] The memory cell array 210 may include a plurality of blocks. Each of the plurality of blocks may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells. Each page of the memory cells may be uniquely identified by a corresponding row address, and when the row address is decoded by a row decoder, a word line corresponding to the page is selected (e.g., to provide access to the memory cells of the page). In the memory cell array 210, an erase operation of data may be performed on each block. For example, the memory controller 100 may perform an erase operation in units of blocks, so that a block of memory cells is erased in the same erase operation. A block of memory cells may be the smallest erase unit in the memory cell array 210, and may be formed by all pages (e.g., memory cells of a certain number of rows arranged side by side in the column direction) arranged in a specific physical area within the memory cell array 210. A write operation and a read operation of data may be performed on each page (e.g., in units of pages). For example, the memory device 200 may perform an erase operation on each block by referring to a block address portion of the address ADDR received from the memory controller 100 , and may perform a write operation and a read operation on each page by referring to a row address portion of the address ADDR received from the memory controller 100 .

[0030] The voltage generator 220 may generate various types of voltages for performing the above-mentioned write operation / read operation and erase operation. For example, a data write operation may be performed using an incremental step pulse programming (ISPP) voltage, and the voltage generator 220 may generate an ISPP voltage including a plurality of voltage pulses, and provide the ISPP voltage to the memory cell array 210. As an example of operation, a write operation of a page of data to a physical page of a memory cell may be performed by a plurality of programming operations using a plurality of voltage pulses. Therefore, references to the write operation and programming operation of data may be mixed and should be understood in context. After each programming operation is performed, a verification operation may be performed to determine the pass or fail of the programming operation, and the voltage generator 220 may generate a verification voltage for the verification operation, and provide the verification voltage to the memory cell array 210. In addition, the voltage generator 220 may generate a read voltage for a read operation of data and provide the read voltage to the memory cell array 210, and may generate an erase voltage having a high voltage level and provide the erase voltage to the memory cell array 210.

[0031] The control logic 230 may control the overall operation of the memory device 200. For example, the control logic 230 may control the voltage generator 220, and the levels of various voltages generated in the voltage generator 220 may be changed based on such control of the control logic 230. In addition, the threshold voltage distribution of the memory cells of the memory cell array 210 may be adjusted according to the voltage generated from the voltage generator 220, and according to example embodiments, the levels of various voltages generated in the voltage generator 220 may be changed according to the result of determining an erase program interval (EPI) to reduce or prevent the degradation of data reliability due to the EPI characteristics corresponding to the period between the erase time and the program time.

[0032] In view of the characteristics of a flash memory device (specifically, a vertical NAND flash memory (VNAND) including a three-dimensional memory block), when the EPI (corresponding to the time between erasing and programming) is long, data reliability may deteriorate. For example, during a period after an erase operation is performed until a programming operation is to be performed, diffusion of holes to a spatial region may occur, and when data is programmed after a relatively long EPI state, electrons may recombine with holes after the programming operation is performed, and thus the threshold voltage distribution characteristics may deteriorate as the threshold voltage distribution shifts. For example, when data is programmed after a long EPI state, the threshold voltage distribution of the memory cell may be reduced more easily and faster (in the direction of reducing the threshold voltage level (e.g., with respect to the threshold voltage distribution) than when data is programmed after a short EPI state. Fig. 9 and Fig.11AThe window margin may be small and the distribution characteristics of the threshold voltage distribution of the memory cell may be degraded. When the block determined to have a long EPI is not used to prevent the above reliability from being degraded due to the EPI, the storage space of the memory device 200 may be inefficiently used and frequent garbage collection operations may be caused, so the life of the memory device 200 may be shortened.

[0033] According to example embodiments, the EPI of a block may be determined as part of a write operation, and conditions (e.g., operating conditions) for performing various memory operations on the block (during a write operation and / or during a subsequent read operation) may be changed according to the detection result, so that even when data is programmed after a long EPI state, degradation of the reliability of the data may be reduced or prevented. For example, with respect to a write operation of a first block, an EPI corresponding to a time period after an erase time of the first block until a programming time may be determined, and when the EPI of the first block is equal to or less than a reference time (e.g., a set reference time value), data may be written to the first block according to a first operating condition. On the other hand, when the EPI of the first block is greater than the reference time, data may be written to the first block according to a second operating condition. Therefore, in the first block, the threshold voltage distribution of a page having data written according to the first operating condition and the threshold voltage distribution of a page having data written according to the second operating condition may be different from each other.

[0034] Notably, the EPI of a block determined during a write operation may not include the time at which the memory cells are physically programmed (this is because, since the EPI may affect how the physical programming of the memory cells is performed, the physical programming of the memory cells occurs after the EPI is determined). Instead, the programming time of the block used to determine the EPI of the block may correspond to the time of the overall programming operation of the block, such as the time when the block is selected for programming (such as by associating the address of the block with a write command to become the target of programming). For example, the EPI may be determined when the memory controller 100 generates a write command with an address identifying the block (e.g., the block address), or the EPI may be determined when the memory device 200 receives a write command with an address identifying the block. Thus, the EPI may correspond to a period of time that has passed since the most recent erase of the block selected for physical programming as part of the overall programming operation.

[0035] According to an embodiment, the memory controller 100 may include an operating condition controller 110, which may determine the EPI of the first block, and may generate control information CTRL_OC for controlling the operating condition of the first block according to the detection result and provide the control information CTRL_OC to the memory device 200. The control logic 230 may store various setting information for writing data to the first block according to various operating conditions, and may control the internal operation of the memory device 200 by providing setting information corresponding to the first operating condition or the second operating condition according to the control information CTRL_OC. For example, the control logic 230 may control the operation of the voltage generator 220 differently according to the control information CTRL_OC, and the level of the program voltage (e.g., ISPP voltage) for data writing and / or the level of the verification voltage may be set differently under the first operating condition and the second operating condition.

[0036] As described above, according to example embodiments, when data is written according to the second operating condition, the threshold voltage distribution may be increased (or moved to the right or in a direction of increasing the threshold voltage level) compared to the case where data is written according to the first operating condition, and / or the width of the threshold voltage distribution may be adjusted to be narrower than the case where data is written according to the first operating condition. Therefore, the degradation of the threshold voltage distribution characteristics that may occur after the long EPI state may be balanced, and thus the reliability of the data may be improved.

[0037] According to example embodiments, when the read condition as an operating condition is changed based on the result of determining the EPI, the level of the read voltage under the first operating condition and the level of the read voltage under the second operating condition may be set differently. For example, information of the EPI determined during the write operation of data may be stored in the memory controller 100 or the memory device 200, and the stored EPI information (or the stored EPI) may be referred to during the read operation of the data. The EPI information may be stored for each page of the block or for a memory group of a unit other than the page as described herein. Assuming that a read operation is performed on the first page of the first block, when the EPI of the first page of the first block stored is relatively short, the level of the first read voltage set under the first operating condition may be relatively high, and when the EPI of the first page of the first block stored is relatively long, the level of the second read voltage set under the second operating condition may be relatively low. When data is written after the long EPI state, since the threshold voltage distribution of the memory cell is reduced, the threshold voltage distribution characteristics of the memory cell may be degraded; however, based on the change in the level of the read voltage as the operating condition, the degradation of the reliability of the data may be reduced or prevented.

[0038] In some embodiments, the operating condition represents conditions of various voltage levels applied to a core (e.g., a memory cell core) including a plurality of blocks, and thus the operating condition may be referred to as a core condition. In addition, the operating condition may include at least one of a programming condition for a programming operation to be performed during a write operation, a verification condition for verifying the programming operation, and a read condition related to a read operation on a block.

[0039] At least one of the various memory operations described above as operations for preventing characteristic degradation due to a long EPI may be changed. For example, only one of the programming condition, the verification condition, and the read condition may be changed based on the result of determining the EPI. Alternatively, as a modifiable example, two or more or all of the programming condition, the verification condition, and the read condition may be changed based on the result of determining the EPI.

[0040] Figure 2 yes Figure 1 1 is a block diagram of an implementation example of a memory controller 100.

[0041] Reference Figure 1 and Figure 2 , the memory controller 100 may include a host interface (HOST I / F) 120, a processor 130, an EPI detector 140, a control information generator 150, a buffer 160, and a memory interface (memory I / F) 170. Figure 2 Although not shown in the figure, the memory controller 100 may also include various other components, such as a RAM for temporarily storing various information and a ROM for storing various information in a non-volatile manner. Each of some of the information may provide a value defining a corresponding operating condition (e.g., one or more of a programming voltage, a verification voltage, etc.), and may be selected based on the determined EPI. The RAM may be used as a working memory, and the processor 130 may control the overall operation of the memory controller 100 by driving the firmware loaded into the RAM. The RAM may be implemented as various types of memory, for example, the RAM may be implemented as at least one of a cache memory, a DRAM, an SRAM, a PRAM, and a flash memory device. As an example of firmware, a flash translation layer (FTL) may be loaded into the RAM, and various functions related to flash memory operations may be performed by driving the FTL.

[0042] The host interface 120 provides a physical connection between the host HOST and the memory system 10 to facilitate communication therebetween. For example, the host interface 120 may include various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), IEEE 1394, Universal Serial Bus (USB), SD card, Multimedia Card (MMC), eMMC, and CF card interfaces.

[0043] The memory interface 170 provides a physical connection between the memory controller 100 and the memory device 200 and facilitates communication therebetween. For example, commands CMD, addresses ADDR, and data DATA may be exchanged between the memory controller 100 and the memory device 200 via the memory interface 170. Data directed by a write request received from the host HOST and data read from the memory device 200 may be temporarily stored in the buffer 160.

[0044] According to an embodiment, the memory controller 100 may determine the EPI of a block of the memory device 200 , and based on the EPI, may control operating conditions related to a write operation and / or a read operation. Figure 1 The operating condition controller 110 shown in FIG. 1 may include various components. For example, the operating condition controller 110 may include an EPI detector 140 and a control information generator 150 .

[0045] The EPI detector 140 may include one or more timers, and may determine the respective EPIs of the blocks included in the memory cell array 210 of the memory device 200. The EPI detector 140 may include various timers capable of measuring time, for example, when the EPI detector 140 measures time based on clock count, the EPI detector 140 may include a counter. According to example embodiments, the memory cell array 210 may include a plurality of blocks, and a timer may be provided for each block. Alternatively, the memory system 10 may be implemented such that: a plurality of blocks share one timer, or a timer is provided for each group of some blocks; or the memory system 10 may be implemented such that: a timer is provided separately for each of a plurality of pages included in each block (or for each group of some pages).

[0046] Based on the detection result of the EPI detector 140, the control information generator 150 may generate the above-mentioned control information CTRL_OC. The control information CTRL_OC may include information for indicating one of a plurality of operating conditions. According to some embodiments, the memory device 200 may store setting information related to a plurality of operating conditions, and may perform a data write operation and / or a read operation according to the control information CTRL_OC received from the memory controller 100.

[0047] Figure 3 yes Figure 1 2 is a block diagram of an implementation example of a memory device 200. Figure 3 An implementation example of a flash memory device as a memory device is shown.

[0048] Reference Figures 1 to 3 , the memory device 200 may include a memory cell array 210, a voltage generator 220, a control logic 230, a row decoder 240, and a page buffer 250. Figure 3 Although not shown in the figure, the memory device 200 may further include other various components related to memory operations, such as a data input / output circuit, an input / output interface, etc.

[0049] The memory cell array 210 may include a plurality of blocks BLK1 to BLKz (where z is an integer greater than 2), and the memory cells of the plurality of blocks BLK1 to BLKz may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. The memory cell array 210 may be connected to a row decoder 240 via word lines WL, string selection lines SSL, and ground selection lines GSL, and may be connected to a page buffer 250 via bit lines BL. Each memory cell may store one or more bits, for example, each memory cell may correspond to a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

[0050] In one embodiment, the memory cell array 210 may include a two-dimensional memory cell array, which may include a plurality of cell strings arranged in row and column directions. According to an embodiment, the memory cell array 210 may include a three-dimensional memory cell array, which may include a plurality of cell strings, and each cell string may include memory cells vertically stacked on a substrate and connected to word lines, respectively. U.S. Patents Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 providing exemplary details of the structure and operation of a three-dimensional memory cell array (including multiple layers and having word lines and / or bit lines shared between multiple layers) are incorporated herein by reference.

[0051] Based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 100, the control logic 230 may output various internal control signals for programming data to the memory cell array 210 or reading data from the memory cell array 210. For example, the control logic 230 may output a voltage control signal CTRL_vol for controlling the levels of various voltages generated in the voltage generator 220, may provide a row address X-ADDR to the row decoder 240, and may provide a column address Y-ADDR to the page buffer 250. In addition, the voltage generator 220 may generate various voltages for the memory device 200, for example, the voltage generator 220 may generate a program voltage Vpgm for a write operation, a verification voltage Vvfy, and a read voltage Vrd for a read operation.

[0052] In addition, the control logic 230 may include an operating condition setter 231, and according to some embodiments, setting information related to a variety of operating conditions may be stored in the operating condition setter 231. The control logic 230 may select one or more operating conditions in response to the control information CTRL_OC, and may output a voltage control signal CTRL_vol based on the setting information corresponding to the selected operating condition, thereby controlling the levels of various voltages. As in the previous embodiment, the level of one or more of the program voltage Vpgm, the verification voltage Vvfy, and the read voltage Vrd may be changed according to the selected operating condition. Figure 3 The operation condition setter 231 is shown to be included in the control logic 230 . However, the embodiments described herein are not limited thereto, and the memory device 200 may be implemented such that the operation condition setter 231 is outside the control logic 230 .

[0053] Figure 4 is a flowchart of a method of operating a memory system according to an example embodiment. Figure 4 In the present invention, a memory system includes a memory controller and a memory device, and an example in which a write operation is performed on a first block of the memory device is shown.

[0054] Reference Figure 4, the memory controller may receive a write request from the host, and may determine (or, detect) the EPI of the first block to which the data is to be written (in operation S11). For example, the memory controller may include a timer, and the timer may determine (e.g., measure or track) a time period that has passed since the most recent erase operation was performed on the first block as the EPI. In addition, it may be determined whether the determined EPI is equal to or less than a reference time Tref (in operation S12), and when the determined EPI is equal to or less than the reference time Tref, it may be determined that a relatively short time has passed since the erase operation was performed on the first block, in which regard, the data may be written to the first block according to the first operating condition (in operation S13). On the other hand, when the determined EPI is greater than the reference time Tref, it may be determined that a relatively long time has passed since the erase operation was performed on the first block, in which regard, the data may be written to the first block according to the second operating condition (in operation S14).

[0055] During the data writing process, the first operating condition may include a programming voltage level and a verification voltage level, and at least one of the programming voltage level and the verification voltage level under the first operating condition may be different from the level under the second operating condition. According to an embodiment, the threshold voltage distribution of the case where data is written according to the second operating condition may be increased compared to the case where data is written according to the first operating condition.

[0056] Figure 5 and Figure 6 is a conceptual diagram of an example of writing data to a block according to an example embodiment.

[0057] Reference Figure 5 When data is requested to be written for the first block BLK1, the EPI of the first block BLK1 may be determined and the determined EPI may be compared with a reference time. When the EPI of the first block BLK1 is equal to or less than the reference time, data may be written to one or more pages based on the first operating condition.

[0058] After writing data to some pages of the first block BLK1 according to the first operating condition, a request to write data to the first block BLK1 may be made again after a period of time. Therefore, the EPI of the first block BLK1 may be determined again, and the EPI may exceed the reference time when the EPI is determined again. Therefore, data may be written to other pages of the first block BLK1 based on the second operating condition.

[0059] Reference Figure 6 As a plurality of operating conditions, first to nth operating conditions may be defined. In this case, a plurality of reference times may be defined, and the EPI determined for the first block BLK1 may be compared with the plurality of reference times.

[0060] When the EPI of the first block BLK1 is equal to or less than the first reference time, data may be written to some pages of the first block BLK1 based on the first operating condition. Thereafter, when a write operation is performed on the first block BLK1 again, the EPI of the first block BLK1 may have a value greater than the first reference time and equal to or less than the second reference time, in which case data may be written to other pages of the first block BLK1 based on the second operating condition. Similarly, as time passes, the operating condition of the first block BLK1 may change, and when the EPI is greater than the (n-1)th reference time, data may be written to other pages of the first block BLK1 based on the nth operating condition.

[0061] The reference time may be set differently. For example, the reference time may have a size greater than 10 minutes. In some examples, the reference time may be less than 100 minutes (such as less than 1 hour). The time standard may increase proportionally, for example, the first reference time may correspond to 25 minutes, and the second reference time may correspond to 50 minutes. However, one or more embodiments described herein are not limited thereto, and the reference time may be set according to various methods.

[0062] Figures 7 to 11B is a diagram of an example of changing an operating condition according to an example embodiment. Figures 7 to 11B An example is shown in which the writing condition of data is changed according to the result of determining EPI.

[0063] Reference Figure 7 , the operating condition may be changed according to a method of changing the level of the ISPP voltage to write data into the block. For example, when the EPI of the block is equal to or less than the reference time, an ISPP voltage ISPP1 according to a first operating condition (e.g., a normal operating condition) may be generated, and on the other hand, when the EPI of the block is greater than the reference time, an ISPP voltage ISPP2 according to a second operating condition (e.g., a changed operating condition) may be generated.

[0064] The ISPP voltage may include a plurality of voltage pulses whose levels gradually increase. According to an embodiment, a voltage increment ΔV2 (also referred to as Δ2) of the ISPP voltage ISPP2 under the second operating condition may be small compared to a voltage increment ΔV1 (also referred to as Δ1) of the ISPP voltage ISPP1 under the first operating condition. In addition, the number of voltage pulses of the ISPP voltage ISPP2 under the second operating condition may be greater than the number of voltage pulses of the ISPP voltage ISPP1 under the first operating condition. In this regard, as Figure 7As shown in , the width of the threshold voltage distribution of the memory cell having data written according to the second operating condition can be smaller than the width of the distribution corresponding to the result of writing data according to the first operating condition represented by the dotted line, so the characteristics of the distribution can be improved. That is, when the memory cell has a plurality of threshold voltage distributions, the distance between the distributions can be increased, and even when the threshold voltage distribution is reduced due to the long EPI, the window margin between the distributions can be fully obtained. Therefore, the reliability of the data can be improved.

[0065] Figure 8 Characteristics of the voltage pulse of the ISPP voltage under the first operating condition and the second operating condition are shown.

[0066] exist Figure 8 In the figure, the horizontal axis represents time (T) and the vertical axis represents voltage (V). Figure 8 , the number of voltage pulses of the ISPP voltage ISPP1 under the first operating condition may correspond to A, and the voltage increment of the ISPP voltage ISPP1 may correspond to ΔV1. On the other hand, the number of voltage pulses of the ISPP voltage ISPP2 under the second operating condition selected when the EPI is relatively long may correspond to (A+ɑ), and the voltage increment of the ISPP voltage ISPP2 may correspond to ΔV2. The voltage increment ΔV1 of the ISPP voltage ISPP1 under the first operating condition may be greater than the voltage increment ΔV2 of the ISPP voltage ISPP2 under the second operating condition, and the maximum level Vmax of the voltage pulse of the ISPP voltage ISPP1 may be the same as the maximum level Vmax of the voltage pulse of the ISPP voltage ISPP2. Therefore, the number of voltage pulses of the ISPP voltage ISPP2 under the second operating condition may be greater than that of the first operating condition. In some examples, the number of voltage pulses of the ISPP voltage ISPP1 and the number of voltage pulses of the ISPP voltage ISPP2 may correspond to the maximum number of voltage pulses that can be applied when programming to a specific voltage threshold of a page of memory cells. For example, when a verify operation confirms that all memory cells have been properly programmed to the desired voltage threshold, the number of voltage pulses applied when programming to a particular voltage threshold level may be less than the maximum number of voltage pulses described.

[0067] Fig. 9 An example is shown in which the level of a verification voltage as an operation condition is changed according to a result of determining EPI.

[0068] Reference Fig. 9, after performing a programming operation to write data into a block, the level of a verification voltage used for the verification operation may be changed according to a result of determining the EPI, for example, the level of the second verification voltage Vvfy2 under the second operation condition where the determined EPI is greater than the reference time may be greater than the level of the first verification voltage Vvfy1 under the first operation condition where the EPI is equal to or less than the reference time. For example, when writing data into a block having a long EPI, the distribution of the threshold voltage level may be reduced. However, since the verification operation is performed using the second verification voltage Vvfy2 having a relatively high level during the process of programming data, the distribution of the threshold voltage level may be relatively increased, and thus the degradation of data reliability due to the long EPI may be balanced.

[0069] According to an embodiment, the operating condition may include a program voltage (or ISPP voltage) and a verification voltage together. In this regard, Figure 8 and 9 The embodiments shown in the can be applied together to the inventive concept. For example, together with the program operation performed using the ISPP voltage whose voltage increment is relatively small under the second operating condition, the verification operation can be performed using a verification voltage with a relatively high voltage level. In this regard, compared with the case where data is written according to the first operating condition, in the case where data is written under the second operating condition, the distribution of the threshold voltage level can be located on the right side, and the width of the distribution can be reduced. Therefore, the degradation of the reliability of the data due to the long EPI can be reduced or prevented.

[0070] Fig.10 An example of defining various operating conditions according to example embodiments and changing the levels of a program voltage and a verification voltage together according to a result of determining an EPI is shown.

[0071] Reference Fig.10 As the EPI between the erase time and the program time for the block increases, the operating condition of the block may change, for example, the operating condition may change stepwise as the EPI elapses.

[0072] When the EPI of the block is equal to or less than the first reference time Tref1, the write operation may be performed according to the first operating condition, and the level of the ISPP voltage may be relatively high, which may show that the increment of the voltage pulse of the ISPP voltage is relatively large. In addition, when the EPI is equal to or less than the first reference time Tref1, the level of the verification voltage Vvfy may be relatively low, and thus, the threshold voltage distribution obtained after the write operation is completed may be located on the left side compared to the threshold voltage distribution obtained after the write operation is performed according to another operating condition.

[0073] As the EPI of the block elapses, when the EPI is greater than the first reference time Tref1 and equal to or less than the second reference time Tref2, a write operation may be performed according to the second operating condition, in which case the level of the ISPP voltage may be reduced, which may show that the increment of the voltage pulse of the ISPP voltage may be reduced compared to the first operating condition. In addition, the level of the verification voltage Vvfy under the second operating condition may be increased compared to the first operating condition, and the threshold voltage distribution may be located on the right side compared to the case where the write operation is performed according to the first operation.

[0074] Similarly, as the EPI of the block elapses, when the EPI is greater than the second reference time Tref2, a write operation may be performed according to a third operating condition, an increment of a voltage pulse of the ISPP voltage may be reduced compared to the second operating condition, and a level of the verification voltage Vvfy may be increased compared to the second operating condition.

[0075] Fig.11A and Fig. 11B An example of changing the level of the read voltage Vrd as an example of an operation condition is shown. For example, an example in which the first block BLK1 includes a plurality of pages (page 1 to page k) and data is read from the first block BLK1 is shown.

[0076] Reference Fig.11A and Fig. 11B According to some embodiments, the EPI may be determined when a write operation is performed on the first block BLK1, and information about the determined EPI may be stored in a meta region of the memory cell array (or the first block BLK1). In the meta region, the EPI corresponding to a period between an actual erase time and a program time may be stored, or information related to an operating condition of each page may be stored. Fig. 11B An example is shown in which information on the operating conditions OC1 and OC2 is stored in the meta area.

[0077] In a write operation for some pages of the first block BLK1, when EPI is equal to or less than the first reference time Tref1, the first operating condition OC1 may be applied. Fig. 11B In the write operation for other pages of the first block BLK1, when EPI is greater than the first reference time Tref1, the second operating condition OC2 may be applied. Fig. 11B In the embodiment, information related to the second operating condition OC2 may be stored in a meta region related to the (k-2)th page to the kth page (page (k-2) to page k).

[0078] During the process of reading data, the information of the above-mentioned meta area may be read, and the level of the read voltage may be set based on the read information. According to example embodiments, the control of the level of the read voltage may be performed by a memory controller reading the information of the meta area within the memory device and thereby controlling the memory device. Alternatively, when performing a read operation, the memory device may read the information of the meta area and may change the level of the read voltage by itself.

[0079] Reference Fig.11A , the threshold voltage distribution of the memory cell having data written at a relatively short EPI may be relatively located on the right side, while the threshold voltage distribution of the memory cell having data written at a relatively long EPI may be relatively located on the left side. Therefore, the level of the second read voltage Vrd2 set under the second operating condition may be lower than the level of the first read voltage Vrd1 set under the first operating condition.

[0080] although Fig. 11B An example is shown in which the information related to the operating condition is stored in the memory device, but one or more embodiments described herein are not limited thereto, and the information related to the operating condition may be stored in a separate storage circuit within the memory controller.

[0081] An operation of balancing the characteristic degradation caused by EPI by changing the read condition may be selectively performed. For example, when a method of changing the operating condition according to the result of determining EPI during the process of writing data is not used, a balancing operation may be performed by changing the read condition according to some embodiments. Optionally, as a modifiable example, the change of the operating condition during the process of writing data and the change of the operating condition during the process of reading data may be performed together. Optionally, as another modifiable example, EPI may be classified into a plurality of stages according to the degree of passage of time, and in some stages, the change of the operating condition in the write operation may be selectively performed, while in other stages, the change of the operating condition in the write operation and the change of the operating condition in the read operation may be performed together.

[0082] Fig.12 is a flow chart of a read operation according to an example embodiment. Fig.12 An example is shown in which a process of changing an operating condition is selectively performed during a read operation.

[0083] First, the memory system may receive a read request for a first page of a first block (in operation S21), and the memory controller may control the memory device so that data may be read from the first page by using a first read voltage (in operation S22). In addition, an error correction operation may be performed on the read data, and it may be determined whether an uncorrectable error exists (in operation S23). When there is no error or when the error is correctable, the operation of reading the data may be completed (operation S26).

[0084] On the other hand, according to some embodiments, when an error of the read data cannot be corrected, the EPI or information related to the operating condition when writing is performed for the first page may be read from the meta region (in operation S24), and the level of the read voltage may be changed according to the read information related to the operating condition. For example, data may be read from the first page by using a second read voltage having a level different from that of the above-mentioned first read voltage (in operation S25), and when there is no error or when the error can be corrected, the operation of reading the data may be completed by a read operation using the second read voltage (operation S26).

[0085] Fig.13 is a block diagram of an example of writing data according to a modifiable embodiment.

[0086] For example, with respect to the first block BLK1, when data is written to the first block BLK1, the EPI of the first block BLK1 may be determined, and the operating condition of the first block BLK1 may be changed according to the determined EPI. As an example, when the EPI of the first block BLK1 is equal to or less than a reference time, a first operating condition may be selected, and data may be written to some pages (e.g., the first page to the (p-1)th page) of the first block BLK1 based on the first operating condition.

[0087] Thereafter, as time passes, the EPI of the first block BLK1 may increase, and when data is written again to other pages of the first block BLK1, the EPI of the first block BLK1 may be greater than the reference time. In this regard, in an area adjacent to the (p-1)th page having data written according to the first operating condition, the influence of hole diffusion may be significant, and therefore, the distribution characteristics of the pages adjacent to the (p-1)th page may be significantly deteriorated.

[0088] According to an embodiment, when the EPI of the first block BLK1 is greater than the reference time, dummy data unrelated to actual data may be written to at least one page adjacent to the (p-1)th page having data written according to the above-mentioned first operating condition, and data may be written according to the second operating condition starting from the next page. Fig.13An example is shown in which data is written to some pages (e.g., pages (p+2) to (q)) according to the second operating condition after dummy data is written to two pages (e.g., pages p to (p+1)), but one or more embodiments described herein are not limited thereto. For example, after dummy data is written to one or more pages, a write operation according to the second operating condition may be performed.

[0089] Fig.14 and Fig.15 is a flowchart of a method of operating a memory controller according to example embodiments. Fig.14 and Fig.15 An example is shown in which a block is identified based on determining an address received from a host and an operating condition is changed accordingly.

[0090] Reference Fig.14 , the memory controller may control a memory device including a plurality of blocks, for example, the memory controller may receive a write request and a corresponding address from a host (in operation S31). According to some embodiments, the memory controller may convert a logical address received from the host into a physical address by driving the FTL, and may determine a block to which data is to be written by referring to the physical address (in operation S32). In addition, the memory controller may include a plurality of timers for determining the EPI, and when one timer is arranged to correspond to one block, the EPI of the determined block may be determined (or, detected) by referring to the value of the timer corresponding to the determined block (in operation S33).

[0091] According to some embodiments, the determined EPI may be compared with the reference time Tref (in operation S34), and when the determined EPI is equal to or less than the reference time Tref, the memory controller may generate control information indicating a normal write condition and output the control information to the memory device (in operation S35). In some embodiments, the normal write condition may correspond to the first write condition, and therefore, the level increment of the voltage pulse of the ISPP voltage under the normal write condition may be relatively large, and the level of the verification voltage may be relatively low. On the other hand, when the determined EPI is greater than the reference time Tref, the memory controller may generate control information indicating a changed write condition and output the control information to the memory device (in operation S36). The level increment of the voltage pulse of the ISPP voltage under the changed write condition may be relatively small, and the level of the verification voltage may be relatively high.

[0092] Fig.15 An example is shown in which the operating condition is changed by changing the level of the read voltage.

[0093] Reference Fig.15, the memory controller may receive a read request and a corresponding address from the host (in operation S41), and the memory controller may determine a block and a page to which the data read request points based on the received address (in operation S42). The EPI information determined during the process of writing data to the page may be stored in the memory controller or the memory device, and the EPI information corresponding to the page may be identified during the process of reading data (in operation S43).

[0094] Based on the identified EPI information, it may be determined whether the EPI is equal to or less than the reference time Tref during the process of writing data to the page (in operation S44), and when the identified EPI is equal to or less than the reference time Tref, the memory controller may generate control information indicating a normal read condition and output the control information to the memory device (in operation S45). On the other hand, when the identified EPI is greater than the reference time Tref, the memory controller may generate control information indicating a changed read condition and output the control information to the memory device (in operation S46).

[0095] Fig.16A and Fig. 16B is a block diagram of a memory system according to a modifiable embodiment.

[0096] Reference Fig.16A , the memory system 300 may include a memory controller 310 and a memory device 320, and the memory controller 310 may include an EPI detector 311 and a control information generator 312. The memory device 320 may include a memory cell array 321 including a plurality of blocks BLK1 to BLKz and a control logic 322. The memory controller 310 may provide a command CMD / address ADDR to the memory device 320, may send data DATA to the memory device 320 or receive data DATA from the memory device 320, and according to an embodiment, the memory controller 310 may provide control information CTRL_OC for controlling an operating condition to the memory device 320.

[0097] The EPI detector 311 may include a plurality of timers Timer 1 to Timer z, and the number of the timers Timer 1 to Timer z may correspond to the number of the blocks BLK1 to BLKz. The memory controller 310 may determine the location of the block pointed to by the data write request received from the host, and the EPI detector 311 may determine the EPI of the corresponding block by referring to the value of the timer corresponding to the determined block.

[0098] Each of the timers Timer 1 to Timer z may determine the EPI based on determining a time period between an erase time and a write time of a corresponding block. For example, the first timer Timer 1 corresponding to the first block BLK1 may determine the EPI of the first block BLK1 by determining a time elapsed from a most recent erase operation of the first block BLK1. The control information generator 312 may generate control information CTRL_OC indicating an operating condition based on the determined EPI of the first block BLK1, and provide the control information CTRL_OC to the memory device 320.

[0099] Reference Fig. 16B , the memory system 400 may include a memory controller 410 and a memory device 420, and the memory controller 410 may include an EPI detector 411 and a control information generator 412. The memory device 420 may include a memory cell array 421 including a plurality of blocks BLK1 to BLKz and a control logic 422. The EPI detector 411 may include one or more timers, Fig. 16B An example of one timer shared by at least two blocks is shown. According to example embodiments, the memory system 400 may include a storage circuit for storing information related to the EPI of the plurality of blocks BLK1 to BLKz, for example, the memory controller 410 may include an erase time storage circuit 413, or information related to the erase time of the plurality of blocks BLK1 to BLKz may be stored in a partial region of the memory cell array 421 (e.g., a meta region or an erase time storage region).

[0100] An example of the timer in the EPI detector 411 detecting the EPI of the first block BLK1 and the second block BLK2 is as follows. The timer can determine a specific time point based on the time that has passed since the reference point, and thus can determine the time after the erase operation is performed on the first block BLK1 and the time after the erase operation is performed on the second block BLK2. For example, the erase time of the first block BLK1 and the erase time of the second block BLK2 may be different from each other, and the determined erase time may be stored in the erase time storage circuit 413 or the meta region of the memory cell array 421.

[0101] Thereafter, the timer may continue to determine the elapsed time, and when a write request for the first block BLK1 is received, the write time of the first block BLK1 may be determined. The EPI detector 411 may identify information indicating the erase time of the first block BLK1 previously stored, may determine an EPI indicating a time period between the write time and the erase time, and according to some embodiments, the memory device 420 may perform a write operation on the first block BLK1 according to one of a plurality of operating conditions based on the determined EPI. Similarly, the timer may determine the write time of the second block BLK2, and may determine the EPI of the second block BLK2 based on information indicating the erase time of the second block BLK2 previously stored and the write time of the second block BLK2.

[0102] Fig.17 is a block diagram of a memory system 500 according to another modifiable embodiment. Fig.17 An example is shown in which setting information related to various operating conditions is stored in the memory controller.

[0103] Reference Fig.17 , the memory system 500 may include a memory controller 510 and a memory device 520, and the memory controller 510 may include an EPI detector 511, a control information generator 512, and a setting information generator 513. The memory device 520 may include a memory cell array 521 including a plurality of blocks BLK1 to BLKz, a voltage generator 522, and a control logic 523. The memory controller 510 may provide a command CMD / address ADDR to the memory device 520, and may transmit or receive data DATA to or from the memory device 520.

[0104] According to some embodiments, the memory controller 510 may determine the block pointed to by the data write request received from the host, and may determine the EPI of the determined block. The EPI detector 511 may provide the detection result Det obtained by determining the EPI of the block pointed to by the write request to the control information generator 512, and the control information generator 512 may compare the EPI of the block pointed to by the write request with one or more reference times, and based on the comparison result thereof, may provide the control information CTRL_OC to the setting information generator 513.

[0105] The setting information generator 513 may store setting information Info_set for setting the levels of various voltages for memory operations within the memory device 520. According to an embodiment, the memory device 520 may perform a write operation according to one of a plurality of operating conditions based on the detection result of the EPI of the block, and the setting information generator 513 may output setting information Info_set of an operating condition corresponding to the control information CTRL_OC among the setting information of the plurality of operating conditions.

[0106] Fig.18 is a block diagram of a memory system 600 according to another modifiable embodiment. Fig.18 An example of determining the EPI of a block within a memory device is shown.

[0107] Reference Fig.18 , the memory system 600 may include a memory controller 610 and a memory device 620, and the memory device 620 may include a memory cell array 621 including a plurality of blocks BLK1 to BLKz, a voltage generator 622, an EPI detector 623, and a control logic 624. The memory controller 610 may provide a command CMD / address ADDR to the memory device 620, may transmit or receive data DATA to or from the memory device 620, and may provide a control signal CTRL for controlling a memory operation to the memory device 620.

[0108] The memory device 620 may determine a block to which data is to be written based on an address ADDR provided from the memory controller 610 together with a write command. For example, the address ADDR may include a block address indicating one of a plurality of blocks of the memory cell array 621, and the EPI detector 623 may determine the EPI of the block selected based on the block address. As in the previous embodiment, the EPI detector 623 may include one or more timers, for example, the EPI detector 623 may include as many timers as the blocks of the memory cell array 621, or may include less than the number of timers for the blocks.

[0109] For example, regarding the first block, an erase operation may be performed on the first block according to a command received from the memory controller 610, or an erase operation may be performed on the first block by an internal operation (such as a garbage collection operation) within the memory device 620. The EPI detector 623 may determine an erase time of the first block, may determine an EPI of the first block by determining a time that has passed since a most recent erase operation of the first block, and may provide EPI information Info_EPI indicating the determined EPI to the control logic 624.

[0110] The control logic 624 may include an operating condition setter, and the operating condition setter may include setting information related to a plurality of operating conditions. The control logic 624 may set the operating condition of the memory device 620 based on the EPI information Info_EPI about the first block received from the EPI detector 623. For example, the control logic 624 may control the voltage generator 622 according to the setting information corresponding to one operating condition selected from among the plurality of operating conditions, and the voltage generator 622 may output a program voltage, a verification voltage, and a read voltage having changed levels.

[0111] Fig.19 and Fig. 20 is a flowchart of an operating method of a memory system according to a modifiable embodiment.

[0112] Reference Fig.19 According to some embodiments, the memory system may determine the EPI when performing a write operation on a block, and upon receiving a write request for a first block, the EPI of the first block may be determined (or, detected) (in operation S51). The determined EPI of the first block may be compared with a reference time Tref (in operation S52), and when the EPI of the first block is equal to or less than the reference time Tref, data may be written to the first block according to a normal write condition (in operation S53). On the other hand, according to some embodiments, when the EPI of the first block is greater than the reference time Tref, data may be written to the first block by using a changed write condition in which the level of at least one of a program voltage and a verification voltage is changed, for example, data may be written to the first block according to one of a first changed condition to an Nth changed condition as a plurality of changed write conditions (in operation S54). That is, as time passes after erasing the first block, the EPI of the first block may be determined using one of a plurality of stages, and one of a plurality of changed write conditions may be selected according to a result of determining the EPI.

[0113] During the operation of the memory system, a sudden power outage (SPO) may occur. Due to the occurrence of SPO, a timer for determining the EPI of a block may be reset, or information indicating the erase time of the block may be erased, and therefore, the accuracy of the EPI detection result may be reduced. According to an embodiment, the memory system may detect SPO (in operation S55), and may receive a data write request for the first block after determining SPO (in operation S56). In this regard, when a write request is received after the occurrence of SPO, it may be assumed that a long time has passed after the erase operation is performed on the actual first block, and data may be written to the first block according to one of the first changed conditions to the Nth changed conditions of the first block (in operation S54). In the case of defining multiple changed write conditions, when SPO does not occur, a changed write condition may be selected according to the EPI determined for the block requested to be written, and after the occurrence of SPO, one of the multiple changed write conditions may be selected for the block requested to be written, or a specific changed write condition may be selected.

[0114] Fig. 20 An example of a memory operation to which an operating condition is applied according to example embodiments is illustrated.

[0115] Reference Fig. 20 The memory system may perform various memory operations through requests received from the host and internal operations, and may determine the type of memory operation performed (in operation S61). The memory operation may be performed on one block, or may be performed on a plurality of blocks simultaneously or sequentially.

[0116] According to an embodiment, it may be determined whether the memory operation corresponds to writing user data, writing metadata, or garbage collection (in operation S62). For example, when the memory operation does not correspond to the above operation, the corresponding memory operation may be performed without separately performing EPI detection and setting of operating conditions (in operation S63). On the other hand, according to some embodiments, when the memory operation corresponds to a write operation of user data or metadata, a block to which the user data or metadata will be written may be determined, the EPI of the determined block may be determined (in operation S64), and it may be determined whether the determined EPI is equal to or less than the reference time Tref (in operation S65). When the determined EPI is equal to or less than the reference time Tref, the memory operation may be performed on the block using normal operating conditions (in operation S66). On the other hand, when the determined EPI is greater than the reference time Tref, the memory operation may be performed on the block using changed operating conditions (in operation S67).

[0117] When the memory operation corresponds to a garbage collection operation, valid data stored in one or more blocks may be moved to another block, and a free block may be generated by erasing one or more blocks after moving the valid data. For example, when a garbage collection operation is performed on a first block, valid data in the first block may be moved to a second block, and in this regard, an EPI of the second block may be determined. That is, based on a result of comparing the EPI determined for the second block with a reference time Tref, valid data may be written to the second block by using a normal operating condition, or valid data may be written to the second block by using a changed operating condition.

[0118] Fig.21 is a block diagram of an example of a memory device in an SSD system according to an embodiment.

[0119] Reference Fig.21 , the SSD system 700 may include a host 710 and an SSD 720. The SSD 720 may exchange signals with the host 710 via a signal connector SGL, and may receive power via a power connector PWR. The SSD 720 may include an SSD controller 721, an auxiliary power supply 722, and memory devices 723_1 to 723_n. In some example embodiments, the SSD controller 721 may exchange data with the memory devices 723_1 to 723_n via channels Ch1, Ch2, ... Chn (here, n is an integer equal to or greater than 3). In this regard, the SSD 720 may use the above reference Figures 1 to 20 According to an embodiment, the SSD controller 721 may include an operation condition controller 721_1, and each of the memory devices 723_1 to 723_n may include a plurality of blocks.

[0120] The embodiments described herein may be Fig.21 The SSD system 700 shown in FIG. 7 is implemented that during a write operation and / or a read operation of memory devices 723_1 to 723_n, the SSD controller 721 may determine the EPI of each block, and based on the detection result, the operating conditions of the memory devices 723_1 to 723_n may be controlled. The operating condition controller 721_1 may include an element for determining the EPI and an element for generating control information for indicating the operating condition. In addition, each of the memory devices 723_1 to 723_n may store setting information for performing a memory operation according to an operating condition based on the control information. According to some embodiments, when data is programmed after a long EPI state, the threshold voltage distribution may be reduced after the programming operation, and the degradation of the threshold voltage distribution characteristics may be balanced by changing at least one of the programming voltage, the verification voltage, and the read voltage.

[0121] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made in the embodiments without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a memory system, the memory system comprising a memory device including a plurality of blocks, the method comprising: When a first write request for first data of a first block is received, determining a first erase programming interval representing a time period that elapses after erasing the first block; In response to the first write request and in response to determining that the first erase programming interval is less than a reference time, programming first data to one or more first pages of the first block based on a first operating condition selected from among a plurality of operating conditions; receiving a second write request for second data of the first block after programming the first data to the one or more first pages of the first block; when a second write request is received, determining a second erase programming interval representing a second period of time that has elapsed after erasing the first block; as well as In response to the second erase programming interval being greater than a reference time, programming second data to one or more second pages of the first block based on a second operating condition selected from among the plurality of operating conditions, Wherein a level of at least one of a program voltage and a verification voltage under the first operating condition is different from a corresponding level under the second operating condition.

2. The operating method according to claim 1, in, The programming voltage includes an incremental step pulse programming voltage including a plurality of voltage pulses, and The voltage increment of the voltage pulse under the second operating condition is smaller than the voltage increment of the corresponding voltage pulse under the first operating condition.

3. The operating method according to claim 2, wherein: The maximum number of voltage pulses under the second operating condition is greater than the maximum number of voltage pulses under the first operating condition.

4. The operating method according to claim 1, wherein: A level of the verification voltage under the second operating condition is higher than a level of the corresponding verification voltage under the first operating condition.

5. The operating method according to claim 1, in, The operation method further includes: storing information related to a determined first erase programming interval for a first page in a memory device when a first write request is received; When a read request for first data of the one or more first pages of the first block is received, reading the stored information related to the determined first erase programming interval of the one or more first pages; and selecting a level of a read voltage according to information related to a first erase programming interval, In response to the information related to the first erase programming interval indicating that the first erase programming interval is less than a reference time, the first data of the one or more first pages are read using a first read voltage.

6. The operating method according to claim 1, in, The memory system further includes a memory controller configured to communicate with the host, The operation method further includes: determining, via the memory controller, a first block to which first data is to be written based on an address received from a host; and Control information is output to the memory device via the memory controller, wherein the control information indicates an operation condition selected according to the determined first erase program interval.

7. The operating method according to claim 6, in, The memory device stores first setting information and second setting information, The memory device selects one of the first setting information and the second setting information in response to control information received from the memory controller, and The selected one of the first setting information and the second setting information is used to set a level of at least one of a program voltage and a verification voltage for a write operation on a first block of the memory device.

8. The operating method according to claim 1, further comprising: detecting a sudden power failure of the memory system; After a sudden power failure occurs, receiving a third write request for third data of the first block; as well as In response to the third write request, third data is written to the first block based on the second operation condition regardless of the first erase program interval of the first block.

9. A memory controller, the memory controller being configured to control a memory device including a plurality of blocks, the memory controller comprising: A host interface configured to communicate with a host and receive a first data write request and an address from the host; an erase programming interval detector configured to determine a first erase programming interval representing a period of time that elapses after erasing a first block of the plurality of blocks of the memory device to which a first data write request is directed; as well as a control information generator configured to output control information indicating a first operating condition selected from among a plurality of operating conditions based on the first erase programming interval being less than a reference time, so that the first data will be written to one or more first pages of the first block according to the first operating condition, The host interface is configured to sequentially receive a first data write request and a second data write request from the host, wherein the erase programming interval detector is configured to determine, upon receiving the second data write request, a second erase programming interval representing a time period that has elapsed after erasing the first block to which the second data write request refers, wherein the control information generator is configured to output control information indicating a second operating condition selected from among the plurality of operating conditions based on the determination that the second erase programming interval is greater than the reference time, so that the second data will be written into the first block according to the second operating condition, The control information includes information for changing a level of at least one of a program voltage and a verification voltage for a write operation of the memory device.

10. The memory controller according to claim 9, in, The programming voltage includes an incremental step pulse programming voltage including a plurality of voltage pulses, and The control information further includes the following information: setting a voltage increment of a voltage pulse for a write operation of the memory device under the second operating condition to be smaller than a voltage increment of a corresponding voltage pulse under the first operating condition.

11. The memory controller according to claim 9, wherein: The control information also includes information for setting a level of a verification voltage under the second operating condition to be higher than a level of a corresponding verification voltage under the first operating condition.

12. A memory system comprising a memory device including a plurality of blocks, wherein: The memory device comprises: a voltage generator configured to generate a program voltage and a verification voltage for a write operation with respect to the plurality of blocks; and The control logic is configured to: when a first write request for first data of one or more first pages of a first block is received, in response to a first erase programming interval representing a time period elapsed after erasing the first block when the first write request is received being less than a reference time, set a first level of at least one of a programming voltage and a verification voltage; and is configured to: when a second write request for second data of one or more second pages of the first block is received, in response to a second erase programming interval representing a time period elapsed after erasing the first block when the second write request is received being greater than a reference time, set a second level of at least one of a programming voltage and a verification voltage.

13. The memory system according to claim 12, in, The programming voltage includes an incremental step pulse programming voltage including a plurality of voltage pulses, and In response to the first erase programming interval being shorter than the reference time, the voltage increment of the voltage pulse is set to be relatively large; and in response to the second erase programming interval being longer than the reference time, the voltage increment of the voltage pulse is set to be relatively small.

14. The memory system according to claim 12, wherein: In response to the first erase programming interval being less than a reference time, the level of the verification voltage is set to be relatively low; And in response to the second erase program interval being greater than the reference time, the level of the verification voltage is set to be relatively high.

15. The memory system of claim 12, further comprising: a memory controller including an operation condition controller configured to determine a first erase program interval of a first block and output control information indicating one operation condition among a plurality of operation conditions based on the first erase program interval, The control logic is further configured to set a level of at least one of a program voltage and a verification voltage in response to the control information.

16. The memory system according to claim 15, in, The control logic includes an operation condition setter configured to store first setting information corresponding to the first operation condition and store second setting information corresponding to the second operation condition, and The control logic is further configured to set a level of at least one of a program voltage and a verification voltage according to one of the first setting information and the second setting information selected in response to the control information.

17. The memory system according to claim 15, in, The width of the threshold voltage distribution of the one or more second pages is relatively narrow compared to the width of the threshold voltage distribution of the one or more first pages, and / or The threshold voltage distributions of the one or more second pages are shifted to the right or in a direction of increasing a threshold voltage level compared to the threshold voltage distributions of the one or more first pages.

18. The memory system according to claim 12, in, The memory device is configured to perform a garbage collection operation to move valid data of the first block to the second block, and Wherein, during the garbage collection operation, a level of at least one of a program voltage and a verification voltage for writing valid data to the second block is set based on an erase program interval of the second block.

Images