Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. A semiconductor device and a method of manufacturing a semiconductor device are provided. In an embodiment, a passivation process is used to reduce dangling bonds and defects in a work function layer within a gate stack. The passivation process introduces a passivation element that will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments, the passivation element will trap other elements and reduce or prevent their diffusion into other parts of the structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing methods. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing layers of insulating or dielectric material, conductive material, and semiconductor material over a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method comprising: depositing a gate dielectric over a semiconductor fin; depositing a first p-metal work function layer over the gate dielectric; depositing a first n-metal work function layer over the first p-metal work function layer; and exposing the first n-metal work function layer to a fluorine-containing gas.

[0005] According to another embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method comprising: depositing a first n-metal work function layer over and in physical contact with a first p-metal work function layer and a gate dielectric located over a semiconductor fin; and capturing a first element within the first n-metal work function layer, the capturing being performed at least in part by exposing the first n-metal work function layer to a passivation precursor.

[0006] According to yet another embodiment of the present disclosure, there is provided a semiconductor device comprising: a semiconductor fin; a gate dielectric located over the semiconductor fin; a first p-metal work function layer located over the gate dielectric; a first n-metal work function layer located over the first p-metal work function layer and in physical contact with the first p-metal work function layer, the first n-metal work function layer comprising a region having a non-zero tungsten concentration; and aluminum located within both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer and the first p-metal work function layer but ends before extending to the gate dielectric. Brief Description of the Drawings

[0007] As will be best understood from the following detailed description, when read in conjunction with the accompanying drawings, it should be noted that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view showing the formation of a semiconductor fin according to some embodiments is presented.

[0009] Figure 2 The formation of source / drain regions according to some embodiments is shown.

[0010] Figure 3 The formation of materials for a gate stack according to some embodiments is shown.

[0011] Figure 4 A passivation process according to some embodiments is shown.

[0012] Figure 5 The deposition of a fill material according to some embodiments is shown.

[0013] Figure 6 The formation of a cap according to some embodiments is shown. Detailed Description

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and not restrictive. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, spatial relative terms (e.g., "below", "beneath", "under", "above", "over", etc.) may be used herein for ease of description to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] Embodiments will now be described with respect to a specific example including a finFET device having multiple threshold voltages for a 5 nm or 3 nm technology node. However, the embodiments are not limited to the examples provided herein, and these ideas may be implemented in a variety of embodiments.

[0017] Now referring to Figure 1 , a perspective view of a semiconductor device 100 such as a finFET device is shown. In an embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 may be a silicon substrate, but other substrates such as semiconductor-on-insulator (SOI), strained SOI, and silicon germanium on insulator may also be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, it may be an n-type semiconductor.

[0018] In other embodiments, the substrate 101 may be selected as a material that will particularly enhance the performance of the devices formed from the substrate 101 (e.g., enhance carrier mobility). For example, in some embodiments, the material of the substrate 101 may be selected as an epitaxially grown semiconductor material layer, e.g., epitaxially grown silicon germanium, which helps to enhance some performance measurements of the devices formed from the epitaxially grown silicon germanium. However, while using these materials may be able to enhance some performance characteristics of the devices, using these same materials may affect other performance characteristics of the devices. For example, using epitaxially grown silicon germanium may deteriorate (relative to silicon) the interface and charge defects (D it ). The embodiments described herein may help to improve the deterioration of the interface and charge defects (D it ).

[0019] The first trench 103 may be formed as an initial step in ultimately forming the first isolation region 105. The first trench 103 may be formed using a mask layer ( Figure 1 not shown separately) and a suitable etching process. For example, the mask layer may be a hard mask including silicon nitride formed by a process such as chemical vapor deposition (CVD), but other materials (e.g., oxides, oxynitrides, silicon carbide, combinations thereof, etc.) and other processes (e.g., plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even nitridation after oxide formation) may also be used. Once formed, the mask layer may be patterned by a suitable lithography process to expose those portions of the substrate 101 that are to be removed to form the first trench 103.

[0020] However, as those skilled in the art will recognize, the above processes and materials for forming the mask layer are not the only methods available for exposing other portions of the substrate 101 while protecting a portion of the substrate 101 to form the first trench 103. Any suitable process (e.g., patterning and developing a photoresist) can be used to expose the portion of the substrate 101 that is to be removed to form the first trench 103. All such methods are fully intended to be included within the scope of this embodiment.

[0021] Once the mask layer has been formed and patterned, the first trench 103 is formed in the substrate 101. The exposed substrate 101 can be removed by a suitable process such as reactive ion etching (RIE) to form the first trench 103 in the substrate 101, but any suitable process can also be used. In an embodiment, the first trench 103 can be formed to have a first depth that is less than about from the surface of the substrate 101, e.g., about

[0022] However, as those of ordinary skill in the art will recognize, the above process for forming the first trench 103 is only one possible process and is not meant to be the only embodiment. Instead, any suitable process by which the first trench 103 can be formed can be used, and any suitable process that includes any number of masking and removal steps can be used.

[0023] In addition to forming the first trench 103, the masking and etching processes additionally form fins 107 from those portions of the substrate 101 that remain unremoved. For convenience, the fins 107 have been shown in the figures as separated from the substrate 101 by dashed lines, but a physical indication of separation may or may not be present. As discussed below, these fins 107 can be used to form the channel regions of multi-gate FinFET transistors. While Figure 1 only three fins 107 formed from the substrate 101 are shown, any number of fins 107 can be used.

[0024] The fins 107 can be formed such that they have a width between about 5 nm and about 80 nm at the surface of the substrate 101, e.g., about 30 nm. Additionally, the fins 107 can be spaced apart from each other by a distance between about 10 nm and about 100 nm, e.g., about 50 nm. By spacing the fins 107 in this manner, the fins 107 can each form separate channel regions while still being close enough to share a common gate (discussed further below).

[0025] In addition, the fin 107 can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fin 107, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, which allow patterns to be created that have, for example, smaller pitch than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 107.

[0026] Once the first trench 103 and the fin 107 are formed, the first trench 103 can be filled with a dielectric material, and the dielectric material can be recessed within the first trench 103 to form the first isolation region 105. The dielectric material can be an oxide material, a high density plasma (HDP) oxide, etc. The dielectric material can be formed using a chemical vapor deposition (CVD) method (e.g., HARP process), a high density plasma CVD method, or other suitable formation methods known in the art, after an optional cleaning and liner formation for the first trench 103.

[0027] The first trench 103 can be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material, and then removing the excess material outside the first trench 103 and the fin 107 by a suitable process (e.g., chemical mechanical polishing (CMP), etching, a combination of these, etc.). In an embodiment, the removal process also removes any dielectric material located above the fin 107, such that the removal of the dielectric material will expose the surface of the fin 107 to further process steps.

[0028] Once the first trench 103 has been filled with a dielectric material, the dielectric material can then be recessed away from the surface of the fin 107. The recessing can be performed to expose at least a portion of the sidewall of the fin 107 adjacent to the top surface of the fin 107. The dielectric material can be recessed using wet etching by immersing the top surface of the fin 107 in an etchant such as HF, but other etchants (e.g., H2) and other methods (e.g., reactive ion etching, dry etching using an etchant such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning) can also be used. The dielectric material can be recessed to a distance between about and about For example, about In addition, the recessing can also remove any remaining dielectric material located above the fin 107 to ensure that the fin 107 is exposed for further processing.

[0029] However, as those of ordinary skill in the art will recognize, the above steps may only be a part of the entire process flow for filling and recessing the dielectric material. For example, a liner formation step, a cleaning step, an annealing step, a gap filling step, combinations thereof, etc. may also be used to form and fill the first trench 103 with the dielectric material. All possible process steps are fully intended to be included within the scope of this embodiment.

[0030] After the first isolation region 105 is formed, a dummy gate dielectric 109, a dummy gate electrode 111 above the dummy gate dielectric 109, and a first spacer 113 may be formed above each fin 107. In an embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and used for forming a gate dielectric. Depending on the gate dielectric formation technique, the thickness of the dummy gate dielectric 109 on top of the fin 107 may be different from the thickness of the gate dielectric on the sidewalls of the fin 107.

[0031] The dummy gate dielectric 109 may include a material such as silicon dioxide or silicon oxynitride, which has a thickness ranging from about 3 angstroms to about 100 angstroms, for example, about 10 angstroms. The dummy gate dielectric 109 may be formed of a high dielectric constant (high-k) material (e.g., relative dielectric constant greater than about 5) (e.g., lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or a combination thereof), which has an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, for example, about 10 angstroms or less. Additionally, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0032] The dummy gate electrode 111 may include a conductive or non-conductive material and may be selected from the group consisting of: polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputter deposition, or other techniques known in the art and used for depositing conductive materials. The thickness of the dummy gate electrode 111 may be in the range of about to about . The top surface of the dummy gate electrode 111 may have a non-planar top surface and may be planarized before patterning or gate etching of the dummy gate electrode 111. Ions may or may not be introduced into the dummy gate electrode 111 at this time. For example, ions may be introduced by ion implantation techniques.

[0033] Once formed, the dummy gate dielectric 109 and the dummy gate electrode 111 can be patterned to form a series of stacks 115 over the fin 107. The stacks 115 define a plurality of channel regions on each side of the fin 107 that are located beneath the dummy gate dielectric 109. The stacks 115 can be formed by depositing and patterning a gate mask ( Figure 1 not shown separately in ) on the dummy gate electrode 111 using, for example, deposition and lithography techniques known in the art. The gate mask can comprise conventional mask and sacrificial materials such as, but not limited to, silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and can be deposited to a thickness between about and about

[0034] . A dry etching process can be used to etch the dummy gate electrode 111 and the dummy gate dielectric 109 to form the patterned stacks 115. Figure 1 not shown separately in

[0035] Once the stacks 115 have been patterned, a first spacer 113 can be formed. The first spacer 113 can be formed on opposite sides of the stacks 115. The first spacer 113 is typically formed by blanket depositing a spacer layer ( not shown separately in ) on the previously formed structure. The spacer layer can include SiN, nitrogen oxides, SiC, SiON, SiOCN, SiOC, oxides, etc., and can be formed by methods used to form such layers, e.g., chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, and other methods known in the art. The spacer layer can include different materials having different etch characteristics or the same material as the dielectric material within the first isolation region 105. The first spacer 113 can then be patterned, e.g., by one or more etches to remove the spacer layer from the horizontal surfaces of the structure to form the first spacer 113.

[0036] Figure 2Illustrated is the regrowth of removing fin 107 and source / drain regions 201 from those regions not protected by stack 115 and first spacer 113. Removing fin 107 from those regions not protected by stack 115 and first spacer 113 can be performed by: reactive ion etching (RIE) using stack 115 and first spacer 113 as a hard mask, or any other suitable removal process. The removal can continue until fin 107 is coplanar with the surface of the first isolation region 105 (as shown) or below the surface of the first isolation region 105.

[0037] Once these portions of fin 107 have been removed, a hard mask (not shown separately) is placed and patterned to cover dummy gate electrode 111 to prevent growth, and source / drain regions 201 can be regrown in contact with each fin 107. In an embodiment, source / drain regions 201 can be regrown, and in some embodiments, source / drain regions 201 can be regrown to form a stressor that will apply stress to the channel region of fin 107 located beneath stack 115. In an embodiment where fin 107 comprises silicon and the FinFET is a p-type device, source / drain regions 201 can be regrown by a selective epitaxial process that uses a material such as silicon or a material such as silicon germanium having a lattice constant different from that of the channel region. The epitaxial growth process can use precursors such as silane, dichlorosilane, germane, etc., and can last for a time between about 5 minutes and about 120 minutes, e.g., about 30 minutes.

[0038] In an embodiment, source / drain regions 201 can be formed to have a thickness between about and about and a height above the first isolation region 105 between about and about e.g., about In this embodiment, source / drain regions 201 can be formed to have a height between about 5 nm and about 250 nm above the upper surface of the first isolation region 105, e.g., about 100 nm. However, any suitable height can be used.

[0039] Once the source / drain regions 201 are formed, dopants can be implanted into the source / drain regions 201 by implanting appropriate dopants to supplement the dopants in the fin 107. For example, p-type dopants such as boron, gallium, indium, etc. can be implanted to form PMOS devices. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, etc. can be implanted to form NMOS devices. These dopants can be implanted by using the stack 115 and the first spacer 113 as masks. It should be noted that those of ordinary skill in the art will recognize that many other processes, steps, etc. can be used to implant dopants. For example, those of ordinary skill in the art will recognize that various combinations of spacers and liners can be used to perform multiple implantations to form source / drain regions having specific shapes or characteristics suitable for specific purposes. Any of these processes can be used to implant dopants, and the above description is not meant to limit the present embodiment to the above steps.

[0040] In addition, at this time, the hard mask covering the dummy gate electrode 111 during the formation of the source / drain regions 201 is removed. In an embodiment, a wet or dry etching process selective to the material of the hard mask can be used to remove the hard mask, for example. However, any suitable removal process can be used.

[0041] Figure 2 Also shown is the formation of an interlayer dielectric (ILD) layer 203 (shown in dashed lines in Figure 2 for a clearer view of the underlying structure) over the stack 115 and the source / drain regions 201. The ILD layer 203 can include a material such as borophosphosilicate glass (BPSG), but any suitable dielectric can also be used. A process such as PECVD can be used to form the ILD layer 203, but other processes such as LPCVD can be used alternatively. The ILD layer 203 can be formed to a thickness between about and about . Once formed, the ILD layer 203 can be planarized with the first spacer 113 using, for example, a planarization process (e.g., chemical mechanical polishing process), but any suitable process can also be used.

[0042] Figure 3 Shown is Figure 2 a cross-sectional view along line 3-3' to better show the removal and replacement of the materials of the dummy gate electrode 111 and the dummy gate dielectric 109. In an embodiment, the dummy gate electrode 111 and the dummy gate dielectric 109 can be removed using, for example, one or more wet or dry etching processes that utilize an etchant selective to the materials of the dummy gate electrode 111 and the dummy gate dielectric 109. However, any suitable (one or more) removal process can be used.

[0043] Once the dummy gate electrode 111 and the dummy gate dielectric 109 have been removed, the process for forming the first gate stack 603 can be initiated by depositing a series of layers. In an embodiment, the series of layers can include an interface layer 301, a first dielectric material 303, a first metal material 305, and a first p-metal work function layer 307.

[0044] Optionally, the interface layer 301 can be formed before the first dielectric material 303. In an embodiment, the interface layer 301 can be a material such as silicon dioxide, which is formed by a process such as in situ steam generation (ISSG) or a deposition process (e.g., chemical vapor deposition or atomic layer deposition). In another embodiment, the interface layer 301 can be a high-k material (e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc.), which has a first thickness between about and about For example, about In embodiments utilizing a deposition process, the interface layer 301 can be formed uniformly as shown, while in embodiments utilizing ISSG, the interface layer 301 can be formed along the bottom of the opening and not extend along the sidewalls of the first spacer 113.

[0045] Once the interface layer 301 is formed, the first dielectric material 303 can be formed as a capping layer over the interface layer 301. In an embodiment, the first dielectric material 303 is a high-k material deposited by a process such as atomic layer deposition, chemical vapor deposition, etc., e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc. The first dielectric material 303 can be deposited to a second thickness between about and about However, any suitable material and thickness can also be used.

[0046] Optionally, the first metal material 305 or the metal gate capping layer may be formed adjacent to the first dielectric material 303 as a barrier layer, and may be formed of a metal material such as the following: TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. The first metal material 305 may be deposited to a third thickness between about and about using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc., but any suitable deposition process or thickness may also be used.

[0047] The first p-metal work function layer 307 may be formed adjacent to the first metal material 305 and, in certain embodiments, may be similar to the first metal material 305. For example, the first p-metal work function layer 307 may be formed of a metal material such as the following: TiN, Ti, TiAlN, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, Al, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. Additionally, the first p-metal work function layer 307 may be deposited to a fourth thickness between about and about using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc., but any suitable deposition process or thickness may also be used.

[0048] Figure 3 The deposition of the first n-metal work function layer 309 is also shown. In an embodiment, the first n-metal work function layer 309 may be a material such as the following: TiAlC, TiAlN, Ti, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-metal work function layer 309 may be deposited to a sixth thickness between about and about such as about However, any suitable materials and processes may be used to form the first n-metal work function layer 309.

[0049] However, after depositing the first n-metal work function layer 309, the material of the first n-metal work function layer 309 (e.g., TiAlC) does not have the desired high quality. Specifically, the first n-metal work function layer 309 will have a large number of dangling bonds and defects. If left alone when depositing the first n-metal work function layer 309, the dangling bonds and defects will cause the undesired diffusion of some elements (e.g., aluminum) away from the first n-metal work function layer 309, which may lead to interface defects (D it ) in the device between the interface layer 301 and the underlying channel within the fin 107. Such deterioration may lead to a reduction in the overall performance of the device.

[0050] Figure 4 Illustrated is a passivation process (represented by the arrow labeled 401 in Figure 4 ) or a treatment process, which is performed to help passivate the existing dangling bonds without increasing the total thickness of the structure, and also helps to capture elements that might otherwise diffuse. In an embodiment, the passivation process 401 can be performed in-situ using a deposition process and employing one or more suitable passivation elements (e.g., fluorine, etc.).

[0051] In a specific embodiment using fluorine, fluorine can be introduced into the first n-metal work function layer 309 using a gaseous precursor containing fluorine atoms. For example, in some embodiments, fluorine can be introduced into the first n-metal work function layer 309 by introducing a passivation precursor such as a fluorine-containing precursor (e.g., tungsten fluoride (WF x ), nitrogen fluoride (NF x ), titanium fluoride (TiF x ), tantalum fluoride (TaF x ), hafnium fluoride (HfF x ), a combination of these, etc., where x can be between 1 and 6). However, any suitable passivation precursor based on the desired passivation element can be used.

[0052] In an embodiment, the passivation process 401 can be initiated by introducing the passivation precursor into the first n-metal work function layer 309 in a passivation chamber. This introduction can be performed by using a carrier gas such as argon to bring the passivation precursor into the passivation chamber. The combined passivation precursor and carrier gas can be introduced into the passivation chamber at a flow rate between about 100 sccm and about 6,000 sccm.

[0053] In the passivation chamber, the passivation precursor can contact the first n-metal work function layer 309 to initiate a chemical reaction within the first n-metal work function layer 309. In some embodiments, the chemical reaction can be carried out in the passivation chamber at a temperature between about 25 °C and about 500 °C (e.g., about 300 °C) and at a pressure between about 0.5 Torr and about 50 Torr. However, any suitable parameters can be used.

[0054] In embodiments where a fluorine precursor is used as a passivation precursor, by utilizing passivation process 401, the fluorine present in the fluorine precursor (e.g., WF6) will react with the aluminum in the first n-metal work function layer 309. This reaction will produce fluorine by-products such as aluminum fluoride.

[0055] In some embodiments, passivation process 401 can be performed to incorporate fluorine into the first n-metal work function layer 309. Thus, passivation process 401 can be performed for a time between about 1 second and about 1 hour, e.g., between about 30 seconds and about 60 seconds. For these time periods, passivation process 401 can result in the first n-metal work function layer 309 having a fluorine concentration between about 1 atomic % and about 30 atomic %. However, any suitable concentration of fluorine and any suitable time period can be used.

[0056] Additionally, in some embodiments, other elements present in the fluorine precursor can be at least partially incorporated within the top surface of the first n-metal work function layer 309. For example, in embodiments where tungsten hexafluoride (WF6) is used as the fluorine precursor, at least a portion of the tungsten in the tungsten hexafluoride will be incorporated into the top surface of the first n-metal work function layer 309 (after the fluorine reacts with the aluminum). In some embodiments, the tungsten can have a concentration of less than 10 wt% along the top surface of the first n-metal work function layer 309, e.g., between about 2 wt% and about 3 wt%. However, any suitable concentration can be used.

[0057] By utilizing passivation process 401, the passivation element (e.g., fluorine) present in the passivation precursor will diffuse into the structure and react. Thus, a concentration gradient will exist within each of the first p-metal work function layer 307, the first metal material 305, the first dielectric material 303, and the interface layer 301, thereby improving D it .

[0058] By introducing a passivation element (e.g., fluorine) into the structure, the dangling bonds and defects that would otherwise be present will be reduced by the introduction of the passivation element (e.g., fluorine). Additionally, this reduction can be achieved without causing an increase in the thickness of the first n-metal work function layer 309. Specifically, the passivation element will react with the dangling bonds, thereby passivating the dangling bonds and repairing the defects. Thus, the number of dangling bonds and the number of defects will be reduced by passivation process 401 while the first n-metal work function layer 309 remains at the sixth thickness.

[0059] Additionally, in embodiments where the first n-metal work function layer 309 includes a material that may have one or more elements that can undesirably diffuse (e.g., aluminum in the material TiAlC), the passivation process 401 has an additional benefit in that it helps reduce or eliminate the diffusion of the elements. For example, a passivating element (e.g., fluorine) will react with at least some of the aluminum present in the first n-metal work function layer 309. By bonding fluorine to the aluminum present in the first n-metal work function layer 309 to form aluminum fluoride, the aluminum is at least partially trapped and cannot diffuse as much into other regions of the structure. Thus, although there may still be a concentration gradient in each of the underlying layers, the concentration gradient can be reduced, or in some embodiments, eliminated.

[0060] In a specific embodiment, by trapping aluminum with fluorine, the aluminum bonded to the passivating element cannot diffuse into the underlying structures, such as the first p-metal work function layer 307, the first metal material 305, the first dielectric material 303, and the interface layer 301. By reducing the amount of aluminum that can diffuse, the total amount of aluminum that will diffuse into these underlying layers can also be reduced. In some embodiments, aluminum diffusion into the first dielectric material 303 and the interface layer 301 can be completely prevented.

[0061] Figure 5 The deposition of the glue layer 501 and the filler material 503 is shown. Once the first n-metal work function layer 309 has been formed, the glue layer 501 can be formed to help adhere the overlying filler material 503 to the underlying first n-metal work function layer 309 and to provide a nucleation layer for forming the filler material 503. In an embodiment, the glue layer 501 can be a material such as titanium nitride, or can be a material similar to the first n-metal work function layer 309, and can be formed using a similar process (e.g., ALD) to a seventh thickness between about and about For example, about However, any suitable materials and processes can be used.

[0062] Once the glue layer 501 has been formed, the filler material 503 is deposited to fill the remaining portion of the opening using the glue layer 501. In an embodiment, the filler material 503 can be a material such as: tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc., and can be formed using deposition processes such as: electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, etc. Additionally, the filler material 503 can be deposited to a thickness between about to about For example, about However, any suitable material can be used.

[0063] Figure 6 It is shown that after the fill material 503 has been deposited to fill and overfill the opening, the material can be planarized to form the first gate stack 603. In an embodiment, a chemical mechanical polishing process, for example, can be used to planarize the material with respect to the first spacer 113, but any suitable process, such as grinding or etching, can also be used.

[0064] After the material of the first gate stack 603 has been formed and planarized, the material of the first gate stack 603 can be recessed and capped with a capping layer 601. In an embodiment, the material of the first gate stack 603 can be recessed using, for example, a wet or dry etching process that uses an etchant selective to the material of the first gate stack 603. In an embodiment, the material of the first gate stack 603 can be recessed a distance between about 5 nm and about 150 nm, for example, about 120 nm. However, any suitable process and distance can be used.

[0065] Once the material of the first gate stack 603 has been recessed, the capping layer 601 can be deposited and planarized with respect to the first spacer 113. In an embodiment, the capping layer 601 is a material such as SiN, SiON, SiCON, SiC, SiOC, combinations thereof, etc., deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. The capping layer 601 can be deposited to a thickness between about and about and then planarized using a planarization process such as chemical mechanical polishing such that the capping layer 601 is coplanar with the first spacer 113.

[0066] By utilizing the embodiments described herein, the diffusion of aluminum from the first n-metal work function layer 309 can be reduced or eliminated. Thus, less aluminum diffuses into the various layers, and specifically, the amount of aluminum diffusing into the first dielectric material 303 and the interface layer 301 and negatively affecting the interface and charge defects (D it ) of the first dielectric material 303 and the interface layer 301 can be minimized. In addition to the usual benefits, this reduction in charge defects becomes particularly useful when materials such as silicon germanium, which may be more preferred but have higher interface and charge defects, are used as the material for the channel within the fin 107.

[0067] Additionally, the benefits of reducing the impact of diffusion can be reduced without reducing the subsequent process window. Specifically, by utilizing the passivation process 401 as described herein, no additional layer is required before or after depositing the first n-metal work function layer 309, and the passivation process 401 will not add additional thickness to the first n-metal. Thus, the gap fill window for subsequent processing (e.g., deposition of the fill material 503) can remain wide while still obtaining the desired benefits.

[0068] In an embodiment, a method of manufacturing a semiconductor device includes: depositing a gate dielectric over a semiconductor fin; depositing a first p-metal work function layer over the gate dielectric; depositing a first n-metal work function layer over the first p-metal work function layer; and exposing the first n-metal work function layer to a fluorine-containing gas. In an embodiment, the fluorine-containing gas is tungsten fluoride. In an embodiment, depositing the first n-metal work function layer deposits titanium aluminum carbide. In an embodiment, the tungsten fluoride reacts with aluminum in the titanium aluminum carbide. In an embodiment, the exposure increases the tungsten concentration in the top surface of the first n-metal work function layer. In an embodiment, the method further includes: depositing a glue layer over the first n-metal work function layer after exposing the first n-metal work function layer. In an embodiment, the first n-metal work function layer has a first thickness before exposing the first n-metal work function layer and also has the first thickness after exposing the first n-metal work function layer.

[0069] In another embodiment, a method of manufacturing a semiconductor device includes: depositing a first n-metal work function layer over a first p-metal work function layer and a gate dielectric located over a semiconductor fin and in physical contact with the first p-metal work function layer; and capturing a first element within the first n-metal work function layer, the capturing being performed at least in part by exposing the first n-metal work function layer to a passivation precursor. In an embodiment, the passivation precursor is a fluorine-containing gas. In an embodiment, the fluorine-containing gas is tungsten fluoride. In an embodiment, the fluorine-containing gas is nitrogen fluoride. In an embodiment, the fluorine-containing gas is hafnium tungsten fluoride. In an embodiment, the fluorine-containing gas is tantalum fluoride. In an embodiment, exposing the first n-metal work function layer is performed at a temperature between 25 °C and 500 °C and for a time between 30 seconds and 60 seconds.

[0070] In yet another embodiment, a semiconductor device includes: a semiconductor fin; a gate dielectric located above the semiconductor fin; a first p-metal work function layer located above the gate dielectric; a first n-metal work function layer located above the first p-metal work function layer and in physical contact with the first p-metal work function layer, the first n-metal work function layer including a region having a non-zero tungsten concentration; and aluminum located within both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer and the first p-metal work function layer but ends before extending to the gate dielectric. In an embodiment, the first n-metal work function layer contains titanium aluminum carbide. In an embodiment, the first p-metal work function layer includes titanium nitride. In an embodiment, a fluorine concentration within the first n-metal work function layer is between about 1 atomic % and about 30 atomic %. In an embodiment, the non-zero tungsten concentration is between about 2 wt % and about 3 wt %. In an embodiment, the semiconductor device further includes: a glue layer located above the first n-metal work function layer; a fill material located above the glue layer; and a dielectric capping layer located above the fill material.

[0071] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0072] Example 1 is a method of manufacturing a semiconductor device, the method including: depositing a gate dielectric above a semiconductor fin; depositing a first p-metal work function layer above the gate dielectric; depositing a first n-metal work function layer above the first p-metal work function layer; and exposing the first n-metal work function layer to a fluorine-containing gas.

[0073] Example 2 is the method of Example 1, wherein the fluorine-containing gas is tungsten fluoride.

[0074] Example 3 is the method of Example 2, wherein depositing the first n-metal work function layer deposits titanium aluminum carbide.

[0075] Example 4 is the method of Example 3, wherein the tungsten fluoride reacts with aluminum in the titanium aluminum carbide.

[0076] Example 5 is the method of Example 4, wherein the exposure increases a tungsten concentration within a top surface of the first n-metal work function layer.

[0077] Example 6 is the method described in Example 1, further comprising: depositing a glue layer on the first n-metal work function layer after exposing the first n-metal work function layer.

[0078] Example 7 is the method described in Example 1, wherein the first n-metal work function layer has a first thickness before exposing the first n-metal work function layer and also has the first thickness after exposing the first n-metal work function layer.

[0079] Example 8 is a method of manufacturing a semiconductor device, the method comprising: depositing a first n-metal work function layer on a first p-metal work function layer and a gate dielectric above a semiconductor fin and in physical contact with the first p-metal work function layer; and capturing a first element within the first n-metal work function layer, the capturing being performed at least in part by exposing the first n-metal work function layer to a passivation precursor.

[0080] Example 9 is the method described in Example 8, wherein the passivation precursor is a fluorine-containing gas.

[0081] Example 10 is the method described in Example 9, wherein the fluorine-containing gas is tungsten fluoride.

[0082] Example 11 is the method described in Example 9, wherein the fluorine-containing gas is nitrogen fluoride.

[0083] Example 12 is the method described in Example 9, wherein the fluorine-containing gas is hafnium tungsten fluoride.

[0084] Example 13 is the method described in Example 9, wherein the fluorine-containing gas is tantalum fluoride.

[0085] Example 14 is the method described in Example 9, wherein exposing the first n-metal work function layer is performed at a temperature between 25 °C and 500 °C and for a time between 30 seconds and 60 seconds.

[0086] Example 15 is a semiconductor device, comprising: a semiconductor fin; a gate dielectric above the semiconductor fin; a first p-metal work function layer above the gate dielectric; a first n-metal work function layer above the first p-metal work function layer and in physical contact with the first p-metal work function layer, the first n-metal work function layer including a region having a non-zero tungsten concentration; and aluminum within both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer and the first p-metal work function layer but ends before extending to the gate dielectric.

[0087] Example 16 is the semiconductor device described in Example 15, wherein the first n-metal work function layer contains aluminum titanium carbide.

[0088] Example 17 is the semiconductor device described in Example 15, wherein the first p-metal work function layer comprises titanium nitride.

[0089] Example 18 is the semiconductor device described in Example 15, wherein the fluorine concentration in the first n-metal work function layer is between about 1 atomic % and about 30 atomic %.

[0090] Example 19 is the semiconductor device described in Example 15, wherein the non-zero tungsten concentration is between about 2 wt% and about 3 wt%.

[0091] Example 20 is the semiconductor device described in Example 15, further comprising: an adhesive layer above the first n-metal work function layer; a filler material above the adhesive layer; and a dielectric capping layer above the filler material.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: Depositing a gate dielectric over a semiconductor fin; Depositing a first p-metal work function layer over the gate dielectric; Depositing a first n-metal work function layer over the first p-metal work function layer; And Exposing the first n-metal work function layer to a fluorine-containing gas, wherein after exposing the first n-metal work function layer to the fluorine-containing gas, the first n-metal work function layer comprises a region having a non-zero tungsten concentration, Wherein aluminum is located within both the first p-metal work function layer and the first n-metal work function layer, and wherein the concentration gradient of the aluminum extends from the first n-metal work function layer and the first p-metal work function layer, but ends before extending to the gate dielectric.

2. The method according to claim 1, wherein The fluorine-containing gas is tungsten fluoride.

3. The method according to claim 2, wherein Depositing the first n-metal work function layer deposits titanium aluminum carbide.

4. The method according to claim 3, wherein, The tungsten fluoride reacts with the aluminum in the titanium aluminum carbide.

5. The method according to claim 4, wherein The exposure increases the tungsten concentration within the top surface of the first n-metal work function layer.

6. The method according to claim 1 further comprises: After exposing the first n-metal work function layer, a glue layer is deposited over the first n-metal work function layer.

7. The method according to claim 1, wherein The first n-metal work function layer has a first thickness before exposing the first n-metal work function layer and also has the first thickness after exposing the first n-metal work function layer.

8. A method of manufacturing a semiconductor device, the method comprising: Depositing a first n-metal work function layer over and in physical contact with a first p-metal work function layer and a gate dielectric located over a semiconductor fin; And Trapping a first element within the first n-metal work function layer, the trapping being performed at least in part by exposing the first n-metal work function layer to a passivation precursor, wherein after exposing the first n-metal work function layer to the passivation precursor, the first n-metal work function layer comprises a region having a non-zero tungsten concentration, Wherein the first element is located within both the first p-metal work function layer and the first n-metal work function layer, and wherein the concentration gradient of the first element extends from the first n-metal work function layer and the first p-metal work function layer, but ends before extending to the gate dielectric.

9. The method according to claim 8, wherein The passivation precursor is a fluorine-containing gas.

10. The method according to claim 9, wherein The fluorine-containing gas is tungsten fluoride.

11. The method according to claim 9, wherein, The fluorine-containing gas is hafnium tungsten fluoride.

12. The method according to claim 9, wherein, Exposing the first n-metal work function layer is performed at a temperature between 25 °C and 500 °C and for a time between 30 seconds and 60 seconds.

13. A semiconductor device, comprising: A semiconductor fin; A gate dielectric located over the semiconductor fin; A first p-metal work function layer located over the gate dielectric; A first n-metal work function layer located over the first p-metal work function layer and in physical contact with the first p-metal work function layer, the first n-metal work function layer comprising a region having a non-zero tungsten concentration; And Aluminum, which is within both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer and the first p-metal work function layer, but ends before reaching the gate dielectric.

14. The semiconductor device according to claim 13, wherein, The first n-metal work function layer contains titanium aluminum carbide.

15. The semiconductor device according to claim 13, wherein, The first p-metal work function layer includes titanium nitride.

16. The semiconductor device according to claim 13, wherein A fluorine concentration within the first n-metal work function layer is between 1 atomic percent and 30 atomic percent.

17. The semiconductor device according to claim 13, wherein, The non-zero tungsten concentration is between 2 weight percent and 3 weight percent.

18. The semiconductor device according to claim 13, further comprising: An adhesive layer, located above the first n-metal work function layer; A filling material, located above the adhesive layer; And A dielectric capping layer, located above the filling material.

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