Electronic device

Abstract

The present invention is entitled "Electronic device". The present invention discloses an electronic device, and the electronic device may include a HEMT. In an embodiment, the HEMT may include a gate electrode, a drain electrode, and an access region. The access region may include a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film may cover a portion of the access region, and an upper dielectric region may cover another portion of the access region. In another embodiment, the dielectric film may have a relatively positive or negative charge and a varying thickness. In another embodiment, the HEMT may include a gate interconnect that extends through a contact opening to the gate electrode.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly to electronic devices including high electron mobility transistors, the high electron mobility transistors including gate electrodes and dielectric films. Background Art

[0002] Enhancement-mode high electron mobility transistors may have a gate field electrode extending toward the drain electrode to help improve device reliability. However, the gate field electrode increases the gate-drain capacitance C GD , which results in a higher Miller ratio C GD / C GS , where C GS is the gate-source capacitance. Other parameters affecting device performance include the subthreshold slope and the on-state resistance R DSON . For the subthreshold slope, the drain current I D can be plotted against the gate voltage V GS when the transistor is turned on. The subthreshold slope can be determined for a specific I D or I D range when the device is off. Ideally, the subthreshold slope is uniform and R DSON is low when the device is on. Improving one variable typically comes at the expense of one of the other parameters. For example, increasing the resistance to gate bounce may be accompanied by lower device reliability, and an increase in the uniformity of the subthreshold slope may be accompanied by a higher R DSON etc. Accordingly, those skilled in the art seek improved performance with little or no adverse impact on device parameters. Summary of the Invention

[0003] The problem to be solved by the present invention is to reduce the Miller ratio of a high electron mobility transistor without increasing the on-state resistance of the high electron mobility transistor to an unacceptable level.

[0004] According to one aspect of the present invention, there is provided an electronic device. The electronic device may include a high electron mobility transistor. The high electron mobility transistor may include: a gate electrode; a drain electrode; an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; a first dielectric film including a first material and covering the first portion of the access region without covering the second portion of the access region; and a second dielectric film including a second material and covering the second portion of the access region, where the second material is different from the first material.

[0005] In an embodiment, the gate electrode has a top surface and a first sidewall intersecting at a first corner, and the first dielectric film contacts the top surface and the sidewall of the gate electrode at the first corner.

[0006] In certain embodiments, the electronic device may further include a gate interconnect, wherein the gate electrode has a second sidewall opposite the first sidewall, the second sidewall intersects the top surface at a second corner, and the gate interconnect contacts a portion of the top surface of the gate electrode and is spaced apart from the first corner and the second corner.

[0007] In more specific embodiments, the gate field electrode is part of or electrically connected to the gate interconnect, wherein a first dielectric film is disposed between the gate field electrode and the first portion of the access region, and the first dielectric film extends a first distance above the access region, the gate field electrode extends a second distance above the access region, and the second distance is in the range of 0.5 times to 2.0 times the first distance.

[0008] In another more specific embodiment, the electronic device may further include a source electrode, wherein the second dielectric film includes a first portion extending from the gate interconnect to the drain electrode and a second portion extending from the gate interconnect to the source electrode.

[0009] In another embodiment, the gate electrode has a body region and an extension region extending from the body region, wherein the body region and the extension region have the same composition and are positioned along the bottom surface of the gate electrode, and the drain electrode is closer to the extension region than to the body region.

[0010] In a further embodiment, the first dielectric film includes Si3N4, SiO k N l (where k < l), AlN, AlO r N s (where r < s) or another nitrogen-containing dielectric material providing a negatively charged dielectric film, and the second dielectric film includes Al2O3, AlO t N u (where t > u), SiO2, HfO2, SiO m N n (where m > n) or another oxygen-containing dielectric material providing a positively charged dielectric film.

[0011] In another aspect, an electronic device is provided. The electronic device may include a high electron mobility transistor. The high electron mobility transistor may include: a gate electrode having a top surface and sidewalls; a drain electrode; an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; and a dielectric film contacting the top surface and sidewalls of the gate electrode and covering the access region. The dielectric film may be a negatively charged film and is relatively thicker above the first portion of the access region and relatively thinner above the second portion of the access region, or the dielectric film may be a positively charged film and is relatively thinner above the first portion of the access region and relatively thicker above the second portion of the access region.

[0012] In an embodiment, the electronic device may further include a gate field electrode that is part of or electrically connected to the gate electrode, wherein the gate field electrode extends above the relatively thinner portion of the dielectric film and does not extend above the relatively thicker portion of the dielectric film.

[0013] In a further aspect, an electronic device is provided. The electronic device may include a high electron mobility transistor. The high electron mobility transistor may include: a gate electrode; a dielectric film covering the gate electrode and defining an opening to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the opening of the dielectric film and contacting a portion of the dielectric film and the gate electrode.

[0014] The technical effects achieved by the present invention allow the high electron mobility transistor to have a relatively low Miller ratio without increasing the on-state resistance of the high electron mobility transistor to an unacceptable level. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Embodiments are illustrated by way of example in the drawings and are not limited to the drawings.

[0016] Figure 1 Including diagrams which include a cross-sectional view of a portion of a workpiece including a substrate, a buffer layer, a channel layer, a barrier layer, and a gate electrode.

[0017] Figure 2 Including a diagram of a cross-sectional view of a workpiece including after forming a lower dielectric film Figure 1 of the workpiece.

[0018] Figure 3 Including a diagram of a cross-sectional view of a workpiece including after forming a mask feature and patterning the lower dielectric film Figure 2 of the workpiece.

[0019] Figure 4 Including a diagram of a cross-sectional view of a workpiece including after removing the mask feature and forming an upper dielectric film Figure 3Illustration of a cross-sectional view of a workpiece.

[0020] Figure 5 Including after forming the interlayer dielectric layer and the drain and source electrodes, including Figure 4 Illustration of a cross-sectional view of a workpiece.

[0021] Figure 6 Including after forming another interlayer dielectric layer, a conductive member, and a gate interconnect, including Figure 5 Illustration of a cross-sectional view of a workpiece.

[0022] Figure 7 Including after forming another interlayer dielectric layer and a patterned conductive layer, including Figure 6 Illustration of a cross-sectional view of a workpiece.

[0023] Figure 8 And Figure 9 Illustration of a top view and a cross-sectional view of a part of a workpiece including a patterned opening to a gate electrode according to another embodiment.

[0024] Figure 10 Illustration of a cross-sectional view of a part of a workpiece including a recessed barrier layer according to another embodiment.

[0025] Figure 11 Illustration of a cross-sectional view of a part of a workpiece including a lower dielectric film formed within a recessed barrier layer according to another embodiment.

[0026] Figure 12 Illustration of a cross-sectional view of a part of a workpiece including a lower dielectric film that includes a portion extending from a gate electrode toward a source electrode according to another embodiment.

[0027] Figure 13 Illustration of a cross-sectional view of a part of a workpiece including a gate electrode having a body region and an extended region according to another embodiment.

[0028] Figure 14 Illustration of a cross-sectional view of a part of a workpiece including a dielectric film having a varying thickness above a drain-side access region according to another embodiment.

[0029] Those skilled in the art will recognize that the elements in the figures are shown for simplicity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to facilitate understanding of the embodiments of the present invention. Detailed Description

[0030] The following description is provided in conjunction with the accompanying drawings to facilitate understanding of the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be construed as a limitation on the scope or applicability of the teachings. However, other embodiments may be employed based on the teachings disclosed in this application.

[0031] III-V materials are intended to denote materials that include at least one Group 13 element and at least one Group 15 element. III-N materials are intended to mean semiconductor materials that include at least one Group 13 element and nitrogen.

[0032] When referring to a film or layer, the terms "negatively charged" and "positively charged" are used relative to the electron density of a two-dimensional electron gas along a heterojunction between two layers, such as a channel layer and a barrier layer. In the case where there is no negatively or positively charged film or layer covering the upper layer of the two layers (e.g., the barrier layer), the two-dimensional electron gas has a baseline electron density. When a negatively charged film or layer covers the upper layer (e.g., the barrier layer), electrons are repelled from the heterojunction, thus reducing the electron density and increasing the sheet resistance of the two-dimensional electron gas. When a positively charged film or layer covers the upper layer (e.g., the barrier layer), electrons are attracted to the heterojunction, thereby increasing the electron density and reducing the sheet resistance of the two-dimensional electron gas. Negatively and positively charged films or layers have opposite effects on the hole density of a two-dimensional hole gas. A negatively charged film or layer increases the hole density of the two-dimensional hole gas, while a positively charged film or layer reduces the hole density of the two-dimensional hole gas.

[0033] The term "comprising", "containing", "including", "having", or any other variation thereof is intended to cover non-exclusive inclusion. For example, a method, article, or device that includes a series of features is not necessarily limited to those features, but may include other features not expressly listed or inherent to such method, article, or device. Additionally, unless expressly stated to the contrary, "or" refers to an inclusive or rather than an exclusive or. For example, the condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or absent), A is false (or absent) and B is true (or present), and both A and B are true (or present).

[0034] Additionally, "a" or "an" is used to describe the elements and components described herein. This is merely for convenience and gives a general sense of the scope of the invention. This description should be considered to include one (a), at least one (a), or the singular form also includes the plural form, and vice versa, unless expressly stated to the contrary. For example, when a single item is described herein, more than one item may be used in place of the single item. Similarly, when more than one item is described herein, a single item may be substituted for the more than one item.

[0035] The use of the terms "about", "approximately" or "substantially" is intended to mean that a value of a parameter is close to a specified value or position. However, small differences may prevent the value or position from being exactly as specified. Thus, a difference of up to ten percent (10%) from the ideal target as described exactly is a reasonable difference for a value.

[0036] The group number corresponds to a column in the periodic table of elements based on the IUPAC periodic table of November 28, 2016 edition.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. In cases not described herein, many details regarding specific materials and processing actions are conventional and can be found in textbooks and other sources in the semiconductor and electronics fields.

[0038] The characteristics of a high electron mobility transistor (HEMT) can be utilized and the performance of the HEMT can be improved. The extended region of the lower dielectric film can locally increase the sheet resistance of the two-dimensional electron gas (2DEG) near the gate electrode and allow for faster charge depletion. A locally higher sheet resistance can be designed so that the R of the HEMT DSON cannot increase by more than 1 ohm·mm. The upper dielectric film can help reduce the sheet resistance of the 2DEG to help offset some of the increased sheet resistance corresponding to the lower dielectric film. C GD may be low and provide a low Miller ratio. The output capacitance (C OSS ) of the HEMT is low. Thus, the HEMT has improved switching characteristics. The lower dielectric film can cover the corners of a portion of the top surface of the gate electrode and help have a more uniform subthreshold slope and increase the gate breakdown voltage during conduction.

[0039] Other features can also provide other advantages or alternatives for the design of the HEMT. When the HEMT is turned on, the contact area between the gate electrode and the gate interconnect can be reduced to reduce the gate current. A recess in the barrier layer near the gate electrode can be used to help increase the threshold voltage of the HEMT. The recess may or may not include the extended region of the lower dielectric film. The lower dielectric film can include a source-side extended region above the source-side access region of the barrier layer. The source-side extended region can help increase the threshold voltage of the HEMT. The gate electrode can include a body region and an extended region that can help increase the threshold voltage of the HEMT.

[0040] In one aspect, an electronic device may include a high electron mobility transistor that includes a gate electrode, a drain electrode, and an access region that includes a first portion closer to the gate electrode and a second portion closer to the drain electrode. The electronic device may further include a first dielectric film and a second dielectric film, where the first dielectric film includes a first material and covers the first portion of the access region but not the second portion, and the second dielectric film includes a second material and covers the second portion of the access region, where the second material is different from the first material.

[0041] In another aspect, an electronic device may include a high electron mobility transistor that includes a gate electrode having a top surface and sidewalls, a drain electrode, and an access region that includes a first portion closer to the gate electrode and a second portion closer to the drain electrode. The electronic device may further include a dielectric film that contacts the top surface and sidewalls of the gate electrode and covers the access region. The dielectric film may include a first negatively charged material and is relatively thicker over the first portion of the access region and relatively thinner over the second portion of the access region, or the dielectric film may include a second positively charged material and is relatively thinner over the first portion of the access region and relatively thicker over the second portion of the access region.

[0042] In another aspect, an electronic device may include a high electron mobility transistor that includes a gate electrode; a dielectric film that covers the gate electrode and defines an opening to the gate electrode, where a portion of the dielectric film is disposed between the openings; and a gate interconnect that extends into the opening of the dielectric film and contacts a portion of the dielectric film and the gate electrode.

[0043] Figure 1 A cross-sectional view of a portion of a workpiece 100 on which a HEMT is being formed. The workpiece 100 may include a substrate 102, a buffer layer 104, a channel layer 106, a barrier layer 108, and a gate electrode 124. The substrate 102 may include silicon, sapphire (single crystal Al2O3), silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga2O3), spinel (MgAl2O4), another suitable substantially single crystal material, etc. The choice of the specific material and crystal orientation along the main surface may be selected according to the composition of the semiconductor layer covered thereon.

[0044] The buffer layer 104 may include a III-N material and, in a specific embodiment, includes Al a Ga (1-a)N, where 0 ≤ a ≤ 1. The composition of the buffer layer 104 can depend on the composition of the channel layer 106 and the designed operating voltage of the HEMT. The composition of the buffer layer 104 can vary with thickness such that the buffer layer 104 has a relatively high aluminum content closer to the substrate 102 and a relatively high gallium content closer to the channel layer 106. In a particular embodiment, the cation (metal atom) content in the buffer layer 104 near the substrate 102 can be 10 atomic % to 100 atomic % Al, with the remainder being Ga, and the cation content in the buffer layer 104 near the channel layer 106 can be 0 atomic % to 50 atomic % Al, with the remainder being Ga. In another embodiment, the buffer layer 104 can include multiple films. The buffer layer 104 can have a thickness in the range of about 1 micron to 5 microns.

[0045] The channel layer 106 can include Al x Ga (1-x) N, where 0 ≤ x ≤ 0.1, and has a thickness in the range of about 20 nm to 4000 nm. In a particular embodiment, the channel layer 106 is a GaN layer (x = 0). The channel layer 106 can be unintentionally doped or doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant. The 2DEG 110 can form near the interface of the channel layer 106 and the barrier layer 108 and is responsible for the high mobility and lower resistivity of the transistor structure when in the on state. Any reduction in the 2DEG electrons will increase the R of the HEMT DSON . In one embodiment, the concentration of the acceptor (when the carrier is an electron) or the donor (when the carrier is a hole) can be reasonably kept as low as possible.

[0046] In a specific embodiment, when metalorganic chemical vapor deposition (MOCVD) is used to form the channel layer 106, the acceptor can include carbon from the source gas (e.g., Ga(CH3)3). In one specific embodiment, the lowest trap concentration is desired, but may be limited by the growth or deposition conditions and the precursor purity. Thus, as the channel layer 106 grows, some carbon may become incorporated, and this carbon can lead to unintentional doping. The carbon content can be controlled by controlling deposition conditions such as deposition temperature and flow rate. In an embodiment, the channel layer 106 has a carrier impurity concentration greater than 0 and less than 1×10 14 atoms / cm 3 or less than 1×10 15 atoms / cm 3 and in another embodiment at most 1×10 16 atoms / cm 3 and in yet another embodiment, the carrier impurity concentration is between 1×10 13 atoms per cubic centimeter and 1×10 16within the range of atoms per cubic centimeter.

[0047] In one embodiment, the channel layer 106 has a thickness of at least 50 nm. When the thickness is less than 50 nm, it may be more difficult to generate, maintain, or both, the 2DEG. In another embodiment, the channel layer 106 has a thickness of at most 5000 nm. In another embodiment, the thickness of the channel layer 106 can be at most 1000 nm and provide good dynamic R DSON . In a particular embodiment, a thickness in the range of 50 nm to 1000 nm can provide a thick enough channel layer 106 to allow proper generation and maintenance of the 2DEG and still obtain reasonable dynamic R DSON . Although not shown, an interlayer can be used between the channel layer 106 and the barrier layer 108 if desired.

[0048] The barrier layer 108 can comprise a III-V semiconductor material, such as a III-N semiconductor material. In an embodiment, the barrier layer 108 can include Al y In z Ga (1-y-z) N, where 0 ≤ y ≤ 1.0, 0 ≤ z ≤ 0.3, and 0 < (y + z) ≤ 1. Compared with the channel layer 106, the barrier layer 108 can have a lower Ga content. In an embodiment, as previously described with respect to the channel layer 106, the barrier layer 108 can be undoped or unintentionally doped. The barrier layer 108 can have any dopant concentration as previously described with respect to the channel layer 106. In an embodiment, the barrier layer 108 and the channel layer 106 can have substantially the same concentration or different dopant concentrations. In another embodiment, at least a portion of the barrier layer 108 can be doped with a p-type dopant that can improve the contact resistance; however, a lower contact resistance may be accompanied by an increase in the sheet resistance associated with the 2DEG 110 at the interface between the channel layer 106 and the barrier layer 108.

[0049] The barrier layer 108 can include a single film or multiple films. When the barrier layer 108 includes multiple films, the aluminum content can remain substantially the same or increase with increasing distance from the channel layer 106. As the aluminum content in the barrier layer 108 increases, the thickness of the barrier layer 108 can be relatively thin. In one embodiment, the barrier layer 108 has a thickness of at least 10 nm, and in another embodiment, the barrier layer 108 has a thickness of at most 150 nm. In a particular embodiment, the barrier layer 108 has a thickness in the range of 20 nm to 90 nm.

[0050] The buffer layer 104, the channel layer 106, and the barrier layer 108 are formed using epitaxial growth techniques, and thus at least a portion of the barrier layer 108, the channel layer 106, and the buffer layer 104 can be single crystal. In a specific embodiment, a metal-containing film can be formed using metalorganic chemical vapor deposition.

[0051] The gate electrode 124 can include a III-V semiconductor material. Examples of such materials can include p-type semiconductor materials. In an embodiment, the gate electrode 124 can include p-type doped Al c Ga (1 - c) N, where 0 ≤ c ≤ 1. In a particular embodiment, the gate electrode 124 includes a p-type dopant such as Mg, Zn, Cd, etc. In another embodiment, the dopant concentration in the gate electrode 124 can have at least 1×10 18 atoms / cm 3 of dopant concentration. In another embodiment, the dopant concentration is at most 1×10 21 atoms per cubic centimeter. The thickness of the gate electrode 124 is in the range of 20 nm to 300 nm.

[0052] The gate electrode layer for the gate electrode 124 can be formed using any technique that can be used to form the channel layer 106 or the barrier layer 108. The p-type dopant can be incorporated in-situ or introduced into the film after deposition. The gate electrode layer can be patterned to form the gate electrode 124. Except under the gate 124, the 2DEG 110 is located along the interface between the channel layer 106 and the barrier layer 108. Thus, the formed transistor is an enhancement-mode HEMT. The gate electrode 124 has a drain-side sidewall 1242, a source-side sidewall 1246, a top surface 1244, and a bottom surface 1248. The drain-side sidewall 1242 and the top surface 1244 intersect at the upper drain-side corner, and the drain-side sidewall 1242 and the bottom surface 1248 intersect at the lower drain-side corner. The source-side sidewall 1246 and the top surface 1244 intersect at the upper source-side corner, and the source-side sidewall 1246 and the bottom surface 1248 intersect at the lower source-side corner. The importance of the surfaces and corners will be introduced in a later part of this specification. The portion of the barrier layer 108 not covered by the gate electrode 124 is referred to herein as the access region and includes a drain-side access region 132 and a source-side access region 136.

[0053] As Figure 2As shown, a lower dielectric film 242 is formed over the gate electrode 124 and the barrier layer 108. The lower dielectric film 242 can be a negatively charged film. The negative charges in the negatively charged film can be generated by (1) fixed negative charges at the interface between such a film (e.g., the lower dielectric film 242) and an adjacent film or layer closer to the 2DEG (e.g., the barrier layer 108) or (2) negative charges within the body of such a film (e.g., the lower dielectric film 242). Thus, electrons are repelled from the interface between the channel layer 106 and the barrier layer 108. The position of the 2DEG 210 is similar to that of the 2DEG 110 and has a higher sheet resistance (lower conductivity) compared to the 2DEG 110. In an embodiment, the lower dielectric film 242 can include a nitrogen-containing compound. When the material of the lower dielectric film 242 includes an oxynitride, the atomic content of N in the oxynitride can be greater than the atomic content of O in the oxynitride. The lower dielectric film 242 can include Si3N4, SiO k N l (where k < 1), AlN, AlO r N s (where r < s), or another nitrogen-containing dielectric material suitable for generating a negatively charged film.

[0054] The thickness of the lower dielectric film 242 is sufficient to affect the sheet resistance of the 2DEG. The lower dielectric film 242 contacts the sidewalls 1242 and 1246 and the top surface 1244 of the gate electrode 124. In an embodiment, the thickness of the lower dielectric film 242 is at least 1 nm. The sheet resistance of the 2DEG increases as the thickness of the lower dielectric film 242 increases until the thickness is greater than 10 nm. Further increases in thickness can be used; however, such increased thickness will not significantly increase the sheet resistance. In an embodiment, the thickness can be at most 50 nm, at most 25 nm, or at most 15 nm. Plasma enhanced atomic layer deposition (PEALD) or low pressure chemical vapor deposition (LPCVD) can be used to form the lower dielectric film 242. If desired or required, the lower dielectric film 242 can be annealed at a temperature in the range of 400 °C to 800 °C for a time in the range of 2 minutes to 120 minutes. A variety of different gases can be used during annealing. The annealing gas can include ammonia (NH3), hydrogen (H2) with or without an inert gas (such as a noble gas), oxygen (O2), etc.

[0055] As Figure 3As shown, the mask feature 342 is formed over the lower dielectric film 242, and the exposed portion of the lower dielectric film 242 is removed. The remaining portion of the lower dielectric film 242 covers the sidewalls 1242 and 1246 and the top surface 1244 of the gate electrode 124, and includes a drain-side extension region 2422 that covers the drain-side access region 132 of the barrier layer 108 and extends laterally toward the location where the drain electrode will subsequently be formed. When covering the drain-side sidewall 1242, the top surface 1244, and the upper drain-side corner of the gate electrode 124, the subthreshold slope of the HEMT can be improved (more uniform when the transistor is turned on) compared to the case where there is no lower dielectric film 242 on the top surface 1244 and the upper corner of the gate electrode 124. More information regarding the drain-side extension 2422 is provided later in this specification with respect to the subsequently formed gate field electrode. In another embodiment shown and described later in this specification, the lower dielectric film 242 can have a source-side extension region that covers the source-side access region 136 and extends laterally toward the location where the source electrode will subsequently be formed. After the lower dielectric film 242 is patterned, the mask feature is removed.

[0056] As Figure 4 shown, an upper dielectric film 444 is formed over the lower dielectric film 242 and the barrier layer 108. The upper dielectric film 444 can be a positively charged film. The positive charges in the positively charged film can be generated by (1) fixed positive charges at the interface between such a film (e.g., the upper dielectric film 444) and an adjacent film or layer closer to the 2DEG (e.g., the barrier layer 108) or (2) positive charges within the bulk of such a film (e.g., the upper dielectric film 444). Thus, electrons can be attracted to the interface between the channel layer 106 and the barrier layer 108. Compared to the 2DEG 210, the 2DEG 410 has a lower sheet resistance (higher conductivity). Compared to the 2DEG110, the 2DEG 410 can have a substantially the same or lower sheet resistance. In an embodiment, the upper dielectric film 444 can include an oxygen-containing compound. When the material of the upper dielectric film 444 includes an oxynitride, the atomic content of O in the oxynitride can be greater than the atomic content of N in the oxynitride. The upper dielectric film 444 can include Al2O3, AlO t N u (where t > u), SiO2, HfO2, SiO m N n (where m > n) or another oxygen-containing dielectric material suitable for generating a positively charged film.

[0057] The thickness of the upper dielectric film 444 is sufficient to affect the sheet resistance of the 2DEG. In an embodiment, the thickness of the upper dielectric film 444 is at least 1 nm. The sheet resistance decreases as the thickness of the upper dielectric film 444 increases until the thickness is greater than 10 nm. Further increases in thickness can be used; however, such increased thickness does not significantly reduce the sheet resistance. In an embodiment, the thickness can be at most 50 nm, at most 25 nm, or at most 15 nm. The upper dielectric film 444 can be formed using plasma enhanced atomic layer deposition (PEALD) or by depositing a thin film of metal and thermally oxidizing the metal. Unlike the lower dielectric film 242, the upper dielectric film 444 covers all of the access regions 132 and 136 and is not patterned at this time in the process. If desired or required, the upper dielectric film 444 can be annealed for a time in the range of 2 minutes to 120 minutes at a temperature in the range of 400 °C to 800 °C. A variety of different gases can be used during annealing. The annealing gas can include ammonia (NH3), hydrogen (H2) with or without an inert gas (such as a noble gas), oxygen (O2), etc. In a particular embodiment, the lower dielectric film 242 may not be annealed prior to forming the upper dielectric film 444, and both the dielectric films 242 and 444 can be annealed during the same annealing period.

[0058] Figure 5 A workpiece after forming an interlayer dielectric (ILD) layer 500, a drain electrode 522, and a source electrode 526 is shown. The ILD layer 500 can be formed over the upper dielectric film 444. The ILD layer 500 can include an oxide, a nitride, or a nitroxide and includes one film or more than one film. The ILD layer 500 can have a thickness in the range of 50 nm to 500 nm.

[0059] The ILD layer 500 can be patterned to define contact openings 502 and 506 for the drain electrode 522 and the source electrode 526. The contact openings 502 and 506 can extend through the ILD layer 500 and the dielectric films 242 and 444. In an embodiment, the contact openings 502 and 506 land on the barrier layer 108. In another embodiment, the contact openings 502 and 506 can extend through a portion but not the entire thickness of the barrier layer 108, or extend through the entire thickness of the barrier layer 108 and contact the channel layer 106. In a particular embodiment, the contact openings 502 and 506 are formed such that a portion of the barrier layer 108 is disposed between the channel layer 106 and the drain electrode 522 and the source electrode 526. The thickness of the barrier layer 108 under the drain electrode 522 and the source electrode 526 can be different from the thickness of the barrier layer 108 under the bottom surface 1248 of the gate electrode 124.

[0060] A conductive layer for the drain electrode 522 and the source electrode 526 is formed over the ILD layer 500 and within the contact openings 502 and 506. The conductive layer can include a single film or multiple films. In one embodiment, the conductive layer can include an adhesion film and a barrier film. Such films can include Ta, TaSi, Ti, TiW, TiSi, TiN, etc. The conductive layer can further include a bulk film. The bulk film can include Al, Cu, or another material that is more conductive than the other films within the conductive layer. In one embodiment, the bulk film can include at least 90 wt% of Al or Cu. The bulk film can have a thickness that is at least as thick as the other films within the conductive layer. In one embodiment, the thickness of the bulk film is in the range of 20 nm to 900 nm, and in a more specific embodiment, in the range of 50 nm to 500 nm. More or fewer films can be used in the conductive layer. The number and composition of the films within the conductive layer can depend on the needs or desires of a particular application. After reading this specification, one of ordinary skill in the art will be able to determine the composition of the conductive layer tailored to their device. The conductive layer is patterned to form the drain electrode 522 and the source electrode 526.

[0061] Figure 6 Shown is a workpiece after forming another ILD layer 600, conductive members 622 and 626, and a gate interconnect 624. The insulating layer 600 can have any composition, number of films, and thickness as previously described with respect to the ILD layer 500. Compared to the ILD layer 500, the ILD 600 can have the same composition or a different composition, the same or different number of films, and the same or different thicknesses.

[0062] The ILD layer 600 can be patterned to define openings for the conductive members 622 and 626 and the gate interconnect 624. The contact openings for the conductive members 622 and 626 extend through the ILD layer 600 to the drain electrode 522 and the source electrode 526. The contact opening for the gate interconnect 624 can extend through the ILD layers 500 and 600 and the dielectric films 242 and 444. As Figure 6 can be seen, the contact opening for the gate interconnect 624 is laterally offset such that the dielectric films 242 and 444 cover the upper drain side corner and the upper source side corner of the gate electrode 124 and a portion of the top surface 1244. Compared to a self-aligned gate process where the upper corners are not covered by dielectric films with a relatively negative charge, the embodiments described herein have a better subthreshold slope because the lower dielectric film 242 helps counteract holes (positive charge carriers) in the gate electrode 124.

[0063] A conductive layer for the conductive members 622 and 626 and the gate interconnect 624 is formed over the ILD layer 600 and within the contact openings. The conductive layer for the conductive members 622 and 626 and the gate interconnect 624 can have any composition, number of films, and thickness as previously described for the conductive layer for the drain electrode 522 and the source electrode 526. Compared with the conductive layer for the drain electrode 522 and the source electrode 526, the conductive layer for the conductive members 622 and 626 and the gate interconnect 624 can have the same composition or a different composition, the same or different numbers of films, and the same or different thicknesses. The conductive layer is patterned to form the conductive members 622 and 626 and the gate interconnect 624.

[0064] In this embodiment, the gate interconnect 624 includes a gate field electrode 6242. Each of the drain-side extension 2422 of the lower dielectric film 242 and the gate field electrode 6242 extends laterally over the drain-side access region 132. As used herein, laterally or the lateral direction is substantially parallel to the interface between the channel layer 106 and the barrier layer 108. In an embodiment, each drain-side extension region 2422 and the gate field electrode 6242 extends laterally over the drain-side access region 132 by up to 8 microns, up to 6 microns, or up to 4 microns. When expressed as a fraction, each drain-side extension region 2422 and the gate field electrode can extend laterally by up to 0.5 times, up to 0.4 times, or up to 0.3 times the distance of the drain-side access region 132 between the gate electrode 124 and the drain electrode 522. In an embodiment, the distances by which the drain-side extension region 2422 and the gate field electrode 6242 extend laterally over the drain-side access region 132 can be substantially the same. In an embodiment, the distance by which the gate field electrode 6242 extends laterally over the drain-side access region 132 can be in the range of 0.5 times to 2.0 times the distance by which the drain-side extension 2422 of the lower dielectric film 242 extends laterally over the drain-side access region 132. In a particular embodiment, the distances by which the drain-side extension region 2422 and the gate field electrode 6242 extend laterally over the drain-side access region 132 are substantially the same.

[0065] In another embodiment, the gate field electrode 6242 can be separate from the gate interconnect 624. For example, an intervening conductive member can provide the gate interconnect, and another conductive member can include the gate field electrode 6242. In another embodiment, the intervening conductive member can be located between the gate electrode 124 and another conductive member including the gate interconnect and the gate field electrode. In all embodiments, the gate field electrode 6242 is not required. The gate field electrode 6242 is an optional feature that can help influence the electric field near the gate electrode 124 along the drain side of the transistor.

[0066] Figure 7Illustrated is a workpiece after forming another ILD layer 700 and conductive members 722 and 726. The insulating layer 700 may have any composition, number of films, and thickness as previously described with respect to the ILD layer 500. Compared with each of the ILD layers 500 and 600, the ILD 700 may have the same composition or a different composition, the same or different numbers of films, and the same thickness or a different thickness. The ILD layer 700 may be patterned to define openings for the conductive members 722 and 726. The contact openings for the conductive members 722 and 726 extend through the ILD layer 700 to the conductive members 622 and 626 that are respectively connected to the drain electrode 522 and the source electrode 526.

[0067] A conductive layer for the conductive members 722 and 726 is formed over the ILD layer 700 and within the contact openings. The conductive layer for the conductive members 722 and 726 may have any composition, number of films, and thickness as previously described with respect to the conductive layers of the drain electrode 522 and the source electrode 526. Compared with the conductive layers for the drain electrode 522 and the source electrode 526 and the conductive members 622 and 626, the conductive layer for the conductive members 722 and 726 may have the same composition or a different composition, the same or different numbers of films, and the same thickness or a different thickness. The conductive layer is patterned to form the conductive members 722 and 726.

[0068] In this embodiment, the conductive member 722 includes a drain field electrode 7222 that extends laterally above the drain side access region 132, and the conductive member 726 includes a source field electrode 7262 that extends laterally above the drain side access region 132. The space between the drain field electrode 7222 and the source field electrode 7262 is sufficient such that the chance of breakdown or leakage current between the drain terminals and the source terminals connected to the conductive members 722 and 726 is small. Similar to the gate field electrode 6242, the drain field electrode 7222 and the source field electrode 7262 affect the electric field along and below the drain side access region 132. Compared with the gate field electrode 6242, the source field electrode 7262 extends further laterally above the drain side access region 132, and the drain electrode 522 is closer to the source field electrode 7262 than the gate field electrode 6242.

[0069] Figure 8 and Figure 9 Illustrated is a workpiece having a patterned opening to the gate electrode 124 according to another embodiment. As Figure 4As shown, after forming the upper dielectric film 444, the lower dielectric film 242 and the upper dielectric film 444 above the gate electrode 124 can be patterned to define an opening 824 to the gate electrode 124. In the illustrated embodiment, the remaining portions of the dielectric films 242 and 444 form a lattice defining the opening 824. After forming the ILD layer 500, the ILD layer 500 is patterned to form a source contact opening 506 and a gate contact opening 904. A conductive layer is formed and patterned to form a source electrode 526 and a gate interconnect 924. In this embodiment, the gate interconnect 924 is formed of the same conductive layer as the source electrode 526. In another embodiment, the gate interconnect 924 can be formed at a different height compared to the source electrode 526. The gate interconnect 924 includes a gate field electrode 9242, which can have any composition and dimensions as previously described with respect to the gate interconnect 624 and the gate field electrode 6242. A drain electrode 522 can also be formed; however, Figure 8 and Figure 9 the ratio of Figures 5 to 7 to better illustrate Figure 8 and Figure 9 the features in

[0070] Compared to the contact opening for the gate interconnect 624, the opening 824 reduces the amount of contact area between the gate electrode 124 and the gate interconnect 924. The reduced contact area increases the resistance between the gate terminal coupled to the gate interconnect 924 and the gate electrode 124. When the HEMT is turned on or the HEMT is turned off by a negative gate voltage (V GS <0), the increased resistance can help reduce the gate current (I G ).

[0071] In another embodiment, as Figure 10 shown, the barrier layer 108 can include a recess 1032 within the drain side access region 132. The recess 1032 can help increase the threshold voltage of the formed HEMT. The recess 1032 can have a depth of up to 60%, up to 40%, or up to 20% of the thickness of the barrier layer 108 extending therethrough. The recess 1032 can laterally extend into the drain side access region 132 any distance as previously described with respect to the drain side extension region 2422 of the lower dielectric film 242. In a particular embodiment, the lower dielectric film 242 may not be formed, and the remaining processes starting from the formation of the upper dielectric film 444 as described above can be performed. In another particular embodiment, the lower dielectric film 242 with or without the drain side extension region 2422 can be formed within the recess 1032, as Figure 11As shown. Compared with the drain-side extension region 2422, the recess 1032 can extend laterally by approximately the same distance into the drain-side access region 132. In another embodiment, compared with the drain-side extension region 2422, the drain-side extension region 2422 can extend laterally by a significantly different distance into the drain-side access region 132. When expressed as a fraction, the distance that the recess 1032 extends laterally into the drain-side access region 132 can be in the range of 0.5 times to 2.0 times the distance that the drain-side extension 2422 extends laterally above the drain-side access region 132. The 2DEG 1110 is located below the drain-side extension 2422 and has a higher sheet resistance than the 2DEG 410. The sheet resistance of the 2DEG 1110 can be substantially the same as or significantly higher than that of the 2DEG 210.

[0072] Figure 12 An embodiment is shown in which the lower dielectric film 1243 includes a drain-side extension region 12432 and a source-side extension region 12436. The drain-side extension region 12432 can be used for any of the reasons previously described for the extension region 2422 of the lower dielectric film 242. The source-side extension region 12436 can help increase the threshold voltage of the HEMT.

[0073] The lower dielectric film 1243 can have any composition and thickness as previously described for the lower dielectric film 242. The drain-side extension region 12432 can extend above the drain-side access region 132 by any distance. The source-side extension region 12436 can extend laterally from the gate electrode 124 partially or completely to the source electrode 526 above the source-side access region 136. In an embodiment, the source-side extension region 12436 can extend laterally from the gate electrode 124 by a distance in the range of 0.1 micrometer to 0.2 micrometer. Such a distance can help increase the threshold voltage without increasing the sheet resistance of the 2DEG, which would increase if the source-side extension region 12436 covered all of the source-side access region 136. The 2DEG 210 is located below the source-side extension region 12436, while the 2DEG 410 is located below the portion of the source-side access region 136 that is not covered by the source-side extension region 12436.

[0074] Figure 13Another embodiment is shown in which the gate electrode 1324 includes a body region 13244 and an extension region 13242. The extension region 13242 may help increase the sheet resistance of the 2DEG 1310 below the extension region 13242. The thickness of the extension region 13242 is sufficient to increase the sheet resistance of the 2DEG 1310, but not so thick as to effectively eliminate the 2DEG 1310. In an embodiment, the thickness of the extension region 13242 is at least 5 nm, at least 8 nm, or at least 11 nm, and in another embodiment, the thickness of the extension region 13242 is at most 40 nm, at most 36 nm, or at most 32 nm. The extension region 13242 may laterally extend towards the drain electrode 522 any distance as previously described for the extension region 2422 of the lower dielectric film 242. Thus, the drain electrode 522 is closer to the extension region 13242 than to the body region 13244. The lower dielectric film 242 is not required, and thus, the lower dielectric film 242 is optional. In another embodiment (not shown), another extension region of the gate electrode 1324 may laterally extend from the body region 13244 towards the source electrode 526.

[0075] Figure 14 Another embodiment is included in which a dielectric film 1444 having a varying thickness may be used as an alternative to the upper dielectric film 242 and the lower dielectric film 444. The dielectric film 1444 is not drawn to scale to enhance understanding of the concept. In the embodiment shown, the dielectric film 1444 may be a negatively charged film and include any material as previously described for the lower dielectric film 242. Above the drain side access region 132, the dielectric film 1444 is thicker closer to the gate electrode 124 and thinner closer to the drain electrode 522. The variation in thickness results in a variation in the electron density within the 2DEG 1410. For the 2DEG 1410, near the gate electrode 124, the electron density is lower, the sheet resistance is higher, and near the drain electrode 522, the electron density is higher and the sheet resistance is lower.

[0076] In another embodiment (not shown), the dielectric film 1444 may be a positively charged film and include any material as described above for the upper dielectric film 444. Above the drain side access region 132, the dielectric film 1444 is thinner closer to the gate electrode 124 and thicker closer to the drain electrode 522. The variation in thickness results in a variation in the electron density within the 2DEG 1410. For the 2DEG 1410, near the gate electrode 124, the electron density is lower, the sheet resistance is higher, and near the drain electrode 522, the electron density is higher and the sheet resistance is lower.

[0077] When the thickness of the negatively or positively charged dielectric film is greater than 10 nm or more, as the thickness of the dielectric film further increases, the change in the electron density of the 2DEG 1410 becomes less obvious. When the dielectric film 1444 is a negatively charged film, its thickness can be at least 10 nm or more near the gate electrode 124 and can have a thickness of 1 nm near the drain electrode 522. The dielectric film 1444 may or may not completely extend to the drain electrode 522. When the dielectric film 1444 is positively charged, its thickness can be at least 10 nm or more near the drain electrode 522 and can have a thickness of 1 nm near the gate electrode 124. The dielectric film 1444 may or may not completely extend to the gate electrode 124. The thickness of the dielectric film 1444 can change as a continuous function of distance or can change in discontinuous steps.

[0078] In yet another embodiment, when the dielectric film 1444 (as the lower dielectric film) is a negatively charged film, the dielectric film 1444 and its varying thickness can be used with the upper dielectric film 444, or when the dielectric film 1444 (as the upper dielectric film) is a positively charged film, the dielectric film and its varying thickness can be used with the lower dielectric film 242.

[0079] In another embodiment, the gate electrode 124 can be replaced by a gate dielectric layer and a metal gate electrode. The gate dielectric layer can include one or more films of electrically insulating nitride or oxide. The thickness of the gate dielectric layer can be in the range of 2 nm to 40 nm. The gate electrode can include one or more films of metal, metal alloy, metal silicide, etc. The film closest to the gate dielectric layer can have a work function that helps provide a desired threshold voltage for the HEMT. The gate electrode can include Ti, TiN, Al, Pd, Pt, W, Au, Ni, or a stack thereof or any combination thereof, and the thickness is in the range of 50 nm to 500 nm. Without departing from the concepts described herein, other compositions and thicknesses for the gate dielectric layer and the gate electrode can be used. The process flow can continue to form Figure 2 the lower dielectric film 242 and other subsequently formed features as described above.

[0080] The embodiments described herein can contribute to the performance of the transistor. The extended region of the lower dielectric film can locally increase the sheet resistance of the 2DEG near the gate electrode and allow for faster charge depletion. The locally higher sheet resistance can be designed so that the R DSON of the transistor cannot increase by more than 1 ohm.mm. The upper dielectric film can help reduce the sheet resistance of the 2DEG to help offset some of the increased sheet resistance corresponding to the lower dielectric film. C GD may be low and provide a low Miller ratio. The output capacitance (C OSS)Lower. Therefore, the HEMT has improved switching characteristics. The lower dielectric film helps to obtain a more uniform subthreshold slope during conduction and increases the gate breakdown voltage.

[0081] Certain embodiments can provide additional advantages or alternatives for the design of the HEMT. When the HEMT is turned on, the contact area between the gate electrode and the gate interconnect can be reduced to reduce the gate current. Such an embodiment may be useful when the gate electrode contacts the barrier layer or the channel layer. A recess in the barrier layer near the gate electrode can be used to help increase the threshold voltage of the HEMT. The recess may or may not include an extended region of the lower dielectric film.

[0082] The lower dielectric film can include a source-side extended region above the source-side access region of the barrier layer. The source-side extended region can help increase the threshold voltage of the HEMT. In certain embodiments, the source-side extension can only partially extend laterally towards the source electrode, so that the 2DEG near the source electrode can have a lower sheet resistance compared to a source-side extension that extends completely to the source electrode.

[0083] In yet another embodiment, the gate electrode can include a body region and an extended region. The extended region for the lower dielectric film may or may not be used. The lower dielectric film can still be used along the sidewalls and the top surface of the gate electrode to protect the upper drain-side and source-side corners of the gate electrode, which can help improve the subthreshold characteristics of the HEMT.

[0084] Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, those skilled in the art will recognize that those aspects and embodiments are merely exemplary and do not limit the scope of the present invention. Embodiments can be based on any one or more of the items listed below.

[0085] Embodiment 1. An electronic device including a high electron mobility transistor, the high electron mobility transistor including: a gate electrode, a drain electrode; an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; a first dielectric film including a first material and covering the first portion of the access region but not covering the second portion of the access region; a second dielectric film including a second material and covering the second portion of the access region, wherein the second material is different from the first material.

[0086] Embodiment 2. The electronic device according to Embodiment 1, wherein the first dielectric film includes Si3N4, SiO k N l (where k < l), AlN, AlO r N s(where r < s) or another nitrogen-containing dielectric material providing a negatively charged dielectric film, and the second dielectric film includes Al2O3, AlO t N u (where t > u), SiO2, HfO2, SiO m N n (where m > n) or another oxygen-containing dielectric material providing a positively charged dielectric film.

[0087] Embodiment 3. The electronic device according to Embodiment 1, wherein the gate electrode has a top surface and a first sidewall intersecting at a first corner, and the first dielectric film contacts the top surface and the sidewall of the gate electrode at the first corner.

[0088] Embodiment 4. The electronic device according to Embodiment 3, the electronic device further includes a gate interconnect, wherein the gate electrode has a second sidewall opposite to the first sidewall, the second sidewall intersects the top surface at a second corner, and the gate interconnect contacts a portion of the top surface of the gate electrode and is spaced apart from the first corner and the second corner.

[0089] Embodiment 5. The electronic device according to Embodiment 4, wherein the first dielectric film defines an opening to the gate electrode, a portion of the first dielectric film is disposed between the openings, and the gate interconnect extends into the opening of the dielectric film and contacts the gate electrode.

[0090] Embodiment 6. The electronic device according to Embodiment 4, wherein the gate field electrode is a part of the gate interconnect or electrically connected to the gate interconnect, and the first dielectric film is disposed between a first part of the access region and the gate field electrode.

[0091] Embodiment 7. The electronic device according to Embodiment 6, wherein the first dielectric film extends a first distance above the access region, the gate field electrode extends a second distance above the access region, and the second distance is in the range of 0.5 times to 2.0 times the first distance.

[0092] Embodiment 8. The electronic device according to Embodiment 7, the electronic device further includes a source electrode and a source field electrode that is a part of the source electrode or electrically connected to the source electrode, wherein:

[0093] The drain electrode is closer to the first corner of the gate electrode than to the second corner closer to the gate electrode,

[0094] The first dielectric film includes silicon nitride, the second dielectric film includes aluminum oxide,

[0095] The first dielectric film contacts the top surface and the second sidewall of the gate electrode at the second corner,

[0096] The second dielectric film covers a first part of the access region, and

[0097] The drain electrode is closer to the source field electrode than to the gate field electrode.

[0098] Embodiment 9. The electronic device according to Embodiment 8, wherein the second dielectric film includes a first portion extending from the gate interconnect to the drain electrode and a second portion extending from the gate interconnect to the source electrode.

[0099] Embodiment 10. The electronic device according to Embodiment 4, the electronic device further comprising a source electrode and a source field electrode that is part of or electrically connected to the source electrode, wherein at least a portion of the source field electrode covers the gate field electrode.

[0100] Embodiment 11. The electronic device according to Embodiment 1, the electronic device further comprising a barrier layer under the gate electrode, wherein the barrier layer is relatively thin closer to the gate electrode and relatively thick closer to the drain electrode.

[0101] Embodiment 12. The electronic device according to Embodiment 1, wherein the gate electrode has a body region and an extension region extending from the body region, wherein the body and the extension region have the same composition and are positioned along the bottom surface of the gate electrode, and the drain electrode is closer to the extension region than to the body region.

[0102] Embodiment 13. The electronic device according to Embodiment 1, the electronic device further comprising a source electrode, wherein the first dielectric film extends at least a portion of the distance from the gate electrode towards the source electrode.

[0103] Embodiment 14. The electronic device according to Embodiment 1, the electronic device further comprising: a channel layer comprising Al x Ga (1-x) N, where 0 ≤ x ≤ 0.1; and a barrier layer comprising Al y In z Ga (1-y-z) N, where 0 ≤ y ≤ 1.0, 0 ≤ z ≤ 0.3, 0 < (y + z) ≤ 1, the barrier layer has a lower Ga content compared to the channel layer, and the barrier layer is disposed between the channel layer and the gate electrode.

[0104] Embodiment 15. The electronic device according to Embodiment 1, wherein the gate electrode comprises a III-N semiconductor material.

[0105] Embodiment 16. The electronic device according to Embodiment 1, the electronic device further comprising a gate dielectric layer under the gate electrode, wherein the gate electrode comprises a metal or a metal alloy in contact with the gate dielectric layer.

[0106] Embodiment 17. An electronic device including a high electron mobility transistor, the high electron mobility transistor including: a gate electrode having a top surface and sidewalls; a drain electrode; an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; a dielectric film that contacts the top surface and sidewalls of the gate electrode and covers the access region; the dielectric film may be a negatively charged film and is relatively thick above the first portion of the access region and relatively thin above the second portion of the access region, or the dielectric film may be a positively charged film and is relatively thin above the first portion of the access region and relatively thick above the second portion of the access region.

[0107] Embodiment 18. The electronic device according to Embodiment 17, the electronic device further including a gate field electrode that is part of the gate electrode or electrically connected to the gate electrode, wherein the gate field electrode extends above the relatively thin portion of the dielectric film and does not extend above the relatively thick portion of the dielectric film.

[0108] Embodiment 19. An electronic device including a high electron mobility transistor, the high electron mobility transistor including: a gate electrode dielectric film that covers the gate electrode and defines an opening to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect that extends into the opening of the dielectric film and contacts a portion of the dielectric film and the gate electrode.

[0109] Embodiment 20. The electronic device according to Embodiment 19, the electronic device further including a channel layer and a barrier layer covering the channel layer, wherein the gate electrode includes a III-N semiconductor material and contacts the channel or the barrier layer.

[0110] It should be noted that not all of the activities described above in the general description or examples are required, a portion of a particular activity may not be required, and one or more additional activities may be performed in addition to those described. Also, the order in which the listed activities are presented is not necessarily the order in which the activities are performed.

[0111] Advantages, other advantages, and problem solutions have been described above with respect to specific embodiments. However, these advantages, advantages, problem solutions, and any features that may cause any advantage, advantage, or solution to occur or become more apparent should not be construed as critical, required, or essential features of any or all of the claims.

[0112] The description and illustration of the embodiments described herein are intended to provide a general understanding of the structures of the various embodiments. The description and illustration are not intended to be an exhaustive and comprehensive description of all elements and features of the devices and systems using the structures or methods described herein. Separate embodiments may also be provided in a single embodiment in combination, and conversely, the various features described in the context of a single embodiment for simplicity may also be provided individually or in any sub-combination. Additionally, references to values expressed as ranges include all values within that range. Many other embodiments will be apparent only to those skilled in the art after reading this specification. Other embodiments may be used and derived from this disclosure such that structural substitutions, logical substitutions, or other changes may be made without departing from the scope of this disclosure. Accordingly, this disclosure should be regarded as exemplary and not restrictive.

Claims

1. An electronic device including a high electron mobility transistor, the electronic device comprising: A gate electrode; A drain electrode; An access region, the access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; A first dielectric film, the first dielectric film comprising a first material and covering the first portion of the access region but not covering the second portion of the access region, wherein the first dielectric film is a negatively charged dielectric film and comprises Si3N4, SiO k N l , AlN, AlO r N s or another nitrogen-containing dielectric material providing the negatively charged dielectric film, where k < l and where r < s; A second dielectric film, the second dielectric film comprising a second material and covering the second portion of the access region, wherein the second material is different from the first material, and the second dielectric film is a positively charged dielectric film and comprises Al2O3, AlO t N u , SiO2, HfO2, SiO m N n or another oxygen-containing dielectric material providing the positively charged dielectric film, where t > u, where m > n; An interlayer dielectric layer covering the first dielectric film and the second dielectric film; and A gate interconnect extending through an opening in the interlayer dielectric layer and contacting the gate electrode.

2. The electronic device according to claim 1, wherein the gate electrode has a top surface and a first sidewall intersecting at a first corner, and the first dielectric film contacts the top surface and the sidewall of the gate electrode at the first corner.

3. The electronic device according to claim 2, wherein the gate electrode has a second sidewall opposite to the first sidewall, the second sidewall intersects the top surface at a second corner, and the gate interconnect contacts a portion of the top surface of the gate electrode and is spaced apart from the first corner and the second corner.

4. The electronic device according to claim 3, wherein a gate field electrode is part of the gate interconnect or electrically connected to the gate interconnect, wherein the first dielectric film is disposed between the first portion of the access region and the gate field electrode, and the first dielectric film extends a first distance above the access region, the gate field electrode extends a second distance above the access region, and the second distance is in the range of 0.5 times to 2.0 times the first distance.

5. The electronic device according to claim 3, the electronic device further comprising a source electrode, wherein the second dielectric film includes a first portion extending from the gate interconnect to the drain electrode and a second portion extending from the gate interconnect to the source electrode.

6. The electronic device according to claim 1, wherein the gate electrode has a body region and an extension region extending from the body region, wherein the body region and the extension region have the same composition and are positioned along the bottom surface of the gate electrode, and the drain electrode is closer to the extension region than to the body region.

7. An electronic device including a high electron mobility transistor, the electronic device comprising: A gate electrode having a top surface and sidewalls; A drain electrode; An access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode, wherein each of the first portion and the second portion is between the gate electrode and the drain electrode; A first dielectric film contacting the top surface and the sidewalls of the gate electrode and covering the first portion of the access region, wherein the The first dielectric film is a negatively charged film and includes Si3N4, SiO k N l , AlN, AlO r N s or another nitrogen-containing dielectric material providing the negatively charged film, wherein k < l, where r < s; A second dielectric film, the second dielectric film covering the second portion of the access region, wherein the second dielectric film is a positively charged dielectric film and includes Al2O3, AlO t N u , SiO2, HfO2, SiO m N n or another oxygen-containing dielectric material providing the positively charged dielectric film, wherein t > u, wherein m > n.

8. The electronic device according to claim 7, the electronic device further comprising a gate field electrode that is part of the gate electrode or electrically connected to the gate electrode, wherein the gate field electrode extends above the first portion of the access region and does not extend above the second portion of the access region.

9. The electronic device according to any one of claims 1 to 8 further includes a blocking layer having a first portion closer to the gate electrode and a second portion closer to the drain electrode, wherein the first dielectric film contacts the first portion of the blocking layer, and the second dielectric film contacts the second portion of the blocking layer.

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