Semiconductor device

Abstract

A semiconductor device includes a plurality of active regions extending in a first direction on a substrate, a device isolation layer located between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer, a first gate electrode and a second gate electrode extending in a second direction crossing the first direction on the substrate and intersecting the plurality of active regions, respectively, the first gate electrode being spaced apart from the second gate electrode in the second direction, a first gate separation layer located between the first gate electrode and the second gate electrode, and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2019-0043851 entitled "Semiconductor Devices", filed with the Korean Intellectual Property Office on April 15, 2019, are incorporated herein by reference. Technical Field

[0003] The examples involve semiconductor devices. Background Technology

[0004] As the demand for high performance, high speed, and multifunctionality in semiconductor devices increases, the integration level of semiconductor devices also increases. In manufacturing semiconductor elements with fine patterns to correspond to this trend of high integration, patterns with fine widths or fine spacing can be achieved. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising: a plurality of active regions extending on a substrate along a first direction; a device isolation layer located between the plurality of active regions such that the upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending on the substrate in a second direction intersecting the first direction and intersecting the plurality of active regions, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separator layer located between the first gate electrode and the second gate electrode; and a second gate separator layer located below the first gate separator layer and between the first gate electrode and the second gate electrode, the second gate separator layer extending upward in a third direction intersecting the first and second directions into the device isolation layer.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: a plurality of active regions extending on a substrate along a first direction; a first gate electrode and a second gate electrode extending on the substrate in a second direction intersecting the first direction and intersecting the plurality of active regions, the first gate electrode being spaced apart from the second gate electrode in the second direction; and a gate separation portion located between the first gate electrode and the second gate electrode, wherein the gate separation portion comprises at least two layers stacked in a third direction perpendicular to the first direction and the second direction and having different widths.

[0007] Embodiments can be implemented by providing a semiconductor device including a plurality of active regions extending in one direction; a dummy active region parallel to the plurality of active regions; a first gate electrode and a second gate electrode intersecting the plurality of active regions and the dummy active region, the first gate electrode being spaced apart from the second gate electrode on a straight line; a first gate separation layer extending downward from an upper surface of the first gate electrode and an upper surface of the second gate electrode, the first gate separation layer being located between the first gate electrode and the second gate electrode; and a second gate separation layer located below the first gate separation layer, the second gate separation layer being in contact with the first gate separation layer and the dummy active region. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details. It is also intended that all such embodiments can be made and obtained within the scope of the invention, and that features of the invention can be used in any combination or permutation, without limitation.

[0009] FIG. 1 shows a top view of a semiconductor device according to an example embodiment;

[0010] FIG. 2A and FIG. 2B shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0011] FIG. 3 shows a perspective view of a semiconductor device according to an example embodiment;

[0012] FIG. 4A and FIG. 4B shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0013] FIG. 5A and FIG. 5B shows a top view and a cross-sectional view of a semiconductor device according to an example embodiment;

[0014] FIG. 6A to FIG. 6C shows a top view and a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] FIG. 7A and FIG. 7B shows a top view and a cross-sectional view of a semiconductor device according to an example embodiment;

[0016] FIG. 8 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0017] FIG. 9A and FIG. 9B shows a top view and a cross-sectional view of a semiconductor device according to an example embodiment;

[0018] FIG. 10A to FIG. 10Lviews showing stages in a method of manufacturing a semiconductor device according to a process sequence, according to example embodiments;

[0019] FIG. 11A to FIG. 11G views showing stages in a method of manufacturing a semiconductor device according to a process sequence, according to example embodiments;

[0020] FIG. 12A to FIG. 12C views showing stages in a method of manufacturing a semiconductor device according to a process sequence, according to example embodiments;

[0021] FIG. 13 a circuit diagram showing an SRAM cell including a semiconductor device, according to example embodiments;

[0022] FIG. 14 a diagram showing an electronic device including a semiconductor device, according to example embodiments; and

[0023] FIG. 15 a diagram showing a system including a semiconductor device, according to example embodiments. DETAILED DESCRIPTION

[0024] FIG. 1 a top view of a semiconductor device, according to example embodiments. FIG. 2A and FIG. 2B cross-sectional views of the semiconductor device of FIG. 1 along lines I-I' and II-II', and III-III' and IV-IV', respectively. FIG. 3 perspective view of a portion of the semiconductor device of FIG. 1 For ease of illustration, only major components of the semiconductor device are shown in FIG. 1 to FIG. 3

[0025] Referring to FIG. 1 to FIG. 3 , the semiconductor device 100 can include a substrate 101, an active region 105, a device isolation layer 110, a source / drain region 150, a gate structure 160, and a gate separation portion 170. The gate structure 160 can include a gate dielectric layer 162, a gate electrode 165, and a gate spacer layer 166. The gate separation portion 170 can include a first gate separation layer 172 and a second gate separation layer 174.

[0026] The semiconductor device 100 can include a FinFET device in which the active region 105 has a fin structure. The FinFET device can include transistors around the active region 105 and the gate structure 160 that cross each other.

[0027] ​The substrate 101 can have an upper surface extending in the X-direction and the Y-direction (e.g., a plane defined by the X-direction and the Y-direction, i.e., an X-Y plane). The substrate 101 can include a semiconductor material, e.g., a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The substrate 101 can be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like.

[0028] The device isolation layer 110 can define the active regions 105 in the substrate 101. In one implementation, the device isolation layer 110 can include regions extending deeper (e.g., in a Z-direction perpendicular or orthogonal to the X-Y plane) into a lower portion of the substrate 101 between the active regions 105, and can be a single layer by being connected to each other along the X-direction at the ends. In one implementation, the device isolation layer 110 can have a curved upper surface (e.g., curved or concave inwardly toward the substrate 101 along the Z-direction) with a higher height (e.g., with a portion away from the substrate 101 in the Z-direction) near or adjacent to the active regions 105. The device isolation layer 110 can be made of an insulating material. The device isolation layer 110 can be, for example, an oxide, a nitride, or a combination thereof. As FIG. 2A As shown in the cross-sectional view, at a lower portion and outside of the gate structure 160, the upper surface (e.g., the surface facing away from the substrate 101) of the device isolation layer 110 can have different heights. In one implementation, the height difference of the upper surface can be variously modified.

[0029] The active regions 105 can be defined by the device isolation layer 110 in or on the substrate 101, and can extend along a first direction (e.g., the X-direction). The active regions 105 can have a structure of active fins protruding (e.g., along the Z-direction) from the substrate 101. The upper end of the active regions 105 can protrude (e.g., along the Z-direction) from the upper surface of the device isolation layer 110 to a predetermined height (e.g., further away from the substrate 101 than the upper surface of the device isolation layer 110). In one implementation, the active regions 105 can be formed by a portion of the substrate 101, or can include an epitaxial layer grown from the substrate 101. In one implementation, on both sides of the gate structure 160, the active regions 105 on the substrate 101 can be partially recessed, and the source / drain regions 150 can be located on the recessed active regions 105. For example, as shown in FIG. 2A and FIG. 2B As shown in the cross-sectional view, at a lower portion and outside of the gate structure 160, the upper surface (e.g., the surface facing away from the substrate 101) of the device isolation layer 110 can have different heights. In one implementation, the height difference of the upper surface can be variously modified.

[0030] Dummy active regions 105D can further be included between the active regions 105. The dummy active regions 105D can be regions in which a channel region of a transistor is not formed in the semiconductor device 100 and substantially does not perform an electrical function. The dummy active regions 105D can have a similar shape extending in the X direction as the active regions 105, and can be provided at regular intervals together with the active regions 105. As shown in FIG. 1, the dummy active regions 105D can be provided in the lower portion of the gate separation portion 170 or adjacent to the lower portion of the gate separation portion 170, or below the gate separation portion 170. FIG. 2A and FIG. 2B As shown in FIG. 1, the height H2 (e.g., in the Z direction) of the dummy active regions 105D in the lower portion of the gate separation portion 170 or adjacent to the lower portion of the gate separation portion 170, or below the gate separation portion 170, can be lower than the height H1 (in the Z direction) of the active regions 105. This can be a shape formed by a process of partially removing the active regions 105 and forming the dummy active regions 105D. This will be described in more detail below. FIG. 10A to FIG. 11G with reference to FIGS. 2A and 2B.

[0031] In an embodiment, the height H2 of the dummy active regions 105D on or both sides of the gate structure 160 can also be lower than the height H3 (in the Z direction) of the recessed active regions 105. In this case, the dummy active regions 105D can have a form recessed into the device isolation layer 110. In an embodiment, on both sides of the gate structure 160, the height of the dummy active regions 105D can be the same as or similar to the height H3 of the active regions 105. In an embodiment, on both sides of the gate structure 160 and in the lower portion of the gate separation portion 170, the dummy active regions 105D can have the same height. In an embodiment, similar to the active regions 105, the height of the dummy active regions 105D on both sides of the gate structure 160 can also be lower than the height in the lower portion of the gate separation portion 170.

[0032] Source / drain regions 150 can be located on the active regions 105 on both sides of the gate structure 160, respectively. The source / drain regions 150 can be provided as source regions or drain regions of a transistor. The source / drain regions 150 can have a raised source / drain shape in which an upper surface thereof is higher than a lower surface (e.g., a surface facing the substrate) of the gate structure 160 (e.g., the gate electrode 165).

[0033] In an embodiment, the source / drain region 150 can have a hexagonal shape. In an embodiment, a portion of the source / drain region 150 can have a hexagonal shape, while another portion of the source / drain region 150 can have a pentagonal shape. In an embodiment, the source / drain region 150 can have various shapes, such as any one of, for example, a polygonal shape, a circular shape, and a rectangular shape. In an embodiment, the source / drain region 150 can be connected or merged with each other on two or more active regions 105 that are disposed adjacent to each other to form one source / drain region 150.

[0034] The source / drain region 150 can be made of a semiconductor material. In an embodiment, the source / drain region 150 can be formed of an epitaxial layer. For example, the source / drain region 150 can include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). In an embodiment, the source / drain region 150 can include a plurality of regions including elements having different concentrations and / or different doped elements.

[0035] The gate structure 160 can extend in one direction (e.g., a Y direction) to intersect the active region 105 in or on an upper portion of the active region 105. A channel region of a transistor can be formed in the active region 105 that intersects the gate structure 160. The gate structure 160 can include a gate dielectric layer 162, a gate electrode 165, and a gate spacer layer 166.

[0036] The gate dielectric layer 162 can be located between the active region 105 and the gate electrode 165, and can cover a lower surface and two side surfaces of the gate electrode 165. In an embodiment, the gate dielectric layer 162 can be formed only on a lower surface of the gate electrode 165 (e.g., can not extend along side surfaces of the gate electrode 165). The gate dielectric layer 162 can include an oxide, a nitride, or a high dielectric constant (high-k) material. The high-k material can refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The high-k material can be any one of, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), lanthanum hafnium oxide (LaHfO4), hafnium aluminum oxide (HfAlO4), and praseodymium oxide (Pr2O3). x O y x O y x O y x O y x O y ​​​​​

[0037] The gate electrode 165 may comprise a conductive material and may comprise, for example, a metal nitride (e.g., titanium nitride film (TiN), tantalum nitride film (TaN), or tungsten nitride film (WN)), and / or a metallic material (e.g., aluminum (Al), tungsten (W), molybdenum (Mo), etc.), or a semiconductor material (e.g., doped polycrystalline silicon). The gate electrode 165 may be formed from two or more multilayer structures. The gate electrode 165 may be separated from at least a portion of adjacent transistors by a gate separation portion 170, depending on the configuration of the semiconductor device 100.

[0038] Gate spacer layer 166 may be located on both sides of gate electrode 165. Gate spacer layer 166 may insulate source / drain regions 150 from gate electrode 165. According to an example embodiment, gate spacer layer 166 may be formed of a multilayer structure. Gate spacer layer 166 may include oxide, nitride, or oxynitride, such as a low dielectric constant film.

[0039] Between at least a portion of the transistors, a gate separator 170 may separate each gate electrode 165 extending in one direction (e.g., the Y direction) into a first gate electrode 165A and a second gate electrode 165B. The gate separator 170 may extend in a direction perpendicular to the extension direction of the gate electrode 165 (e.g., in the X direction) to separate the gate dielectric layer 162 and the gate electrode 165. The gate separator 170 may include a first gate separator layer 172 and a second gate separator layer 174 vertically connected to each other. The first gate separator layer 172 may separate the gate electrode 165 from the upper portion of the gate structure 160, and the second gate separator layer 174 may be located below the first gate separator layer 172 and may extend into the device isolation layer 110 between active regions 105 (e.g., active regions 105 adjacent to each other in the Y direction).

[0040] In one embodiment, the first gate separator layer 172 may be located on a plane to separate the gate dielectric layers 162 and the gate electrode 165 on both sides, such as FIG. 1 As shown. In one embodiment, the first gate separator 172 may only separate the gate electrode 165. The first gate separator 172 may extend downward (along the Z direction) from the upper surface of the gate electrode 165 and may extend to the upper surface of the active region 105 or to a similar height level (e.g., at a similar distance from the substrate 101 in the Z direction). The lower surface of the first gate separator 172 may be located at a height higher than the upper surface of the device isolation layer 110 (e.g., at a distance from the substrate 101 in the Z direction). In one embodiment, the upper surface of the first gate separator 172 may be coplanar with the gate electrode 165.

[0041] The second gate separation layer 174 can be located on the dummy active region 105D, and an upper surface of the second gate separation layer 174 can be in contact (e.g., direct contact) with the first gate separation layer 172. The second gate separation layer 174, together with the dummy active region 105D, can have the same or similar shape as the active region 105. For example, the second gate separation layer 174 can have a shape corresponding to (e.g., similar to or the same as) an upper region of the active region 105, and an upper surface of the second gate separation layer 174 can be located at substantially the same height as an upper surface of the adjacent active region 105. The second gate separation layer 174 can protrude upward and downward from or relative to an upper surface of the device isolation layer 110. For example, a lower portion of the second gate separation layer 174 can extend into the device isolation layer 110 to be located in a recessed form or a recessed region of the device isolation layer 110, as shown in FIG. 1C. FIG. 2A

[0042] In an embodiment, a lower surface of the second gate separation layer 174 can be at a lower height level (e.g., closer to the substrate 101 in the Z direction) than a height level of the upper surface of the device isolation layer 110, and can have a downward convex shape (e.g., convex shape toward the substrate 101 in the Z direction). In an embodiment, the lower surface of the second gate separation layer 174 can have a flat surface according to a manufacturing method thereof. In an example embodiment, a depth D1 of the second gate separation layer 174 recessed from the upper surface of the device isolation layer 110 and a protruding height H4 can be varied differently. A side surface of the second gate separation layer 174 at an upper portion thereof (e.g., away from the substrate 101 in the Z direction) can be in contact (e.g., direct contact) with the gate dielectric layer 162. A side surface of the second gate separation layer 174 at a lower portion thereof (e.g., close to the substrate 101 in the Z direction) can be in contact (e.g., direct contact) with the device isolation layer 110.

[0043] In an embodiment, a width W2 (in the Y direction) of the second gate separation layer 174 can be smaller than a width W1 (in the Y direction) of the first gate separation layer 172. For example, there can be a stepped portion or a curved portion depending on the width difference between the first gate separation layer 172 and the second gate separation layer 174. The width W1 of the first gate separation layer 172 can be, for example, 5 nm to 100 nm, and the width W2 of the second gate separation layer 174 can be, for example, 1 nm to 20 nm. In an embodiment, the width W2 of the second gate separation layer 174 can be the same or similar to a width of the active region 105. In an embodiment, as shown in FIG. 1C, the width W2 of the second gate separation layer 174 can be smaller than the width W1 of the first gate separation layer 172. FIG. 2B ​The second gate separation layer 174 can have a side surface perpendicular to an upper surface of the dummy active region 105D, as shown in a cross section of III-III'. In one embodiment, the second gate separation layer 174 can have a shape corresponding to a shape of the gate structure 160. For example, the second gate separation layer 174 can also have a shape in which a width is widened toward a lower portion in the cross section of III-III'. The second gate separation layer 174 can be located only on a lower portion of the first gate separation layer 172 on the plane, as shown in FIG. 1 and can not extend to a lower portion of the gate spacer layer 166. In one embodiment, the second gate separation layer 174 can also extend to the lower portion of the gate spacer layer 166.

[0044] The first gate separation layer 172 and the second gate separation layer 174 can include the same or different insulating materials. The first gate separation layer 172 and the second gate separation layer 174 can be made of a material having etching selectivity with respect to the device isolation layer 110 under a specific etching condition, and can be made of a material capable of having etching selectivity with respect to the second sacrificial layer 184, etc., as described with reference to FIG. 10E In one embodiment, the first gate separation layer 172 and the second gate separation layer 174 can each independently include, for example, SiN, SiOCN, AlN, etc.

[0045] The gate separation portion 170 can include the first gate separation layer 172 and the second gate separation layer 174 stacked in a vertical direction and disposed such that the adjacent first gate electrode 165A and the second gate electrode 165B can be electrically separated and completely isolated. For example, the second gate separation layer 174 can be formed using the dummy active region 105D to completely electrically separate the first gate electrode 165A and the second gate electrode 165B in the X direction and block a leakage current. For example, even when the gate structure 160 has a shape widened in the X direction in a region adjacent to the device isolation layer 110, the second gate separation layer 174 can fill a region between a pair of gate spacer layers 166 so that the first gate electrode 165A and the second gate electrode 165B can be completely electrically insulated from each other.

[0046] As FIG. 1As shown, a distance W3 from a side surface of the second gate separation layer 174 in the Y direction to a side surface of the adjacent active region 105 can be a factor that affects characteristics of a threshold voltage of a transistor such as formed by the active region 105 and the gate structure 160. For this, in one embodiment, the gate separation portion 170 can include the second gate separation layer 174 at a lower portion thereof compared to a case where the gate separation portion 170 includes only the first gate separation layer 172 (e.g., does not have the second gate separation layer 174), and can form a portion that affects characteristics of the transistor without any process bias, and can further improve the electrical characteristics of the semiconductor device 100.

[0047] FIG. 4A and FIG. 4B A cross-sectional view of a semiconductor device according to an example embodiment is shown. FIG. 4A and FIG. 4B A region corresponding to a cross-section along I-I' in FIG. 2A is shown.

[0048] Referring to FIG. 4A In the semiconductor device 100a, the first gate separation layer 172a of the gate separation portion 170a can cover a portion of a side surface of the second gate separation layer 174. For example, the first gate separation layer 172a can extend along the side surface of the second gate separation layer 174 from an upper portion of the second gate separation layer 174 downward (e.g., toward the substrate 101 in the Z direction) by a predetermined depth. In one embodiment, a lower surface of the first gate separation layer 172a located on the side surface of the second gate separation layer 174 can extend along the side surface of the second gate separation layer 174 to have a more curved shape.

[0049] The gate dielectric layer 162 can be located between the second gate separation layer 174 and the gate electrode 165, and can not be on an upper surface and a side surface of the second gate separation layer 174 that is in contact with the first gate separation layer 172a.

[0050] Referring to FIG. 4B In the semiconductor device 100b, the first gate separation layer 172b of the gate separation portion 170b can cover a portion of an upper surface of the second gate separation layer 174 and a portion of one side surface (e.g., only one side surface) of the second gate separation layer 174. For example, the first gate separation layer 172b can extend along the one side surface of the second gate separation layer 174 from an upper portion of the second gate separation layer 174 downward to a predetermined depth. In one embodiment, a lower surface of the first gate separation layer 172b located on the side surface of the second gate separation layer 174 can extend along the side surface of the second gate separation layer 174 to have a more curved shape.

[0051] The gate dielectric layer 162 can be located between the second gate separation layer 174 and the gate electrode 165, and can not be on the upper surface and side surfaces of the second gate separation layer 174 that are in contact with the first gate separation layer 172b.

[0052] FIG. 5A and FIG. 5B Cross-sectional views and plan views of a semiconductor device according to example embodiments are shown. FIG. 5B Cross-sectional views and plan views of a semiconductor device according to example embodiments are shown. FIG. 5A Cross-sectional views and plan views of a semiconductor device according to example embodiments are shown.

[0053] Referring to FIG. 5A and FIG. 5B In the semiconductor device 100c, the gate dielectric layer 162P of the gate structure 160 can be further provided on the side surfaces of the first gate separation layer 172 (e.g., the side surfaces of the first gate separation layer 172 facing the Y direction). As shown in FIG. 5B The gate dielectric layer 162P can extend on the side surfaces of the first gate separation layer 172 as well as on the side surfaces of the second gate separation layer 174. This structure can be produced by a fabrication method described below with reference to FIG. 12A to FIG. 12C In one implementation, as shown in FIG. 5A The gate dielectric layer 162P can not be on the side surfaces of the first gate separation layer 172 facing the X direction.

[0054] FIG. 6A to FIG. 6C Cross-sectional views and plan views of a semiconductor device according to example embodiments are shown. FIG. 6B and FIG. 6C Cross-sectional views and plan views of a semiconductor device according to example embodiments are shown. FIG. 6A Cross-sectional views and plan views of a semiconductor device according to example embodiments are shown.

[0055] Referring to FIG. 6A to FIG. 6C In the semiconductor device 100d, the second gate separation layer 174c of the gate separation portion 170c can have a shape extending along the X direction together with the dummy active region 105D. For example, on or at both sides of the gate structure 160, the second gate separation layer 174c can be located between adjacent source / drain regions 150, as shown in the cross-sectional view taken along II-II' in FIG. 6B The height H6 of the portion of the second gate separation layer 174c outside the gate structure 160 is lower than the height H5 of the second gate separation layer 174c in or below the lower portion of the first gate separation layer 172. For example, growth of the source / drain regions 150 can be more easily performed. In one implementation, the height H5 of the second gate separation layer 174c below the first gate separation layer 172 can be the same as the height H6 outside the gate structure 160.

[0056] FIG. 7A and FIG. 7B A plan view and cross-sectional views of a semiconductor device according to an example embodiment are shown. FIG. 7B A cross-section of the semiconductor device of FIG. 7A along the cut lines I-I' and II-II' is shown.

[0057] Referring to FIG. 7A and FIG. 7B In the semiconductor device 100e, the second gate separation layer 174d of the gate separation portion 170d can be located on the device isolation layer 110. For example, the dummy active region 105D can not exist, e.g., can not be under the lower portion of the second gate separation layer 174d of the gate separation portion 170d. This structure can be formed by removing the active region 105 under the lower portion of the second gate separation layer 174d or not forming the active region 105. The second gate separation layer 174d can extend into or between the device isolation layers 110, and the second gate separation layer 174d can be disposed so that a lower surface and a portion of a side surface are in contact with the device isolation layer 110 and at the same time have a protruding shape on the device isolation layer 110. In one implementation, the shape of the second gate separation layer 174d can not correspond to (e.g., can be independent of) the shape of the active region 105. For example, the width of the upper portion and the width of the lower portion of the second gate separation layer 174d can be substantially the same, or the width of the lower portion can be narrower.

[0058] The second gate separation layer 174d can have a shape that extends together with the active region 105 in the X direction to the outside of the gate structure 160. The height H7 of the second gate separation layer 174d under the lower portion of the first gate separation layer 172 (e.g., between the first gate separation layer 172 and the substrate 101 in the Z direction or third direction) can be the same as or different from the height H8 outside the gate structure 160. If the height H8 outside the gate structure 160 is smaller than the height H7 of the lower portion of the first gate separation layer 172, growth of the source / drain region 150 can be easier. In one implementation, similar to the semiconductor device 100 of FIG. 1 the second gate separation layer 174d can not be disposed outside the gate structure 160.

[0059] FIG. 8 A cross-sectional view of a semiconductor device according to an example embodiment is shown. FIG. 8 A region corresponding to the cross-section along the line I-I' of FIG. 2A is shown.

[0060] Referring to FIG. 8In the semiconductor device 100f, the gate separation portion 170e can have a shape in which the first gate separation layer 172e extends into the dummy active region 105D, and the second gate separation layer 174e can have a shape that contacts the first gate separation layer 172e on a side surface of the dummy active region 105D.

[0061] The first gate separation layer 172e can have a recessed form, for example, in a recess in the dummy active region 105D, and a depth D2 of the recess can be selected so that a lower end of the first gate separation layer 172e is located at a height level lower than that of an upper surface of the active region 105 and at a height level higher than that of an upper surface of the device isolation layer 110. For example, in the Z direction, a distance from the substrate 101 to a lower surface of the first gate separation layer 172e can be greater than a distance from the substrate 101 to the upper surface of the device isolation layer 110 and can be less than a distance from the substrate 101 to the upper surface of the active region 105. The second gate separation layer 174e can be formed from or of a portion of the gate dielectric layer 162 and can be made of the same material as the gate dielectric layer 162 or can further include impurities in the material of the gate dielectric layer 162. In one embodiment, the second gate separation layer 174e can also include a layer formed by oxidizing or nitriding the dummy active region 105D. In one embodiment, the dummy active region 105D can also include impurities in an upper portion thereof. Due to the presence of the impurities, the dummy active region 105D can have substantially insulating properties.

[0062] According to the gate separation portion 170e of the present embodiment, a process for forming the second gate separation layer 174e can be simplified, and thus a manufacturing process can be relatively easily performed. For example, even if a size of a structure of the semiconductor device 100f including the gate structure 160 is reduced, the second gate separation layer 174e can be easily formed.

[0063] FIG. 9A and FIG. 9B A plan view and cross-sectional views of a semiconductor device according to an example embodiment are shown. FIG. 9B A plan view and cross-sectional views of a semiconductor device according to an example embodiment are shown. FIG. 9A A cross-section of the semiconductor device of

[0064] Referring to FIG. 9A and FIG. 9B , the semiconductor device 100g can include a first region R1 in which the gate structure 160A includes a gate electrode 165 having a first length L1 in the X direction and a second region R2 in which the gate structure 160B includes a gate electrode 165 having a second length L2 in the X direction. The second length L2 can be greater than the first length L1. In the first region R1, as in theFIG. 1 As in the semiconductor device 100, the gate separation portion 170 can include the first gate separation layer 172 and the second gate separation layer 174. In the second region R2, unlike the first region R1, the gate separation portion 170f can be formed of a single layer, can isolate the first gate electrode 165A and the second gate electrode 165B, and can extend from an upper portion or a surface thereof in the Z direction at least to an upper surface of the device isolation layer 110.

[0065] As described above, in a part of the semiconductor device 100g, the gate structure 160A can be isolated by the gate separation portion 170 having a plurality of layers stacked vertically, while in other regions of the semiconductor device 100g, the gate structure 160A can be isolated by the gate separation portion 170f having a single layer. In one embodiment, the first region R1 and the second region R2 can be divided according to the length of the gate structure 160A and 160B. In one embodiment, the first region R1 and the second region R2 can be divided according to the interval distance between the first gate electrode 165A and the second gate electrode 165B, and when the interval distance is large, the gate separation portion 170f having a single layer can be used. Further, the first region R1 and the second region R2 can be selected in consideration of the size and integration of elements in the semiconductor device 100g. For example, a structure and a process suitable for each region can be selectively applied to the semiconductor device 100g, so that a manufacturing process can be efficiently performed while ensuring reliability.

[0066] FIG. 10A to FIG. 10L Views of each stage in a method of manufacturing a semiconductor device according to a process sequence according to example embodiments are shown. In FIG. 10A to FIG. 10L example embodiments of a manufacturing method for manufacturing a semiconductor device FIG. 1 to FIG. 3 will be described.

[0067] Referring to FIG. 10A , the substrate 101 can be patterned to form a trench region TI defining the active region 105.

[0068] First, a pad oxide pattern 142 and a first mask pattern 144 can be formed on the substrate 101. In one embodiment, the pad oxide pattern 142 can be a layer for protecting an upper surface of the active region 105. In one embodiment, the pad oxide pattern 142 can be omitted. The first mask pattern 144 can be a mask layer for patterning the substrate 101, and can include silicon nitride, a carbon-containing material, or the like. The first mask pattern 144 can be formed of a multi-layer structure.

[0069] The substrate 101 can be anisotropically etched using the pad oxide pattern 142 and the first mask pattern 144 to form the trench region TI. The trench region TI can have a high aspect ratio, and the width thereof can be narrowed toward the lower portion, and thus the active region 105 can have a shape that is narrowed toward the upper portion.

[0070] Referring to FIG. 10B The device isolation layer 110 that fills the trench region TI can be formed.

[0071] After the trench region TI is filled with the insulating material, a process of planarizing the trench region TI along the upper surface of the active region 105 can be performed. During the planarization process, at least a portion of the pad oxide pattern 142 and the first mask pattern 144 can be removed. In one embodiment, the pad oxide pattern 142 can remain on the upper surface of the active region 105 until the process steps described with reference to FIG. 10D Referring to

[0072] A portion of the active region 105 can be removed to form the dummy active region 105D between the active regions 105. FIG. 10C

[0073] First, a second mask pattern 146 that exposes the active region 105 to be the dummy active region 105D can be formed on the device isolation layer 110. The second mask pattern 146 can be a mask layer for removing a portion of the exposed active region 105, and can include a material having etching selectivity with respect to the material of the device isolation layer 110 and the active region 105. The second mask pattern 146 can be formed as a multilayer structure.

[0074] Next, the dummy active region 105D can be formed by removing the exposed active region 105 from the upper surface to a predetermined depth. The active region 105 to be recessed can be selectively removed with respect to the device isolation layer 110 by wet etching or the like, and the recess depth can be controlled by adjusting the etching time or the like, and various changes can be made to the recess depth in an example embodiment.

[0075] The semiconductor device 100e described with reference to FIG. 7A and FIG. 7B may be formed by removing or not forming a portion of the active region 105, removing the device isolation layer 110 from the upper portion to a predetermined depth to form the second gate separation layer 174d, and then performing subsequent steps.

[0076] Referring to FIG. 10D The second gate separation layer 174 can be formed on the dummy active region 105D, and the active region 105 and the second gate separation layer 174 can be formed to protrude onto the device isolation layer 110.​

[0077] First, a material for forming the second gate separation layer 174 can be filled in the dummy active region 105D (which has been recessed in the device isolation layer 110) as shown to form the second gate separation layer 174. After forming the second gate separation layer 174, the second mask pattern 146 can be removed, and a planarization process can be further performed if necessary. FIG. 10C

[0078] Next, the device isolation layer 110 can be partially removed from the upper portion to perform a process of protruding the active region 105 and the second gate separation layer 174 onto or from the device isolation layer 110. This process can be performed by, for example, a wet etching process, and can be performed in a state in which the pad oxide pattern 142 or a separate mask layer is formed on the active region 105 to protect the active region 105. For example, the active region 105 and the second gate separation layer 174 can be protruded to a predetermined height from the upper portion of the device isolation layer 110, and in an example embodiment, the protrusion height can be variously changed. The pad oxide pattern 142 or the separate mask layer can also be removed together during the etching process. FIG. 10A

[0079] Referring to FIG. 10E , a first sacrificial layer 182 and a second sacrificial layer 184 can be formed on the active region 105, the second gate separation layer 174, and the device isolation layer 110.

[0080] The first sacrificial layer 182 and the second sacrificial layer 184 can be patterned to have a linear shape extending in the Y direction intersecting the active region 105. The first sacrificial layer 182 and the second sacrificial layer 184 can be patterned using a third mask pattern layer 186. The first sacrificial layer 182 and the second sacrificial layer 184 can be sacrificial gate structures formed in regions in which the gate dielectric layer 162 and the gate electrode 165 are disposed by a subsequent process as shown. FIG. 3

[0081] In one embodiment, the first sacrificial layer 182 and the second sacrificial layer 184 can be an insulating layer and a conductive layer, respectively. In one embodiment, the first sacrificial layer 182 and the second sacrificial layer 184 can be formed of a single layer. For example, the first sacrificial layer 182 can include silicon oxide, and the second sacrificial layer 184 can include polysilicon. The third mask pattern layer 186 can include silicon oxide and / or silicon nitride.

[0082] Referring to FIG. 10F , at least a portion of the second gate separation layer 174 can be removed from both sides or the outside of the first sacrificial layer 182 and the second sacrificial layer 184.

[0083] ​​​The second gate separation layer 174 can be selectively removed with respect to the active regions 105, the dummy active regions 105D, and the device isolation layer 110, so that the upper surfaces of the dummy active regions 105D can be exposed. The second gate separation layer 174 can remain only at or under the lower portions of the first and second sacrificial layers 182 and 184. In one embodiment, the second gate separation layer 174 can be partially removed from its upper surface, rather than entirely, to a predetermined depth. As described above, when the second gate separation layer 174 is removed on both sides of the first and second sacrificial layers 182 and 184, the growth of the source / drain regions 150 is not interfered with by the second gate separation layer 174 when the source / drain regions 150 are formed in a subsequent process.

[0084] The semiconductor device 100d described with reference to FIG. 6A and FIG. 6B may be prepared by removing only a portion of the second gate separation layer 174 in the present step or by omitting the present step.

[0085] With reference to FIG. 10G , the gate spacer layer 166 can be formed on the active regions 105, the device isolation layer 110, and the third mask pattern layer 186, and the exposed active regions 105 can be recessed, so that the source / drain regions 150 can be formed.

[0086] First, the gate spacer layer 166 having a uniform thickness can be formed along the upper and / or side surfaces of the active regions 105, the device isolation layer 110, the first and second sacrificial layers 182 and 184, and the third mask pattern layer 186. The gate spacer layer 166 can be made of a material having a low dielectric constant, and can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0087] Next, the gate spacer layer 166 can be removed from the upper surface of the active region 105 to expose the upper surface of the active region 105, and then the exposed active region 105 can be recessed from the upper surface to a predetermined depth. The recessing process can be performed, for example, by sequentially applying a dry etching process and a wet etching process. For example, in this step, the height of the active region 105 outside the first and second sacrificial layers 182 and 184 can be lower than the height of the lower portion of the first and second sacrificial layers 182 and 184. Alternatively, after the recessing process, a process of curing the surface of the recessed active region 105 can be performed by a separate process. Alternatively, a process of implanting impurities into the active region 105 can be performed before or after the recessing process. During these processes, the gate spacer layer 166 can have a shape as shown, which is partially removed and remains only on the side surfaces of the first and second sacrificial layers 182 and 184 and the third mask pattern layer 186. In one embodiment, the material used to form the gate spacer layer 166 can also remain in the form of a spacer on the sidewall of the active region 105. In one embodiment, during the process, the device isolation layer 110 can be partially removed outside the first and second sacrificial layers 182 and 184, and its height can be relatively reduced.

[0088] The source / drain region 150 can be formed using, for example, a selective epitaxial growth (SEG) process. The source / drain region 150 can be, for example, a silicon (Si) layer or a silicon germanium (SiGe) layer. During growth of the source / drain region 150, impurities such as phosphorus (P), boron (B), etc. can be doped in situ after growth or separately implanted. In one embodiment, depending on the material used to form the source / drain region 150, the source / drain region 150 can grow in a crystallographically stable surface during growth to have a hexagonal, pentagonal, or similar shape.

[0089] Referring to FIG. 10H The interlayer insulating layer 190 can be formed on the source / drain region 150, and the first and second sacrificial layers 182 and 184, i.e., the sacrificial gate structure, can be removed.

[0090] First, the interlayer insulating layer 190 can be formed by depositing an insulating material to cover the source / drain region 150, the third mask pattern layer 186, and the gate spacer layer 166, and then exposing the upper surface of the second sacrificial layer 182 by a planarization process. In the planarization process, the third mask pattern layer 186 can be removed. The interlayer insulating layer 190 can include, for example, at least one of an oxide, a nitride, and a nitride oxide, and can include a material having a low dielectric constant.

[0091] The first and second sacrificial layers 182 and 184 can be selectively removed with respect to the lower active region 105, the device isolation layer 110, and the second gate separation layer 174, and a gate region GR exposing the active region 105, the device isolation layer 110, and the second gate separation layer 174 can be formed. The process of removing the first and second sacrificial layers 182 and 184 can be performed using at least one of a dry etching process and a wet etching process.

[0092] Referring to FIG. 10I A gate dielectric layer 162 and a gate electrode 165 can be formed in the gate region GR, thereby finally forming a gate structure 160.

[0093] The gate dielectric layer 162 can be formed substantially conformally along sidewalls and a lower surface of the gate region GR. The gate dielectric layer 162 can include an oxide, a nitride, and a high-k material. The gate electrode 165 can fill a space inside the gate dielectric layer 162. The gate electrode 165 can include a metal or a semiconductor material.

[0094] After forming the gate dielectric layer 162 and the gate electrode 165, a planarization process such as a chemical mechanical polishing (CMP) process can be used to remove a material remaining on the interlayer insulating layer 190.

[0095] Referring to FIG. 10J and FIG. 10K A portion of the gate dielectric layer 162 and the gate electrode 165 can be removed to form an opening OP. FIG. 10K A cross-section taken along a cut line V-V' in FIG. 10J is shown.

[0096] The opening OP can at least divide the gate electrode 165 of the gate structure 160 into a first gate electrode 165A and a second gate electrode 165B in the Y direction. The opening OP can be formed by removing not only a portion of the gate electrode 165 but also a portion of the gate dielectric layer 162. In an embodiment, the opening OP can also be formed by removing a gate spacer layer 166 adjacent thereto in the Y direction.

[0097] As shown in FIG. 10K , an upper surface of the second gate separation layer 174 can be exposed through a lower portion of the opening OP. In this step, the opening OP can not penetrate the entire thickness of the gate electrode 165, and can be formed by removing only the gate electrode 165 to the upper surface of the second gate separation layer 174, and the process can be relatively easily performed. In addition, a lower portion of the gate electrode 165 can be isolated by the second gate separation layer 174, a margin of a size, e.g., a width in the Y direction, of the opening OP can be reduced, and the process can be more easily performed.

[0098] Referring to FIG. 10LThe first gate separation layer 172 can be formed by filling the opening OP with an insulating material, and the contact plug 195 can be formed. The first gate separation layer 172 can be formed by filling the opening OP with an insulating material such as silicon nitride.

[0099] Next, the interlayer insulating layer 190 can be patterned to form a contact hole, and a conductive material can be embedded in the contact hole to form the contact plug 195. The contact hole can be formed by removing the interlayer insulating layer 190 on both sides of the gate structure 160 using a separate mask layer such as a photoresist pattern. The lower surface of the contact hole can have a curvature along the upper surface of the source / drain region 150. When the interlayer insulating layer 190 is removed, the upper portion of the source / drain region 150 can be partially recessed. The contact plug 195 can be formed by depositing a conductive material in the contact hole to electrically connect the source / drain region 150. In an embodiment, various changes can be made to the shape and arrangement of the contact plug 195.

[0100] FIG. 11A to FIG. 11G Views showing stages in a method of manufacturing a semiconductor device according to a process sequence according to example embodiments are shown. In FIG. 11A to FIG. 11G another example embodiment for a manufacturing method of a semiconductor device according to FIG. 1 to FIG. 3 example embodiments will be described. Hereinafter, descriptions that are repetitive of those described above with reference to FIG. 10A to FIG. 10L example embodiments can be omitted.

[0101] With reference to FIG. 11A , the active region 105 and the device isolation layer 110 can be formed by patterning the substrate 101, and the active region 105 can protrude from the device isolation layer 110.

[0102] First, the substrate 101 can be patterned to form a trench region T1 defining the active region 105, and the device isolation layer 110 can be formed embedded in the trench region T1, as described with reference to FIG. 10A and FIG. 10B .

[0103] Next, a process of protruding the active region 105 from the device isolation layer 110 can be performed by partially removing the device isolation layer 110. However, unlike the example embodiments described above with reference to FIG. 10A to FIG. 10L , in this step, the first gate separation layer 174 can not be formed.

[0104] With reference to FIG. 11B , the first and second sacrificial layers 182 and 184 can be formed on the active region 105 and the device isolation layer 110.

[0105] As described above with reference to FIG. 10EAs described, the first and second sacrificial layers 182 and 184 can be patterned and formed to have a linear shape extending in the Y direction intersecting the active regions 105. The first and second sacrificial layers 182 and 184 can be patterned using the third mask pattern layer 186.

[0106] Referring to FIG. 11C The dummy active regions 105D can be formed by removing a portion of the exposed upper regions of the active regions 105 from both sides or outside of the first and second sacrificial layers 182 and 184.

[0107] To form the dummy active regions 105D, at least one of the exposed upper regions of the active regions 105 can be selectively removed with respect to the device isolation layer 110. In an example embodiment, various changes can be made to the depth of the active regions 105 removed by the above process. For example, the height of the dummy active regions 105D can be lower than the height of the active regions 105 on both sides of the first and second sacrificial layers 182 and 184. The dummy active regions 105D under (e.g., below) the first and second sacrificial layers 182 and 184 can not be removed, and the height of the dummy active regions 105D can be substantially the same as the height of the active regions 105 below the first and second sacrificial layers 182 and 184.

[0108] Referring to FIG. 11D and FIG. 11E The gate spacer layer 166, the source / drain regions 150, the interlayer insulating layer 190, and the gate structure 160 can be formed, and the opening OP' can be formed. FIG. 11E A cross section along a cutting line VI-VI' of FIG. 11D is shown.

[0109] First, the gate spacer layer 166, the source / drain regions 150, and the interlayer insulating layer 190 can be formed, and the first and second sacrificial layers 182 and 184 can be removed, and then the gate structure 160 can be formed, similar to those described above with reference to 10G to FIG. 10I

[0110] Next, a portion of the gate dielectric layer 162, the gate electrode 165, and the dummy active regions 105D can be removed to form the opening OP', similar to those described above with reference to FIG. 10J and FIG. 10K For example, in the present example embodiment, unlike the example embodiments described above with reference to FIG. 10J and FIG. 10K the opening OP' can be formed by removing not only a portion of the gate electrode 165 but also a portion of the dummy active regions 105D, and the opening OP' can be formed to have a stepped shape with a narrower step. The depth of the dummy active regions 105D removed in the present step can be the same as the depth of the dummy active regions 105D removed in the example embodiment described above with reference to​FIG. 11C The depth of the active region 105 on both sides of the first and second sacrificial layers 182 and 184 removed in the above steps is the same or different.

[0111] Referring to FIG. 11F and FIG. 11G The gate separation portion 170 can be formed by filling the opening OP' with an insulating material to form the first and second gate separation layers 172 and 174 of the gate separation portion 170. FIG. 11G A cross-section taken along the cross-sectional line VII-VII' of FIG. 10F is shown.

[0112] The first and second gate separation layers 172 and 174 can be formed by filling the opening OP' with an insulating material (e.g., silicon nitride, etc.). In one embodiment, the first and second gate separation layers 172 and 174 can be formed by one deposition step, and the first and second gate separation layers 172 and 174 can be formed of the same material and can have a coupled, connected, or integral shape.

[0113] Thereafter, the contact plug 195 can be further formed as described above with reference to FIG. 10L .

[0114] FIG. 12A to FIG. 12C Views showing stages in a method of manufacturing a semiconductor device according to a process sequence according to example embodiments are shown. In FIG. 12A to FIG. 12C , example embodiments of the method of manufacturing a semiconductor device in FIG. 5A and FIG. 5B will be described.

[0115] Referring to FIG. 12A , the active region 105, the device isolation layer 110, the dummy active region 105D, the second gate separation layer 174, the first and second sacrificial layers 182 and 184, the gate spacer layer 166, the source / drain region 150, and the interlayer insulating layer 190 can be formed, and then the first gate separation layer 172 can be formed.

[0116] First, the active region 105, the device isolation layer 110, the dummy active region 105D, the second gate separation layer 174, the gate spacer layer 166, and the source / drain region 150 can be formed as described with reference to FIG. 10A to FIG. 10G .

[0117] Next, the interlayer insulating layer 190 can be formed on the source / drain region 150, a portion of the first and second sacrificial layers 182 and 184 can be removed to form an opening, and the second gate separation layer 174 can be formed by filling the opening to form the gate separation portion 170. In this embodiment, the first gate separation layer 172 can be formed by filling the opening OP' with an insulating material to form the first and second gate separation layers 172 and 174 of the gate separation portion 170.FIG. 10A to 10L The example embodiments described can remove a portion of the first and second sacrificial layers 182 and 184 instead of a portion of the gate dielectric layer 162 and the gate electrode 165 to form the second gate separation layer 174.

[0118] Referring to FIG. 12B The first and second sacrificial layers 182 and 184, i.e., the sacrificial gate structure, can then be removed.

[0119] The first and second sacrificial layers 182 and 184 can be selectively removed with respect to the lower active region 105, the device isolation layer 110, and the gate separation portion 170, and a gate region GR' that exposes the active region 105, the device isolation layer 110, and the gate separation portion 170 can be formed.

[0120] Referring to FIG. 12C The gate dielectric layer 162P and the gate electrode 165 can be formed in the gate region GR', thereby finally forming the gate structure 160.

[0121] The gate dielectric layer 162P and the gate electrode 165 can be formed in a state in which the gate separation portion 170 has been formed, and the gate dielectric layer 162P can also be formed on a side surface (e.g., a surface facing the Y direction) of the first gate separation layer 172.

[0122] Thereafter, the contact plug 195 can be further formed, as described above with reference to FIG. 10L

[0123] FIG. 13 A circuit diagram of an SRAM cell including a semiconductor device according to an example embodiment is shown.

[0124] Referring to FIG. 13 One cell in the SRAM device can include first and second drive transistors TN1 and TN2, first and second load transistors TP1 and TP2, and first and second access transistors TN3 and TN4. In this case, the sources of the first and second drive transistors TN1 and TN2 can be connected to a ground voltage line Vss, and the sources of the first and second load transistors TP1 and TP2 can be connected to a power supply voltage line Vdd.

[0125] ​The first drive transistor TN1 formed of an NMOS transistor and the second load transistor TP1 formed of a PMOS transistor can constitute a first inverter, and the second drive transistor TN2 formed of an NMOS transistor and the second load transistor TP2 formed of a PMOS transistor can constitute a second inverter. At least a part of the first drive transistor TN1 and the second drive transistor TN2, the first load transistor TP1 and the second load transistor TP2, and the first access transistor TN3 and the second access transistor TN4 can include a semiconductor device according to various example embodiments described above with reference to FIG. 1 to FIG. 9B A semiconductor device according to various example embodiments is described.

[0126] The output terminal of the first inverter and the output terminal of the second inverter can be connected to the source of the first access transistor TN3 and the source of the second access transistor TN4. In addition, the first inverter and the second inverter can be connected to each other such that the input terminal and the output terminal cross each other to constitute one latch circuit. The drain of the first access transistor TN3 and the drain of the second access transistor TN4 can be connected to the first bit line BL and the second bit line / BL, respectively.

[0127] FIG. 14 A diagram of an electronic device including a semiconductor device according to an example embodiment is shown. Referring to FIG. 14 , an electronic device 1000 according to an example embodiment can include a communication unit 1010, an input unit 1020, an output unit 1030, a memory 1040, and a processor 1050.

[0128] The communication unit 1010 can include a wired / wireless communication module such as a wireless Internet module, a near field communication module, a global positioning system (GPS) module, a mobile communication module, etc. The wired / wireless communication module included in the communication unit 1010 can transmit and receive data according to various communication standards through connection to an external communication network.

[0129] The input unit 1020 can be provided as a module to be provided to a user to control the operation of the electronic device 1000, and can include a mechanical switch, a touch screen, a voice recognition module, etc. In addition, the input unit 1020 can further include a finger mouse device or a mouse operated using a trackball, a laser pointer, etc. The input unit 1020 can further include various sensor modules through which a user can input data.

[0130] The output unit 1030 can output information processed in the electronic device 1000 in the form of audio or video, and the memory 1040 can store programs, data, etc. to process and control the processor 1050. The processor 1050 can store data and output data by transmitting a command to the memory 1040 according to a desired operation.

[0131] The memory 1040 can communicate with the processor 1050 through an interface embedded in the electronic device 1000 or a separate interface. In the case where the memory 1040 communicates with the processor 1050 through a separate interface, the processor 1050 can store data in or output data from the memory 1040 through various interface standards (e.g., SD, SDHC, SDXC, MICRO SD, USB, etc.).

[0132] The processor 1050 can control operations of various units included in the electronic device 1000. The processor 1050 can perform control and processing operations related to a voice call, a video call, data communication, etc., or can perform control and processing operations to play and manage multimedia. In addition, the processor 1050 can process input transmitted by a user through the input unit 1020 and can output a result through the output unit 1030. In addition, the processor 1050 can store or output data required to control operations of the electronic device 1000 in or from the memory 1040, as described above. At least one of the processor 1050 and the memory 1040 can include a semiconductor device according to various example embodiments, as described above.

[0133] FIG. 15 A schematic diagram of a system including a semiconductor device according to an example embodiment is illustrated.

[0134] Referring to FIG. 15 The system 2000 can include a controller 2100, an input / output device 2200, a memory 2300, and an interface 2400. The system 2000 can be a system such as a mobile system that transmits or receives information. The mobile system can be a PDA, a portable computer, a netbook, a wireless phone, a mobile phone, a digital music player, or a memory card.

[0135] The controller 2100 can execute a program and control the system 2000. The controller 2100 can be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device as described above.

[0136] The input / output device 2200 can be used to input or output data of the system 2000. The system 2000 can connect to an external device (e.g., a personal computer or a network) using the input / output device 2200 to exchange data with the external device. The input / output device 2200 can be, for example, a keypad, a keyboard, or a display.

[0137] The memory 2300 can store a code and / or data for operation of the controller 2100, and / or can store processed data in the controller 2100.

[0138] The interface 2400 can be a data transmission path between the system 2000 and other external devices. The controller 2100, the input / output device 2200, the memory 2300, and the interface 2400 can communicate with each other via the bus 2500.

[0139] At least one of the controller 2100 or the memory 2300 can include a semiconductor device according to various example embodiments described above with reference to FIG. 1 to FIG. 9B

[0140] By summarizing and reviewing, in order to overcome the limitations of the element characteristics of the planar MOSFET, efforts have been made to develop a semiconductor device including a FinFET having a three-dimensional structure of a channel.

[0141] One or more embodiments can provide a semiconductor device having improved reliability.

[0142] As described above, by forming a gate separation layer for separating a gate electrode into a plurality of layers stacked in a vertical direction, a semiconductor device having improved reliability can be provided.

[0143] Example embodiments have been disclosed herein, although the use of particular nomenclature or terminology in the description above is merely for the purpose of providing a clear and thorough description of the present application and is not intended to limit the present application. In some instances, features, attributes, and / or benefits of the compositions, articles, and / or methods described in connection with a particular embodiment can be used in combination with features, attributes, and / or benefits of another embodiment, even though not explicitly described or shown in the same combination. In addition, it is contemplated that structures, features, attributes, and / or benefits from one embodiment can be incorporated into another embodiment, even though not explicitly described or shown in the same embodiment. Thus, it is intended that the present application embrace all such alterations, modifications, and variations as come within the spirit and scope of the present application, which is defined by the appended claims.​

Claims

1. A semiconductor device, the semiconductor device comprising: Multiple active regions, the multiple active regions extending on the substrate along a first direction; A device isolation layer is located between the plurality of active regions, such that the upper part of the plurality of active regions protrudes from the device isolation layer; A first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode respectively extending on the substrate in a second direction intersecting the first direction and intersecting the plurality of active regions, the first gate electrode being spaced apart from the second gate electrode in the second direction; A first gate separation layer is located between the first gate electrode and the second gate electrode; A second gate separation layer is located below the first gate separation layer and between the first gate electrode and the second gate electrode, and the second gate separation layer extends upward into the device isolation layer at a third direction intersecting the first direction and the second direction; as well as A dummy active region is provided, which extends along the first direction and is located below the second gate separator layer. in: The second gate separator layer is located between the first gate separator layer and the dummy active region in the third direction, and The curved portion, depending on the width difference, is located between the first gate separator layer and the second gate separator layer.

2. The semiconductor device of claim 1, wherein, The height of the upper surface of the second gate separator layer relative to the substrate in the third direction is higher than the height of the upper surface of the device isolation layer relative to the substrate in the third direction.

3. The semiconductor device according to claim 1, wherein, The height of the upper surface of the second gate separator layer relative to the substrate in the third direction is substantially the same as the height of the upper surface of the plurality of active regions below the first gate electrode and the second gate electrode relative to the substrate in the third direction.

4. The semiconductor device according to claim 1, wherein, The width of the second gate separator layer in the second direction is narrower than the width of the first gate separator layer in the second direction.

5. The semiconductor device according to claim 1, wherein, The height of the dummy active region relative to the substrate in the third direction is lower than the height of the plurality of active regions relative to the substrate in the third direction.

6. The semiconductor device according to claim 1, wherein, The lower surface of the second gate separator layer is in contact with the device isolation layer.

7. The semiconductor device according to claim 1, wherein, Both the first gate separator layer and the second gate separator layer independently include insulating material.

8. The semiconductor device of claim 1, further comprising a gate dielectric layer located between the plurality of active regions and the first gate electrode and the second gate electrode.

9. The semiconductor device according to claim 8, wherein, The gate dielectric layer covers: The lower surface of the first gate electrode and the lower surface of the second gate electrode, and The side surface of the portion of the second gate separator layer located outside the device isolation layer.

10. The semiconductor device according to claim 9, wherein, The gate dielectric layer extends from the side surface of the second gate separator layer, thereby also covering the side surface of the first gate separator layer.

11. The semiconductor device according to claim 1, wherein, The portion of the second gate separator layer located between the first gate electrode and the second gate electrode has a first height relative to the substrate in the third direction, and The portion of the second gate separator layer located on both sides of the first gate electrode and the second gate electrode in the first direction has a second height relative to the substrate in the third direction, the second height being lower than the first height.

12. The semiconductor device according to claim 1, wherein, The second gate separator layer is located between the first gate electrode and the second gate electrode, and does not extend in the first direction on either side of the first gate electrode and the second gate electrode.

13. The semiconductor device according to claim 1, wherein, The width of the first gate separator layer in the second direction is greater than the width of the active region in the second direction and the width of the dummy active region in the second direction.

14. The semiconductor device according to claim 1, wherein, The second gate separator layer, together with the dummy active region, has a shape substantially the same as the active region among the plurality of active regions.

15. A semiconductor device, the semiconductor device comprising: Multiple active regions, the multiple active regions extending on the substrate along a first direction; A first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode extending on the substrate in a second direction intersecting the first direction and intersecting the plurality of active regions, the first gate electrode being spaced apart from the second gate electrode in the second direction; A gate separation portion, wherein the gate separation portion is located between the first gate electrode and the second gate electrode; as well as A dummy active region is provided, which is located below the gate separator portion. in: The gate separation portion includes: A first gate separator layer, the first gate separator layer being located above the gate separator portion and extending into the recess of the dummy active region, and The second gate separator layer is located on the upper sidewall of the dummy active region and the lower sidewall of the first gate separator layer.

16. The semiconductor device according to claim 15, wherein, The gate separation portion extends along the first direction between the first gate electrode and the second gate electrode.

17. A semiconductor device, the semiconductor device comprising: Multiple active regions, wherein the multiple active regions extend in one direction; A virtual active region is provided, and the virtual active region is parallel to the plurality of active regions; A first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode intersect with the plurality of active regions and the dummy active regions, and the first gate electrode is spaced apart from the second gate electrode in a straight line; A first gate separator layer extends downward from the upper surface of the first gate electrode and the upper surface of the second gate electrode, and is located between the first gate electrode and the second gate electrode; and A second gate separator layer is located below the first gate separator layer, and the second gate separator layer is in contact with the first gate separator layer and the dummy active region. in: The second gate separator layer is located on the dummy active region. The second gate separator layer, together with the dummy active region, has a shape substantially the same as the active region among the plurality of active regions, and The lower surface of the first gate separator is at a height higher than the height of the lowest surface of each of the first gate electrode and the second gate electrode.

18. The semiconductor device according to claim 17, wherein, The upper surface of the first gate separator layer is substantially coplanar with the upper surface of the first gate electrode and the upper surface of the second gate electrode.

19. The semiconductor device of claim 17, further comprising a device isolation layer located between the plurality of active regions, such that the upper portions of the plurality of active regions protrude from the upper surface of the device isolation layer. in, The lower surface of the second gate separator layer is at a lower height than the upper surface of the device isolation layer.

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