Gate polysilicon feeding structure for trench devices

Abstract

The present invention relates to a gate polysilicon feed structure for a trench device. In a general aspect, a device may include a trench disposed in a semiconductor region of a substrate. The trench may be lined with a gate dielectric and include an electrode disposed in the trench. The device may include a polysilicon layer disposed above the trench. The trench may have an end portion disposed below an opening in the polysilicon layer. The end portion of the trench may be disposed between a first side of the opening and a second side of the opening.

Description

[0001] Related Applications

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 16 / 589,479, filed on October 1, 2019, which claims priority to and the benefit of U.S. Provisional Application No. 62 / 834,642, filed on April 16, 2019, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention generally relates to gate polysilicon feed structures for trench devices. Background Art

[0004] Characteristics of semiconductor devices such as metal oxide semiconductor field effect transistor (MOSFET) devices may affect device performance in an unfavorable manner. Some MOSFET devices may have at least one gate electrode disposed within a dielectric filled trench that serves as a gate dielectric. MOSFET devices having a gate dielectric layer that is thinned in some areas, for example due to manufacturing processes and / or device layout, may be problematic for at least some device applications. Therefore, systems, methods, and apparatus are needed to address the deficiencies of the prior art and to provide other novel and innovative features. Summary of the invention

[0005] In a general aspect, a device may include a trench disposed in a semiconductor region of a substrate. The trench may be lined with a gate dielectric and include an electrode disposed in the trench. The device may include a polysilicon layer disposed above the trench. The trench may have an end portion disposed below an opening in the polysilicon layer. The end portion of the trench may be disposed between a first side of the opening and a second side of the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and Figure 1B is a diagram of a transistor device according to an embodiment described herein.

[0007] Figures 2 to 5 A transistor device is shown, which is Figure 1A and Figure 1B A variation of the transistor device shown.

[0008] Figure 6 is a diagram illustrating a method of making a transistor device described herein.

[0009] 7A to 9D Shows Figure 6 Parts of the method shown.

[0010] Fig. 10A , Fig. 10B , Fig. 10C and Fig.11 Shows Figure 1A and Figure 1B Additional transistor device variations of the transistor devices shown.

[0011] FIG. 12A to FIG. 14D Variations of the transistor devices described herein are shown.

[0012] Fig.15 is a diagram illustrating a cross-sectional view along a trench of a vertical MOSFET structure that can be implemented in conjunction with embodiments described herein. DETAILED DESCRIPTION

[0013] A trench transistor device (e.g., a metal oxide semiconductor field effect transistor (MOSFET) device, a low voltage (LV) MOSFET device) may have a gate electrode disposed within a trench lined with a gate dielectric layer (e.g., a gate oxide layer, a high-K dielectric layer). The layout of the transistor device described herein addresses the issue that portions of the gate dielectric layer within the trench may be weaker (e.g., thinner) in certain areas. For example, the transistor device layout described herein addresses the potential issue that the gate dielectric layer may be particularly weak in the top portion of the trench and / or the bottom portion of the trench. Specifically, the gate polysilicon feed layout of the trench transistor device described herein may be configured to address the potential issue of weak points in the gate dielectric layer.

[0014] As a specific example, the trench transistor devices described herein avoid thinning of the gate dielectric layer that may occur due to the manufacturing process and / or device layout, which may be problematic for at least some device applications (e.g., battery applications). Thinning of the gate dielectric layer on the top portion and / or bottom portion of the trench may cause gate oxide integrity (GOI) issues. Transistor devices with a striped trench pattern layout may be prone to gate dielectric layer thinning at the end portion (e.g., tip) of the trench (e.g., the bottom of the trench and / or the facet (on both sides of the trench)). A wider trench pattern (e.g., a trapezoidal trench pattern) may alleviate thinning at the end portion of the trench. However, these wider trench pattern designs may cause gate thinning to occur at other locations within the trench, such as along the top corners of the trench (e.g., along the top sidewalls of the trench). The gate polysilicon feed layout of the trench transistor device described herein can be configured to address gate thinning issues at the end portion of the trench and / or other locations within the trench (including the top corners of the trench).

[0015] Figure 1A 1 shows a plan view of a layout of a portion of a transistor device 100 according to at least one embodiment. Figure 1A In the drawings (and in many of the drawings), some dielectric layers are not shown to simplify the plan view and highlight the components.

[0016] like Figure 1A As shown, the transistor device 100 includes a trench 110A (from a plurality of parallel trenches 110 or a trench group 110) wherein an electrode 112A (e.g., a gate electrode) is lined with a trench dielectric 114A (e.g., a gate dielectric, a gate oxide). An end portion 111A (e.g., a tip) of the trench 110A terminates within (e.g., below, vertically below) an opening 124 (e.g., an opening region) within a polysilicon layer 120. The polysilicon layer 120 defines a polysilicon ring 122 (e.g., a gate polysilicon ring depicted by dashed lines) around the end portion 111A of the trench 110A. The polysilicon layer 120 is directly coupled (e.g., electrically coupled) to the electrode 112A (which may also be made of polysilicon) in the trench 110A. A contact opening 130B is shown, and a metal layer 191 (e.g., a gate layer 192) is shown. Figure 1B The contact opening 130B (e.g., a portion of a metal layer) is coupled (e.g., directly coupled) to the polysilicon layer 120 (via a polysilicon contact (not labeled)) through the contact opening. Thus, the contact opening 130B is in fluid communication with the electrode 112A via the polysilicon ring 122 (or a portion thereof). In some embodiments, the polysilicon ring 122 can be configured to minimize the resistance (e.g., Rg increase) associated with a gate (e.g., gate switching). Although the description is with respect to trench 110A in the trench group 110, the principles described herein can be applied to one or more trenches in the trench 110.

[0017] like Figure 1A As shown, the end portion 111A of the trench 110A terminates between the two sides of the polysilicon ring 122 (or the opening 124 in the polysilicon layer 120). Figure 1A As shown, a first side 122-1 (or first edge) of the polysilicon ring 122 is disposed on a first side of an end portion 111A of the trench 110A, and a second side 122-2 of the polysilicon ring 122 is disposed on a second side of the end portion 111A. In some embodiments, the end portion 111A may be centered between the first side 122-1 and the second side 122-2 of the polysilicon ring 122. The first side 122-1 of the polysilicon ring 122 may be coupled to (e.g., electrically coupled to) an electrode 112A (e.g., a gate electrode).

[0018] like Figure 1A As shown, a first side 122-1 of the polysilicon ring 122 is disposed over (e.g., above) a portion of the trench 110A, while a second side 122-2 is not disposed over any portion of the trench 110A. The remaining sides (not labeled, third side, fourth side) of the polysilicon ring 122 (between sides 122-1 and 122-2) are aligned parallel to the trench 110A.

[0019] Although the polysilicon ring 122 is Figure 1A The polysilicon ring 122 is shown as having a rectangular profile (or a substantially rectangular profile). In some embodiments, the polysilicon ring 122 may have a different shape or profile. For example, in some embodiments, the polysilicon ring 122 may have a square profile, may have a rectangular profile with rounded corners, etc. In some embodiments, the polysilicon ring 122 may have a circular shape, an elliptical shape, etc.

[0020] In some embodiments, the length (longitudinal link) of one or more of the trenches 110 may be different. In such embodiments, one of the trenches 110 may terminate between the first side 122-1 and the second side 122-2 of the polysilicon ring 122 at a different distance (or position) than another of the trenches 110.

[0021] In some embodiments, at least a portion of the trench 110 can be disposed in an active region of the transistor device 100. In some embodiments, at least a portion (e.g., an end portion) of the trench 110 can be disposed in a termination region of the transistor device 100. For example, the polysilicon ring 122 and the end portion 111A of the trench 110A can be disposed in the termination region of the transistor device 100. In some embodiments, at least a portion (e.g., an active portion) of the source region can be disposed between the trench pair 110 (e.g., in a mesa region therebetween).

[0022] In some embodiments, the width of each of the grooves 110 may be about several micrometers (eg, 5 μm, 10 μm, 16 μm, 20 μm). The width may be a dimension perpendicular to the longitudinal length of the groove 110. Figure 1A As shown, the contact opening 130B may have a longitudinal length (from top to bottom of the figure) that is aligned perpendicular to the longitudinal length of the trench set 110 (from left to right of the figure (and orthogonal to the width)).

[0023] Figure 1B yes Figure 1A The transistor device 100 is shown in a side cross-sectional view along line A1. Figure 1B As shown, the end portion 111A of the trench 110A terminates below (within the area projected below) the opening 124 in the polysilicon layer 120. In other words, the end portion 111A of the trench 110A is disposed below a plane aligned with the bottom of the polysilicon ring 122. Thus, the corner 113A of the trench 110A is below (e.g., vertically below) the opening 124 in the polysilicon layer 120. The polysilicon ring 122 is disposed around the end portion 111A of the trench 110A (but disposed on a layer above the end portion). As shown in FIG. Figure 1BAs shown, a first side 122-1 (or a first edge) of the polysilicon ring 122 (or the opening 124 in the polysilicon layer 120) is disposed on a first side of the end portion 111A of the trench 110A, and a second side 122-2 of the polysilicon ring 122 is disposed on a second side of the end portion 111A.

[0024] like Figure 1B As shown, contact opening 130B is coupled to polysilicon layer 120. In this embodiment, polysilicon layer 120 is insulated from substrate 170 by dielectric layer 150 (also referred to as polysilicon insulating dielectric layer). In some embodiments, dielectric layer 150 can be formed using local oxidation of silicon (e.g., can be a LOCOS layer). In some embodiments, dielectric layer 150 can be a relatively thick dielectric to avoid electrostatic discharge (ESD) and / or reliability risks due to contact etching damage during manufacturing.

[0025] In this embodiment, active area 130A (which may be a contact opening region to trench 110) is shown, and metal layer 191 (which may be a portion of the same metal layer over contact opening 130B) is insulated from electrode 112A by dielectric 140. In some embodiments, metal layer 191 may be or may have a metal contact to a source region within a mesa region (not shown) between trenches 110 of an active portion within active area 130A of transistor device 100. A gate dielectric is not explicitly shown in all figures, but in each of the embodiments described herein, a gate dielectric lines the trench.

[0026] Figure 2 A transistor device 200 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 shown. Figure 2 The principles described may be applied to any of the embodiments described herein.

[0027] Figure 2 The transistor device 200 shown includes a trench group 110 having a trapezoidal portion 117 having a trapezoidal pattern. The trapezoidal portion 117 of the trench is disposed within an opening 124 within the polysilicon layer 120. The trapezoidal portion 117 includes transverse trenches 110T (e.g., transverse trench 110T-1 and transverse trench 110T-2) that are coupled between the trenches 110 (e.g., having electrodes electrically coupled to electrodes). For example, transverse trench 110T-1 is disposed and coupled between trenches 110C and 110A. Trench 110C includes an electrode 112C that is electrically coupled to electrode 112A of trench 110A via transverse trench 110T-1.

[0028] In this embodiment, the transverse grooves 110T are aligned perpendicular to (orthogonal to) the longitudinal length of the parallel grooves 110. In order to define a trapezoidal pattern, the transverse grooves 110T are offset along the longitudinal length of the grooves 110. For example, the first transverse groove 110T-1 between the first groove pair 110A, 110C is at a first longitudinal distance or first length along the groove 110. The second transverse groove 110T-2 between the second groove pair (including the groove 110C) is at a second longitudinal distance or length along the groove 110. In other words, the first transverse groove 110T-1 between the first groove pair 110A, 110C is at a first distance B1 from the end of the grooves 110A, 110C. The second transverse groove 110T-2 between the second groove pair (including the groove 110C) is at a second distance B2 from the end of the second groove pair (including the groove 110C). The lateral trenches 110T- 1 and 110T- 2 may be referred to as being concave (eg, set back from the ends of the trench 110 ).

[0029] like Figure 2 As shown, the end segment of each trench in the trench group 110 extends (e.g., away from the active area 130A, toward the contact opening 130B) beyond the transverse trench 110T. In other words, one or more transverse trenches in the transverse trenches 110T may be recessed from the end of one or more trenches in the trenches 110. For example, the end segment of the trench 110A (having a length C1) extends beyond the transverse trench 110T-1, and the end segment of the trench 110C (length not labeled) extends beyond the transverse trench 110T-2. The length of the end segment of the trench 110A extending beyond the transverse trench 110T-1 is different from the length of the end segment of the trench 110C extending beyond the transverse trench 110T-2.

[0030] In some embodiments, transverse trenches 110T may be aligned such that distances B1 and B2 are aligned or the same (or equal). In such embodiments, the end segments of trench set 110 extending beyond transverse trenches 110T will be the same or equal. Transverse trenches 110T-1 and 110T-2 may be referred to as non-recessed (e.g., not set back or aligned from the ends of trench 110).

[0031] In some embodiments, one or more of the transverse grooves 110T may be aligned with one or more ends of one or more of the grooves 110 so as not to include an end segment. In other words, one or more of the transverse grooves 110T may not be recessed from one or more ends of one or more of the grooves 110.

[0032] In addition, if Figure 2As shown, the trench 110 includes a trench 110B that terminates below the active area 130A. The trench 110B is shorter than the trench 110A (e.g., shorter in the longitudinal direction). The trench 110B terminates before the polysilicon layer 120. In other words, the trench 110B terminates outside the polysilicon layer 120 (or the polysilicon pattern) (e.g., outside its area). Although Figure 2 1, but the connection with the trench 110B is outside the polysilicon layer 120 (or polysilicon pattern). The trench 110B is coupled (e.g., the corresponding electrode is electrically coupled) to the trench 110A via the lateral trench 110T-3. The trench 110B (which ends outside the area of ​​the polysilicon layer 120) is electrically coupled via the lateral trench 110T-3, while the rest of the trench 110 (which ends in the area of ​​the polysilicon layer 120) is electrically coupled via the polysilicon layer 120. The lateral trench 110T-3 may be recessed from the trench 110B. Therefore, the trench 110B may have an end section extending beyond the trench 110T-3 (toward the polysilicon layer 120).

[0033] A trench such as trench 110B, which is shorter than the rest of the parallel trench 110 that ends in the polysilicon layer 120, may be referred to as a staggered trench. The ends of trench 110B and the remaining trenches 110 (which may be referred to as full-length trenches) are staggered by a distance X1. Although not shown in this embodiment, the staggered trenches may be disposed between groups of parallel trenches that are longer than the staggered trenches.

[0034] Despite Figure 2 Although not shown in the figure, the transistor device 200 may include a polysilicon dielectric. In addition, although not shown, the lateral trench 110T-3 coupled between 110A and 110B may be at the end of the trench 110B. In other words, the trench 110B may not be recessed from the trench 110T-3. In such embodiments, the lateral trench 110T-3 may be referred to as an end trench (or referred to as an end lateral trench). Although not shown in all embodiments herein, in any of the embodiments, the lateral trench may be implemented as an end trench.

[0035] Figure 3 A transistor device 300 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 shown. Figure 3 The principles described may be applied to any of the embodiments described herein.

[0036] Figure 3The transistor device 300 shown includes a trench group 110 having an H-shaped portion 118 having an H-shaped pattern. For example, trenches 110A and 110C are coupled via a lateral trench 110T-4 to define an H-shaped pattern, and trenches 110D and 110E are coupled via a lateral trench 110T-5 to define an H-shaped pattern. The H-shaped pattern (and the lateral trenches 110T-4, 110T-5 therein) are disposed within a region of an opening 124 (e.g., a polysilicon ring 122) within a polysilicon layer 120. In this embodiment, the lateral trenches 110T-4, 110T-5 are aligned (e.g., aligned along the same line). In some embodiments, the lateral trenches 110T-4, 110T-5 may not be aligned along the same line.

[0037] In this embodiment, the pairs of trenches defining the H-shape are not coupled via lateral trenches. In other words, no lateral trenches are included between the pairs of trenches. In this embodiment, no lateral trenches are included between trenches 110C and 110D (which are adjacent trenches). These H-shaped pairs of trenches are electrically coupled via polysilicon layer 120 (e.g., polysilicon ring 122). Although in Figure 3 Not shown, but transistor device 300 may include a polysilicon dielectric and / or different types of lateral trenches.

[0038] Figure 4 A transistor device 400 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 shown. Figure 4 The principles described may be applied to any of the embodiments described herein.

[0039] Figure 4 The transistor device 400 shown includes a first trench group 410-1 having a trapezoidal portion 417-1 and a second trench group 410-2 having a trapezoidal portion 417-2. The trapezoidal portion 417-1 of the first trench group 410-1 is associated with (e.g., disposed below) a first opening 424-1 in the polysilicon layer 120, and the trapezoidal portion 417-2 of the second trench group 410-1 is associated with (e.g., disposed below) a second opening 424-2 in the polysilicon layer 120. Some of the transverse trenches within the trapezoidal portion 417-1 are aligned along the same line and are parallel to at least one other transverse trench. The transverse trenches within the trapezoidal portion 417-2 are configured in the same manner as the transverse trenches in the trapezoidal portion 417-1.

[0040] In this embodiment, the third groove group 410-3 is coupled via transverse grooves (e.g., a trapezoidal pattern). The third groove group 410-3 can be a staggered groove. In this embodiment, all third groove groups 410-3 are coupled to other grooves within the third groove group 410-3 via transverse grooves, or are coupled to the first groove group 410-1 or the second groove group 410-2 via transverse grooves. Therefore, the third groove group 410-3 (or staggered grooves) is arranged between the groove groups 410-1 and 410-2. The transverse grooves associated with the third groove group are arranged below the active area 130A. Although in Figure 4 Not shown, but transistor device 400 may include a polysilicon dielectric and / or different types of lateral trenches (eg, termination trenches).

[0041] In this embodiment, all grooves 410-1, 410-2, and 410-3 are coupled via transverse grooves. In some embodiments, at least some adjacent groove pairs may not be coupled via transverse grooves. For example, at least some of the grooves 410-1 may not be coupled via transverse grooves within the opening 424-1, and / or at least some of the grooves 410-2 may not be coupled via transverse grooves within the opening 424-2.

[0042] like Figure 4 As shown, contact opening 130B has a length D1. Contact opening 130B spans between openings 424-1 and 424-2. In other words, length D1 of contact opening 130B is longer than the spacing between openings 424-1 and 424-2. Length D1 of contact opening 130B allows for better electrical connection to devices associated with openings 424-1 and 424-2.

[0043] Figure 5 A transistor device 500 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 is shown. The transistor device 500 includes Figure 4 Many features shown.

[0044] Figure 5The transistor device 500 shown includes a first trench group 510-1 having an H-shaped portion 517-1 and a second trench group 510-2 having an H-shaped portion 517-2. The H-shaped shape 517-1 of the first trench group 510-1 is associated with (e.g., disposed below) a first opening 524-1 in the polysilicon layer 120, and the H-shaped shape 517-2 of the second trench group 510-1 is associated with (e.g., disposed below) a second opening 524-2 in the polysilicon layer 120. In this embodiment, the third trench group 510-3 (e.g., staggered trenches 510-3) is coupled via a lateral trench 510T (which is an end trench (e.g., a lateral end trench)). Although in Figure 5 Not shown, but transistor device 500 may include a polysilicon dielectric and / or different types of lateral trenches.

[0045] Figure 6 is a diagram showing a method of making a transistor device as described herein. Figure 6 As shown, a set of trenches may be formed in a substrate (block 610). In some implementations, a hard mask (also referred to as a hard mask dielectric layer) may be used to form the set of trenches.

[0046] FIG. 7A to FIG. 7D Shows Figure 6 Specifically, Fig. 7A A plan view of a trench structure 710 (which may also be referred to as a trench or trench group) including H-shaped portions, staggered trenches, laterally terminated trenches, etc. is shown. FIG. 7B to FIG. 7D 7B to 7D are cross-sectional views of the trench structure 710 . In this embodiment, the trench structure 710 is formed in the substrate 700 using a hard mask 711 .

[0047] like Figure 6 As shown, one or more dielectric layers may be formed (block 615). The dielectric layers may include, for example, sacrificial oxide layers, gate oxide layers, etc. One or more of the dielectric layers may line the surface of the trench group.

[0048] like Figure 6 As shown, a polysilicon electrode may be formed in the trench group (block 620). The electrode may be, for example, a gate electrode. Figure 6 As shown, a Zener diode component (or module) may also be formed (block 625). As shown in block 630, a polysilicon photoetch process may be performed.

[0049] FIG. 8A to FIG. 8D Shows Figure 6 The polysilicon photolithography / etching process in block 630 is described in detail. Fig. 8AA plan view of a trench structure 710 is shown in which a gate polysilicon 810 and a gate oxide (or dielectric) 820 line the trench structure 710 . FIG. 8B to FIG. 8D They are cross-sectional views of the trench structure cut along lines 8B to 8D. FIG. 8A to FIG. 8D As shown, a polysilicon ring 822 (eg, a gate polysilicon ring) is formed on a hard mask 850 (or a dielectric layer). Fig.8D A polysilicon ring 822 is shown that forms a contact (eg, a polysilicon contact) with the gate polysilicon 810. Fig.8D As shown, at location 880 , no gate polysilicon 810 is disposed on the tip of a trench (eg, a trench in trench structure group 710 ).

[0050] like Figure 6 As shown, a number of additional structures may be formed using a variety of processes. For example, a channel may be implanted (block 635), a drain may be implanted (e.g., a lightly doped drain, an N-type lightly doped drain) (block 640), an interlayer dielectric (ILD) may be formed (e.g., an intermetallic dielectric layer) (block 645), contacts may be formed (e.g., contact photoetching) (block 650), source and drain regions may be formed (e.g., a second N-type source implant and drain implant, a second source implant and drain implant (block 655), a body region may be formed (block 660), one or more metal layers may be formed (e.g., Figure 1A and Figure 1B The metal layer 191 shown, Fig. 9B , Fig.9D Metal layers 991A, 991B as shown) (block 665), and / or pad silicon nitride (SiN) and / or polyimide may be formed (block 670).

[0051] 9A to 9D At least some of the structures associated with the processes of blocks 635 to 665 are shown. Specifically, Fig.9A A plan view of a metal layer on the trench structure 710 is shown. FIG. 9B to FIG. 9D They are cross-sectional views of the structure taken along lines 9B to 9D, respectively.

[0052] Fig.9A Active region 930A is shown. FIG. 9B to FIG. 9D The features are shown to be connected to the metal layers 991A, 991B (in Fig. 9B and Fig.9D The metal layer 991B contacts the polysilicon ring 822 via the polysilicon contact 931B in the contact opening 930B. Fig. 9B A channel 970 and a source / drain region 975 are shown in FIG. Fig.9DAs shown, at position 980, no gate polysilicon is disposed on the tip of a trench (eg, a trench in trench structure group 710). Fig.9D As shown, the channel implant 970 penetrates the hard mask 850 and then diffuses via a thermal process.

[0053] In at least one embodiment, a method of forming a device described herein may include, for example, forming a trench disposed in a semiconductor region of a substrate, wherein the trench is lined with a gate dielectric and includes an electrode disposed in the trench. The method may include forming a polysilicon layer disposed over the trench, wherein the trench has an end portion disposed below an opening in the polysilicon layer, and the end portion of the trench is disposed between a first side of the opening and a second side of the opening.

[0054] In another embodiment, a method of forming a device described herein may include, for example, forming a pair of trenches disposed in a semiconductor region of a substrate, wherein each trench in the pair of trenches is lined with a gate dielectric and includes an electrode disposed in each trench in the pair of trenches. The method may include forming a polysilicon layer disposed over the pair of trenches, wherein each trench in the pair of trenches has an end portion disposed below an opening in the polysilicon layer, and the pair of trenches is joined by a lateral trench disposed in the opening.

[0055] In yet another embodiment, a method of forming a device described herein may include forming a trench disposed in a semiconductor region of a substrate, wherein the trench may be lined with a gate dielectric and may include an electrode disposed in the trench. The method may include forming a polysilicon layer disposed above the trench and defining a ring, wherein the ring has a first portion disposed above the trench and insulated from the trench. The first portion of the ring may be disposed on a first side of an end of the trench. The method may also include forming a metal contact (through a contact opening) in direct contact with a second portion of the ring, wherein the second portion of the ring is disposed on a second side of the end of the trench opposite the first side of the end of the trench.

[0056] FIG. 10A to FIG. 10C A transistor device 1000 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 is shown. The transistor device 1000 includes and / or may include many of the features described above in conjunction with other embodiments.

[0057] In this embodiment, the end portion 1011A of the trench 1010 extends beyond the polysilicon layer 1020 and is not disposed below the polysilicon layer (eg, disposed outside of the polysilicon layer). Fig. 10AThe polysilicon ring structure is not included. The contact opening 1030B (through which the metal layer 1091B can be contacted) and the active area 1030A (through which the metal layer 1091A can be contacted) are shown. In this embodiment, the trench 1010 includes an H-shaped portion. One of the parallel trenches does not include the H-shaped portion. In some embodiments, other types of structures (e.g., trapezoidal, U-shaped (not shown)) can be implemented at the end portion 1011A of the trench 1010. Fig. 10A Metal layers 1091A and 1091B are shown in FIG. Fig. 10A The polysilicon layer 1020 is shown as a solid line in FIG. 1 , even though the trench 1020 is below the polysilicon layer 1020 ( Figures 11 to 14D The views in are shown in a similar manner).

[0058] Fig. 10A Shown is line 10B, which corresponds to Fig. 10B and line 10C, which corresponds to Fig. 10C Sectional view in . Fig. 10B A metal layer 1091B is shown in contact with the polysilicon layer 1020 (ie, electrically connected to the polysilicon in the trench 1010 via the contact opening 1030B). Fig. 10B A dielectric layer 1040 and a hard mask 1050 are also shown. Fig. 10C A cross-sectional view along the length of one of the grooves 1010 is shown. Fig. 10C A channel implant 1070 (eg, a channel region) is shown in FIG.

[0059] Fig.11 A transistor device 1100 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 is shown. The transistor device 1100 includes and / or may include many of the features described above in conjunction with other embodiments.

[0060] In this embodiment, an end portion 1111A of the trench 1110 extends beyond the polysilicon layer 1120 and is not disposed beneath the polysilicon layer. Fig.11 The polysilicon ring structure is not included. Contact openings 1130B and active areas 1130A (through which one or more metal layers may be contacted) are shown. Contact openings 1130B are open to polysilicon layer 1120 (and may include polysilicon contacts). Contact openings 1130B are disposed on opposite sides of trench 1110. In this embodiment, trench 1110 includes a trapezoidal portion. In some embodiments, other types of structures may be implemented at end portion 1111A of trench 1110. Although in FIG. 10A to FIG. 10C and Fig.11 Not shown, but in FIG. 10A to FIG. 10C The transistor device 1000 or in Fig.11 The transistor device 1100 may include staggered trenches such as 110B (in Figures 2 to 3 ), 410-3 (in Figure 4 ) and 510-3 (shown in Figure 5 ).

[0061] Fig. 12A A transistor device 1200 is shown, which is Figure 1A and Figure 1B 12 is a variation of the transistor device 100 shown. The transistor device 1200 includes and / or may include many of the features described above in conjunction with other embodiments. In this embodiment, the end portion 1211A of the trench 1210 extends beyond the polysilicon layer 1220 and is not disposed below the polysilicon layer. Therefore, Fig. 12A The polysilicon ring structure (in which the trench 1210 terminates) is not included. This embodiment includes a contact opening 1230B (through which the metal layer 1291B can be contacted) above the portion 1223 of the polysilicon layer 1220 that extends beyond the end of the trench 1210. An active area 1230A (through which the metal layer 1291A can be contacted) is also shown. In this embodiment, the trench 1210 does not include a connecting lateral trench such as in the ladder portion.

[0062] like Fig. 12A As shown, a complete polysilicon ring structure is not included, but a partial ring is formed by polysilicon runner 1221, necked portion 1222, and portion 1223. These elements form a C-shape or concave shape in which the ends of the defining trench 1210 terminate.

[0063] In some embodiments, other types of structures (eg, a trapezoidal portion) may be implemented at the end portion 1211A of the trench 1210. Fig. 12A As shown, the transistor device 1200 includes a staggered trench 1210-1 having an end lateral trench. In some embodiments, the staggered trench 1210-1 may have a Fig. 12A Different configurations shown.

[0064] like Fig. 12A As shown, the polysilicon flow channel 1221 of the polysilicon layer 1220 is configured to be coupled to the electrode of the trench 1210. In addition, the necked portion 1222 is continuously coupled between the polysilicon flow channel 1221 and the portion 1223. In some embodiments, the portion 1223 of the polysilicon layer 1220 may be thicker than other portions of the polysilicon layer 1220 (e.g., the necked portion 1222, the polysilicon flow channel 1221).

[0065] Although the contact opening 1230B is disposed over the portion 1223 of the polysilicon layer 1220 that extends beyond the end of the trench 1210, in some embodiments, the contact opening may be disposed over a portion of the polysilicon layer 1220 that is between the trenches 1210 (e.g., does not extend beyond the end of the trench 1210). For example, the contact opening may be disposed over the necked portion 1222 of the polysilicon layer 1220.

[0066] Fig. 12B Shown along Fig. 12A A cross-sectional view along line 12B is shown. Fig. 12B A metal layer 1291B is shown in contact with the polysilicon layer 1220 (ie, electrically connected to the polysilicon in the trench 1210 via the contact opening 1230B). Fig. 12B Also shown is a dielectric layer 1240 and a hard mask 1250. Fig. 12B A channel implant 1270 (eg, a channel region) and source / drain regions 1275 are shown.

[0067] Fig.13 A transistor device 1300 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 is shown. The transistor device 1300 includes and / or may include many of the features described above in conjunction with other embodiments. Fig.13 Not shown are metal layers that are included in a manner similar to metal layers associated with other embodiments.

[0068] In this embodiment, the end portions 1311A-1, 1311A-2 of the trench 1310 are disposed in polysilicon rings 1322-1 and 1322-2. This embodiment includes contact openings 1330B on portions of the polysilicon layer 1320 (which may be disposed on a hard mask (not shown)) that extend beyond the ends of the trench 1310. An active area 1330A is also shown.

[0069] In this embodiment, the trenches 1310 are connected in the metal region via staggered trenches 1310-1, 1310-2, 1310-3, so that the number of trenches ending in the polysilicon rings 1322-1 and 1322-2 is relatively small (e.g., half or less of the number of parallel trenches 1310, more than half of the number of parallel trenches 1310). Specifically, the parallel trenches (e.g., trenches 1310A, 1310B) are separated by staggered trenches (e.g., staggered trench 1310-1). Since, for example, the parallel trenches (or full-length trenches) 1310A, 1310B are separated by staggered trenches 1310-1, the full-length trenches in the parallel trenches 1310 can have wider ends along the direction P1 (orthogonal to the longitudinal length of the trenches 1310) and the above-mentioned problems (e.g., GOI problems) can be avoided.

[0070] In some embodiments, the staggered grooves 1310-1 to 1310-3 may have, in some embodiments, Fig.13 In some embodiments, other types of structures can be implemented at the ends 1311A- 1 , 1311A- 2 of the trench 1310 .

[0071] FIG. 14A to FIG. 14D A transistor device 1400 is shown, which is Figure 1A and Figure 1B A variation of the transistor device 100 is shown. FIG. 14A to FIG. 14D The variants of can be implemented in any combination and / or can be combined with the above embodiments (or features). The transistor device 1400 includes and / or can include many of the features described above in conjunction with other embodiments. FIG. 14A to FIG. 14D The active region 1440A is shown in FIG. FIG. 14A to FIG. 14D Not shown are metal layers that are included in a manner similar to metal layers associated with other embodiments.

[0072] exist Fig.14AIn the illustrated embodiment (and in many variations), end portions 1411A of trenches 1410 (which include trenches 1410-1, 1410-2, 1410-3) are disposed in polysilicon rings that are offset (along a longitudinal length or direction (from the left to the right of the figure)) within the polysilicon layer 1320. Thus, end portions 1411A of trenches 1410 terminate at different lengths (e.g., trenches 1410-1, 1410-3 are longer or pushed out (full length), while trench 1410-2 is a shorter or staggered trench). The embodiment includes a contact opening 1430B over a portion of the polysilicon layer 1420. The contact opening 1430B contacts the polysilicon layer 1420 (via a polysilicon contact), which may be disposed on a hard mask (not shown). The contact opening 1430B is disposed on opposite sides of the trench 1410-2. In this embodiment, each of the trenches 1410-1, 1410-2, 1410-3 terminates within a different (and corresponding) polysilicon ring 1422-1, 1422-2, 1422-3.

[0073] In this embodiment, the end portion 1411A of the groove pair 1410 is connected to the transverse groove (U-shaped, using the transverse end groove). In some embodiments, the end portion 1411A of the groove pair 1410 is not connected to the transverse groove. This embodiment can solve the area (such as circle Q1) that is prone to misalignment problems in some embodiments. In this embodiment, T-shaped connections (e.g., associated with staggered grooves between full-length grooves) are avoided, which may cause the grooves to have different depths and may cause performance problems in some embodiments. In some embodiments, other types of structures can be implemented at the end portion 1411A of the groove 1410.

[0074] Fig. 14B Shows Fig.14A 1. A variation of transistor device 1400 is shown. In this variation, (one or more) polysilicon rings extend over adjacent trenches that do not terminate within the polysilicon rings (as indicated by the arrows). For example, at least one of the trenches 1410-2 (which may be referred to as a through trench) extends below polysilicon ring 1422-1. At least one of the trenches 1410-2 instead terminates within polysilicon ring 1422-2. Trench 1410-1 terminates within polysilicon ring 1422-1. This embodiment may also address areas that are prone to misalignment issues in some embodiments (as indicated by the small double-headed arrow at R1).

[0075] Fig. 14C Shows Fig.14A and Fig. 14BA variation of transistor device 1400 is shown in which no lateral trench is included. In this embodiment, contact opening 1430B is disposed outside the end of trench 1410, rather than being divided into multiple contacts. Contact opening 1430B spans the distance of polysilicon rings 1422-1 to 1422-3. Although not shown, in some embodiments, this variation may not include one or more through trenches.

[0076] Fig.14D Shows FIG. 14A to FIG. 14C A variation of the transistor device 1400 is shown in which no lateral trenches are included and in which at least some of the trenches do not terminate within a polysilicon ring (e.g., the polysilicon ring 1422-2 in other embodiments is removed). Instead, the trench 1410-2 terminates within a recess 1422B or cavity of the polysilicon layer 1420. In some embodiments, other types of structures (e.g., trapezoidal, U-shaped, H-shaped) may be implemented at the end portion 1411A of at least some of the trenches 1410. Although not shown, in some embodiments, this variation may not include one or more through trenches.

[0077] Fig.15 is a diagram illustrating a cross-sectional view along a trench of a vertical MOSFET structure 1500 that can be implemented in conjunction with embodiments described herein.

[0078] The specific structural and functional details disclosed herein are merely representative and are intended only for purposes of describing example embodiments. Example embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

[0079] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and the like.

[0080] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit these embodiments. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the features, steps, operations, elements and / or parts is specified, but the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof is not excluded.

[0081] It should also be understood that when an element such as a layer, a region or a substrate is mentioned on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to another element, or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, the element shown as directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the drawings.

[0082] As used in this specification, singular forms may include plural forms unless the context clearly indicates a specific case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include lateral adjacent or horizontal adjacent.

[0083] Exemplary embodiments of the inventive concepts of the present invention are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate structures) of exemplary embodiments. Therefore, changes in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the exemplary embodiments of the inventive concepts of the present invention should not be understood as being limited to the specific shapes of the regions shown herein, but should be understood to include shape deviations, for example, caused by manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the device regions, nor are they intended to limit the scope of the exemplary embodiments.

[0084] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, a "first" element may be referred to as a "second" element without departing from the teachings of the embodiments of the present invention.

[0085] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined herein.

[0086] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of a specific implementation. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A transistor device comprising: a trench disposed in a semiconductor region of a substrate, the trench being lined with a gate dielectric and including an electrode disposed in the trench; and A polysilicon layer is disposed over the trench, the trench having an end portion disposed below the opening in the polysilicon layer, the end portion of the trench being disposed between a first side of the opening and a second side of the opening. 2 . The transistor device of claim 1 , wherein the first side of the opening is disposed over a portion of the trench, and the second side of the opening is not disposed over any portion of the trench. The transistor device of claim 1 , wherein a third side of the opening is aligned parallel to the trench.

4. The transistor device according to claim 1, wherein the trench is a first trench, The transistor device further comprises a second trench having an end portion disposed below the opening in the polysilicon layer; and a transverse groove disposed within the opening and aligned orthogonally to the first groove and the second groove and coupled between the first groove and the second groove, The first groove has an end section extending beyond the lateral groove or the lateral groove is recessed from ends of the first groove and the second groove.

5. The transistor device according to claim 1, wherein the trench is a first trench, The transistor device further comprises a second trench having an end portion disposed below the opening in the polysilicon layer; and A terminal transverse groove is disposed within the opening and is aligned orthogonally to the first groove and the second groove and coupled between the first groove and the second groove.

6. A transistor device comprising: a pair of trenches disposed in a semiconductor region of a substrate, each trench in the pair of trenches being lined with a gate dielectric and including an electrode disposed in each trench in the pair of trenches; and A polysilicon layer is disposed over the pair of trenches, each trench in the pair of trenches having an end portion disposed below an opening in the polysilicon layer, the pair of trenches being joined by a lateral trench disposed within the opening. 7 . The transistor arrangement of claim 6 , wherein the trench pair and the lateral trench define a portion of an H-shape or a trapezoidal pattern.

8. The transistor device of claim 6, wherein the lateral trench is recessed from an end of each trench in the trench pair. 9 . The transistor device of claim 6 , wherein at least one trench of the pair of trenches has a tip that is insulated from the polysilicon layer or disposed vertically below the opening.

10. A transistor device comprising: a trench disposed in a semiconductor region of a substrate, the trench being lined with a gate dielectric and including an electrode disposed in the trench; a polysilicon layer disposed over the trench and defining a ring having a first portion disposed over and insulated from the trench, the first portion of the ring disposed on a first side of a terminal end of the trench; and A contact opening is above a second portion of the ring, the second portion of the ring being disposed on a second side of the end of the groove opposite the first side of the end of the groove.

11. The transistor device of claim 10, wherein the first portion of the ring is disposed on one side of an opening in the polysilicon layer, and the second portion of the ring is disposed on an opposite side of the opening in the polysilicon layer, The transistor device further comprises: A metal layer is electrically coupled to the second portion of the ring through the contact opening by a contact. 12 . The transistor arrangement of claim 10 , wherein the second portion of the ring is insulated from the substrate by a dielectric layer or by a hard mask dielectric layer. 13 . The transistor device of claim 10 , further comprising a lateral trench disposed within the polysilicon ring and coupled to the trench.

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