Light emitting device, optical device and information processing device

Abstract

A light-emitting device, an optical device, and an information processing device, which facilitate the proximity of a driving element to a light-emitting element array, compared with a structure in which a circuit element is provided on the driving element side of the light-emitting element array. The light-emitting device comprises: a wiring substrate; a light-emitting element array having a first side surface and a second side surface facing each other and a third side surface and a fourth side surface facing each other connecting the first side surface and the second side surface, and provided on the wiring substrate; a driving element provided on the wiring substrate on the first side surface and driving the light-emitting element array; a first circuit element and a second circuit element arranged in a direction along the second side surface on the wiring substrate on the second side surface; and a wiring component provided on the third side surface and the fourth side surface and extending from an upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array.

Description

Technical Field

[0001] The invention relates to a light emitting device, an optical device and an information processing device. Background Art

[0002] Patent document 1 describes an imaging device comprising: a light source; a light diffusion component having a plurality of lenses arranged adjacent to each other on a predetermined plane and diffusing light emitted from the light source; and an imaging element receiving reflected light from a subject obtained by reflecting the light diffused by the light diffusion component, wherein the plurality of lenses are arranged in such a way that the period of interference fringes in the diffused light becomes less than three pixels.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2018-054769

[0004] However, when it is desired to reduce the inductance of the circuit driving the light emitting element array, wiring such as bonding wires may be provided not only on one side surface of the light emitting element array but also on multiple side surfaces. Also, multiple circuit elements such as light receiving elements or temperature detecting elements may be arranged close to the side surfaces of the light emitting element array.

[0005] In this case, the following structure can be considered, namely, a plurality of circuit elements are separately arranged on the wiring substrate on the driving element side that drives the light emitting element array and on the wiring substrate on the side opposite to the driving element sandwiching the light emitting element array, and wiring such as bonding wires are provided on the remaining side.

[0006] However, if a circuit element is disposed between the light emitting element array and the driving element, the path of the wiring pattern connecting the light emitting element array and the driving element is limited, which may increase the inductance of the circuit. Summary of the invention

[0007] The present invention provides a light emitting device and the like having a structure in which a driving element and a light emitting element array can be easily brought closer together, compared with a structure in which a circuit element is provided on the driving element side of the light emitting element array.

[0008] The invention described in Scheme 1 is a light-emitting device, which comprises: a wiring substrate; a light-emitting element array having a first side surface and a second side surface opposite to each other and a third side surface and a fourth side surface opposite to each other connecting the first side surface and the second side surface, and arranged on the wiring substrate; a driving element, which is arranged on the wiring substrate on the first side surface and drives the light-emitting element array; a first circuit element and a second circuit element, which are arranged on the wiring substrate on the second side surface in a direction along the second side surface; and a wiring component, which is arranged on the third side surface and the fourth side surface, and extends from the upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array.

[0009] The invention described in claim 2 is the light emitting device described in claim 1, wherein at least one of the first circuit element and the second circuit element is a light receiving element that receives light emitted from the light emitting element array.

[0010] The invention described in claim 3 is the light emitting device described in claim 1, wherein at least one of the first circuit element and the second circuit element is a temperature detection element that detects the temperature of the light emitting element array.

[0011] The invention described in Scheme 4 is a light-emitting device described in any one of Schemes 1 to 3, wherein no wiring component extending from the upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array is provided between the second side surface and the first circuit element and the second circuit element.

[0012] The invention described in Scheme 5 is a light-emitting device described in any one of Schemes 1 to 4, wherein the first circuit element and the second circuit element respectively have a plurality of terminals, the first circuit element is arranged closer to the third side surface than the second circuit element, and the wirings respectively connected to the plurality of terminals of the first circuit element are led out to the third side surface, and the second circuit element is arranged closer to the fourth side surface than the first circuit element, and the wirings respectively connected to the plurality of terminals of the second circuit element are led out to the fourth side surface.

[0013] The invention described in claim 6 is the light emitting device according to any one of claims 1 to 5, wherein a light diffusing member for diffusing light emitted from the light emitting element array toward the outside is provided on an emission path of the light emitting element array.

[0014] The invention described in Scheme 7 is that in the light-emitting device described in Scheme 6, at least one of the first circuit element and the second circuit element is a light receiving element that receives light emitted by the light-emitting element array, and the light diffusion component is arranged at a position where the light-emitting element array and the light receiving element overlap when viewed from above.

[0015] The invention described in claim 8 is the light emitting device according to any one of claims 1 to 7, wherein the light emitting element array includes a plurality of light emitting elements connected in parallel to each other.

[0016] The invention described in Scheme 9 is an optical device, which comprises: a light-emitting device as described in any one of Schemes 1 to 8; and a light receiving unit, which receives reflected light emitted from a light-emitting element array possessed by the light-emitting device and reflected by an object to be measured, and the light receiving unit outputs a signal corresponding to the time from the time when the light is emitted from the light-emitting element array to the time when the light is received by the light receiving unit.

[0017] The invention described in Scheme 10 is an information processing device, which comprises: the optical device described in Scheme 9; and a shape determination unit, which determines the three-dimensional shape of the object to be measured based on the reflected light emitted from the light emitting element array of the optical device and reflected by the object to be measured and received by the light receiving unit of the optical device.

[0018] The invention described in claim 11 is the information processing device described in claim 10, comprising: an authentication processing unit that performs authentication processing related to the use of its own device based on the determination result in the shape determination unit.

[0019] Effects of the Invention

[0020] According to the first aspect of the present invention, compared with a configuration in which a circuit element is provided on the driving element side of the light emitting element array, it is easier to bring the driving element closer to the light emitting element array.

[0021] According to the second aspect of the present invention, light emitted from the light emitting element array is received at a position close to the light emitting element array.

[0022] According to the third aspect of the present invention, the temperature of the light emitting element array is detected at a position close to the light emitting element array.

[0023] According to the fourth aspect of the present invention, the circuit element and the light emitting element array can be arranged close to each other, compared with a case where wiring members are provided between the second side surface and the first circuit element and between the second side surface and the second circuit element.

[0024] According to the fifth aspect of the present invention, compared with the case where the wiring connected to the first circuit element and the wiring connected to the second circuit element are led out on the same side, it is easier to arrange the two circuit elements and the light emitting element array close to each other.

[0025] According to the sixth aspect of the present invention, compared with a structure without a light diffusion member, light emitted from the light emitting element array is irradiated in a wider range.

[0026] According to the seventh aspect of the present invention, the amount of light emitted from the light emitting element array and reflected by the light diffusing member received by the light receiving element increases compared to a case where the light emitting element array and the light receiving element are not provided at a position overlapping the light emitting element array and the light receiving element.

[0027] According to the eighth aspect of the present invention, light with a higher light intensity can be irradiated compared to a structure in which a light emitting element is driven alone.

[0028] According to a ninth aspect of the present invention, there is provided an optical device capable of three-dimensional measurement.

[0029] According to a tenth aspect of the present invention, there is provided an information processing device capable of measuring a three-dimensional shape.

[0030] According to an eleventh aspect of the present invention, there is provided an information processing device equipped with an authentication process based on a three-dimensional shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Embodiments of the present invention will be described in detail with reference to the following drawings.

[0032] Figure 1 is a diagram showing an example of an information processing device;

[0033] Figure 2 is a block diagram illustrating the structure of an information processing device;

[0034] Figure 3 is a top view of the light emitting element array;

[0035] Figure 4 A diagram illustrating a cross-sectional structure of a VCSEL in a light emitting element array;

[0036] Figure 5 This is a diagram for explaining an example of a light diffusion member. Figure 5 (a) is a top view. Figure 5 (b) in the Figure 5 (a) is a cross-sectional view along the VB-VB line;

[0037] Figure 6 is a diagram showing an example of an equivalent circuit for driving a light emitting element array by low-side driving;

[0038] Figure 7 2 is a diagram for explaining a light emitting device to which this embodiment is applied. Figure 7 (a) is a top view. Figure 7 (b) in the Figure 7 The cross-sectional view along line VIIB-VIIB of (a) is shown in FIG. Figure 7 (c) in Figure 7 A cross-sectional view along line VIIC-VIIC in (a);

[0039] Figure 8 1 is a diagram for explaining a wiring pattern provided on a wiring board and a base material in a light emitting device to which this embodiment is applied. Figure 8 (a) is the surface of the wiring board. Figure 8 (b) is the surface of the substrate, Figure 8 (c) is the back side of the substrate;

[0040] Fig. 9 is a top view illustrating a light emitting device shown for comparison, Fig. 9 (a) is a top view. Fig. 9 (b) in the Fig. 9The cross-sectional view along the IXB-IXB line in (a) is shown in FIG. Fig. 9 (c) in Fig. 9 (a) is a cross-sectional view along the IXC-IXC line;

[0041] Fig.10 FIG. 2 is a diagram for explaining a wiring pattern provided on a wiring substrate and a base material in a light emitting device shown for comparison. Fig.10 (a) is the surface of the wiring board. Fig.10 (b) is the surface of the substrate, Fig.10 (c) in the figure is the back side of the substrate.

[0042] Explanation of symbols

[0043] 1-information processing device, 2-user interface (UI) unit, 3-optical device, 4, 4'-light-emitting device, 5-3D sensor, 6-resistance element, 7, 70-capacitor, 8-optical device control unit, 9-system control unit, 10-wiring substrate, 11-1, 11-2, 111-1F, 111-2F, 111-1B, 111-2B-anode wiring pattern for light-emitting element array, 12, 112F, 112B-cathode wiring pattern for light-emitting element array, 13, 113F, 113B-anode wiring pattern for PD, 14, 114F, 114B-cathode wiring pattern for PD, 15, 115F, 115B-anode wiring pattern for TD, 16, 116F, 116B-cathode wiring pattern for TD, 20-light-emitting element Array, 21A, 21B, 22A, 22B-side, 23A, 23B, 23C-bonding wire, 30-light diffusion component, 40-light receiving element (PD) for monitoring light quantity, 45-temperature detection element (TD), 50-driving unit, 51-MOS transistor, 52-signal generating circuit, 60-holding unit, 81-shape determining unit, 82-power supply, 83-power supply line, 84-ground line, 91-authentication processing unit, 100-substrate, 200-semiconductor substrate, 202-lower DBR, 206-active region, 208-upper DBR, 210-current narrowing layer, 210A-oxidation region, 210B-conductive region, 214-cathode electrode, 218-anode electrode, M-mesa, VCSEL-vertical cavity surface emitting laser. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] In many cases, an information processing device is configured to identify whether the access of a user who has accessed the information processing device is permitted, and to permit the use of the device itself, i.e., the information processing device, only when the user is authenticated as being permitted to access. Up to now, methods for authenticating users based on passwords, fingerprints, irises, etc. have been used. Recently, a more secure authentication method has been required. As such a method, authentication based on a three-dimensional image such as the user's face shape has gradually been performed.

[0046] Here, as an example, the information processing device is described as a portable information processing terminal, and the user is authenticated by recognizing the face shape captured as a three-dimensional image. In addition, the information processing device can be applied to information processing devices such as personal computers (PCs) other than portable information processing terminals.

[0047] Furthermore, the structure, function, method, etc. described in this embodiment can also be applied to the recognition of three-dimensional shapes other than facial shapes as the object to be detected. That is, it can also be applied to the recognition of the shape of objects other than faces. Furthermore, the distance to the object to be detected is not limited.

[0048] (Information Processing Device 1)

[0049] Figure 1 1 is a diagram showing an example of the information processing device 1. As described above, the information processing device 1 is a portable information processing terminal as an example.

[0050] The information processing device 1 includes a user interface unit (hereinafter referred to as a UI unit) 2 and an optical device 3 for acquiring a three-dimensional image. The UI unit 2 is composed of, for example, a display device for displaying information to a user and an input device for inputting a command for information processing through a user's operation. The display device is, for example, a liquid crystal display or an organic electroluminescent (EL) display, and the input device is, for example, a touch panel.

[0051] The optical device 3 includes a light emitting device 4 and a three-dimensional sensor (hereinafter, referred to as a 3D sensor) 5. The light emitting device 4 irradiates light toward an object to be measured for obtaining a three-dimensional image, and in the example described here, irradiates light toward the face. The 3D sensor 5 obtains the light irradiated by the light emitting device 4 and reflected by the face. Here, a three-dimensional image of the face is obtained based on the so-called ToF (Time of Flight) technology based on the flight time of light. Hereinafter, even when obtaining a three-dimensional image of the face, the face is marked as a measured object. In addition, a three-dimensional image can be obtained of a thing other than the face as a measured object. Sometimes obtaining a three-dimensional image is marked as 3D sensing. The 3D sensor 5 is an example of a light receiving unit.

[0052] The information processing device 1 is configured as a computer including a CPU, a ROM, a RAM, etc. The ROM includes a nonvolatile rewritable memory such as a flash memory. The information processing device 1 operates by developing programs or constants stored in the ROM in the RAM and executing them by the CPU, and performs various information processing.

[0053] Figure 2 This is a block diagram for explaining the structure of the information processing device 1 .

[0054] The information processing device 1 includes the optical device 3, an optical device control unit 8, and a system control unit 9. The optical device control unit 8 controls the optical device 3. The optical device control unit 8 includes a shape determination unit 81. The system control unit 9 controls the information processing device 1 as a system. The system control unit 9 includes an authentication processing unit 91. The system control unit 9 is connected to the UI unit 2, a speaker 92, and a two-dimensional camera (in Figure 2 In the figure, it is marked as a 2D camera. )93 etc.

[0055] The following will be described in order.

[0056] The light emitting device 4 provided in the optical device 3 includes a wiring substrate 10, a base material 100, a light emitting element array 20, a light diffusion member 30, and a light receiving element for monitoring light quantity (in Figure 2 and below, marked as PD.) 40. Temperature detection element (in Figure 2 And below, marked as TD. )45, drive unit 50, holding unit 60 and capacitor 70. Furthermore, the light emitting device 4 has passive elements such as resistor element 6 and capacitor 7 in order to operate the drive unit 50. The drive unit 50 has a drive element for driving the light emitting element array 20 as described later. Therefore, in the figure, it is marked as a drive unit (drive element). In addition, two capacitors 70 are shown in the figure, but it can be one or more than two. Moreover, the resistor element 6 and the capacitor 7 can be multiple, respectively. Here, the capacitor 70, 3D sensor 5, resistor element 6, capacitor 7, etc. other than the light emitting element array 20, PD40, TD45 and drive unit 50 are sometimes marked as circuit components without distinguishing from each other.

[0057] The light emitting element array 20, PD40 and TD45 are provided on the substrate 100. The substrate 100 is composed of an electrically insulating member. Furthermore, the substrate 100, the driving unit 50, the capacitor 70, the resistor 6 and the capacitor 7 are provided on the wiring substrate 10. That is, the light emitting element array 20, PD40 and TD45 are provided on the wiring substrate 10 via the substrate 100. Here, it is assumed that the light emitting element array 20, PD40 and TD45 are provided on the wiring substrate 10 even when via the substrate 100. In addition, as an example, the driving unit 50 is composed of a semiconductor integrated circuit.

[0058] The light emitting element array 20 is formed as an array of a plurality of light emitting elements arranged two-dimensionally (see the following description). Figure 3 ). As an example, the light emitting element is a vertical cavity surface emitting laser VCSEL (Vertical Cavity Surface Emitting Laser). In the following, the light emitting element is explained as a vertical cavity surface emitting laser VCSEL. Moreover, the vertical cavity surface emitting laser VCSEL is marked as VCSEL. The light emitting element array 20 emits light in a vertical direction relative to the surface of the wiring substrate 10 or the substrate 100. When three-dimensional sensing is performed by ToF technology, the light emitting element array 20 is required to emit pulsed light of more than 100 MHz and a rise time of less than 1ns (hereinafter, marked as emitted light pulses.). In addition, when taking face recognition as an example, the distance at which the light is irradiated is about 10 cm to about 1 m. Moreover, the range for measuring the 3D shape is about 1 m square. In addition, the distance at which the light is irradiated is marked as the measurement distance, and the range for measuring the 3D shape of the object to be measured is marked as the measurement range or the irradiation range. In addition, the surface assumed to be set in the measurement range or the irradiation range is marked as the irradiation surface.

[0059] PD40 is a pin-type photodiode composed of a p-type Si region as an anode, an i (intrinsic) type Si region, and an n-type Si region as a cathode, which outputs an electrical signal corresponding to the amount of light received (hereinafter, referred to as the amount of light received). In addition, an anode electrode is provided in the p-type Si region, and a cathode electrode is provided in the n-type Si region. In addition, PD40 is an example of a first circuit element and an example of a light receiving element.

[0060] TD45 is a temperature detection element for detecting the temperature of the substrate 100. TD45 is, for example, a surface-mounted negative temperature coefficient thermistor (NTC: Negative Temperature Coefficient Thermistor) or a positive temperature coefficient thermistor (PTC: Positive Temperature Coefficient Thermistor). If the temperature of a negative temperature coefficient thermistor rises, the resistance value decreases, and if the temperature of a positive temperature coefficient thermistor exceeds a certain temperature, the resistance value increases sharply. By utilizing the above-mentioned characteristics of TD45, the temperature of the substrate 100 is detected and the temperature of the light-emitting element array 20 is indirectly monitored. Therefore, TD45 is preferably configured close to the light-emitting element array 20, for example. Thermistors do not have polarity, but there are elements with polarity among other temperature sensor elements. In addition, TD45 is an example of a second circuit element.

[0061] The light diffusion component 30 is provided in a manner covering the light emitting element array 20 and the PD40. That is, the light diffusion component 30 is provided at a predetermined distance from the light emitting element array 20 and the PD40 on the substrate 100 by the holding portion 60 provided on the substrate 100. In addition, the light diffusion component 30 covering the light emitting element array 20 and the PD40 means that the light diffusion component 30 is provided on the emission path of the light emitted by the light emitting element array 20, and is provided in a manner that the light emitted by the light emitting element array 20 transmits the light diffusion component 30. It refers to a state in which the light emitting element array 20 and the PD40 overlap with the light diffusion component 30 when viewed from above. Here, the view from above refers to the state in which the light emitting element array 20 and the PD40 are overlapped with each other when viewed from above. Here, the view from above refers to the state in which the light emitting element array 20 and the PD40 are overlapped with each other when viewed from above. Figure 3 , Figure 7 In (a) and the like, the case of observing in the xy plane. In addition, the PD 40 is preferably arranged close to the light emitting element array 20 at a position covered by the light diffusing member 30 in such a manner that it can easily receive a portion of the light reflected by the light diffusing member 30 among the light emitted by the light emitting element array 20. Figure 2 In the embodiment, the light diffuser 30 is provided so as to also cover the TD 45, but the light diffuser 30 may be provided so as not to cover the TD 45. If the light diffuser 30 is provided so as not to cover the TD 45, the area of ​​the expensive light diffuser 30 can be reduced.

[0062] The holding portion 60 is provided at the edge of the light diffusion component 30 and holds the light diffusion component 30. Here, the holding portion 60 is provided in a manner of surrounding the light emitting element array 20, the PD 40 and the TD 45. Here, the outer shape of the substrate 100, the outer shape of the light diffusion component 30 and the outer shape of the holding portion 60 are set to be the same. Therefore, the outer edges of the substrate 100, the light diffusion component 30 and the holding portion 60 overlap. In addition, the outer shape of the substrate 100 can also be made larger than the outer shape of the light diffusion component 30 or the outer shape of the holding portion 60.

[0063] The wiring board 10 , the base material 100 , the light emitting element array 20 , the light diffusion member 30 , the driving unit 50 , and the holding unit 60 in the light emitting device 4 will be described in detail later.

[0064] The 3D sensor 5 has a plurality of light receiving units. For example, each light receiving unit is configured in such a manner that it receives a pulsed reflected light from the object to be measured (hereinafter, referred to as a receiving pulse) in response to an emitted light pulse from the light emitting element array 20, and accumulates a charge corresponding to the time until the light is received for each light receiving unit. The 3D sensor 5 is configured as a device of a CMOS structure in which each light receiving unit has two gates and a charge accumulation unit corresponding to them. Moreover, by alternately applying pulses to the two gates, the generated photoelectrons are transmitted to either of the two charge accumulation units at a high speed. Charges corresponding to the phase difference between the emitted light pulse and the received pulse are accumulated in the two charge accumulation units. Moreover, the 3D sensor 5 outputs a digital value corresponding to the phase difference between the emitted light pulse and the received pulse as a signal for each light receiving unit via an AD converter. That is, the 3D sensor 5 outputs a signal corresponding to the time from the emission of light from the light emitting element array 20 to the reception by the 3D sensor 5. In addition, the AD converter may be provided with the 3D sensor 5 or may be provided outside the 3D sensor 5.

[0065] As described above, when taking face authentication as an example, the light emitting element array 20 is required to irradiate light within an irradiation range of about 1m square and at a distance of about 10cm to about 1m. In addition, the 3D sensor 5 receives reflected light from the object to be measured and measures the 3D shape of the object to be measured. Therefore, the light emitting element array 20 is required to have a large output and effectively dissipate the heat generated by the light emitting element array 20, and it is required to suppress overheating of the light emitting element array 20.

[0066] The shape determination unit 81 of the optical device control unit 8 acquires the digital value obtained for each light receiving unit from the 3D sensor 5, calculates the distance to the object to be measured for each light receiving unit, and determines the 3D shape of the object to be measured based on the calculated distance.

[0067] When the determination result determined by the shape determination unit 81, i.e., the 3D shape of the object to be measured, is a 3D shape previously stored in a ROM or the like, the authentication processing unit 91 of the system control unit 9 performs authentication processing related to the use of the information processing device 1. In addition, as an example, the authentication processing related to the use of the information processing device 1 refers to processing to determine whether to permit the use of the own device, i.e., the information processing device 1. For example, when it is determined that the 3D shape of the object to be measured, i.e., the face, is consistent with the face shape stored in a storage unit such as a ROM, the use of the information processing device 1 including various application programs provided by the information processing device 1 is permitted.

[0068] As an example, the shape identification unit 81 and the authentication processing unit 91 are constituted by a program. Alternatively, they may be constituted by an integrated circuit such as an ASIC or an FPGA. Alternatively, they may be constituted by software such as a program and an integrated circuit such as an ASIC.

[0069] exist Figure 2 In the figure, the optical device 3, the optical device control unit 8, and the system control unit 9 are shown separately from each other, but the system control unit 9 may include the optical device control unit 8. Furthermore, the optical device control unit 8 may be included in the optical device 3. Furthermore, the optical device 3, the optical device control unit 8, and the system control unit 9 may be integrally configured.

[0070] Next, before describing the light emitting device 4, a circuit for driving the light emitting element array 20, the light diffusion member 30, and the light emitting element array 20 constituting the light emitting device 4 will be described. The circuit for driving the light emitting element array 20 includes a driving unit 50, a capacitor 70, a PD 40, and a TD 45.

[0071] (Structure of Light Emitting Element Array 20)

[0072] Figure 3 It is a top view of the light emitting element array 20. The shape of the light emitting element array 20 when viewed from above, i.e., the plane shape, is a quadrilateral, and a plurality of VCSELs are arranged in a two-dimensional array. The right direction of the paper is set as the x direction, and the upper direction of the paper is set as the y direction. The direction orthogonal to the x direction and the y direction in a counterclockwise direction is set as the z direction. In addition, the x, y, and z directions in each of the drawings are the same. In addition, the surface refers to the surface on the +z direction side, and the back surface refers to the surface on the -z direction side. The same applies to other situations. In addition, as Figure 3 As shown, the plurality of VCSELs do not necessarily have to be arranged at the intersections of the grid, but may be arranged at the vertices of a plurality of adjacently arranged triangles, or may be arranged in other arrangements.

[0073] The VCSEL is stacked on a semiconductor substrate 200 (see Figure 4 ) is provided between the lower multilayer film reflector and the upper multilayer film reflector on the semiconductor substrate 200, and an active area serving as a light-emitting area is provided, and a light-emitting element that emits a laser beam in the vertical direction of the semiconductor substrate 200, i.e., the +z direction. Thus, two-dimensional arraying is easily achieved. As an example, the number of VCSELs possessed by the light-emitting element array 20 is 100 to 1000. In addition, a plurality of VCSELs are connected in parallel to each other and driven in parallel. The number of VCSELs mentioned above is an example, and the number of VCSELs of the light-emitting element array 20 can be set according to the measurement distance or the measurement range.

[0074] A plurality of anode electrodes 218 (see below) common to VCSELs are provided on the surface of the light emitting element array 20. Figure 4A cathode electrode 214 is provided on the back side of the light emitting element array 20 (see Figure 4 ). That is, a plurality of VCSELs are connected in parallel. By connecting a plurality of VCSELs in parallel and driving them, high-intensity light is emitted simultaneously and irradiated to the object to be measured, compared with the case where the VCSELs are driven separately.

[0075] Here, the side surface of the light emitting element array 20 having a quadrilateral planar shape on the +x direction side is marked as side surface 21A, the side surface on the -x direction side is marked as side surface 21B, the side surface on the +y direction side is marked as side surface 22A, and the side surface on the -y direction side is marked as side surface 22B. Side surface 21A and side surface 21B are opposite to each other. Side surface 22A and side surface 22B are respectively connected to side surface 21A and side surface 21B, and are opposite to each other. Here, side surface 21A is an example of the first side surface, side surface 21B is an example of the second side surface, side surface 22A is an example of the third side surface, and side surface 22B is an example of the fourth side surface.

[0076] (VCSEL structure)

[0077] Figure 4 This is a diagram for explaining the cross-sectional structure of one VCSEL in the light emitting element array 20. This VCSEL is a VCSEL of a λ resonator structure. The upward direction of the paper is defined as the z direction.

[0078] The VCSEL is composed of an n-type lower distributed Bragg reflector (DBR: Distributed Bragg Reflector) 202, an active region 206 including a quantum well layer sandwiched by an upper spacer layer and a lower spacer layer, and a p-type upper distributed Bragg reflector 208, which is composed of AlGaAs layers with different Al compositions, stacked in sequence on a semiconductor substrate 200 such as n-type GaAs. Hereinafter, the distributed Bragg reflector is referred to as DBR.

[0079] The n-type lower DBR202 is Al 0.9 Ga 0.1 The As layer and the GaAs layer are provided as a pair of stacked bodies, and the thickness of each layer is λ / 4n r (where λ is the oscillation wavelength, n r is the refractive index of the medium) and are alternately stacked in 40 cycles. The carrier concentration after doping with n-type impurities, i.e. silicon, is, for example, 3×10 18 cm -3 .

[0080] The active region 206 is composed of a stacked lower spacer layer, a quantum well active layer, and an upper spacer layer. For example, the lower spacer layer is undoped Al 0.6 Ga 0.4As layer, the quantum well active layer is an undoped InGaAs quantum well layer and an undoped GaAs barrier layer, and the upper spacer layer is an undoped Al 0.6 Ga 0.4 As layer.

[0081] The p-type upper DBR 208 converts the p-type Al 0.9 Ga 0.1 The As layer and the GaAs layer are provided as a pair of stacked bodies, and the thickness of each layer is λ / 4n r , and stacked in 29 cycles. The carrier concentration after doping with p-type impurities, i.e., carbon, is, for example, 3×10 18 cm -3 For example, it is preferable that a contact layer composed of p-type GaAs is formed at the uppermost layer of the upper DBR 208 , and a current constriction layer 210 composed of p-type AlAs is formed at the lowermost layer of the upper DBR 208 or inside thereof.

[0082] A cylindrical mesa M is formed on the semiconductor substrate 200 by etching the semiconductor layers stacked from the upper DBR 208 to the lower DBR 202. As a result, the current constriction layer 210 is exposed on the side of the mesa M. Through the oxidation process, an oxidized region 210A oxidized from the side of the mesa M and a conductive region 210B surrounded by the oxidized region 210A are formed in the current constriction layer 210. In addition, in the oxidation process, the oxidation rate of the AlAs layer is faster than that of the AlGaAs layer, and the oxidized region 210A is oxidized from the side of the mesa M toward the inside at a substantially constant rate, so that the planar shape of the conductive region 210B becomes a shape reflecting the outer shape of the mesa M, that is, a circular shape, and its center is substantially consistent with the axial direction of the mesa M indicated by the single-dot chain line. In the present embodiment, the mesa M has a columnar structure.

[0083] A ring-shaped p-side electrode 212 made of a metal such as Ti / Au is formed in the uppermost layer of the mesa M. The p-side electrode 212 is in ohmic contact with a contact layer provided in the upper DBR 208. The surface of the upper DBR 208 inside the ring-shaped p-side electrode 212 becomes a light emission port 212A for emitting a laser beam to the outside. That is, in the VCSEL, light is emitted in a direction perpendicular to the semiconductor substrate 200, and the axial direction of the mesa M becomes the optical axis. Moreover, a cathode electrode 214 is formed as an n-side electrode on the back side of the semiconductor substrate 200. In addition, the surface of the upper DBR 208 inside the p-side electrode 212 is a light emission surface. That is, the optical axis of the VCSEL becomes the light emission direction.

[0084] In addition, an insulating layer 216 is provided in a manner that covers the surface of the mesa M except for the portion connected to the anode electrode (anode electrode 218 described later) of the p-side electrode 212 and the light emission port 212A. In addition, the anode electrode 218 is provided in a manner that is in ohmic contact with the p-side electrode 212 except for the light emission port 212A. In addition, the anode electrode 218 is provided so as to be common to a plurality of VCSELs. That is, in a plurality of VCSELs constituting the light emitting element array 20, each p-side electrode 212 is connected in parallel via the anode electrode 218. In addition, the anode electrode 218 is an example of an upper surface electrode of the light emitting element array.

[0085] In addition, VCSEL can oscillate in a single transverse mode or in multiple transverse modes. As an example, the light output of one VCSEL is 4mW to 8mW. Therefore, when the light emitting element array 20 is composed of 500 VCSELs, the light output of the light emitting element array 20 becomes 2W to 4W. In such a high-output light emitting element array 20, the heat generated by the light emitting element array 20 is large.

[0086] (Structure of the light diffusion member 30)

[0087] Figure 5 This is a diagram for explaining an example of the light diffusion member 30 . Figure 5 (a) is a top view. Figure 5 (b) in the Figure 5 The cross-sectional view along the VB-VB line in (a). Figure 5 In (a), the right direction of the paper is set as the x direction, and the upward direction of the paper is set as the y direction. The direction perpendicular to the x direction and the y direction in the counterclockwise direction is set as the z direction. Figure 5 In (b), the right direction of the paper is the x direction, and the upper direction of the paper is the z direction.

[0088] like Figure 5 As shown in (b) of FIG. 1 , the light diffusion component 30 includes a glass substrate 31 having two parallel and flat surfaces and a resin layer 32 provided on the back of the glass substrate 31 and having a concave-convex shape for diffusing light. The light diffusion component 30 further expands the beam divergence angle of the light incident from the VCSEL of the light emitting element array 20 and emits it. That is, the concave-convex shape formed on the resin layer 32 of the light diffusion component 30 refracts or scatters the light so that the beam divergence angle β of the emitted light is greater than the beam divergence angle α of the incident light. That is, as Figure 5As shown in (b) in FIG. 1 , the beam divergence angle β of the light emitted from the light diffuser 30 after passing through the light diffuser 30 becomes larger than the beam divergence angle α of the light emitted from the VCSEL (α<β). Therefore, if the light diffuser 30 is used, the area of ​​the irradiated surface irradiated by the light emitted from the light emitting element array 20 is expanded compared to the case where the light diffuser 30 is not used. In addition, the light density in the irradiated surface decreases. In addition, the light density refers to the irradiance, and the beam divergence angles α and β are the full width at half maximum (FWHM).

[0089] The light diffuser 30 has a rectangular shape in plan view, for example, and a width W in the x direction of x and the width W in the y direction y 1mm~10mm, thickness t in z direction d If the light diffuser 30 is of the above size and shape, it is particularly suitable for face recognition of a portable information processing terminal or measurement at a relatively close distance of about several meters. In addition, the planar shape of the light diffuser 30 may also be other shapes such as a polygon or a circle.

[0090] (Circuit for driving the light emitting element array 20)

[0091] When the light emitting element array 20 is to be driven at a higher speed, for example, low-side driving is preferably performed. Low-side driving refers to a structure in which a driving element such as a MOS transistor is located on the downstream side of a current path relative to a driving object such as a VCSEL. Conversely, a structure in which a driving element is located on the upstream side is called high-side driving.

[0092] Figure 6 1 is a diagram showing an example of an equivalent circuit for driving the light emitting element array 20 by low-side driving. Figure 6 , VCSELs of the light emitting element array 20, a driving unit 50, a capacitor 70, a power source 82, a PD 40, a light amount detection resistor 41 for detecting a current flowing through the PD 40, a TD 45, and a temperature detection resistor 46 for detecting a current flowing through the TD 45 are shown. The capacitor 70 is connected in parallel to the power source 82.

[0093] In addition, the power supply 82 is provided at Figure 2 The optical device control unit 8 is shown. The power supply 82 generates a DC voltage with the + side being a power supply potential and the - side being a ground potential. The power supply potential is supplied to the power supply line 83, and the ground potential is supplied to the ground line 84.

[0094] As described above, the light emitting element array 20 is composed of a plurality of VCSELs connected in parallel. Figure 4 ) is connected to the power line 83.

[0095] The driving unit 50 includes an n-channel MOS transistor 51 and a signal generating circuit 52 for turning on and off the MOS transistor 51. The drain of the MOS transistor 51 is connected to the cathode electrode 214 (refer to Figure 4 ) is connected. The source of the MOS transistor 51 is connected to the ground line 84. Moreover, the gate of the MOS transistor 51 is connected to the signal generating circuit 52. That is, the MOS transistor 51 of the VCSEL and driving unit 50 is connected in series between the power supply line 83 and the ground line 84. The signal generating circuit 52 generates an "H level" signal for setting the MOS transistor 51 to the conducting state and an "L level" signal for setting the MOS transistor 51 to the off state under the control of the optical device control unit 8.

[0096] One terminal of the capacitor 70 is connected to the power line 83, and the other terminal is connected to the ground line 84. That is, the capacitor 70 is connected in parallel with the power supply 82. When there are a plurality of capacitors 70, the plurality of capacitors 70 are connected in parallel. In addition, the capacitor 70 is, for example, an electrolytic capacitor or a ceramic capacitor.

[0097] The cathode electrode of the PD 40 is connected to the power line 83, and the anode electrode is connected to one terminal of the light amount detection resistor element 41. Furthermore, the other terminal of the light amount detection resistor element 41 is connected to the ground line 84. That is, the PD 40 and the light amount detection resistor element 41 are connected in series between the power line 83 and the ground line 84. Furthermore, the connection point between the PD 40 and the light amount detection resistor element 41, that is, the output terminal 42, is connected to the optical device control unit 8.

[0098] One terminal of the temperature detection resistor 46 is connected to the power line 83, and the other terminal is connected to one electrode of the TD45. Furthermore, the other electrode of the TD45 is connected to the ground line 84. That is, the temperature detection resistor 46 and TD45 are connected in series between the power line 83 and the ground line 84. Furthermore, the connection point of the temperature detection resistor 46 and TD45, that is, the output terminal 47, is connected to the optical device control unit 8.

[0099] Next, a method of driving the light emitting element array 20 which is low-side driving will be described.

[0100] First, assume that the signal generated by the signal generating circuit 52 in the driving unit 50 is at "L level". In this case, the MOS transistor 51 is in the off state. That is, the current does not flow between the source and the drain of the MOS transistor 51. Therefore, the current does not flow in the VCSELs connected in series. The VCSELs are non-luminescent.

[0101] At this time, capacitor 70 is charged by power supply 82. That is, one terminal of capacitor 70 connected to power supply line 83 is at power supply potential, and the other terminal connected to ground line 84 is at ground potential. Capacitor 70 accumulates charge determined by capacity, power supply voltage (=power supply potential - ground potential) and time.

[0102] Next, when the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "H level", the MOS transistor 51 changes from the off state to the on state. Then, the charge accumulated in the capacitor 70 is discharged, and current flows through the MOS transistor 51 and the VCSEL connected in series, and the VCSEL emits light.

[0103] When the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "L level", the MOS transistor 51 changes from the on state to the off state. Thus, the light emission of the VCSEL is stopped. Then, the power supply 82 starts to accumulate charges in the capacitor 70 again.

[0104] As described above, when the signal output from the signal generating circuit 52 changes to the "L level" and the "H level" each time, the MOS transistor 51 is repeatedly turned on and off, so that the light emission of the VCSEL repeats the stop state, that is, the non-light emission and the light emission. That is, the light pulse is emitted from the VCSEL. The repetition of the on and off of the MOS transistor 51 is sometimes called a switching. Here, Figure 6 As shown in the equivalent circuit of , the current path to the light emitting element array 20 composed of the light emitting element array 20, the MOS transistor 51 and the capacitor 70 is marked as a circuit or a circuit for driving the light emitting element array 20.

[0105] Here, the MOS transistor 51 is an example of a driving element for driving the light emitting element array 20. The driving element may be a field effect transistor or a bipolar transistor other than a MOS transistor. That is, the driving unit 50 includes the driving element. Therefore, here, the driving unit 50 is sometimes marked as a driving element.

[0106] Alternatively, the capacitor 70 may not be provided and charge (current) may be supplied directly to the VCSEL from the power supply 82. However, charge is accumulated in the capacitor 70, and when the MOS transistor 51 switches from on to off, the accumulated charge is discharged and current is rapidly supplied to the VCSEL, thereby shortening the start-up time of the light emission of the VCSEL.

[0107] The PD40 is connected in the reverse direction between the power line 83 and the ground line 84 via the light amount detection resistor element 41. Therefore, when the light is not irradiated, the current does not flow. As described above, if the PD40 receives a part of the light reflected by the light diffusion component 30 in the light emitted by the VCSEL, a current corresponding to the amount of light received flows in the PD40. Therefore, the current flowing through the PD40 is measured as the voltage of the output terminal 42, thereby detecting the light output of the light emitting element array 20. Here, the optical device control unit 8 controls the light output of the light emitting element array 20 to become a preset light output according to the amount of light received by the PD40. For example, when the light output of the light emitting element array 20 is less than the preset light output, the optical device control unit 8 increases the amount of charge accumulated in the capacitor 70 by increasing the power supply potential of the power supply 82, thereby increasing the current flowing through the VCSEL. On the other hand, when the light output of the light emitting element array 20 is greater than the preset light output, the amount of charge accumulated in the capacitor 70 is reduced by reducing the power supply potential of the power supply 82, thereby reducing the current flowing through the VCSEL. Thereby, the light output of the light emitting element array 20 is controlled.

[0108] Furthermore, when the amount of light received by the PD 40 is extremely reduced, the light diffusion component 30 falls off or is damaged, causing the light emitted by the light emitting element array 20 to directly irradiate the outside. In this case, the light output of the light emitting element array 20 is controlled by the optical device control unit 8. For example, the emission of light from the light emitting element array 20, that is, the irradiation of light to the object to be measured is stopped.

[0109] As described above, the PD 40 is provided to detect the light output of the light emitting element array 20. Therefore, the farther the PD 40 is arranged from the light emitting element array 20, the smaller the amount of light received becomes, and the lower the detection sensitivity of the light output of the light emitting element array 20 becomes. Therefore, the PD 40 is preferably arranged near the light emitting element array 20, for example.

[0110] TD45 is connected in series with the temperature detection resistor 46 between the power line 83 and the ground line 84. Therefore, the output terminal 47 becomes a voltage obtained by dividing the power supply voltage (=power supply potential-ground potential) by the temperature detection resistor 46 and TD45. When TD45 is, for example, a negative temperature coefficient thermistor (NTC), as described above, the resistance value decreases as the temperature of the substrate 100 increases. Therefore, the voltage of the output terminal 47 decreases as the temperature of the substrate 100 increases. The optical device control unit 8 detects the temperature of the substrate 100, that is, the light emitting element array 20, from the voltage of the output terminal 47. In addition, when the temperature of the light emitting element array 20 exceeds a preset allowable temperature, the operation of the light emitting element array 20 becomes unstable or the light emitting element array 20 is destroyed. Here, when it is detected from the voltage of the output terminal 47 that the temperature of the light emitting element array 20 exceeds the allowable temperature, the optical device control unit 8 controls the drive unit 50 to suppress the current flowing through the light emitting element array 20, or cuts off the current flowing through the light emitting element array 20. In this way, overheating of the light emitting element array 20 is suppressed.

[0111] As described above, TD45 is provided to detect the temperature of the light emitting element array 20. Therefore, the farther TD45 is arranged from the light emitting element array 20, the smaller the temperature change of TD45 becomes, and the lower the detection sensitivity of the temperature of the light emitting element array 20 becomes. Therefore, TD45 is preferably arranged near the light emitting element array 20, for example.

[0112] That is, the PD 40 and the TD 45 are examples of circuit elements to be arranged close to the light emitting element array 20 .

[0113] (Light emitting device 4)

[0114] Next, the light emitting device 4 will be described in detail.

[0115] Figure 7 This is a diagram for explaining a light emitting device 4 to which this embodiment is applied. Figure 7 (a) is a top view. Figure 7 (b) in the Figure 7 The cross-sectional view along line VIIB-VIIB of (a) is shown in FIG. Figure 7 (c) in Figure 7 The cross-sectional view of (a) below the line VIIC-VIIC. Figure 7 In (a), the right direction of the paper is set as the x direction, and the upward direction of the paper is set as the y direction. The direction perpendicular to the x direction and the y direction in the counterclockwise direction is set as the z direction. Figure 7 (b) Figure 7 In (c), the right direction of the paper is the x direction, and the upper direction of the paper is the z direction. The same applies to the same drawings shown below.

[0116] like Figure 7 (b) Figure 7 As shown in (c) in FIG. 1 , the light emitting device 4 includes a substrate 100 and a driving unit 50 on a wiring substrate 10. Furthermore, a light emitting element array 20, a PD 40, a TD 45, and a holding unit 60 are provided on the substrate 100. A light diffusion component 30 is provided on the holding unit 60. Figure 7 As shown in (a) in FIG. 1 , the light emitting element array 20, PD 40 and TD 45 are covered by the light diffusion member 30. Therefore, a part of the light emitted from the light emitting element array 20 and reflected by the back surface of the light diffusion member 30 is received by the PD 40. In addition, the holding portion 60 may be provided on the wiring substrate 10.

[0117] Moreover, if Figure 7 As shown in (a) of FIG. 1 , in the light emitting device 4, the PD 40 and the TD 45, the light emitting element array 20 and the driving unit 50 are arranged in a straight line along the x direction. That is, the MOS transistor 51 (refer to FIG. 1 ) which is the driving element Figure 6 ) is disposed on the side 21A side of the light emitting element array 20, and the PD40 and TD45 are disposed on the side 21B side of the light emitting element array 20. Moreover, the PD40 and TD45 are arranged in a line along the direction of the side 21B. That is, the PD40 and TD45 are arranged in the order of TD45 and PD40 along the y direction on the side 21B side of the light emitting element array 20.

[0118] By configuring like this, Figure 7 The distance D1 from the end of the light emitting element array 20 on the driving unit 50 side, that is, the side surface 21A, to the end of the light emitting element array 20 on the driving unit 50 is shorter than that of the comparative example described later (refer to the comparative example described later). Fig. 9 The distance D2 in (a) is connected to the cathode electrode 214 of the light emitting element array 20 and the drain of the MOS transistor 51 of the driving unit 50 (see Figure 6 ) of the light emitting element array cathode wiring pattern 12 (refer to the following Figure 8 (a)) is arranged in a straight line along the x direction. Therefore, if the distance D1 from the end of the light emitting element array 20 on the driving unit 50 side to the driving unit 50 is short, the length of the cathode wiring pattern 12 for the light emitting element array in the x direction becomes short. As a result, the inductance of the circuit driving the light emitting element array 20 becomes small, so that the light emitting element array 20 can be turned on and off at a high speed.

[0119] In the right Figure 7 (b) Figure 7 Before describing the cross-sectional view of the light emitting device 4 shown in FIG. 5 (c), the wiring patterns provided on the wiring substrate 10 and the base material 100 will be described in detail.

[0120] Figure 8 The diagrams are for explaining the wiring patterns of the wiring board 10 and the base material 100 provided in the light emitting device 4 to which the present embodiment is applied. Figure 8 (a) is the surface of the wiring substrate 10, Figure 8 (b) is the surface of the substrate 100, Figure 8 (c) in the figure is the back side of the substrate 100 .

[0121] The wiring substrate 10 is, for example, a three-layer multilayer substrate. That is, the wiring substrate 10 includes a first conductive layer, a second conductive layer, and a third conductive layer from the surface side on which the base material 100 or the drive unit 50 is mounted. In addition, an insulating layer is provided between the first conductive layer and the second conductive layer and between the second conductive layer and the third conductive layer. For example, the third conductive layer is provided as a power line 83, and the second conductive layer is provided as a ground line 84.

[0122] The first conductive layer, the second conductive layer, and the third conductive layer are made of conductive materials such as metals such as copper (Cu) and silver (Ag) or conductive pastes containing these metals, etc. The insulating layer is made of, for example, epoxy resin and ceramics.

[0123] Figure 8 (a) shows a wiring pattern based on the first conductive layer of the wiring substrate 10, but does not show a wiring pattern based on the second conductive layer, i.e., the ground line 84, and the third conductive layer, i.e., the power line 83. The second conductive layer and the third conductive layer are adhesive films except for the portion where the through hole is provided for connection with the wiring pattern composed of the first conductive layer.

[0124] like Figure 8 As shown in (a), the first conductive layer is used to form anode wiring patterns 11-1 and 11-2 for light emitting element arrays, which constitute a part of the current path to the light emitting element array 20, cathode wiring patterns 12 for light emitting element arrays, anode wiring patterns 13 for PDs, which constitute a part of the current path to PDs 40, cathode wiring patterns 14 for PDs, anode wiring patterns 15 for TDs, which constitute a part of the current path to TDs 45, and cathode wiring patterns 16 for TDs. In addition, when the anode wiring patterns 11-1 and 11-2 for light emitting element arrays and the cathode wiring patterns 12 for light emitting element arrays are not distinguished from each other, they are marked as wiring patterns or wiring. The same applies to other cases.

[0125] In this way, by configuring the wiring substrate 10 as a multi-layer substrate, the power line 83 as the third conductive layer, and the ground line 84 as the second conductive layer, it is easy to suppress the fluctuation of the power supply potential and the ground potential. In addition, the wiring pattern formed by the first conductive layer and the second conductive layer or the third conductive layer are electrically connected via a through hole. A through hole refers to a conductive portion formed by filling a conductive material in a hole that penetrates the wiring substrate 10 in the thickness direction.

[0126] Here, the anode wiring patterns 11-1 and 11-2 for the light emitting element array are wirings connected to the anode electrode 218 of the light emitting element array 20 via a wiring pattern provided on the substrate 100. The cathode wiring pattern 12 for the light emitting element array is wirings connected to the cathode electrode 214 of the light emitting element array 20 and the drain of the MOS transistor 51, which is an example of a driving element of the driving unit 50, via a wiring pattern provided on the substrate 100.

[0127] The PD anode wiring pattern 13 is connected to the anode electrode of the PD 40 via a wiring pattern provided on the substrate 100. The PD cathode wiring pattern 14 is connected to the cathode electrode of the PD 40 via a wiring pattern provided on the substrate 100. The anode electrode and cathode electrode of the PD 40 are terminals of the PD 40.

[0128] The TD anode wiring pattern 15 is a wiring connected to one terminal of the TD 45 (a terminal on the + side when polarity is provided) via a wiring pattern provided on the substrate 100. The TD cathode wiring pattern 16 is a wiring connected to the other terminal of the TD 45 (a terminal on the - side when polarity is provided) via a wiring pattern provided on the substrate 100.

[0129] Furthermore, a wiring pattern for connecting circuit components such as the capacitor 70, the resistor 6, and the capacitor 7 is formed through the first conductive layer. In addition, illustration of these wiring patterns is omitted.

[0130] The planar shape of the light emitting element array cathode wiring pattern 12 is a quadrilateral. The light emitting element array anode wiring patterns 11-1 and 11-2 are adjacently provided on the ±y direction side of the light emitting element array cathode wiring pattern 12 so as to face each other across the ±y direction.

[0131] The PD anode wiring pattern 13 and the PD cathode wiring pattern 14 are provided on the -x direction side of the light emitting element array anode wiring patterns 11-1, 11-2 and the light emitting element array cathode wiring pattern 12. Furthermore, the PD anode wiring pattern 13 is provided on the +y direction side, and the PD cathode wiring pattern 14 is provided in an L-shape bent from the center of the wiring substrate 10 toward the +y direction side. That is, the wiring connected to the anode electrode and the cathode electrode of the PD 40 is led out to the side 22A side of the light emitting element array 20.

[0132] The TD anode wiring pattern 15 and the TD cathode wiring pattern 16 are provided on the -x direction side of the light emitting element array anode wiring patterns 11-1, 11-2 and the light emitting element array cathode wiring pattern 12. Furthermore, the TD anode wiring pattern 15 is provided on the -y direction side, and the TD cathode wiring pattern 16 is provided in an inverted L shape bent from the center of the wiring substrate 10 to the -y direction side. That is, the wiring connected to the two terminals of the TD 45 is led out to the side 22B side of the light emitting element array 20.

[0133] The substrate 100 is made of an electrically insulating material. In addition, the light emitting element array 20 is provided on the substrate 100, so it is preferably made of a heat dissipation component that is electrically insulating and has a higher thermal conductivity than the wiring substrate 10. As an electrically insulating heat dissipation component, there are ceramics such as silicon nitride or aluminum nitride. If the substrate 100 is made of a heat dissipation component, the heat generated by the light emitting element array 20 is conducted to the holding portion 60 and the light diffusion component 30 via the substrate 100, and it becomes easy to dissipate heat, thereby improving the heat dissipation efficiency.

[0134] exist Figure 8 The surface of the substrate 100 shown in (b) is formed with anode wiring patterns 111-1F and 111-2F for light emitting element array, cathode wiring pattern 112F for light emitting element array, anode wiring pattern 113F for PD, cathode wiring pattern 114F for PD, anode wiring pattern 115F for TD, and cathode wiring pattern 116F for TD. Except for cathode wiring pattern 112F for light emitting element array, anode wiring patterns 111-1F and 111-2F for light emitting element array, anode wiring pattern 113F for PD, cathode wiring pattern 114F for PD, anode wiring pattern 115F for TD, and cathode wiring pattern 116F for TD are respectively connected to Figure 8The anode wiring patterns 11-1 and 11-2 for light emitting element array, the anode wiring pattern 13 for PD, the cathode wiring pattern 14 for PD, the anode wiring pattern 15 for TD, and the cathode wiring pattern 16 for TD shown in (a) are arranged on the wiring substrate 10 in the same plane shape. The length of the cathode wiring pattern 112F for light emitting element array in the x direction becomes shorter than the cathode wiring pattern 12 for light emitting element array of the wiring substrate 10. This is because a part of the +x direction side of the cathode wiring pattern 12 for light emitting element array is not covered with the substrate 100.

[0135] exist Figure 8 The back side of the substrate 100 shown in (c) is formed with anode wiring patterns 111-1B and 111-2B for light emitting element array, cathode wiring pattern 112B for light emitting element array, anode wiring pattern 113B for PD, cathode wiring pattern 114B for PD, anode wiring pattern 115B for TD, and cathode wiring pattern 116B for TD. The planar shapes of these wiring patterns are Figure 8 The anode wiring patterns 111-1F and 111-2F for the light emitting element array, the cathode wiring pattern 112F for the light emitting element array, the anode wiring pattern 113F for PD, the cathode wiring pattern 114F for PD, the anode wiring pattern 115F for TD, and the cathode wiring pattern 116F for TD formed on the surface of the substrate are mirror-reversed shapes.

[0136] Furthermore, the anode wiring patterns 111-1F, 111-2F for the light emitting element array, the cathode wiring pattern 112F for the light emitting element array, the anode wiring pattern 113F for PD, the cathode wiring pattern 114F for PD, the anode wiring pattern 115F for TD, and the cathode wiring pattern 116F for TD formed on the surface of the substrate 100 are electrically connected to the anode wiring patterns 111-1B, 111-2B for the light emitting element array, the cathode wiring pattern 112B for the light emitting element array, the anode wiring pattern 113B for PD, the cathode wiring pattern 114B for PD, the anode wiring pattern 115B for TD, and the cathode wiring pattern 116B for TD formed on the back side of the substrate 100 via conductive lines, i.e., through holes, which are provided through the thickness direction of the substrate 100 via the wiring patterns with the same number. Figure 7 (b) Figure 7 As shown in (c) of FIG. 1 , the number of the through hole pair wiring pattern is marked with "V". For example, Figure 7 As shown in (b), the anode wiring pattern 111-2F for the light emitting element array provided on the front surface is connected to the anode wiring pattern 111-2B for the light emitting element array provided on the back surface through a through hole 111-2V. By connecting a set of wiring patterns using a plurality of through holes, the inductance of the circuit is reduced.

[0137] Moreover, if Figure 7 As shown in FIG. 8 ( a ), a light emitting element array 20 , a PD 40 , and a TD 45 are mounted on a substrate 100 .

[0138] First, the cathode electrode 214 of the light emitting element array 20 is bonded to the cathode wiring pattern 112F for the light emitting element array of the substrate 100 by a conductive adhesive or the like (see Figure 4 ). Moreover, the anode electrode 218 of the light emitting element array 20 (refer to Figure 4 ) are connected to the anode wiring patterns 111-1F and 111-2F for the light emitting element array by bonding wires 23A and 23B.

[0139] Furthermore, the cathode electrode of PD40 is bonded to the cathode wiring pattern 114F for PD of the substrate 100 by a conductive adhesive, and the anode electrode of PD40 is connected to the anode wiring pattern 113F for PD of the substrate 100 by a bonding wire 23C. Furthermore, one terminal of TD45 (a + side terminal when having polarity) is connected to the anode wiring pattern 115F for TD of the substrate 100 by a conductive adhesive or solder, and the other terminal of TD45 (a - side terminal when having polarity) is connected to the cathode wiring pattern 116F for TD of the substrate 100 by a conductive adhesive or solder.

[0140] Moreover, in Figure 8 The substrate 100 is mounted at the position indicated by the dotted line of the wiring substrate 10 in (a). Thus, the anode wiring patterns 11-1 and 11-2 for the light emitting element array of the wiring substrate 10 are connected to the anode wiring patterns 111-1B and 111-2B for the light emitting element array of the substrate 100, and the cathode wiring pattern 12 for the light emitting element array of the wiring substrate 10 is connected to the cathode wiring pattern 112B for the light emitting element array of the substrate 100. Similarly, the anode wiring pattern 13 for PD of the wiring substrate 10 is connected to the anode wiring pattern 113B for PD of the substrate 100, and the cathode wiring pattern 14 for PD of the wiring substrate 10 is connected to the cathode wiring pattern 114B for PD of the substrate 100. The TD anode wiring pattern 15 of the wiring substrate 10 is connected to the TD anode wiring pattern 115B of the base 100, and the TD cathode wiring pattern 16 of the wiring substrate 10 is connected to the TD cathode wiring pattern 116B of the base 100. These connections are made, for example, by a conductive adhesive.

[0141] from Figure 8 As can be seen from (a), a portion of the cathode wiring pattern 12 for light emitting element array on the +x direction side is not covered by the substrate 100. Therefore, the drive unit 50 is mounted in a manner connected to the portion of the cathode wiring pattern 12 for light emitting element array not covered by the substrate 100.

[0142] Thus, the Figure 7 (a) Figure 7 (b) Figure 7 The light-emitting device 4 shown in (c) .

[0143] If reference Figure 7 (a) in the further description, by configuring the light emitting element array 20 on the cathode wiring pattern 112F for the light emitting element array of the substrate 100, the cathode electrode 214 (reference Figure 4 ) is connected to the cathode wiring pattern 112F for the light emitting element array. Figure 4 ) is connected to the anode wiring pattern 111-1F of the light emitting element array of the substrate 100 on the side 22A of the light emitting element array 20 by a bonding wire 23A. The anode electrode 218 (reference Figure 4 ) is connected to the anode wiring pattern 111-2F for the light emitting element array of the substrate 100 on the side 22B of the light emitting element array 20 by the bonding wire 23B. Moreover, the anode wiring pattern for the light emitting element array is not provided on the side 21A, 21B of the light emitting element array 20. That is, no bonding wire connecting the anode electrode 218 and the anode wiring pattern for the light emitting element array is provided on the side 21A, 21B of the light emitting element array 20. Therefore, the driving unit 50 can be arranged close to the light emitting element array 20, and an example of a circuit element to be arranged close to the light emitting element array 20, namely, PD40 and TD45, can be arranged close to the light emitting element array 20. Here, the bonding wires such as the bonding wires 23A, 23B are an example of a wiring component extending from the upper surface electrode of the light emitting element array 20 toward the outside of the light emitting element array 20.

[0144] Moreover, if Figure 7 As shown in the cross-sectional view taken along line VIIB-VIIB from the center of the wiring substrate 10 in the y direction toward the -y direction side in (b), the anode wiring pattern 111-2F for the light emitting element array on the surface of the substrate 100 is connected to the anode wiring pattern 111-2B for the light emitting element array on the back side of the substrate 100 via the through hole 111-2V, and the anode wiring pattern 111-2B for the light emitting element array is connected to the anode wiring pattern 11-2 for the light emitting element array of the wiring substrate 10. The same is true for the anode wiring pattern 111-1F for the light emitting element array, the anode wiring pattern 111-1B for the light emitting element array, and the anode wiring pattern 11-1 for the light emitting element array.

[0145] And, if Figure 7As shown in the cross-sectional view taken along line VIIC-VIIC of the central part of the wiring substrate 10 in the y direction in (a), the cathode wiring pattern 112F for the light emitting element array on the surface of the substrate 100 is connected to the cathode wiring pattern 112B for the light emitting element array on the back of the substrate 100 via the through hole 112V, and the cathode wiring pattern 112B for the light emitting element array is connected to the cathode wiring pattern 12 for the light emitting element array of the wiring substrate 10. The cathode wiring pattern 12 for the light emitting element array is connected to the driving unit 50.

[0146] The light emitting element array anode wiring patterns 11-1 and 11-2 are connected to one terminal of the capacitor 70. Alternatively, the capacitor 70 may be provided for each of the light emitting element array anode wiring patterns 11-1 and 11-2.

[0147] like Figure 7 As shown in the cross-sectional view (b) in FIG. 1 , the TD cathode wiring pattern 116F on the surface of the substrate 100 is connected to the TD cathode wiring pattern 116B on the back of the substrate 100 via the through hole 116V, and the TD cathode wiring pattern 116B is connected to the TD cathode wiring pattern 16 of the wiring board 10 .

[0148] Similarly, the TD anode wiring pattern 115F on the surface of the base material 100 is connected to the TD anode wiring pattern 115B on the back surface of the base material 100 via the through hole 115V, and the TD anode wiring pattern 115B is connected to the TD anode wiring pattern 15 of the wiring board 10 .

[0149] The wiring pattern for connecting the PD 40 is also the same, and therefore the description thereof is omitted.

[0150] In the light emitting device 4 of the present embodiment, the driving unit 50 including the driving element is arranged close to the side surface 21A of the light emitting element array 20. Furthermore, by arranging the PD 40 and the TD 45 to be arranged close to the light emitting element array 20 in parallel on the side surface 21B of the light emitting element array 20, the PD 40 and the TD 45 are arranged close to the light emitting element array 20. Hereinafter, a light emitting device 4' shown for comparison to which the present embodiment is not applied will be described.

[0151] (Light-emitting device 4' of comparative example)

[0152] Fig. 9 This is a plan view for explaining a light emitting device 4 ′ shown for comparison. Fig. 9 (a) is a top view. Fig. 9 (b) in the Fig. 9 The cross-sectional view along the IXB-IXB line in (a) is shown in FIG. Fig. 9 (c) in Fig. 9In the light emitting device 4', components having the same functions as those of the light emitting device 4 are denoted by the same reference numerals as those of the light emitting device 4, and their description is omitted.

[0153] In the light emitting device 4', the PD40 is disposed between the light emitting element array 20 and the driving unit 50 on the substrate 100. That is, the light emitting device 4' is configured such that the PD40 and the TD45 to be disposed close to the light emitting element array 20 sandwich the light emitting element array 20. That is, the PD40 is disposed close to the side surface 21A of the light emitting element array 20, and the TD45 is disposed close to the side surface 21B of the light emitting element array 20. Therefore, the distance D2 between the side surface 21A of the light emitting element array 20 and the end of the driving unit 50 including the driving element on the light emitting element array 20 side becomes greater than the distance D1 of the light emitting device 4. Therefore, the inductance of the circuit driving the light emitting element array 20 becomes larger, and it becomes difficult to turn on and off the light emitting element array 20 at a high speed.

[0154] Fig.10 This is a diagram for explaining a wiring pattern provided on a wiring board 10 and a base material 100 in a light emitting device 4 ′ shown for comparison. Fig.10 (a) is the surface of the wiring substrate 10, Fig.10 (b) is the surface of the substrate 100, Fig.10 (c) in the figure is the back side of the substrate 100 .

[0155] like Fig.10 As shown in (a) of FIG. 1 , the anode wiring pattern 13 for PD and the cathode wiring pattern 14 for PD are arranged in a manner opposite to each other in the ±y direction, sandwiching the cathode wiring pattern 12 for the light emitting element array. That is, the wiring connected to the anode electrode and the cathode electrode of PD40 are led out in opposite directions along the side 21A of the light emitting element array 20. Similarly, the anode wiring pattern 15 for TD and the cathode wiring pattern 16 for TD are arranged in a manner opposite to each other in the ±y direction. That is, the wiring connected to the anode electrode and the cathode electrode of TD45 are led out in opposite directions along the side 21B of the light emitting element array 20.

[0156] Moreover, if Fig.10 As shown in (a) of FIG. 1 , in the light emitting device 4′, in order to suppress the increase in the inductance of the circuit driving the light emitting element array 20, the planar shape of the cathode wiring pattern 12 for the light emitting element array is set to a quadrilateral, and the cathode electrode 214 of the light emitting element array 20 and the drain of the MOS transistor 51 of the driving unit 50 are connected in a straight line. For this purpose, the cathode wiring pattern 12 for the light emitting element array and the cathode wiring pattern 114F for the PD are three-dimensionally crossed with an electrically insulating member sandwiched therebetween.

[0157] Therefore, if Fig.10(b) Fig.10 As shown in (c) in FIG. 1 , the length of the PD cathode wiring pattern 114B corresponding to the PD cathode wiring pattern 114F in the y direction is made shorter than that of the PD cathode wiring pattern 114F in the -y direction. This prevents the PD cathode wiring pattern 114B from contacting the light emitting element array cathode wiring pattern 12 and causing a short circuit when the base material 100 is mounted on the portion indicated by the dotted line of the wiring substrate 10.

[0158] As described above, regarding the light emitting device 4' of the comparative example, if the cathode wiring pattern 12 for the light emitting element array is set to a quadrilateral shape in order to suppress the increase of the inductance of the circuit driving the light emitting element array 20, and if the cathode electrode 214 of the light emitting element array 20 and the driving unit 50 are to be connected in a straight line, the wiring is three-dimensionally crossed. That is, the electrically insulating substrate 100 is used.

[0159] On the other hand, in the light emitting device 4 to which this embodiment is applied, Figure 8 (a) Figure 8 (b) Figure 8 As can be seen from (c) in FIG. 1 , no circuit element is provided on the side surface 21A of the light emitting element array 20, so there is no need to provide wiring that crosses the cathode wiring pattern 12 for the light emitting element array. Figure 7 , Figure 8 In the embodiment, the substrate 100 is used, but the substrate 100 may not be used. Figure 8 On the wiring substrate 10 shown in (a) in FIG. 1 , the light emitting element array 20, the PD 40, and the TD 45 are mounted without the substrate 100. In this case, the wiring substrate 10 may be an electrically insulating heat dissipating member.

[0160] As described above, in the light emitting device 4 to which the present embodiment is applied, the driving unit 50 including the driving element is disposed close to the side surface 21A of the light emitting element array 20. Furthermore, the PD 40 and the TD 45 to be disposed close to the light emitting element array 20 are arranged in parallel along the side surface 21B on the side surface 21B of the light emitting element array 20. Thus, it becomes easy to bring the light emitting element array 20 and the driving unit 50 including the driving element close to each other.

[0161] In addition, in this embodiment, a light receiving element (PD40) for monitoring light quantity is described as an example of the first circuit element, and an element (TD45) for temperature detection is described as an example of the second circuit element. However, other circuit elements such as a capacitor 70 that supplies current to the light emitting element array 20 may be configured as the first circuit element or the second circuit element.

[0162] In the present embodiment, the light diffusion member 30 is used. However, the light diffusion member 30 may be replaced by a structure having a member that transmits light, for example, a transparent substrate such as a protective cover, or an optical member such as a condenser lens or a microlens array.

[0163] The above-mentioned embodiments of the present invention are provided for the purpose of illustration and description. In addition, the embodiments of the present invention do not fully and exhaustively include the present invention, and do not limit the present invention to the disclosed methods. Obviously, various modifications and changes are self-evident to those skilled in the art to which the present invention belongs. The present embodiment is selected and described in order to most easily understand the principles of the present invention and its application. Thus, other technicians in the art can understand the present invention through various variations optimized for specific uses assumed to be various embodiments. The scope of the present invention is defined by the above claims and their equivalents.

Claims

1. A light emitting device comprising: Wiring substrate; A light emitting element array having a first side surface and a second side surface facing each other and a third side surface and a fourth side surface facing each other connecting the first side surface and the second side surface, and disposed on the wiring substrate; A driving element, which is disposed on the wiring substrate on the first side surface and drives the light emitting element array; The first circuit element and the second circuit element are arranged side by side in a direction along the second side surface on the wiring substrate on the second side surface; and The wiring member is provided on the third side surface and the fourth side surface and extends from the upper surface electrode of the light emitting element array toward the outside of the light emitting element array.

2. The light emitting device according to claim 1, wherein: At least one of the first circuit element and the second circuit element is a light receiving element that receives light emitted by the light emitting element array.

3. The light emitting device according to claim 2, wherein: The other of the first circuit element and the second circuit element is a temperature detection element that detects the temperature of the light emitting element array.

4. The light emitting device according to any one of claims 1 to 3, wherein: No wiring member extending from the upper surface electrode of the light emitting element array toward the outside of the light emitting element array is provided between the second side surface and the first circuit element and the second circuit element.

5. The light emitting device according to any one of claims 1 to 3, wherein: The first circuit element and the second circuit element each have a plurality of terminals. The first circuit element is arranged closer to the third side surface than the second circuit element, and wirings respectively connected to the plurality of terminals of the first circuit element are led out to the third side surface. The second circuit element is arranged closer to the fourth side surface than the first circuit element, and wirings respectively connected to the plurality of terminals of the second circuit element are led out to the fourth side surface.

6. The light emitting device according to any one of claims 1 to 3, wherein: A light diffusion member for diffusing light emitted from the light emitting element array toward the outside is provided on an emission path of the light emitting element array.

7. The light emitting device according to claim 6, wherein: At least one of the first circuit element and the second circuit element is a light receiving element that receives light emitted by the light emitting element array. The light diffusion member is provided at a position where the light emitting element array and the light receiving element overlap in a plan view.

8. The light emitting device according to any one of claims 1 to 3, wherein: The light emitting element array has a plurality of light emitting elements connected in parallel to each other.

9. An optical device comprising: The light emitting device according to any one of claims 1 to 8; and a light receiving unit for receiving reflected light emitted from the light emitting element array of the light emitting device and reflected by the object to be measured, The light receiving unit outputs a signal corresponding to the time from when light is emitted from the light emitting element array to when light is received by the light receiving unit.

10. An information processing device comprising: The optical device of claim 9; and The shape determination unit determines the three-dimensional shape of the object to be measured based on the reflected light emitted from the light emitting element array of the optical device, reflected by the object to be measured, and received by the light receiving unit of the optical device.

11. The information processing device according to claim 10, comprising: The authentication processing unit performs authentication processing related to the use of the own device based on the determination result of the shape determination unit.

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