Overvoltage detection circuit, overcurrent detection circuit, and protection detection circuit

Abstract

The present invention provides an overvoltage detection circuit, an overcurrent detection circuit, and a protection detection circuit. Among them, the overvoltage detection circuit includes: a bandgap reference voltage generation circuit for generating a bandgap reference voltage BG, which includes an operational amplifier OP, a first bipolar transistor Q1, and a second bipolar transistor Q2; a voltage division circuit for generating a first detection voltage based on the input voltage to be detected; a comparator Comp1, whose first input terminal receives the bandgap reference voltage BG, and whose second input terminal receives the first detection voltage; wherein, the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors. Compared with the prior art, in the present invention, the bipolar transistors used to implement voltage detection and / or current detection can use the parasitic PNP bipolar transistors in the ordinary CMOS process, thereby reducing the photolithography steps and further reducing the production cost of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an overvoltage detection circuit, an overcurrent detection circuit, and a protection detection circuit in a battery protection chip.

Background Art

[0002] A battery protection circuit in the prior art, such as Chinese Patent Application No. 201110229489.6, realizes the functions of voltage detection and current detection by sharing a bipolar transistor. However, this implementation method requires an NPN bipolar transistor, which requires a special BiCMOS process, thus requiring an additional lithography step (compared with the ordinary CMOS process), resulting in an increase in cost (because the production cost of a chip generally increases with the increase in lithography steps).

[0003] Therefore, it is necessary to propose a new technical solution to overcome the above problems.

Summary of the Invention

[0004] One object of the present invention is to provide an overvoltage detection circuit, which can not only realize the overvoltage detection function, but also reduce the production cost of the chip.

[0005] Another object of the present invention is to provide an overcurrent detection circuit, which can not only realize the overcurrent detection function, but also reduce the production cost of the chip.

[0006] A third object of the present invention is to provide a protection detection circuit, which can not only realize the overvoltage detection function, but also realize the overcurrent detection function, and can also reduce the production cost of the chip.

[0007] According to one aspect of the present invention, the present invention provides an overvoltage detection circuit, which includes: a bandgap reference voltage generation circuit for generating a bandgap reference voltage BG, which includes an operational amplifier OP, a first bipolar transistor Q1, and a second bipolar transistor Q2; a voltage division circuit for generating a first detection voltage based on the input voltage to be detected; a comparator Comp1, whose first input terminal receives the bandgap reference voltage BG, and whose second input terminal receives the first detection voltage; wherein, the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors.

[0008] Further, the bandgap reference voltage generation circuit further includes a PMOS transistor MP1, and resistors R1, R2, and R3, and the voltage division circuit includes resistors R5 and R4.

[0009] Further, the source of the PMOS transistor MP1 is connected to the input voltage terminal VIN, its gate is connected to the output terminal of the operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through the sequentially connected resistors R1 and R3; the base and collector of the first bipolar transistor Q1 are both grounded; one end of the resistor R2 is connected to the drain of the PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; the base and collector of the second bipolar transistor Q2 are both grounded; the first input terminal of the operational amplifier OP is connected to the connection node A between the resistors R1 and R3, and its second input terminal is connected to the emitter of the second bipolar transistor Q2; the second input terminal of the comparator Comp1 is connected to the drain of the PMOS transistor MP1, and its first input terminal is connected to the connection node C between the resistors R4 and R5; the voltage on the drain of the PMOS transistor MP1 is the bandgap reference voltage BG, the resistors R4 and R5 are sequentially connected between the input voltage terminal VIN and the ground terminal, and the voltage at the connection node between the resistors R3 and R4 is the first detection voltage, wherein the voltage of the input voltage terminal VIN is the battery cell voltage, that is, the input voltage to be detected.

[0010] Further, the resistances of the resistors R1 and R2 are equal; the resistors R1 and R3 are of the same temperature type; the emitter area of the first bipolar transistor Q1 is larger than the emitter area of the second bipolar transistor Q2.

[0011] According to another aspect of the present invention, the present invention provides an overcurrent detection circuit, which includes: a current biasing circuit for generating a bias current, which includes an operational amplifier OP, a first bipolar transistor Q1 and a second bipolar transistor Q2; a comparison circuit including a comparator Comp2, the comparison circuit generates a reference voltage based on the bias current provided by the current biasing circuit, obtains a second detection voltage based on the bias current provided by the current biasing circuit and the input voltage to be detected VM, and the comparator Comp2 compares the reference voltage with the second detection voltage; wherein, the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors.

[0012] Further, the current bias circuit further includes PMOS transistors MP1, MP2, MP3, and resistors R1, R2, R3, R6, and R7. The PMOS transistors MP1, MP2, and MP3 are used to form a current mirror. The comparison circuit further includes a resistor R8, PMOS transistors MP4 and MP5. The PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current bias circuit. The PMOS transistor MP5 and the resistor R8 obtain a second detection voltage based on the bias current provided by the current bias circuit and the input voltage under test VM. Alternatively, the PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current bias circuit and the input voltage under test VM. The PMOS transistor MP5 and the resistor R8 generate a reference voltage based on the bias current provided by the current bias circuit.

[0013] Further, the gates of the PMOS transistors MP1, MP2, and MP3 are interconnected, and the sources are connected to the input voltage terminal VIN. The gate of the PMOS transistor MP1 is connected to the output terminal of the operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through the resistors R1 and R3 connected in series in sequence. The base and collector of the first bipolar transistor Q1 are both grounded. One end of the resistor R2 is connected to the drain of the PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2. The base and collector of the second bipolar transistor Q2 are both grounded. The first input terminal of the operational amplifier OP is connected to the connection node A between the resistors R1 and R3, and its second input terminal is connected to the emitter of the second bipolar transistor Q2. The resistor R6 is connected between the first input terminal of the operational amplifier OP and the ground terminal, and the resistor R7 is connected between the second input terminal of the operational amplifier OP and the ground terminal. The drain of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP4. The second input terminal of the comparator Comp2 is connected to the drain of the PMOS transistor MP2, and its first input terminal is connected to the drain of the PMOS transistor MP3. The gate of the PMOS transistor MP4 receives the input voltage under test VM or is grounded, and its drain is grounded. The drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP5 through the resistor R8. The drain of the PMOS transistor MP5 is grounded, and the gate of the PMOS transistor MP5 is grounded or receives the input voltage under test VM. Herein, the voltage of the input voltage terminal VIN is the voltage of the battery cell, and the input voltage under test VM is the conduction voltage of the power switch in the battery protection circuit.

[0014] Further, the resistance values of the resistors R1 and R2 are equal; the resistance values of the resistors R6 and R7 are equal; the resistors R1 and R3 are of the same temperature type; the emitter area of the first bipolar transistor Q1 is larger than the emitter area of the second bipolar transistor Q2; the ratio of the PMOS transistors MP1, MP2, and MP3 is 1:1:1.

[0015] According to another aspect of the present invention, the present invention provides a protection detection circuit, which is characterized in that it includes: a first bipolar transistor Q1, a second bipolar transistor Q2, and a switch group. The switch group includes several switches. By switching the several switches of the switch group, an overvoltage detection circuit is formed based on the first bipolar transistor Q1 and the second bipolar transistor Q2; by switching the several switches of the switch group, an overcurrent detection circuit is formed based on the first bipolar transistor Q1 and the second bipolar transistor Q2, wherein the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors.

[0016] Further, the protection detection circuit further includes an operational amplifier OP, a first comparator Comp1, and a second comparator Comp2. By switching the several switches of the switch group, an overvoltage detection circuit is formed based on the first bipolar transistor Q1, the second bipolar transistor Q2, the operational amplifier OP, and the first comparator Comp1. In the overvoltage detection circuit, a bandgap reference voltage generation circuit is formed based on the operational amplifier OP, the first bipolar transistor Q1, and the second bipolar transistor Q2. The bandgap reference voltage generation circuit is used to generate a bandgap reference voltage BG; by switching the several switches of the switch group, an overcurrent detection circuit is formed based on the first bipolar transistor Q1, the second bipolar transistor Q2, the operational amplifier OP, and the second comparator Comp2. In the overcurrent detection circuit, a current bias circuit is formed based on the operational amplifier OP, the first bipolar transistor Q1, and the second bipolar transistor Q2. The current bias circuit is used to generate a bias current.

[0017] Further, the protection detection circuit further includes: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9. In the overvoltage detection circuit, a bandgap reference voltage generation circuit is formed based on operational amplifier OP, first bipolar transistor Q1, second bipolar transistor Q2, resistor R1, resistor R2, and resistor R3, and the bandgap reference voltage generation circuit provides a bandgap reference voltage BG for the first comparator Comp1; a voltage division circuit is formed based on resistor R4, resistor R5, and / or resistor R9, and the voltage division circuit provides a first detection voltage for the first comparator Comp1; in the overcurrent detection circuit, a current bias circuit is formed based on operational amplifier OP, first bipolar transistor Q1, second bipolar transistor Q2, resistor R1, resistor R2, resistor R3, resistor R6, and R7; a comparison circuit is formed based on the second comparator Comp2 and resistor R8, and the current bias circuit provides a bias current for the comparison circuit.

[0018] Further, the protection detection circuit further includes PMOS transistors MP1, MP2, MP3, MP4, and MP5. In the overvoltage detection circuit, a bandgap reference voltage generation circuit is formed based on operational amplifier OP, first bipolar transistor Q1, second bipolar transistor Q2, resistor R1, resistor R2, resistor R3, and PMOS transistor MP1. Under the control of the switch group, the overvoltage detection circuit can be changed into a charging overvoltage detection circuit or a discharging overvoltage detection circuit. When it is a charging overvoltage detection circuit, a voltage division circuit is formed based on resistor R4, resistor R5, and resistor R9. When it is a discharging overvoltage detection circuit, a voltage division circuit is formed based on resistor R4 and resistor R5. In the overcurrent detection circuit, a current bias circuit is formed based on operational amplifier OP, first bipolar transistor Q1, second bipolar transistor Q2, resistor R1, resistor R2, resistor R3, resistor R6, resistor R7, PMOS transistors MP1, MP2, and MP3, and PMOS transistors MP1, MP2, and MP3 form a current mirror. A comparison circuit is formed based on second comparator Comp2, resistor R8, PMOS transistors MP4 and MP5. The comparison circuit generates a reference voltage based on the bias current provided by the current bias circuit, obtains a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected, and comparator Comp2 compares the reference voltage with the second detection voltage. Under the control of the switch group, the overcurrent detection circuit can be changed into a charging overcurrent detection circuit or a discharging overcurrent detection circuit. When the overcurrent detection circuit is a discharging overcurrent detection circuit, PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current bias circuit, and PMOS transistor MP5 and resistor R8 obtain a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected. When the overcurrent detection circuit is a charging overcurrent detection circuit, PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected, and PMOS transistor MP5 and resistor R8 generate a reference voltage based on the bias current provided by the current bias circuit.

[0019] Further, the gates of the PMOS transistors MP1, MP2, and MP3 are interconnected, and the sources are connected to the input voltage terminal VIN; the gate of the PMOS transistor MP1 is connected to the output terminal of the operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through the sequentially connected resistors R1 and R3; the base and collector of the first bipolar transistor Q1 are both grounded; one end of the resistor R2 is connected to the drain of the PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; the base and collector of the second bipolar transistor Q2 are both grounded; the first input terminal of the operational amplifier OP is connected to the connection node A between the resistors R1 and R3, and its second input terminal is connected to the emitter of the second bipolar transistor Q2; one end of the resistor R6 is connected to the first input terminal of the operational amplifier OP, and the other end is grounded through the first switch S1; one end of the resistor R7 is connected to the second input terminal of the operational amplifier OP, and the other end is connected to the other end of the resistor R6; the resistors R4, R9, and R5 are sequentially connected between the input voltage terminal VIN and the ground terminal, and the second switch S2 is connected in parallel with the resistor R9; the drain of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP4; the gate of the PMOS transistor MP4 is grounded through the switch S4, and its drain is grounded; the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP5 through the resistor R8; the gate of the PMOS transistor MP5 is grounded through the switch S6, and its drain is grounded; the input voltage under test VM is connected to the gate of the PMOS transistor MP4 through the switch S3, and the input voltage under test VM is connected to the gate of the PMOS transistor MP5 through the switch S5; the first input terminal of the comparator Comp1 is connected to the connection node between the resistors R9 and R5, and its second input terminal is connected to the drain of the PMOS transistor MP1; the second input terminal of the comparator Comp2 is connected to the drain of the PMOS transistor MP2, and its first input terminal is connected to the drain of the PMOS transistor MP3, where the voltage of the input voltage terminal VIN is the voltage of the battery cell, and the input voltage under test VM is the conduction voltage of the power switch in the battery protection circuit.

[0020] Further, when switch S1 is open and switch S2 is open, based on operational amplifier OP, comparator Comp1, first bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, R3, R4, R5, and R9, a charging overvoltage detection circuit is formed. Among them, based on operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, and R3, a bandgap reference voltage generation circuit is formed. The bandgap reference voltage generation circuit provides a bandgap reference voltage VBG with zero temperature coefficient for comparator Comp1. The bandgap reference voltage VBG is the voltage on the drain of PMOS transistor MP1; resistors R4, R5, and R9 form a voltage division circuit. The voltage division circuit samples the voltage of input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node between resistors R9 and R5; the signal output by comparator comp1 represents a charging overvoltage detection signal.

[0021] Further, when switch S1 is open and switch S2 is closed, based on operational amplifier OP, comparator Comp1, first bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, R3, R4, and R5, a discharging overvoltage detection circuit is formed. Among them, based on operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, and R3, a bandgap reference voltage generation circuit is formed. The bandgap reference voltage generation circuit provides a bandgap reference voltage VBG with zero temperature coefficient for comparator Comp1. The bandgap reference voltage VBG is the voltage on the drain of PMOS transistor MP1; resistors R4 and R5 form a voltage division circuit. The voltage division circuit samples the voltage of input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node between resistors R4 and R5; the signal output by comparator comp1 represents a discharging overvoltage detection signal.

[0022] Further, when switch S1 is turned on, S3 and S6 are turned on and S4 and S5 are open, a discharge overcurrent detection circuit is formed based on operational amplifier OP, comparator Comp2, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, and resistors R1, R2, R3, R6, R7 and R8. Among them, based on operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2 and MP3, and resistors R1, R2, R3, R6 and R7 form a current biasing circuit. The current biasing circuit provides a bias current with zero temperature coefficient for the comparison circuit. PMOS transistors MP1, MP2 and MP3 form a current mirror; based on resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2 form a comparison circuit. The PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current biasing circuit. PMOS transistor MP5 and resistor R8 obtain a second detection voltage based on the bias current provided by the current biasing circuit and the input voltage VM to be detected. The signal output by comparator comp2 represents the discharge overcurrent detection signal.

[0023] Further, when switch S1 is turned on, S3 and S6 are open and S4 and S5 are turned on, a charge overcurrent detection circuit is formed based on operational amplifier OP, comparator Comp2, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, and resistors R1, R2, R3, R6, R7 and R8. Among them, based on operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2 and MP3, and resistors R1, R2, R3, R6 and R7 form a current biasing circuit. The current biasing circuit provides a bias current with zero temperature coefficient for the comparison circuit. PMOS transistors MP1, MP2 and MP3 form a current mirror; based on resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2 form a comparison circuit. The PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current biasing circuit and the input voltage VM to be detected. PMOS transistor MP5 and resistor R8 generate a reference voltage based on the bias current provided by the current biasing circuit. The signal output by comparator comp2 represents the charge overcurrent detection signal.

[0024] Compared with the prior art, in the present invention, the bipolar transistor used to implement voltage detection and / or current detection can adopt the parasitic PNP bipolar transistor in the ordinary CMOS process, thereby reducing the photolithography steps and further reducing the production cost of the chip.

Description of the Drawings

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. Among them:

[0026] Figure 1 It is a schematic circuit diagram of a charging overvoltage detection circuit in an embodiment of the present invention;

[0027] Figure 2 It is a schematic circuit diagram of a discharging overcurrent detection circuit in an embodiment of the present invention;

[0028] Figure 3 It is a schematic circuit diagram of a charging overcurrent detection circuit in an embodiment of the present invention;

[0029] Figure 4 It is a schematic circuit diagram of a protection detection circuit in a battery protection chip in an embodiment of the present invention.

Specific Embodiments

[0030] To make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0031] As used herein, the term "an embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in an embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments. Unless otherwise specified, the terms indicating electrical connection such as "connected", "coupled", and "joined" herein all mean directly or indirectly electrically connected.

[0032] As can be seen from the foregoing background art, in Chinese Patent Application No. 201110229489.6, the voltage detection circuit uses an NPN bipolar transistor, which requires a special BiCMOS process. This NPN bipolar transistor has a large current amplification factor, thus requiring an additional lithography step (compared to ordinary CMOS processes). In ordinary CMOS processes, there are only parasitic PNP bipolar transistors, and the current amplification factor of such PNP bipolar transistors is very low, and the structure of 201110229489.6 cannot be achieved. The purpose of the present invention is to use only the parasitic PNP bipolar transistors in ordinary CMOS processes without using NPN bipolar transistors. Such an implementation can reduce the lithography step, thereby reducing the production cost of the chip.

[0033] Please refer to Figure 1As shown, it is a circuit schematic diagram of the charging overvoltage detection circuit in an embodiment of the present invention. Figure 1 The charging overvoltage detection circuit shown includes: an operational amplifier OP, a comparator Comp1, bipolar transistors Q1 and Q2, a PMOS transistor MP1, and resistors R1, R2, R3, R4, and R5. In Figure 1 the embodiment shown, the bipolar transistors Q1 and Q2 can be PNP bipolar transistors parasitic in a common CMOS process. Generally, the emitter area of the first bipolar transistor Q1 is designed to be larger than the emitter area of the second bipolar transistor Q2.

[0034] As Figure 1 shown, the specific connection relationships of each device are as follows: the source of the PMOS transistor MP1 is connected to the input voltage terminal VIN, its gate is connected to the output terminal of the operational amplifier OP, and its drain is connected to the emitter of the bipolar transistor Q1 through the resistors R1 and R3 connected in series in sequence; the base and collector of the first bipolar transistor Q1 are both grounded; one end of the resistor R2 is connected to the drain of the PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; the base and collector of the second bipolar transistor Q2 are both grounded; the non-inverting input terminal (which can be called the first input terminal) of the operational amplifier OP is connected to the connection node A between the resistors R1 and R3, and its inverting input terminal (which can be called the second input terminal) is connected to the emitter of the second bipolar transistor Q2; the resistors R4 and R5 are connected in series between the input voltage terminal VIN and the ground terminal; the inverting input terminal (which can be called the second input terminal) of the comparator Comp1 is connected to the drain of the PMOS transistor MP1, its non-inverting input terminal (which can be called the first input terminal) is connected to the connection node C between the resistors R4 and R5, and its output terminal is connected to the output terminal OC of the charging overvoltage detection circuit, where the voltage of the input voltage terminal VIN is the cell voltage, which can also be called the input voltage to be detected in this embodiment.

[0035] Among them, a bandgap reference voltage generation circuit is constituted by the operational amplifier OP, the first bipolar transistor Q1 and Q2, the PMOS transistor MP1, and the resistors R1, R2, and R3. The bandgap reference voltage generation circuit provides a bandgap reference voltage (or reference voltage) VBG with zero temperature coefficient for the comparator Comp1. The bandgap reference voltage VBG is the voltage at the drain (or node BG) of the PMOS transistor MP1; the resistors R4 and R5 constitute a voltage division circuit. The voltage division circuit samples the voltage of the input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node C between the resistors R4 and R5. The voltage division circuit provides the first detection voltage for the comparator Comp1.

[0036] Figure 1The working principle of the charging overvoltage detection circuit shown is as follows: The operational amplifier OP forms a negative feedback to adjust and make the voltages at its positive and negative input terminals equal. In this way, the voltage at point A (or connection node A) is equal to the base-emitter voltage (Vbe2) of the second bipolar transistor Q2, and the voltage at point B (or connection node B) is equal to the base-emitter voltage (Vbe1) of the first bipolar transistor Q1. The current through resistor R3 is equal to (Vbe2 - Vbe1) / R3 = ΔVbe / R3, where Vbe2 is the base-emitter voltage of the second bipolar transistor Q2, Vbe1 is the base-emitter voltage of the first bipolar transistor Q1, R3 is the resistance value of resistor R3, and ΔVbe is the difference between the base-emitter voltages of the second bipolar transistors Q2 and Q1. ΔVbe is a positive temperature coefficient voltage. If the resistance values of resistors R1 and R2 are equal, the currents of bipolar transistors Q1 and Q2 can be made equal because the voltage across resistor R1 is equal to the voltage across resistor R2. The voltage at point A is Vbe2, which has a negative temperature coefficient. The voltage VR1 across resistor R1 is (ΔVbe / R3).R1, where R1 is the resistance value of resistor R1. If resistors R1 and R3 are of the same type, their temperature coefficients can cancel each other out. Therefore, the voltage across resistor R1 has a positive temperature coefficient. The bandgap reference voltage VBG at node BG (or the drain of PMOS transistor MP1) is VBG = VR1 + Vbe2 = Vbe2 + (ΔVbe / R3).R1. By adjusting the appropriate ratio of R3 / R1, the temperature coefficients of the positive temperature coefficient voltage VR1 and the negative temperature coefficient voltage Vbe2 can be made equal and cancel each other out, thus achieving a bandgap reference voltage VBG with a zero temperature coefficient. The voltage at the input voltage terminal VIN, which is the voltage of the battery cell, is divided by resistors R4 and R5 and then compared with the bandgap reference voltage value VBG. When the voltage at point C (or connection node C) exceeds the bandgap reference voltage value VBG, the comparator Comp1 flips. Using this state change, the determination of charging overvoltage can be realized. Since the bandgap reference voltage VBG is very accurate and the voltage division ratio of resistors R4 and R5 is very accurate, the charging overvoltage threshold voltage of the input voltage terminal VIN can be accurately achieved.

[0037] Please refer to Figure 2 As shown, it is a schematic circuit diagram of the discharge overcurrent detection circuit in an embodiment of the present invention. Figure 2 The discharge overcurrent detection circuit shown includes: an operational amplifier OP, a comparator Comp2, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4, and MP5, and resistors R1, R2, R3, R6, R7, and R8. In Figure 2 In the embodiment shown, the bipolar transistors Q1 and Q2 can be PNP bipolar transistors parasitic in a common CMOS process. Generally, the emitter area of the first bipolar transistor Q1 is designed to be larger than the emitter area of the second bipolar transistor Q2.

[0038] As shown Figure 2 in the figure, the specific connection relationships of the components are as follows: the gates of PMOS transistors MP1, MP2, and MP3 are interconnected, and the sources are connected to the input voltage terminal VIN; the gate of PMOS transistor MP1 is connected to the output terminal of operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through a series connection of resistor R1 and resistor R3 in sequence; both the base and the collector of the first bipolar transistor Q1 are grounded; one end of resistor R2 is connected to the drain of PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; both the base and the collector of the second bipolar transistor Q2 are grounded; the non-inverting input terminal (which can be referred to as the first input terminal) of operational amplifier OP is connected to the connection node A between resistor R1 and resistor R3, and its inverting input terminal (which can be referred to as the second input terminal) is connected to the emitter of the second bipolar transistor Q2; resistor R6 is connected between the non-inverting input terminal (which can be referred to as the first input terminal) of the operational amplifier OP and the ground terminal, and resistor R7 is connected between the inverting input terminal (which can be referred to as the second input terminal) of the operational amplifier OP and the ground terminal; the drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP4; the gate of PMOS transistor MP4 receives the input voltage VM to be detected, and its drain is grounded; the drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP5 through resistor R8; both the gate and the drain of PMOS transistor MP5 are grounded; the inverting input terminal (which can be referred to as the second input terminal) of comparator Comp2 is connected to the drain of PMOS transistor MP2, its non-inverting input terminal (which can be referred to as the first input terminal) is connected to the drain of PMOS transistor MP3, and its output terminal is connected to the output terminal EDI of the discharge overcurrent detection circuit. Among them, the voltage of the input voltage terminal VIN is the cell voltage.

[0039] Among them, based on operational amplifier OP, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, and MP3, and resistors R1, R2, R3, R6, and R7, a current bias circuit is formed. The current bias circuit can provide a bias current with zero temperature coefficient for the comparison circuit, and PMOS transistors MP1, MP2, and MP3 form a current mirror; based on resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2, a comparison circuit is formed. PMOS transistor MP4 generates a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected. PMOS transistor MP5 and resistor 8 generate a reference voltage based on the bias current provided by the current bias circuit, and the comparator Comp2 compares the reference voltage and the second detection voltage.

[0040] Figure 2The working principle of the discharge overcurrent detection circuit shown is as follows: The operational amplifier OP forms a negative feedback to adjust and make the voltages at the positive and negative input terminals of the operational amplifier OP equal, that is, the voltage at point A (or connection node A) is equal to the base-emitter voltage Vbe2 of the second bipolar transistor Q2, and the voltage at point B (or connection node B) is equal to the base-emitter voltage Vbe1 of the first bipolar transistor Q1. Therefore, the current through resistor R3 is equal to (Vbe2 - Vbe1) / R3 = ΔVbe / R3, where Vbe2 is the base-emitter voltage of the second bipolar transistor Q2, Vbe1 is the base-emitter voltage of the first bipolar transistor Q1, R3 is the resistance value of resistor R3, and ΔVbe is the difference between the base-emitter voltages of bipolar transistors Q2 and Q1. ΔVbe is a voltage with a positive temperature coefficient. The current through resistor R6 is equal to Vbe2 / R6. The resistance values of resistors R1 and R2 are designed to be equal, and the resistance values of resistors R6 and R7 are designed to be equal, so that the current through the first bipolar transistor Q1 is equal to the current through the second bipolar transistor Q2. The current through the PMOS transistor MP1 is equal to the sum of the currents through resistor R1 and resistor R2, that is, twice the current through resistor R1. Since ΔVbe is a voltage with a positive temperature coefficient and Vbe2 is a voltage with a negative temperature coefficient, by designing an appropriate resistance value ratio of resistors R3 and R6, the temperature coefficients of the two can be offset. In this way, the current in the PMOS transistor MP1 can be a bias current with a zero temperature coefficient. The PMOS transistors MP3, MP2, and MP1 form a current mirror to copy the current of the PMOS transistor MP1. If their ratio is designed to be 1:1:1, the current through resistor R8 is equal to the current through the PMOS transistor MP3, equal to the current through the PMOS transistor MP1, and also equal to 2.(Vbe2 / R6 + ΔVbe / R3). Then the voltage across resistor R8 is equal to VR8 = 2.(Vbe2 / R6 + ΔVbe / R3).R8, where Vbe2 is the base-emitter voltage of the second bipolar transistor Q2, R6 is the resistance value of resistor R6, R3 is the resistance value of resistor R3, and R8 is the resistance value of resistor R8. In this way, a VR8 with a zero temperature coefficient can be generated. MP4 and MP5 are PMOS transistors with exactly the same size and type. Their function is to raise the detected input voltage VM and the ground voltage by a PMOS threshold voltage |Vthp| respectively. This circuit can compare the voltage of VM + |Vthp| (the second detection voltage) with the voltage of 0 + |Vthp| + VR8 (the reference voltage), which is equivalent to comparing the voltage of VM with VR8. Among them, the voltage of VR8 is designed to be a relatively accurate value with a zero temperature coefficient. The detected input voltage VM is the conduction voltage of the power switch in the battery protection circuit, so it reflects its conduction current, thus achieving the effect of detecting discharge overcurrent. When the output of the comparator Comp2 changes from high level to low level, it indicates that there is discharge overcurrent. The discharge overcurrent comparison threshold is VR8.

[0041] Please refer to Figure 3 as shown, which is a schematic circuit diagram of the charging overcurrent detection circuit in an embodiment of the present invention. Figure 3 The charging overcurrent detection circuit shown is the same as that of Figure 2 the discharging overcurrent detection circuit shown in terms of the components included. Figure 3 The charging overcurrent detection circuit shown includes: operational amplifier OP, comparator Comp2, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, resistors R1, R2, R3, R6, R7 and R8. In Figure 3 the embodiment shown, the bipolar transistors Q1 and Q2 can be PNP bipolar transistors parasitic in the ordinary CMOS process. Generally, the emitter area of the first bipolar transistor Q1 is designed to be larger than that of the second bipolar transistor Q2.

[0042] Figure 3 The connection relationship of the components in Figure 2 is basically the same as that of the components in Figure 3As shown, the specific connection relationships of the components are as follows: The gates of PMOS transistors MP1, MP2, and MP3 are interconnected, and the sources are connected to the input voltage terminal VIN; the gate of PMOS transistor MP1 is connected to the output terminal of operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through resistors R1 and R3 connected in series in sequence; both the base and the collector of the first bipolar transistor Q1 are grounded; one end of resistor R2 is connected to the drain of PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; both the base and the collector of the second bipolar transistor Q2 are grounded; the non-inverting input terminal (which can be referred to as the first input terminal) of operational amplifier OP is connected to the connection node A between resistors R1 and R3, and its inverting input terminal (which can be referred to as the second input terminal) is connected to the emitter of the second bipolar transistor Q2; resistor R6 is connected between the non-inverting input terminal (which can be referred to as the first input terminal) of the operational amplifier OP and the ground terminal, and resistor R7 is connected between the inverting input terminal (which can be referred to as the second input terminal) of the operational amplifier OP and the ground terminal; the drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP4; both the gate and the drain of PMOS transistor MP4 are grounded; the drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP5 through resistor R8; the gate of PMOS transistor MP5 receives the input voltage to be detected VM, and its drain is grounded; the inverting input terminal (which can be referred to as the second input terminal) of comparator Comp2 is connected to the drain of PMOS transistor MP2, its non-inverting input terminal (which can be referred to as the first input terminal) is connected to the drain of PMOS transistor MP3, and its output terminal is connected to the output terminal ECI of the discharge overcurrent detection circuit. Among them, the voltage of the input voltage terminal VIN is the voltage of the battery cell.

[0043] Among them, based on operational amplifier OP, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, and MP3, and resistors R1, R2, R3, R6, and R7, a current bias circuit is formed. The current bias circuit can provide a bias current with zero temperature coefficient for the comparison circuit, and PMOS transistors MP1, MP2, and MP3 form a current mirror; based on resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2 form a comparison circuit. PMOS transistor MP5 and resistor R8 generate a second detection voltage based on the bias current provided by the current bias circuit and the input voltage to be detected VM, and PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current bias circuit. The comparator Comp2 compares the reference voltage and the second detection voltage.

[0044] Figure 3 The discharge overcurrent detection circuit shown is the same as Figure 2 the working principle of the discharge overcurrent detection circuit shown is basically the same. Figure 3The working principle of the discharge overcurrent detection circuit shown is as follows: The operational amplifier OP forms a negative feedback to adjust and make the voltages at the positive and negative input terminals of the operational amplifier OP equal, that is, the voltage at point A (or connection node A) is equal to the base-emitter voltage Vbe2 of the second bipolar transistor Q2, and the voltage at point B (or connection node B) is equal to the base-emitter voltage Vbe1 of the first bipolar transistor Q1. Therefore, the current through resistor R3 is equal to (Vbe2 - Vbe1) / R3 = ΔVbe / R3, where Vbe2 is the base-emitter voltage of the second bipolar transistor Q2, Vbe1 is the base-emitter voltage of the first bipolar transistor Q1, R3 is the resistance value of resistor R3, and ΔVbe is the difference between the base-emitter voltages of bipolar transistors Q2 and Q1. ΔVbe is a voltage with a positive temperature coefficient. The current through resistor R6 is equal to Vbe2 / R6. The resistance values of resistors R1 and R2 are designed to be equal, and the resistance values of resistors R6 and R7 are designed to be equal, then the current of the first bipolar transistor Q1 is made equal to the current of the second bipolar transistor Q2. The current of the PMOS transistor MP1 is equal to the sum of the currents through resistor R1 and resistor R2, that is, twice the current through resistor R1. Since ΔVbe is a voltage with a positive temperature coefficient and Vbe2 is a voltage with a negative temperature coefficient, by designing an appropriate ratio of the resistance values of resistors R3 and R6, the temperature coefficients of the two can be offset. In this way, the current in the PMOS transistor MP1 can be a bias current with a zero temperature coefficient. The PMOS transistors MP3, MP2, and MP1 form a current mirror to copy the current of the PMOS transistor MP1. If their ratio is designed to be 1:1:1, then the current through resistor R8 is equal to the current of the PMOS transistor MP3, equal to the current of the PMOS transistor MP1, and also equal to 2.(Vbe2 / R6 + ΔVbe / R3). Then the voltage across resistor R8 is equal to VR8 = 2.(Vbe2 / R6 + ΔVbe / R3).R8, where Vbe2 is the base-emitter voltage of the second bipolar transistor Q2, R6 is the resistance value of resistor R6, R3 is the resistance value of resistor R3, and R8 is the resistance value of resistor R8. In this way, a VR8 with a zero temperature coefficient can be generated.The input voltage VM to be tested is raised by |Vthp| by MP5, and then after the VR8 voltage is superimposed (the second detection voltage), it is input to the positive input terminal of the comparator Comp2. The ground level is raised by |Vthp| (reference voltage) by the PMOS transistor MP4 and then input to the negative input terminal of the comparator Comp2. The PMOS transistors MP5 and MP4 are designed as devices with exactly the same type and size. Therefore, the |Vthp| raised by both is the same and can cancel each other out. Thus, the comparator Comp2 equivalently compares the voltage of VM + VR8 with the ground level (which can be regarded as 0V), and is also equivalent to comparing VM with -VR8 voltage. When the VM voltage changes from higher than -VR8 voltage to lower than -VR8 voltage, the output of the comparator Comp2 flips from high level to low level, indicating an overcurrent charging situation. The overcurrent charging comparison threshold is -VR8.

[0045] Please refer to Figure 4 as shown, which is a schematic circuit diagram of the protection detection circuit in the battery protection chip in an embodiment of the present invention. Figure 4 The protection detection circuit shown includes bipolar transistors Q1 and Q2, resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9, PMOS transistors MP1, MP2, MP3, MP4, and MP5, switches S1, S2, S3, S4, S5, and S6, operational amplifier OP, comparator Comp1, and comparator Comp2. In Figure 4 the embodiment shown, the bipolar transistors Q1 and Q2 can use the parasitic PNP bipolar transistors in the ordinary CMOS process. Generally, the emitter area of the first bipolar transistor Q1 is designed to be larger than the emitter area of the second bipolar transistor Q2.

[0046] As Figure 4As shown, the specific connection relationships of the components are as follows: The gates of PMOS transistors MP1, MP2, and MP3 are interconnected, and their sources are connected to the input voltage terminal VIN; the gate of PMOS transistor MP1 is connected to the output terminal of operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through a series connection of resistor R1 and resistor R3 in sequence; both the base and the collector of the first bipolar transistor Q1 are grounded; one end of resistor R2 is connected to the drain of PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; both the base and the collector of the second bipolar transistor Q2 are grounded; the non-inverting input terminal (which can be called the first input terminal) of operational amplifier OP is connected to the connection node A between resistor R1 and resistor R3, and its inverting input terminal (which can be called the second input terminal) is connected to the emitter of the second bipolar transistor Q2; one end of resistor R6 is connected to the non-inverting input terminal (which can be called the first input terminal) of the operational amplifier OP, and the other end is grounded through the first switch S1; one end of resistor R7 is connected to the inverting input terminal (which can be called the second input terminal) of the operational amplifier OP, and the other end is connected to the other end of resistor R6; resistors R4, R9, and R5 are connected in series between the input voltage terminal VIN and the ground terminal, and the second switch S2 is connected in parallel with resistor R9; the drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP4; the gate of PMOS transistor MP4 is grounded through switch S4, and its drain is grounded; the drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP5 through resistor R8; the gate of PMOS transistor MP5 is grounded through switch S6, and its drain is grounded; the input voltage to be tested VM is connected to the gate of PMOS transistor MP4 through switch S3, and the input voltage to be tested VM is connected to the gate of PMOS transistor MP5 through switch S5; the non-inverting input terminal (which can be called the first input terminal) of comparator Comp1 is connected to the connection node between resistor R9 and resistor R5, its inverting input terminal (which can be called the second input terminal) is connected to the drain of PMOS transistor MP1, and its output terminal is connected to the overvoltage output terminal OC-OD; the inverting input terminal (which can be called the second input terminal) of comparator Comp2 is connected to the drain of PMOS transistor MP2, its non-inverting input terminal (which can be called the first input terminal) is connected to the drain of PMOS transistor MP3, and its output terminal is connected to the output terminal ECI-EDI of the overcurrent detection circuit. Among them, the voltage of the input voltage terminal VIN is the voltage of the battery cell.

[0047] Figure 4 For the protection detection circuit shown, by switching switches S1 - S6, the first bipolar transistors Q1 and Q2 can be time-division multiplexed for overvoltage detection and / or overcurrent detection, thereby reducing the number of PNP transistors, effectively saving the area of the components, and reducing costs.

[0048] When switch S1 is open (or off) and switch S2 is open (or off), based on operational amplifier OP, comparator Comp1, bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, R3, R4, R5, and R9, a charging overvoltage detection circuit is formed. The circuit structure and operating principle of this charging overvoltage detection circuit are basically the same as those of Figure 1 the charging overvoltage detection circuit shown. Among them, based on operational amplifier OP, bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, and R3, a bandgap reference voltage generation circuit is formed. The bandgap reference voltage generation circuit provides a bandgap reference voltage (or reference voltage) VBG with zero temperature coefficient for comparator Comp1. The bandgap reference voltage VBG is the voltage at the drain (or node BG) of the PMOS transistor MP1; resistors R4, R5, and R9 form a voltage division circuit. The voltage division circuit samples the voltage of the input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node between resistors R9 and R5. The voltage division circuit provides the first detection voltage for comparator comp1. The signal output by comparator comp1 can represent the charging overvoltage detection signal.

[0049] When switch S1 is open and switch S2 is closed, based on operational amplifier OP, comparator Comp1, bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, R3, R4, and R5, a discharging overvoltage detection circuit is formed. The circuit structure and operating principle of this discharging overvoltage detection circuit are basically the same as those of Figure 1 the charging overvoltage detection circuit shown. Among them, based on operational amplifier OP, bipolar transistors Q1 and Q2, PMOS transistor MP1, and resistors R1, R2, and R3, a bandgap reference voltage generation circuit is formed. The bandgap reference voltage generation circuit provides a bandgap reference voltage (or reference voltage) VBG with zero temperature coefficient for comparator Comp1. The bandgap reference voltage VBG is the voltage at the drain (or node BG) of the PMOS transistor MP1; resistors R4 and R5 form a voltage division circuit. The voltage division circuit samples the voltage of the input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node between resistors R4 and R5. The voltage division circuit provides the first detection voltage for comparator comp1. The signal output by comparator comp1 can represent the discharging overvoltage detection signal.

[0050] When the switch S1 is turned on, S3 and S6 are turned on and S4 and S5 are open, a discharge overcurrent detection circuit is formed based on the operational amplifier OP, comparator Comp2, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, and resistors R1, R2, R3, R6, R7 and R8. The circuit structure and working principle of this discharge overcurrent detection circuit are the same as those of Figure 2 the discharge overcurrent detection circuit shown. Among them, based on the operational amplifier OP, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2 and MP3, and resistors R1, R2, R3, R6 and R7, a current bias circuit is formed. The current bias circuit can provide a bias current with zero temperature coefficient for the comparison circuit. The PMOS transistors MP1, MP2 and MP3 form a current mirror; based on the resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2, a comparison circuit is formed. The PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected. The PMOS transistor MP5 and resistor R8 generate a reference voltage based on the bias current provided by the current bias circuit. The signal output by the comparator comp2 can represent the discharge overcurrent detection signal.

[0051] When the switch S1 is turned on, S3 and S6 are open and S4 and S5 are turned on, a charge overcurrent detection circuit is formed based on the operational amplifier OP, comparator Comp2, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, and resistors R1, R2, R3, R6, R7 and R8. The circuit structure and working principle of this charge overcurrent detection circuit are the same as those of Figure 3 the charge overcurrent detection circuit shown. Among them, based on the operational amplifier OP, bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2 and MP3, and resistors R1, R2, R3, R6 and R7, a current bias circuit is formed. The current bias circuit can provide a bias current with zero temperature coefficient for the comparison circuit. The PMOS transistors MP1, MP2 and MP3 form a current mirror; based on the resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2, a comparison circuit is formed. The PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current bias circuit. The PMOS transistor MP5 and resistor R8 obtain a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected. The signal output by the comparator comp2 can represent the charge overcurrent detection signal.

[0052] In the present invention, terms indicating electrical connection such as "connected", "linked", "joined", "connected" etc., unless otherwise specified, represent direct or indirect electrical connection.

[0053] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited solely to the foregoing specific embodiments.

Claims

1. An overcurrent detection circuit, characterized in that, It includes: A current bias circuit for generating a bias current, which includes an operational amplifier OP, a first bipolar transistor Q1, and a second bipolar transistor Q2; A comparison circuit including a comparator Comp2, which generates a reference voltage based on the bias current provided by the current bias circuit, obtains a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected, and compares the reference voltage with the second detection voltage by the comparator Comp2; Wherein, the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors; The current bias circuit further includes PMOS transistors MP1, MP2, MP3, and resistors R1, R2, R3, R6, and R7, and the PMOS transistors MP1, MP2, and MP3 are used to form a current mirror; The comparison circuit further includes a resistor R8, PMOS transistors MP4 and MP5. The PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current bias circuit, and the PMOS transistor MP5 and the resistor R8 obtain a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected; or The PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current bias circuit and the input voltage VM to be detected, and the PMOS transistor MP5 and the resistor R8 generate a reference voltage based on the bias current provided by the current bias circuit. The gates of the PMOS transistors MP1, MP2, and MP3 are interconnected, and their sources are connected to the input voltage terminal VIN; the gate of the PMOS transistor MP1 is connected to the output terminal of the operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through the sequentially connected resistors R1 and R3 in series; the base and collector of the first bipolar transistor Q1 are both grounded; one end of the resistor R2 is connected to the drain of the PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; the base and collector of the second bipolar transistor Q2 are both grounded; the first input terminal of the operational amplifier OP is connected to the connection node A between the resistors R1 and R3, and its second input terminal is connected to the emitter of the second bipolar transistor Q2; the resistor R6 is connected between the first input terminal of the operational amplifier OP and the ground terminal, and the resistor R7 is connected between the second input terminal of the operational amplifier OP and the ground terminal; the drain of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP4; the second input terminal of the comparator Comp2 is connected to the drain of the PMOS transistor MP2, and its first input terminal is connected to the drain of the PMOS transistor MP3. The gate of the PMOS transistor MP4 receives the input voltage to be tested VM or is grounded, and its drain is grounded; the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP5 through the resistor R8; the drain of the PMOS transistor MP5 is grounded, and the gate of the PMOS transistor MP5 is grounded or receives the input voltage to be tested VM. Among them, the voltage of the input voltage terminal VIN is the cell voltage, and the input voltage to be tested VM is the conduction voltage of the power switch in the battery protection circuit.

2. The overcurrent detection circuit according to claim 1, wherein the resistance values of the resistors R1 and R2 are equal; the resistance values of the resistors R6 and R7 are equal; the resistors R1 and R3 are of the same temperature type; the emitter area of the first bipolar transistor Q1 is larger than the emitter area of the second bipolar transistor Q2; the ratio of the PMOS transistors MP1, MP2, and MP3 is 1:1:

1.

3. A protection detection circuit, characterized in that, It includes: a first bipolar transistor Q1, a second bipolar transistor Q2, a switch group, an operational amplifier OP, a first comparator Comp1, a second comparator Comp2, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, PMOS transistors MP1, MP2, MP3, MP4, and MP5, and the switch group includes several switches. Among them, the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors. By switching several switches of the switch group, an overvoltage detection circuit is formed based on the first bipolar transistor Q1, the second bipolar transistor Q2, the operational amplifier OP, and the first comparator Comp1. In the overvoltage detection circuit, a bandgap reference voltage generation circuit is formed based on an operational amplifier OP, a first bipolar transistor Q1, a second bipolar transistor Q2, a resistor R1, a resistor R2, a resistor R3, and a PMOS transistor MP1. The bandgap reference voltage generation circuit provides a bandgap reference voltage BG for a first comparator Comp1. Under the control of a switch group, the overvoltage detection circuit can be changed into a charging overvoltage detection circuit or a discharging overvoltage detection circuit. When it is a charging overvoltage detection circuit, a voltage dividing circuit is formed based on a resistor R4, a resistor R5, and a resistor R9. When it is a discharging overvoltage detection circuit, a voltage dividing circuit is formed based on a resistor R4 and a resistor R5. The voltage dividing circuit provides a first detection voltage for the first comparator Comp1. By switching several switches of the switch group, an overcurrent detection circuit is formed based on a first bipolar transistor Q1, a second bipolar transistor Q2, an operational amplifier OP, and a second comparator Comp2. In the overcurrent detection circuit, a current bias circuit is formed based on an operational amplifier OP, a first bipolar transistor Q1, a second bipolar transistor Q2, a resistor R1, a resistor R2, a resistor R3, a resistor R6, a resistor R7, PMOS transistors MP1, MP2, and MP3. The PMOS transistors MP1, MP2, and MP3 form a current mirror. A comparison circuit is formed based on a second comparator Comp2, a resistor R8, PMOS transistors MP4 and MP5. The comparison circuit generates a reference voltage based on the bias current provided by the current bias circuit, obtains a second detection voltage based on the bias current provided by the current bias circuit and a voltage under test VM, and the comparator Comp2 compares the reference voltage with the second detection voltage. Under the control of the switch group, the overcurrent detection circuit can be changed into a charging overcurrent detection circuit or a discharging overcurrent detection circuit. When the overcurrent detection circuit is a discharging overcurrent detection circuit, the PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current bias circuit, and the PMOS transistor MP5 and the resistor R8 obtain a second detection voltage based on the bias current provided by the current bias circuit and the voltage under test VM. When the overcurrent detection circuit is a charging overcurrent detection circuit, the PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current bias circuit and the voltage under test VM, and the PMOS transistor MP5 and the resistor R8 generate a reference voltage based on the bias current provided by the current bias circuit. The gates of the PMOS transistors MP1, MP2, and MP3 are interconnected, and the sources are connected to the input voltage terminal VIN; the gate of the PMOS transistor MP1 is connected to the output terminal of the operational amplifier OP, and its drain is connected to the emitter of the first bipolar transistor Q1 through the sequentially connected resistors R1 and R3; the base and collector of the first bipolar transistor Q1 are both grounded; one end of the resistor R2 is connected to the drain of the PMOS transistor MP1, and the other end is connected to the emitter of the second bipolar transistor Q2; the base and collector of the second bipolar transistor Q2 are both grounded; the first input terminal of the operational amplifier OP is connected to the connection node A between the resistors R1 and R3, and its second input terminal is connected to the emitter of the second bipolar transistor Q2; one end of the resistor R6 is connected to the first input terminal of the operational amplifier OP, and the other end is grounded through the first switch S1; one end of the resistor R7 is connected to the second input terminal of the operational amplifier OP, and the other end is connected to the other end of the resistor R6; the resistors R4, R9, and R5 are sequentially connected between the input voltage terminal VIN and the ground terminal, and the second switch S2 is connected in parallel with the resistor R9; the drain of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP4; the gate of the PMOS transistor MP4 is grounded through the switch S4, and its drain is grounded; the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP5 through the resistor R8; the gate of the PMOS transistor MP5 is grounded through the switch S6, and its drain is grounded; the input voltage under test VM is connected to the gate of the PMOS transistor MP4 through the switch S3, and the input voltage under test VM is connected to the gate of the PMOS transistor MP5 through the switch S5; the first input terminal of the comparator Comp1 is connected to the connection node between the resistors R9 and R5, and its second input terminal is connected to the drain of the PMOS transistor MP1; the second input terminal of the comparator Comp2 is connected to the drain of the PMOS transistor MP2, and its first input terminal is connected to the drain of the PMOS transistor MP3, wherein, the voltage of the input voltage terminal VIN is the voltage of the battery cell, and the input voltage under test VM is the conduction voltage of the power switch in the battery protection circuit.

4. The protection detection circuit according to claim 3, wherein, When switch S1 is open and switch S2 is open, based on operational amplifier OP, comparator Comp1, first bipolar transistors Q1 and Q2, PMOS transistor MP1, resistors R1, R2, R3, R4, R5 and R9, a charging overvoltage detection circuit is formed. Among them, based on operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistor MP1, resistors R1, R2 and R3, a bandgap reference voltage generation circuit is formed. The bandgap reference voltage generation circuit provides a bandgap reference voltage VBG with zero temperature coefficient for comparator Comp1. The bandgap reference voltage VBG is the voltage on the drain of the PMOS transistor MP1; resistors R4, R5 and R9 form a voltage division circuit. The voltage division circuit samples the voltage of the input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node between resistor R9 and R5; the signal output by comparator comp1 represents the charging overvoltage detection signal. When switch S1 is open and switch S2 is closed, based on operational amplifier OP, comparator Comp1, first bipolar transistors Q1 and Q2, PMOS transistor MP1, resistors R1, R2, R3, R4 and R5, a discharging overvoltage detection circuit is formed. Among them, based on operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistor MP1, resistors R1, R2 and R3, a bandgap reference voltage generation circuit is formed. The bandgap reference voltage generation circuit provides a bandgap reference voltage VBG with zero temperature coefficient for comparator Comp1. The bandgap reference voltage VBG is the voltage on the drain of the PMOS transistor MP1; resistors R4 and R5 form a voltage division circuit. The voltage division circuit samples the voltage of the input voltage terminal VIN to obtain a first detection voltage. The first detection voltage is the voltage at the connection node between resistor R4 and R5; the signal output by comparator comp1 represents the discharging overvoltage detection signal. When the switch S1 is turned on, S3 and S6 are turned on and S4 and S5 are open, based on the operational amplifier OP, comparator Comp2, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, and resistors R1, R2, R3, R6, R7 and R8, a discharge overcurrent detection circuit is formed. Among them, based on the operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2 and MP3, and resistors R1, R2, R3, R6 and R7, a current biasing circuit is formed. The current biasing circuit provides a bias current with zero temperature coefficient for the comparison circuit. PMOS transistors MP1, MP2 and MP3 form a current mirror; based on resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2 form a comparison circuit. The PMOS transistor MP4 generates a reference voltage based on the bias current provided by the current biasing circuit. PMOS transistor MP5 and resistor R8 obtain a second detection voltage based on the bias current provided by the current biasing circuit and the input voltage VM to be detected. The signal output by comparator comp2 represents the discharge overcurrent detection signal. When the switch S1 is turned on, S3 and S6 are open and S4 and S5 are turned on, based on the operational amplifier OP, comparator Comp2, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2, MP3, MP4 and MP5, and resistors R1, R2, R3, R6, R7 and R8, a charge overcurrent detection circuit is formed. Among them, based on the operational amplifier OP, first bipolar transistors Q1 and Q2, PMOS transistors MP1, MP2 and MP3, and resistors R1, R2, R3, R6 and R7, a current biasing circuit is formed. The current biasing circuit provides a bias current with zero temperature coefficient for the comparison circuit. PMOS transistors MP1, MP2 and MP3 form a current mirror; based on resistor R8, PMOS transistors MP4 and MP5, and comparator Comp2 form a comparison circuit. The PMOS transistor MP4 obtains a second detection voltage based on the bias current provided by the current biasing circuit and the input voltage VM to be detected. PMOS transistor MP5 and resistor R8 generate a reference voltage based on the bias current provided by the current biasing circuit. The signal output by comparator comp2 represents the charge overcurrent detection signal.

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