A device and method for generating random vectors obeying a certain distribution

Abstract

The present disclosure discloses a device and method for generating random vectors. The device includes: a storage unit for storing vector data related to random vector generation instructions; a register unit for storing scalar data related to random vector generation instructions; a control unit for decoding random vector generation instructions and controlling the execution process of random vector generation instructions; a random vector generation unit for generating random vectors that obey a specified distribution according to the decoded random vector generation instructions; wherein the random vector generation unit is a customized hardware circuit. The random vector generation device and method provided by the present disclosure implement the complete process of random vector generation instructions through customized hardware circuits, that is, the random vector generation operation can be realized through a random vector generation instruction.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a device and method for generating random vectors that obey a certain distribution. Random vectors of any length that obey a certain distribution can be generated according to instructions. There are many ways of random distribution, including but not limited to uniform distribution and Gaussian distribution. Background Art

[0002] A random vector is a vector in which each value is generated by a certain random distribution. In the restricted Boltzmann machine of an artificial neural network, there is a step that requires sampling a vector composed of a group of neurons, that is, comparing each neuron in the vector with a random number. If the value of the neuron is greater than the vector, it is 1, otherwise it is 0. This requires generating a group of random vectors composed of random numbers that obey a certain distribution and of the same size as the neuron vector. For example, if a group of 32-bit single-precision floating-point numbers is converted to 16-bit half-precision floating-point numbers, if the random carry method is selected, the truncated part needs to be compared with a random number that satisfies a certain distribution, and if it is greater than the random number, it is carried forward by 1. This also requires a group of random numbers that satisfy a certain distribution, namely a random vector.

[0003] In the prior art, one of the most commonly used methods for generating random vectors is to generate random numbers that satisfy a certain distribution one by one on a general-purpose processor. However, this method can only generate one random number at a time, and is inefficient when a large number is required. At the same time, multiple instructions are required to complete the process when generating random numbers.

[0004] Public Content

[0005] In view of this, the present disclosure provides a device and method for generating a random vector obeying a certain distribution, which is used to generate a random vector of any length that satisfies a certain distribution. According to instructions, multiple distributions and arbitrary lengths can be selected.

[0006] According to a first aspect of the present disclosure, a device for generating a random vector is provided, the device comprising:

[0007] A storage unit, used for storing vector data related to random vector generation instructions;

[0008] A register unit for storing scalar data related to random vector generation instructions;

[0009] A control unit, used for decoding the random vector generation instruction and controlling the execution process of the random vector generation instruction;

[0010] A random vector generation unit, used to generate a random vector obeying a specified distribution according to the decoded random vector generation instruction;

[0011] Wherein, the random vector generation unit is a customized hardware circuit.

[0012] Preferably, the scalar data stored in the register unit includes a random vector storage address, a random vector length and a distribution parameter related to a random vector generation instruction; wherein the random vector storage address is an address in the storage unit.

[0013] Preferably, the control unit comprises:

[0014] The instruction queue module is used to sequentially store the decoded random vector generation instructions and obtain scalar data related to the random vector generation instructions.

[0015] Preferably, the control unit comprises:

[0016] The dependency processing unit is used to determine whether there is a dependency relationship between the current random vector generation instruction and the previously unexecuted operation instruction before the random vector generation unit obtains the current random vector generation instruction.

[0017] Preferably, the control unit comprises:

[0018] The storage queue module is used to temporarily store the current random vector generation instruction when there is a dependency relationship between the current random vector generation instruction and the previously unexecuted operation instruction, and send the temporarily stored random vector generation instruction to the random vector generation unit when the dependency relationship is eliminated.

[0019] Preferably, the device further comprises:

[0020] An instruction cache unit, for storing random vector generation instructions to be executed;

[0021] The input-output unit is used to store vector data related to the random vector generation instruction in the storage unit, or to obtain vector data related to the random vector generation instruction from the storage unit.

[0022] Preferably, the random vector generation instruction includes an operation code and an operation field;

[0023] The operation code is used to instruct to perform a random vector generation operation of a specified distribution;

[0024] The operation field includes an immediate value and / or a register number, indicating scalar data related to random vector generation, wherein the register number points to the register unit address.

[0025] Preferably, the storage unit is a high-speed temporary storage memory.

[0026] According to a second aspect of the present disclosure, a device for generating a random vector is provided, wherein the device comprises:

[0027] An instruction fetch module is used to fetch the next random vector generation instruction to be executed from the instruction sequence and transmit the random vector generation instruction to the decoding module;

[0028] A decoding module, used for decoding the random vector generation instruction and transmitting the decoded random vector generation instruction to the instruction queue module;

[0029] An instruction queue module is used to temporarily store the decoded random vector generation instruction and obtain scalar data related to the random vector generation instruction from the random vector generation instruction or the scalar register; after obtaining the scalar data, the random vector generation instruction is sent to the dependency processing unit;

[0030] A scalar register file, comprising a plurality of scalar registers, for storing scalar data related to random vector generation instructions;

[0031] A dependency processing unit, used to determine whether there is a dependency between the random vector generation instruction and the previously unexecuted operation instruction; if there is a dependency, the random vector generation instruction is sent to the storage queue module; if there is no dependency, the random vector generation instruction is sent to the random vector generation unit;

[0032] A storage queue module, used for storing random vector generation instructions having a dependency relationship with previous operation instructions, and sending the random vector generation instructions to the random vector generation unit after the dependency relationship is released;

[0033] A random vector generation unit, configured to generate a random vector that obeys a specified distribution according to a received random vector generation instruction;

[0034] A high-speed scratchpad memory for storing the generated random vectors;

[0035] The input-output access module is used to directly access the high-speed temporary storage memory and is responsible for writing the generated random vector into the high-speed temporary storage memory.

[0036] Preferably, the random vector generation unit is a customized hardware circuit.

[0037] According to a third aspect of the present disclosure, a method for generating a random vector is provided, the method comprising:

[0038] The value fetching module fetches the next random vector generation instruction to be executed from the instruction sequence, and transmits the random vector generation instruction to the decoding module;

[0039] The decoding module decodes the random vector generation instruction and transmits the decoded random vector generation instruction to the instruction queue module;

[0040] The instruction queue module temporarily stores the decoded random vector generation instruction, and obtains scalar data related to the random vector generation instruction operation from the random vector generation instruction or the scalar register; after obtaining the scalar data, the random vector generation instruction is sent to the dependency processing unit;

[0041] The dependency processing unit determines whether there is a dependency relationship between the random vector generation instruction and the previously unexecuted operation instruction; if there is a dependency relationship, the random vector generation instruction is sent to the storage queue module; if there is no dependency relationship, the random vector generation instruction is sent to the random vector generation unit;

[0042] The storage queue module stores the random vector generation instruction that has a dependency relationship with the previous operation instruction, and sends the random vector generation instruction to the random vector generation unit after the dependency relationship is released;

[0043] The random vector generation unit generates a random vector that obeys a specified distribution according to the received random vector generation instruction, and writes the generated random vector into a high-speed temporary storage memory through the input and output access module.

[0044] The random vector generation device and method provided by the present disclosure realizes the complete process of random vector generation instruction through customized hardware circuit, that is, the random vector generation operation can be realized through one random vector generation instruction. The present disclosure temporarily stores the vector data involved in the calculation in a high-speed scratchpad memory (Scratchpad Memory), so that vector data of different widths can be supported more flexibly and effectively. At the same time, the customized random number generation unit can more efficiently generate random data that obeys various distributions, and improve the execution performance of algorithms that require a large number of random vectors. The present disclosure uses one instruction to generate a group of random vectors.

[0045] The present disclosure can be applied to the following scenarios (including but not limited to): various electronic products such as data processing, robots, computers, printers, scanners, telephones, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, etc.; various means of transportation such as airplanes, ships, and vehicles; various household appliances such as televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; and various medical equipment such as magnetic resonance imaging, B-ultrasound, and electrocardiographs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of the structure of the random vector generating device provided by the present disclosure.

[0047] Figure 2It is a format diagram of the random vector generation instruction provided by the present disclosure.

[0048] Figure 3 It is a schematic diagram of the structure of a random vector generating device provided in an embodiment of the present disclosure.

[0049] Figure 4 It is a flowchart of a random vector generation method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0051] The present disclosure provides a device for generating random vectors, including a storage unit, a register unit, a control unit and a random vector generation unit, wherein the storage unit is used to store vectors, the register unit is used to store vector storage addresses and other scalar parameters, the control unit is used to perform decoding operations, and each module is controlled according to an instruction, and the random vector generation unit obtains the vector storage address, distribution parameters, length and other parameters in the instruction or the register unit according to the random vector generation operation instruction, and then generates a random vector that meets the distribution and length specified by the instruction. In the present disclosure, the storage unit adopts a high-speed temporary storage memory, and the present disclosure temporarily stores the generated vector data in the high-speed temporary storage memory, so that vector data of different widths can be supported more flexibly and effectively during the operation process, and the execution performance of algorithms that require a large amount of random vector data is improved.

[0052] Figure 1 is a schematic diagram of the structure of a device for generating a random vector provided by the present disclosure, such as Figure 1 As shown, the device comprises:

[0053] A storage unit is used to store vector data related to random vector generation instructions. In one embodiment, the storage unit can be a high-speed scratchpad memory that can support vector data of different sizes. The present disclosure temporarily stores necessary calculation data in the high-speed scratchpad memory, so that the device can more flexibly and effectively support data of different widths. The vector data related to the random vector generation instruction includes the generated random vector. The high-speed scratchpad memory can be implemented by various different storage devices such as SRAM, DRAM, eDRAM, memristor, 3D-DRAM and non-volatile storage.

[0054] The register unit is used to store scalar data related to random vector generation, such as the storage address of the generated random vector, and can also be used to store scalar data used in other operations, such as the distribution parameters specified by the random vector generation instruction, such as the upper and lower bounds of the uniform distribution, the mean and variance of the Gaussian distribution. Among them, the storage address of the generated random vector is the address where the vector is stored in the storage unit.

[0055] The control unit is used to decode the random vector generation instruction and control the execution process of the random vector generation instruction; it mainly controls the execution process of the random vector generation instruction by controlling the behavior of each module in the device; in one embodiment, the control unit reads the prepared instruction, decodes it to generate a control signal, and sends it to other modules in the device, and the other modules perform corresponding operations according to the obtained control signal.

[0056] A random vector generation unit, which generates a random vector of a specified length that obeys a specified distribution according to instructions. This unit is a vector operation unit, and generates each element in the random vector at the same time. The random vector generation unit is a customized hardware circuit, including but not limited to FPGA, CGRA, application-specific integrated circuit ASIC, analog circuit and memristor, etc.; the random vector generation unit can generate a random vector of any length that obeys a specified distribution by cooperating with other modules in the device.

[0057] It should be noted that, in response to different requirements for random vector generation, the random vector generation unit actually contains multiple parallel random number generation modules, each of which can generate a random number during each execution. Therefore, when generating a random vector, it is actually multiple parallel random number generation modules that continuously generate several random vector segments, and finally obtain a random vector of the required length. For each random number generation module, it contains two main parts to meet the requirements of generating random numbers with arbitrary distribution.

[0058] In one embodiment, the random vector generation unit includes two modules:

[0059] One is the LFSR module, which is used to generate random numbers that obey a uniform distribution. In addition, it can also generate true random numbers by detecting the thermal noise of the resistor;

[0060] The second is the Ziggurat algorithm module, which is used to generate random numbers that obey arbitrary distribution (such as Gaussian distribution). The LFSR module needs to be called during execution. The module that generates uniformly distributed random numbers needs to be configured with a random seed at the beginning, and different modules can be configured with different random seeds.

[0061] According to an embodiment of the present disclosure, the device further includes: an instruction cache unit, which is used to store the operation instructions to be executed. During the execution process, the instructions are also cached in the instruction cache unit. After an instruction is executed, if the instruction is also the earliest instruction among the instructions that have not been submitted in the instruction cache unit, the instruction will be submitted.

[0062] According to one embodiment of the present disclosure, the control unit in the device also includes: an instruction queue module, which is used to sequentially store the decoded random vector generation instructions, which obtains scalar data related to the random vector generation instructions through the operation field in the random vector generation instructions, such as the specified distribution parameters, random vector length and random vector storage address, etc., fills it into the random vector generation instruction and sends it to the dependency processing unit.

[0063] According to one embodiment of the present disclosure, the control unit of the device further includes: a dependency processing unit, which is used to determine whether the random vector generation instruction has a dependency relationship with the previously unexecuted instruction before the random vector generation unit obtains the instruction, such as whether the same vector storage address is accessed. If there is a dependency relationship, the random vector generation instruction is stored in the storage queue module, and after the operation instruction with which it has a dependency relationship is executed, the storage queue module provides the random vector generation instruction to the random vector generation unit; otherwise, the random vector generation instruction is directly provided to the random vector generation unit. Specifically, when the random vector generation instruction accesses the high-speed temporary storage memory, the previous and next instructions may access the same storage space. In order to ensure the correctness of the instruction execution result, if the current instruction is detected to have a dependency relationship with the data of the previous instruction, the instruction must wait in the storage queue until the dependency is eliminated.

[0064] According to one embodiment of the present disclosure, the control unit of the device also includes: a storage queue module, which includes an ordered queue, and instructions that have data dependencies on previous instructions are stored in the ordered queue until the dependency is eliminated. After the dependency is eliminated, it provides the operation instructions to the random vector generation unit.

[0065] According to an embodiment of the present disclosure, the device further includes: an input-output unit, which is used to store the generated random vector in the storage unit and is responsible for reading vector data from the memory or writing vector data.

[0066] According to an embodiment of the present disclosure, the instruction design of the device enables one instruction to generate a random vector of any length.

[0067] In the process of generating random vectors by the device, the device takes out the instruction for decoding, and then sends it to the instruction queue for storage. According to the decoding result, the various parameters in the instruction are obtained. These parameters can be directly written in the operation domain of the instruction, or read from the specified register according to the register number in the instruction operation domain. The advantage of using registers to store parameters is that there is no need to change the instruction itself. As long as the value in the register is changed by the instruction, most of the loops can be realized, thus greatly saving the number of instructions required to solve certain practical problems. After obtaining all operands, the dependency processing unit will determine whether the data actually needed by the instruction has a dependency relationship with the previous instruction, which determines whether this instruction can be immediately sent to the operation unit for execution. Once it is found that there is a dependency relationship with the previous data, the instruction must wait until the instruction it depends on is executed before it can be sent to the operation unit for execution. In the customized operation unit, the instruction will be executed quickly, and the result, that is, the generated random vector, will be written back to the address provided by the instruction, and the instruction will be executed.

[0068] Figure 2 is a schematic diagram of the format of the random vector generation instruction provided by the present disclosure, such as Figure 2 As shown, the random vector generation instruction includes an operation code and at least one operation field, wherein the operation code is used to indicate the random vector to be generated according to a distribution, such as Gaussian distribution or uniform distribution, etc.; the operation field is used to indicate the data information of the operation instruction, wherein the data information can be an immediate number or a register number. For example, when a vector is to be generated, the output vector storage start address and vector length, as well as the distribution parameters can be obtained in the corresponding register according to the register number, and then the random vector generated according to the distribution is stored in the specified address.

[0069] In one embodiment of the present disclosure, the following random vector generation instructions can be implemented:

[0070] A uniform distribution instruction (UNIF), according to which the device reads the upper bound parameter and the lower bound parameter of the uniform distribution, as well as the size and storage address of the random vector to be generated from the instruction or from the register file, and then generates a random vector that obeys the uniform distribution in the random vector generation unit, and writes the generated random vector result back to the storage address of the specified high-speed scratch pad memory.

[0071] Gaussian distribution instruction (GAUS), according to which the device reads the mean parameter and variance parameter of the Gaussian distribution, as well as the size and storage address of the random vector to be generated from the instruction or from the register file, and then generates a random vector that obeys the Gaussian distribution in the random vector generation unit, and writes the generated random vector result back to the storage address of the specified high-speed cache memory.

[0072] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0073] Figure 3 is a schematic diagram of the structure of a random vector generating device provided by an embodiment of the present disclosure, such as Figure 3 As shown, the device includes an instruction fetch module, a decoding module, an instruction queue, a scalar register file, a dependency processing unit, a storage queue, a random vector generation unit, a high-speed register, and an IO memory access module;

[0074] The instruction fetch module is responsible for fetching the next instruction to be executed from the instruction sequence and passing it to the decoding module;

[0075] The decoding module is responsible for decoding the instructions and passing the decoded instructions to the instruction queue;

[0076] Instruction queue module, which is used to temporarily store instructions obtained from the decoding module and obtain data corresponding to instruction operations from instruction or scalar registers, including the length of the generated random vector, storage address and distribution parameters. After obtaining the scalar data, the instruction is sent to the dependency processing unit;

[0077] Scalar register file, which provides the scalar registers required by the device during operation. Various scalar parameters can be given directly in the operation domain of the instruction or read from the scalar register file;

[0078] The dependency processing unit is used to process the storage dependency that may exist between the random vector generation instruction and the previously unexecuted instruction. The random vector generation instruction may access the high-speed temporary storage memory, such as storing the generated random vector in the high-speed temporary storage memory, and the previous and subsequent instructions may access the same storage space. In order to ensure the correctness of the instruction execution result, if the current instruction is detected to have a dependency relationship with the data of the previous instruction, the instruction is sent to the storage queue module to wait until the dependency relationship is eliminated. That is, it is detected whether the storage interval of the input data of this instruction overlaps with the storage interval of the output data of the previously unexecuted instruction. The storage interval is determined by the starting address and the data length. If there is an overlap, it means that this instruction actually requires the execution result of the previous instruction as input, so it must wait until that instruction is executed before this instruction can start execution. In this process, the instruction is actually temporarily stored in the storage queue module.

[0079] A storage queue module, which is an ordered queue. Instructions that have data dependencies with previous instructions are stored in the queue until the storage relationship is eliminated. The random vector generation instructions after the dependency is eliminated are sent to the random vector generation unit.

[0080] A random vector generation unit, which generates a random vector that obeys a specified distribution according to an instruction; the random vector generation unit is implemented as a customized hardware circuit, including but not limited to FPGA, CGRA, application-specific integrated circuit ASIC, analog circuit and memristor, etc.;

[0081] A high-speed temporary storage memory, which is a temporary storage device dedicated to vector data and can support vector data of different sizes; the high-speed temporary storage memory can be used to store the generated random vectors;

[0082] IO memory access module, which is used to directly access the high-speed temporary storage memory and is responsible for reading data from or writing data to the high-speed temporary storage memory.

[0083] Figure 4 is a flow chart of a computing device provided by an embodiment of the present disclosure executing a uniform distribution instruction to generate a random vector satisfying a uniform distribution, such as Figure 4 As shown, the process of executing uniformly distributed instructions includes:

[0084] S1, the instruction fetch module fetches the random number generation instruction and sends the instruction to the decoding module.

[0085] S2, the decoding module decodes the instruction and sends the instruction to the instruction queue.

[0086] S3, in the instruction queue, the random number generation instruction obtains the scalar data corresponding to the four operation fields in the instruction from the instruction itself or from the scalar register stack, including the storage address of the generated random vector, the length of the generated random vector, and the upper and lower bounds of the uniform distribution.

[0087] S4, after obtaining the required scalar data, the instruction is sent to the dependency processing unit.

[0088] S5, the dependency processing unit analyzes whether the instruction has a data dependency with the previous instruction that has not yet been executed. If there is a dependency, the instruction is sent to the storage queue module to wait until it no longer has a data dependency with the previous instruction that has not yet been executed. If there is no dependency, the instruction is directly sent to the random vector generation unit.

[0089] S6, the random vector generation unit generates a random vector of a certain length satisfying the uniform distribution through a hardware circuit according to the upper and lower bound parameters.

[0090] S7, the random vector generation unit continues to generate random vectors of a certain length until the generation of random vectors of a specified length is completed.

[0091] S8, after the operation is completed, the result vector is written back to the specified address of the high-speed temporary storage memory.

[0092] In summary, the present disclosure provides a random vector generation device, which, in conjunction with corresponding instructions, can well solve the increasing number of computing tasks in the current computer field that generate random vectors that meet a certain distribution. Compared with existing traditional solutions, the present disclosure can have the advantages of being easy to use, supporting flexible vector lengths, and having sufficient on-chip cache.

[0093] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A device for generating a random vector, characterized in that: include: A control unit, configured to decode a random vector generation instruction and control an execution process of the random vector generation instruction, wherein the random vector generation instruction comprises an operation code and an operation field, wherein the operation code is used to instruct to execute a random vector generation operation of a specified distribution, and the operation field is used to indicate scalar data related to random vector generation, wherein the scalar data comprises a random vector length and / or distribution parameters related to the random vector generation instruction; A random vector generating unit, configured to perform the random vector generating operation according to the scalar data to generate a random vector obeying a specified distribution; A storage unit, used to store vector data related to the random vector generation instruction; wherein, The distribution parameters include upper bound parameters, lower bound parameters and / or mean parameters, variance parameters, and the device is used to reading the upper bound parameter and the lower bound parameter of the uniform distribution, and the length and storage address of the random vector to be generated, the random vector generation unit generates a random vector that obeys the uniform distribution, and writes the generated random vector result back to the storage unit; and / or The mean parameter and the variance parameter of the Gaussian distribution, as well as the length and storage address of the random vector to be generated are read; the random vector generation unit generates a random vector that obeys the Gaussian distribution, and writes the generated random vector result back to the storage unit.

2. The device according to claim 1, characterized in that The scalar data includes a random vector storage address associated with the random vector generation instruction.

3. The device according to claim 2, characterized in that The operation field includes an immediate value and / or a register number, and the device further includes: A register unit, used for storing scalar data related to the random vector generation instruction; The random vector storage address is an address in the storage unit, and the register number points to the register unit address.

4. The device according to claim 1, characterized in that The control unit comprises: The dependency processing unit is used to determine whether there is a dependency relationship between the current random vector generation instruction and the previously unexecuted operation instruction before the random vector generation unit obtains the current random vector generation instruction.

5. The device according to claim 1, characterized in that The random vector generating unit comprises: LFSR module for generating random numbers from a uniform distribution, and / or Generate true random numbers by detecting the thermal noise of resistors; and / or The Ziggurat algorithm module is used to generate random numbers that obey an arbitrary distribution, wherein the arbitrary distribution includes a Gaussian distribution.

6. A method for generating a random vector, characterized in that include: Decoding a random vector generation instruction and controlling the execution process of the random vector generation instruction, wherein the random vector generation instruction includes an operation code and an operation field, wherein the operation code is used to indicate the execution of a random vector generation operation of a specified distribution, and the operation field is used to indicate scalar data related to random vector generation, wherein the scalar data includes a random vector length and / or distribution parameters related to the random vector generation instruction; According to the scalar data, the random vector generation operation is performed to generate a random vector that obeys a specified distribution; Storing vector data related to the random vector generation instruction; wherein, The distribution parameters include an upper bound parameter, a lower bound parameter and / or a mean parameter, a variance parameter, and the method further includes: Reading the upper bound parameter and the lower bound parameter of the uniform distribution, as well as the length and storage address of the random vector to be generated, generating a random vector that obeys the uniform distribution, and storing the generated random vector result; and / or The mean parameter and the variance parameter of the Gaussian distribution, as well as the length and storage address of the random vector to be generated are read; the random vector generation unit generates a random vector that obeys the Gaussian distribution, and stores the generated random vector result.

7. The method according to claim 6, characterized in that The scalar data includes a random vector storage address associated with the random vector generation instruction.

8. The method according to claim 7, characterized in that The operation field includes an immediate value and / or a register number, and the method further includes: Using a storage unit to store vector data related to the random vector generation instruction; Using a register unit to store scalar data related to the random vector generation instruction; The random vector storage address is an address in the storage unit, and the register number points to the register unit address.

9. The method according to claim 6, characterized in that The method further comprises: Before the random vector generation unit obtains the current random vector generation instruction, it is determined whether there is a dependency relationship between the current random vector generation instruction and the previously unexecuted operation instruction.

10. The method according to claim 6, characterized in that The method further comprises: Generate uniformly distributed random numbers using the LFSR module and / or Generate true random numbers by detecting the thermal noise of resistors; and / or A Ziggurat algorithm module is used to generate random numbers that obey an arbitrary distribution, wherein the arbitrary distribution includes a Gaussian distribution.

11. An electronic device, comprising the device according to any one of claims 1 to 5.

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