Non-volatile memory data bus

Abstract

Embodiments of the present disclosure relate to non-volatile memory data buses. A non-volatile memory integrated circuit has memory planes organized into rows and columns, with the columns containing bit lines. A sense amplifier for each bit line is configured to generate an output signal on a read data channel. The read data channels traverse the memory planes respectively along each bit line. Each read data channel is connected to all of the sense amplifiers of a corresponding bit line.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 1904443, filed on April 26, 2019, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to non-volatile memory integrated circuits and, in particular, to data buses in non-volatile memories. Background Art

[0004] Non-volatile memories typically include memory planes equipped with memory cells, each memory cell being capable of storing one bit. Memory planes are typically organized in rows and columns, with columns containing bit lines.

[0005] In particular, these bit lines enable access to the memory cells in order to read the stored data items therefrom, and for this purpose include dedicated sense amplifiers. Typically, the bit lines run across the memory plane over its entire length (in the column direction). The term "bit line" should be understood to represent a conceptual element of the organization of the memory plane, rather than being understood simply as a physical metal wire for routing signals.

[0006] In particular, at the periphery of the memory plane, a row decoder and a column decoder are provided in order to access the memory cells in matrix form.

[0007] Architectures have been proposed for segmenting the memory plane to form smaller memory plane segments in order to reduce stray effects in the metal lines forming the bit lines. Memory plane segments can share sense amplifiers.

[0008] Each sense amplifier is typically configured to generate an output signal on a read data channel. The read data channels of a memory plane segment are grouped together on a corresponding read data bus, for example 138 channels per bus. The channels of the read data bus of each memory plane segment are multiplexed onto the output bus of the memory.

[0009] Thus, first, at the periphery of the memory plane, each memory plane segment and the output bus of the memory have a multiplexer circuit, and increasing the number of memory plane segments increases the complexity of the multiplexing of the data on the output bus.

[0010] Second, at least one additional bit line (referred to as a redundant bit line) is conventionally provided in order to be able to replace memory cells that may be missing in each row of a memory plane segment. The absence of memory cells may occur statistically during production, and during the test phase, the memory cells to be replaced by the redundant bit line memory cells are identified in the factory.

[0011] For addressing the memory plane in order to implement such substitution via redundancy, it is encoded in the factory, in particular by an additional multiplexing circuit which is itself typically also located at the periphery of the memory plane.

[0012] Thus, for implementing an output bus having at least N + 1 multiplexer blocks, there are at least two multiplexing levels, where N is the number of memory plane segments. The multiplexer blocks are located at the periphery of the memory plane as are the data channel buses they control.

[0013] Thus, a large number of metal lines for the data channels of the bus pass through the periphery of the memory plane. First, this causes both complex and widespread congestion. Second, the space occupied by the metal lines leaving the read amplifier group limits the possibility of reducing the size of the read amplifiers. In addition, the read data channels are formed by thin metal lines having a significant inherent propagation delay.

[0014] Thicker metal lines are not currently used for the read data channels on the periphery, firstly due to their significant thickness multiplied by the large number of channels, and secondly because thicker metal lines at the periphery are generally intended to provide a stable power supply for the circuits at the periphery. SUMMARY OF THE INVENTION

[0015] According to some embodiments, it is proposed to route the read data channels above the memory plane in order to relieve the periphery burden, in particular to free up space with respect to the read amplifier group, while using thicker metal lines introducing a smaller propagation delay.

[0016] According to one aspect, there is proposed a non-volatile memory integrated circuit having a memory plane organized in rows and columns, the columns containing bit lines, each bit line containing a read amplifier, each read amplifier being configured to generate an output signal on a read data channel, where the read data channels pass through the memory plane respectively along (i.e., parallel to) each bit line, and each read data channel is connected to all of the read amplifiers in the read amplifier of the corresponding bit line.

[0017] Thus, all of the above problems associated with the read data channel bus located at the periphery of the memory plane are avoided.

[0018] According to one embodiment, each bit line further contains a multiplexing element configured to provide a data signal on the output bus of the non-volatile memory based on the output signal delivered by the read amplifier of the bit line.

[0019] Since the periphery of the memory plane contains neither the read data channel bus nor the multiplexing elements of the memory plane segments, congestion is eliminated.

[0020] According to one embodiment, the multiplexing element may be positioned in a region that extends in the row direction and is located in the middle of the rows of the memory plane.

[0021] This is advantageous in terms of structure, particularly in terms of a symmetric and compact structure.

[0022] According to one embodiment, the multiplexing element is configured to also receive at least one decoded parameter signal, which is respectively transmitted via at least one decoded parameter channel shared by the multiplexing element.

[0023] According to one embodiment, the integrated circuit includes at least one redundant bit line, and the multiplexing element of the redundant bit line is configured to: based on the output signal delivered by the sense amplifier of the redundant bit line, provide a redundant data signal on the redundant data channel, which is connected to the redundant data input of the multiplexing elements of other bit lines.

[0024] The redundant bit line has substantially the same structure as other bit lines, that is, the memory cells, sense amplifiers, and associated read data channels are the same, except that the multiplexing element of the redundant bit line is configured differently, for example, in response to decoded parameters.

[0025] According to one embodiment, the above-mentioned multiplexing elements of other bit lines (i.e., bit lines that are not redundant bit lines) are configured to: receive a redundant data selection command on the redundant data selection bus, and based on this selection command, provide the data signal based on the output signal delivered by the corresponding sense amplifier or based on the redundant data signal delivered on the redundant data input.

[0026] For example, the redundant data channel includes two differential lines, and the multiplexing element of the redundant bit line is configured to provide a redundant data signal including two inverted digital signals.

[0027] According to one embodiment, each read data channel includes two differential lines, and each sense amplifier is configured to provide an output signal including two inverted digital signals.

[0028] These uses of the inverted digital signals on the two differential lines are advantageous in terms of data transmission because they can contain information about the value of the data item and information about the availability (regarding the ready state) of the data item in the read mode.

[0029] According to one embodiment, the integrated circuit has an interconnect portion including a stack of metal layers, where the read data channels belong to a metal layer including metal tracks having a minimum width greater than 0.5 μm.

[0030] This is achieved by providing the read data channels according to this aspect and enables reducing the propagation time of the read data.

[0031] According to one embodiment, the read data channels include at least one electromagnetic shielding channel and a direct access programming bus channel therebetween.

[0032] When the read amplifier reads a data item, the direct access programming channel can act as a shielding channel. By allocating the read data channels above the memory plane, this simple and advantageous embodiment becomes possible, so that these read data channels are not congested relative to the read amplifier.

[0033] According to one embodiment, the memory plane is segmented into memory plane segments, and each bit line of each memory plane segment contains a read amplifier.

[0034] Specifically, in the segmented architecture of the memory plane, the above-mentioned congestion is particularly problematic at the periphery of the memory plane, and thus the integrated circuit as described above is particularly advantageous in this type of architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other advantages and features of the present invention will become apparent by examining the detailed description and the drawings of the completely non-limiting embodiments, wherein:

[0036] Figure 1 Illustrates a non-volatile memory integrated circuit having a memory plane;

[0037] Figure 2 Illustrates various channels related to read amplifiers and multiplexing elements;

[0038] Figure 3 Illustrates an embodiment of a multiplexing element;

[0039] Figure 4 Illustrates an exemplary embodiment of a complex logic gate;

[0040] Figure 5 Illustrates a plan view of a metal layer of an interconnect portion of a non-volatile memory integrated circuit. DETAILED DESCRIPTION

[0041] Figure 1 Shows a non-volatile memory NVM integrated circuit having a memory plane PM.

[0042] The memory plane PM is organized into rows RG and columns COL, and each column COL contains a plurality of bit lines BL.

[0043] In this organization, the intersections between columns and rows form memory words of, for example, 128 bits (i.e., 128 memory cells). Optionally, 8 additional bits, 1 parity bit, and 1 redundant bit can be selected to provide for an error correction code (ECC) mechanism, so that each memory word forms a total of 138 memory cells.

[0044] In this example, the memory plane PM is divided into memory plane sections BK , i = 0 to 3, and each memory plane section BK Each bit line BL includes a read (sense) amplifier SA. The read amplifier SA is positioned in a section BK in the middle of the row.

[0045] Each bit line BL includes a sense amplifier SA, and each sense amplifier SA is configured to generate an output signal (SAOUT / SAOUTN- Figure 3 ) on the read data channel SABUS / SABUSN.

[0046] Of course, the term "bit line" is considered to mean a conceptual element of the organization of the memory plane, rather than just a physical metal wire for routing signals.

[0047] The read data channels SABUS / SABUSN pass through the memory plane PM along each bit line BL respectively. Each read data channel SABUS / SABUSN is connected to all the sense amplifiers SA of the corresponding bit line BL.

[0048] Thus, in each bit line BL, the output signal from the sense amplifier SA is routed via the read data channel SABUS / SABUSN to the corresponding multiplexing element A, which is advantageously located in a region that is in the middle of the row RG of the memory plane PM and extends in the direction of the row RG.

[0049] Each multiplexing element A is configured to: provide a data signal OUT on the output bus BUS137 of the non-volatile memory NVM based on the output signal SAOUT / SAOUTN delivered by the sense amplifier of the bit line BL <n>。

[0050] The output bus BUS137 of the non-volatile memory NVM is at the end of the area located in the middle of the row RG and can be directly connected to its destination without intermediate elements (in particular, without additional multiplexers at the periphery of the memory plane PM).

[0051] This is also compatible with the design providing at least one redundant bit line BLRED.

[0052] Now refer to Figure 2 , which particularly shows various channels related to the sense amplifier SA and the multiplexing elements A, B.

[0053] The memory plane PM includes a redundant bit line BLRED having a specific multiplexing element B.

[0054] Specifically, in this example, the multiplexing element B of the redundant bit line BLRED is configured to provide redundant data signals RD / RDN on the redundant data channels RD, RDN based on the output signals (SAOUT_RED / SAOUTN_RED - Figure 3 ) delivered by the sense amplifier SA of the redundant bit line BLRED.

[0055] Of course, the output signals from the sense amplifier SA of the redundant bit line BLRED are also transmitted via the read data channels SABUS / SABUSN, which pass through the memory plane PM along the redundant bit line BLRED and are connected to all the sense amplifiers in the sense amplifier SA of the redundant bit line BLRED.

[0056] The redundant data channels RD / RDN are connected to the redundant data inputs of the multiplexing element A of other bit lines BL called normal bit lines.

[0057] Furthermore, in this case, the multiplexing element A of the normal bit line BL can be configured to receive a redundant data selection command on the redundant data selection bus REDBUS.

[0058] And, based on this selection command, the multiplexing element A provides a data signal OUT based on the output signals (SAOUT / SAOUTN) delivered by the corresponding sense amplifier SA or based on the redundant data signals delivered by the multiplexing element B specific to the redundant bit line BLRED on the redundant data inputs RD, RDN. <n>。

[0059] The multiplexing elements A, B may also be configured to further receive at least one decoded parameter signal, which is respectively transmitted via at least one decoded parameter channel VALD, POL / POLN shared by the multiplexing elements A, B.

[0060] Specifically, the decoded parameter signal may include, for example, a validity signal VALD, which indicates that the sense amplifier has completed the data reading process, or, in the case of communication on differential lines, a polarity signal POL / POLN.

[0061] Specifically, the redundant data channels RD / RDN and / or the read data channels SABUS / SABUSN may include two differential lines, each of which transmits digital signals that are inverted with respect to each other.

[0062] This makes it possible to avoid communication errors caused by spurious transitions that may occur on one of the two channels before the sense amplifier effectively delivers its output. Specifically, the differential lines may simultaneously transmit information about the validity value of the data item.

[0063] In addition, both are in the memory plane section BK The sense amplifier SA shared between the two halves (see Figure 1 ) is advantageously configured to perform a differential measurement between the cells in each of the two halves on the respective bit lines BL. Thus, depending on whether the measurement should be performed on one or the other of the two halves, the polarity of the measured differential signal is inverted or not inverted, and this is controlled by the polarity signals POL / POLN.

[0064] In other words, the polarity signals make it possible to define the convention for reading 0 or 1 on the differential signal from such a differential sense amplifier SA.

[0065] In summary, in the example of Figure 2 the read data channels SABUS / SABUSN make it possible to route the output signal from the sense amplifier SA to the respective multiplexing element A.

[0066] The polarity signals transmitted on the channel POL / POLN make it possible to define the differential read convention.

[0067] The validity signal transmitted on the respective channel VALD makes it possible to provide end-of-read information for data recovery. When the group BK a group BK among The sense amplifier SA transfers the corresponding validity signal VALD When (0 ≤ i ≤ 3), an end-of-read information is obtained.

[0068] A redundant data selection signal is transmitted on a redundant data selection bus REDBUS to identify a read operation that requires a redundant bit to be restored from a redundant bit line BLRED. The redundant data selection signal may include, for example, codes on a plurality of bits to identify a bit line BL that is to be transmitted to the redundant bit line BLRED for the read operation.

[0069] When appropriate, data read from the redundant bit line BLRED is transmitted from a multiplexing element B of the redundant bit line BLRED to the identified multiplexing element A via a redundant data channel RD / RDN.

[0070] Depending on an output signal (SAOUT / SAOUTN) from a sense amplifier SA (or, if there is an identification by the redundant data selection signal, depending on a signal from the redundant data channel RD / RDN), a final read data OUT is transmitted by the multiplexing element A <n>, OUT<n+1>, accompanied by a validity signal VALD for the authorized recovery data, where the polarity convention is defined by the polarity signals POL / POLN.

[0071] These numerous functions of the multiplexing element A can be implemented by referring to Figure 3 and Figure 4 the exemplary embodiments described.

[0072] In this regard, reference is made to Figure 3 .

[0073] Figure 3 An exemplary embodiment of the advantageous multiplexing element A is shown.

[0074] According to Figure 2 the example, the multiplexing element A has inputs for receiving signals (such as decoding parameters) and data signals for controlling it.

[0075] Thus, the multiplexing element A includes read data inputs SAOUT and SAOUTN, redundant data inputs RD and RDN, a validity signal input VALD, polarity inputs POL and POLN, a redundant data selection bus input on the 8-bit REDBUS<7:0>, and power inputs Vdd and Gnd, as well as a data output OUT <n>.

[0076] The identification logic component REDID enables a logic test specific to each multiplexing element A to be performed on the 8 bits of the redundant data selection signal REDBUS<7:0>. The identification logic component REDID delivers an identification signal RED / REDN indicating the selected or unselected state of the multiplexing element A in order to recover redundant data.

[0077] The multiplexing element A has two complex logic gates AA, each of which makes it possible to verify the above reference Figure 2 All conditions described except the condition of the validity signal VALD are fulfilled in order to deliver the corresponding data item at the output OUT.

[0078] The output OUT of the first complex logic gate AA is connected to the set input SET of the RS latch, and the output OUT of the second complex logic gate AA is connected to the reset input RESET of the RS latch.

[0079] Relative to the first complex logic gate receiving POL / POLN, the second complex logic gate receives opposite polarity POLN / POL.

[0080] The read data SAOUT / SAOUTN is transmitted to the complex logic gate AA through the preloading device B, and the preloading device B is configured to transmit the data signal SAOUT / SAOUTN if the validity signal VALD=1 satisfies the validity condition.

[0081] The multiplexing element B specific to the redundant bit line BLRED may, for example, simply comprise such a preloading device connected to the redundant data channels RD / RDN. Thus, the specific multiplexing element B still transmits the data from the sense amplifier of the redundant bit line BLRED to all multiplexing elements in the multiplexing elements A of the normal bit lines, which are responsible for selecting them or not selecting them according to the redundant data selection code transmitted on the bus REDBUS.

[0082] Therefore, when all conditions are met, the RS latch delivers the data OUT <n>True items.

[0083] Now refer to Figure 4 , which shows an exemplary embodiment of such a complex logic gate AA.

[0084] The complex logic gate AA receives data signals SAOUT, SAOUTN from a preloading device B and inverts them to form internal data signals Dint, DNint respectively.

[0085] Redundant data signals RD, RDN are also received and inverted to form internal redundant data signals RDint, RDNint respectively.

[0086] Identification signals RED, REDN and polarity signals POL, POLN from an identification logic component are also received.

[0087] In Figure 4 , the complex logic gate AA is divided by a dashed line into two parts, one corresponding to the first polarity such that POL = 1 and POLN = 0, and the other corresponding to the opposite polarity, i.e., POL = 0 and POLN = 1.

[0088] In the case of the first polarity POL = 1 and POLN = 0, the N-type transistors are turned on by the signal POL and connect the ground Gnd (Gnd = logic 0) to two parallel branches, each branch having a pair of series-connected N-type transistors. The above branches are also connected to the output OUT of the complex logic gate AA.

[0089] If the signal RED = 1 and if RDint = 1 (i.e., RD = 0), then the first branch transmits Gnd to the output OUT. In other words, if the redundant identification is verified (RED = 1, REDN = 0), and if the received data redundancy item is 0 (RD = 0), then the output OUT is set to 0.

[0090] If the signal REDN = 1 and if Dint = 1 (i.e., SAOUT = 0), then the second branch transmits Gnd to the output OUT. In other words, if the redundant identification is not verified (RED = 0, REDN = 1), and if the received data read item is 0 (SAOUT = 0), then the output OUT is set to 0.

[0091] Furthermore, still in the case of the first polarity POL = 1 and POLN = 0, the P-type transistors are turned on by the signal POLN and connect two cross-coupled branches to the power supply Vdd (Vdd = logic 1), each branch having a pair of series-connected P-type transistors. The above branches are also connected to the output OUT of the complex logic gate AA.

[0092] If signal RED = 0 and if Dint = 0 (i.e., SAOUT = 1), the first branch conveys Vdd to output OUT. In other words, if the redundancy flag is not verified (RED = 0, REDN = 1), and if the received data read item (SAOUT = 1) is 1, output OUT is set to 1.

[0093] If signal REDN = 0 and if RDint = 0 (i.e., RD = 1), the second branch conveys Vdd to output OUT. In other words, if the redundancy flag is verified (RED = 1, REDN = 0), and if the received data redundancy item (RD = 1) is 1, output OUT is set to 1.

[0094] In the part corresponding to the opposite polarities POL = 0 and POLN = 1, the circuit is identical, but the transistors commanded by the data signals (Dint, RDint) are commanded by the opposite data signals DNint, RDNint, in each of the above cases, to impart an opposite bias on output OUT.

[0095] Figure 5 A plan view of metal layer MET7 of the back-end-of-line (BEOL) interconnect part of a non-volatile memory (NVM) integrated circuit is shown.

[0096] The BEOL interconnect part includes a stack of metal layers, and a read data channel SAOUT / SAOUTN is formed in one of the metal layers.

[0097] The read data channel SAOUT / SAOUTN may include at least one electromagnetic shielding channel GND and a direct access programming bus channel PRGDAMBUS therebetween.

[0098] During a read operation, the direct access programming bus channel PRGDAMBUS is biased to ground GND and thus acts as an electromagnetic shield.

[0099] In particular, as referred to above Figure 1 and Figure 2 the integrated circuit described enables a read data channel SAOUT / SAOUTN to be formed in a metal layer (such as the seventh metal layer MET7) including metal tracks having a minimum thickness greater than 0.5 μm.

[0100] Specifically, reference numeral 1xSAPTCH denotes the width dedicated to the sense amplifier in bit line BL. Thus, considering that here each width 1xSAPTCH only requires four channels (since in this example they optionally include shielding channels and each signal also has a differential configuration with two channels), a metal layer with thicker tracks can be used.

[0101] This provides a major advantage in terms of the propagation time of the signal, particularly in terms of the propagation time of the signal in the data read channels.

[0102] Some specific embodiments have been described, however, the invention is not limited to these embodiments, but encompasses all their variations, for example, with reference to Figure 3 and Figure 4 the circuit of the multiplexing element described is a simple design example, and in the context of the present invention, of course, any other architecture with a similar function can be considered.< / n> < / n> < / n> < / n> < / n>

Claims

1. A non-volatile memory integrated circuit, comprising: A memory plane, organized into rows and columns, the columns containing bit lines; A sense amplifier for each bit line, the sense amplifier being configured to generate an output signal on a read data channel; A multiplexing element for each bit line, the multiplexing element being configured to provide a data signal on an output bus of the non-volatile memory integrated circuit based on the output signal delivered by the sense amplifier of the bit line; And At least one redundant bit line, wherein the multiplexing element of the redundant bit line is configured to: provide a redundant data signal on a redundant data channel based on the output signal delivered by the sense amplifier of the redundant bit line, the redundant data channel being connected to a redundant data input of the multiplexing elements of other bit lines, Wherein the read data channels respectively pass through the memory plane along each bit line; and Wherein each read data channel is connected to all of the sense amplifiers in the sense amplifier of the corresponding bit line.

2. The integrated circuit according to claim 1, wherein the multiplexing element is positioned in a region that extends in the direction of the rows and is located in the middle of the columns of the memory plane.

3. The integrated circuit according to claim 1, wherein the multiplexing element is further configured to receive at least one decoded parameter signal, the at least one decoded parameter signal being respectively transmitted via at least one decoded parameter channel shared by the multiplexing element.

4. The integrated circuit according to claim 1, wherein the multiplexing element of the other bit lines is configured to: receive a redundant data selection command on a redundant data selection bus, and based on the redundant data selection command, provide the data signal based on the output signal delivered by the corresponding sense amplifier or based on the redundant data signal delivered on the redundant data input.

5. The integrated circuit according to claim 1, wherein the redundant data channel includes two differential lines, and the multiplexing element of the redundant bit line is configured to provide the redundant data signal including two inverted digital signals.

6. The integrated circuit according to claim 1, wherein each of the read data channels includes two differential lines, and each sense amplifier is configured to provide the output signal including two inverted digital signals.

7. The integrated circuit according to claim 1, further comprising an interconnect portion, the interconnect portion including a stack of metal layers, wherein the read data channels are provided in the stack of metal layers, the metal layers including metal tracks having a minimum width greater than 0.5 μm.

8. The integrated circuit according to claim 7, wherein the read data channels include at least one electromagnetic shielding channel and a direct access programming bus channel.

9. The integrated circuit according to claim 1, wherein the memory plane is divided into memory plane segments, and each bit line of each memory plane segment includes the sense amplifier.

10. A non-volatile memory integrated circuit, comprising: A memory plane, organized into rows and columns, the columns containing bit lines; Sense amplifiers, coupled to each bit line and configured to generate an output signal on a read data channel; An interconnect portion, extending over the memory plane and including a stack of metal levels, wherein at least one metal level includes metal tracks that extend parallel to the bit lines in the columns to form read data channels; and wherein each read data channel is connected to all of the sense amplifiers in the sense amplifiers corresponding to the respective bit lines.

11. The integrated circuit according to claim 10, further comprising a multiplexing element for each bit line, the multiplexing element being configured to: provide a data signal on an output bus of the non-volatile memory based on the output signal delivered by the sense amplifier of the bit line.

12. The integrated circuit according to claim 11, wherein the multiplexing element is positioned in a region that extends in the direction of the rows and is located in the middle of the columns of the memory plane.

13. The integrated circuit according to claim 11, wherein the multiplexing element is further configured to receive at least one decoded parameter signal, the at least one decoded parameter signal being transmitted separately via at least one decoded parameter channel shared by the multiplexing element.

14. The integrated circuit according to claim 11, further comprising at least one redundant bit line, wherein the multiplexing element of the redundant bit line is configured to: provide a redundant data signal on a redundant data channel based on the output signal delivered by the sense amplifier of the redundant bit line, the redundant data channel being connected to a redundant data input of the multiplexing elements of the other bit lines.

15. The integrated circuit according to claim 14, wherein the multiplexing element of the other bit lines is configured to: receive a redundant data selection command on a redundant data selection bus and, based on the redundant data selection command, provide the data signal based on the output signal delivered by the corresponding sense amplifier or based on the redundant data signal delivered on the redundant data input.

16. The integrated circuit according to claim 14, wherein the redundant data channel includes two differential lines, and the multiplexing element of the redundant bit line is configured to provide the redundant data signal including two inverted digital signals.

17. The integrated circuit according to claim 10, wherein each of the read data channels includes two differential lines, and each sense amplifier is configured to provide the output signal including two inverted digital signals.

18. The integrated circuit according to claim 10, wherein each metal track has a minimum width greater than 0.5 μm.

19. The integrated circuit according to claim 18, wherein the at least one metal level further includes additional metal tracks for at least one electromagnetic shielding channel and a direct access programming bus channel.

20. The integrated circuit according to claim 10, wherein the memory plane is divided into memory plane segments, and each bit line of each memory plane segment includes the sense amplifier.

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