Semiconductor device and method for driving the same

Abstract

Embodiments of the present disclosure relate to semiconductor devices and methods for driving semiconductor devices, the purpose of which is to provide a technology that can increase the speed of voltage increase or decrease of the wiring at a location far from a driver for wiring having large parasitic resistance or large load capacity. The semiconductor device includes: a first wiring having a first portion, a second portion, and a third portion provided between the first portion and the second portion; a plurality of memory cells connected to the third portion; a field effect transistor having a gate and a drain connected to the second portion; and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion close to the first portion, a fifth portion close to the second portion, and a sixth portion arranged between the first portion and the fourth portion. The plurality of memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of the disclosure of Japanese Patent Application No. 2019-085826 filed on April 26, 2019 including its specification, drawings and abstract are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to semiconductor devices and methods of driving semiconductor devices. Background Art

[0004] The present disclosure can be applied to a semiconductor device having a metal wiring with high parasitic resistivity, or to a high load capacity of the metal wiring of the semiconductor device.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-54570

[0007] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2009-252256

[0008] In semiconductor devices manufactured using existing manufacturing processes, the parasitic resistivity of metal wiring tends to be high. For example, to prevent the word line voltage from increasing or decreasing more slowly at locations away from the word line driver due to the influence of the word line's resistance component, a semiconductor device has been proposed in which an auxiliary driver is provided at the other end of the word line that is not connected to the word line driver (for example, see the semiconductor device proposed in Japanese Unexamined Patent Application Publication No. 2017-54570).

[0009] In addition, in a small SRAM (static random access memory), in a memory cell with insufficient static noise margin (hereinafter referred to as SNM), in order to increase the SNM, a semiconductor memory having a circuit for lowering the potential of a word line has been proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-252256). Summary of the Invention

[0010] In Japanese Unexamined Patent Application Publication No. 2017-54570, an auxiliary driver connects or disconnects the other end of the word line to the power supply (Vdd) according to the voltage at the other end of the word line, and the memory cell is connected to the other end of the word line. The higher the parasitic resistivity of the word line, the slower the signal voltage reaches the auxiliary driver. Therefore, the effect of increasing the speed may not be sufficient. In addition, when a memory cell lacking SNM is connected to a word line with a higher parasitic resistivity, if the other end of the word line is connected to the power supply (Vdd) through the auxiliary driver, the operation of the memory cell may become unstable.

[0011] An object of the present disclosure is to provide a technique capable of increasing the rising speed or the falling speed of a wiring voltage at a position far from a driver in a wiring having a high parasitic resistance or a wiring having a large load capacity.

[0012] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0013] An overview of representative embodiments of the present disclosure will be briefly described below.

[0014] According to one embodiment, a semiconductor device includes: a first wiring having a first portion, a second portion different from the first portion, and a third portion different from the first portion and the second portion, the third portion being provided between the first portion and the second portion; a plurality of memory cells connected to the third portion of the first wiring; a field effect transistor having a drain connected to the second portion and a gate; and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion and a fifth portion, the fourth portion being positioned closest to the first portion, and the fifth portion being positioned closest to the second portion. The first wiring also includes a sixth portion different from the first and fourth portions, the sixth portion being provided between the first and fourth portions. The plurality of memory cells includes a first memory cell connected to the fourth portion, and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

[0015] According to the above-described semiconductor device, the rising speed or the falling speed of the wiring voltage at a position distant from the driver circuit can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram illustrating an exemplary configuration of a semiconductor device according to a first embodiment.

[0017] Figure 2 It shows Figure 1 FIG. 1 is a diagram of an exemplary configuration of a memory device.

[0018] Figure 3It is an icon Figure 2 FIG. 1 is a diagram of an exemplary configuration of a unit circuit.

[0019] Figure 4 It shows Figure 3 FIG. 1 is a diagram of an exemplary configuration of a memory cell.

[0020] Figure 5 It shows Figure 3 FIG. 1 is a diagram of an exemplary configuration of a power supply potential generating circuit.

[0021] Figure 6 Is used to explain Figure 3 Flowchart showing the word line potential during a read operation of a cell circuit.

[0022] Figure 7 It is an icon Figure 3 Graph showing the waveform of the word line potential during a read operation of the unit circuit.

[0023] Figure 8 is a diagram for explaining a schematic planar layout of a unit circuit.

[0024] Figure 9 Shown along Figure 8 Schematic cross-sectional view of line AA′.

[0025] Figure 10 : is a diagram showing a modified example of the layout of the second wiring.

[0026] Figure 11 is a diagram illustrating an exemplary configuration of a unit circuit according to the second embodiment.

[0027] Figure 12 is a waveform diagram illustrating the word line potential at the time of the read operation of the unit circuit according to the second embodiment.

[0028] Figure 13 is a diagram illustrating an exemplary configuration of a unit circuit according to a first modification example.

[0029] Figure 14 is a diagram illustrating an exemplary configuration of a unit circuit according to a second modification example.

[0030] Figure 15 : is a diagram showing an exemplary configuration of a unit circuit according to a third modification example.

[0031] Figure 16 : is a diagram showing an exemplary configuration of a unit circuit according to a fourth modification example.

[0032] Figure 17 : is a waveform diagram for explaining the word line potential at the time of the read operation of the unit circuit related to the fourth modification example.

[0033] Figure 18 is a diagram illustrating an exemplary configuration of a memory device according to a fifth modification example.

[0034] Figure 19 is a diagram illustrating an exemplary configuration of a unit circuit according to a sixth modification example.

[0035] Figure 20 is a diagram illustrating an exemplary configuration of a unit circuit according to a seventh modification example.

[0036] Figure 21 3 is a waveform diagram illustrating the word line potential at the time of the read operation of the unit circuit according to the seventh modification example.

[0037] Figure 22 is a diagram illustrating an exemplary configuration of a unit circuit according to the third embodiment.

[0038] Figure 23 is a diagram for explaining the operation of the unit circuit according to the third embodiment.

[0039] Figure 24 is a diagram illustrating an exemplary configuration of a memory device according to an eighth modification example.

[0040] Figure 25 are diagrams for explaining the operation of the memory device according to the eighth modification example.

[0041] Figure 26 is a diagram illustrating an exemplary configuration of a unit circuit of a TCAM according to a fourth embodiment.

[0042] Figure 27 is a diagram for explaining the configuration of an inverter circuit.

[0043] Figure 28 is a diagram for explaining the operation of the unit circuit according to the fourth embodiment.

[0044] Figure 29 is a diagram showing an exemplary configuration of a memory cell TCAMMC. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments and modified examples will be described with reference to the accompanying drawings. However, in the following description, the same components are represented by the same reference numerals, and their repeated descriptions may be omitted. It should be noted that for the sake of clarity, the accompanying drawings may be schematically shown compared to the actual embodiments, but the accompanying drawings are only examples and do not limit the interpretation of the present invention.

[0046] (Configuration Example of Semiconductor Device)

[0047] Figure 11 is a diagram showing an example of a configuration of a semiconductor device according to a first embodiment. The semiconductor device 100 is formed on a single semiconductor chip such as single crystal silicon using a known manufacturing method for CMOS transistors. The semiconductor device 100 constitutes a microcontroller (MCU) and includes a central processing unit (CPU) 101, a volatile memory device (MEM) 102 such as a static random access memory (SRAM), and an electrically rewritable non-volatile memory (ROM) 103 such as a flash memory. The semiconductor device 100 also includes a peripheral circuit (PM0) 104, which includes a plurality of functional modules (e.g., a data transmission device and a communication circuit) having desired functions. The circuits (101, 102, 103, and 104) in the semiconductor device 100 are interconnected by a bus 105. The semiconductor device 100 includes an external terminal 106 to which a power supply potential VDD serving as a first reference potential is supplied; an external terminal 107 to which a ground potential GND serving as a second reference potential different from the first reference potential is supplied; and a plurality of external terminals (not shown) for inputting and outputting signals. The power supply potential VDD and the ground potential GND are supplied to the circuits (101, 102, 103, and 104) in the semiconductor device 100.

[0048] (Configuration Example of Memory Device 102)

[0049] Figure 2 It shows Figure 1 Figure 1 shows an example configuration of a memory device 102. Memory device 102 includes: a memory cell array region MCAR, in which a memory cell array MCA is formed, which includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of complementary bit line pairs BT and / BT; a driver circuit formation region WLDR, in which a plurality of word lines including word line driver circuits WLD are formed; and a word line pull-up circuit formation region WLPUR, in which a plurality of word line pull-up circuits WLPU are formed. Multiple memory cells MC are arranged in a matrix within the memory cell array MCA. Word lines WL and complementary bit line pairs BT and / BT are connected to each of the plurality of memory cells MC.

[0050] The memory device 102 further includes a control unit formation region CNTR in which a control unit CNT for controlling the operation of the memory device 102 is formed, and an input / output unit formation region IOR in which an input / output unit IO (e.g., a read circuit and a write circuit) is formed. The memory device 102 further includes a word line pull-up control circuit formation region WLPUCR in which a word line pull-up control circuit WLPUC for controlling the word line pull-up circuit WLPU is formed, and a word line driver control circuit formation region WLDCR in which a word line driver control circuit WLDC for controlling the word line driver circuit WLD is formed.

[0051] exist Figure 2 In FIG, a unit circuit 4 corresponding to one row (hereinafter, simply referred to as a unit circuit) is indicated by a square dotted line. In a plan view, a plurality of unit circuits 4 are arranged vertically side by side in the regions WLDR, MCAR, and WLPUR.

[0052] (Configuration Example of Unit Circuit 4)

[0053] Figure 3 It is an icon Figure 2 FIG. 4 is a diagram showing a configuration example of the unit circuit 4. Figure 4 It shows Figure 3 FIG. 1 is a diagram of an exemplary configuration of a memory cell. Figure 3 As shown, unit circuit 4 includes a word line driver circuit (drive circuit) WLD, a word line WL connected to word line driver circuit WLD, multiple memory cells MC connected to word line WL, a word line pull-up circuit WLPU connected to word line WL, and wiring L2 arranged in parallel with word line WL. If word line WL is first wiring L1, wiring L2 can be considered second wiring. For simplicity, multiple complementary bit line pairs BT and / BT connected to each of the multiple memory cells MC are not shown in unit circuit 4.

[0054] like Figure 4 As shown, in one example, the circuit configuration MCC of each memory cell MC in the plurality of memory cells MC includes two access transistors NA1 and NA2, two load transistors PQ1 and PQ2, and two driver transistors NQ1 and NQ2. Each of the access transistors NA1 and NA2 and the driver transistors NQ1 and NQ2 is an N-channel MOS field-effect transistor, and the load transistors PQ1 and PQ2 are P-channel MOS field-effect transistors.

[0055] The source-drain path of load transistor PQ1 and the source-drain path of driver transistor NQ1 are connected in series between memory cell power supply potential VDDM2 and ground potential GND. The source-drain path of load transistor PQ2 and the source-drain path of driver transistor NQ2 are connected in series between a second memory power supply potential (memory array power supply potential) VDDM2 and ground potential GND.

[0056] The gate of load transistor PQ1 and the gate of drive transistor NQ1 are connected to form a common gate, the drain of load transistor PQ2 and the drain of drive transistor NQ2 are connected to form a common drain, and the common gate of load transistor PQ1 and drive transistor NQ1 is connected to the common drain of load transistor PQ2 and drive transistor NQ2.

[0057] Similarly, the gate of load transistor PQ2 and the gate of drive transistor NQ2 are connected to form a common gate, the drain of load transistor PQ1 and the drain of drive transistor NQ1 are connected to form a common drain, and the common gate of load transistor PQ2 and drive transistor NQ2 is connected to the common drain of load transistor PQ1 and drive transistor NQ1.

[0058] The source-drain path of access transistor NA1 is connected between bit line BT of the complementary bit line pair BT, / BT and the common drain of load transistor PQ1 and driver transistor NQ1. The gate of access transistor NA1 is connected to word line WL via connection node ND1. The source-drain path of access transistor NA2 is connected between bit line / BT of the complementary bit line pair BT, / BT and the common drain of load transistor PQ2 and driver transistor NQ2. The gate of access transistor NA2 is connected to word line WL via connection node ND2.

[0059] Each layout configuration MCL of the plurality of memory cells MC includes P-type wells PW1 and PW2 formed in the semiconductor chip, an N-type well NW provided between the P-type wells PW1 and PW2 , and four gate electrodes GM1 to GM4 formed of polycrystalline.

[0060] Gate electrodes GM1 and GM2 and an N-type impurity layer NN1 are formed in a P-type well PW1. In the region of the P-type well PW1, gate electrode GM1 forms the gate of access transistor NA1, which is connected to word line WL, and gate electrode GM2 forms the gate of driver transistor NQ1. The N-type impurity layer NN1, which forms the source or drain of access transistor NA1, is connected to bit line BT. The N-type impurity layer NN1, which forms the source of driver transistor NQ1, is connected to a wiring supplied with ground potential GND. The N-type impurity layer NN1, provided between gate electrode GM1 and gate electrode GM2, forms the drain of driver transistor NQ1 or the drain or source of access transistor NA1.

[0061] Gate electrodes GM2 and GM3 and a P-type impurity-introduced layer PP1 are formed in an N-type well NW. In the region of the N-type well NW, gate electrode GM2 forms the gate of load transistor PQ1, and gate electrode GM3 forms the gate of load transistor PQ2. P-type impurity-introduced layer PP1, provided between gate electrode GM2 and gate electrode GM3, forms the source of load transistors PQ1 and PQ2 and is connected to a wiring supplied with a second memory power supply potential VDDM2. P-type impurity-introduced layer PP1, which forms the drain of load transistor PQ1, is connected to gate electrode GM3 and N-type impurity-introduced layer NN1, which forms the drain of drive transistor NQ1, using, for example, first-layer metal wiring.

[0062] Gate electrodes GM3 and GM4 and an N-type impurity layer NN2 are formed in a P-type well PW2. In the region of the P-type well PW2, gate electrode GM4 forms the gate of access transistor NA2, which is connected to word line WL, and gate electrode GM3 forms the gate of driver transistor NQ2. The N-type impurity layer NN2, which forms the source or drain of access transistor NA2, is connected to bit line / BT. The N-type impurity layer NN2, which forms the source of driver transistor NQ2, is connected to a wiring supplied with ground potential GND. The N-type impurity layer NN2, provided between gate electrode GM3 and gate electrode GM4, forms the drain of driver transistor NQ2 or the source or drain of access transistor NA2. The P-type impurity layer PP1, which forms the drain of load transistor PQ2, is connected to gate electrode GM2 and N-type impurity layer NN1, which forms the drain of driver transistor NQ2, using, for example, first-layer metal wiring.

[0063] like Figure 3As shown, word line driver circuit WLD includes an input terminal i, an output terminal o, a P-channel MOS field-effect transistor PM1, and an N-channel MOS field-effect transistor NM1. Input terminal i of word line driver circuit WLD is connected to the output of inverter IV1, serving as a primary circuit, via wiring (third wiring) WLN. Output terminal o of word line driver circuit WLD is connected to word line WL. The source of P-channel MOS field-effect transistor PM1 is connected to a wiring supplied with the output of a power supply potential generating circuit (VWL Gen.) VWL, which generates the power supply potential for word line driver circuit WLD. The drain of P-channel MOS field-effect transistor PM1 is connected to output terminal o. The gate of P-channel MOS field-effect transistor PM1 is connected to input terminal i. The source of N-channel MOS field-effect transistor NM1 is connected to a wiring supplied with ground potential GND. The drain of N-channel MOS field-effect transistor NM1 is connected to output terminal o. The gate of N-channel MOS field-effect transistor NM1 is connected to input terminal i. The word line driver circuit WLD changes the potential of the word line WL by supplying the potential output from the power supply potential generating circuit VWL or the ground potential GND to the word line WL according to the potential input to the input terminal i.

[0064] like Figure 3 As shown, word line WL includes a first portion X1, a second portion X2 different from the first portion X1, and a third portion X3 different from the first and second portions X1 and X2. The third portion X3 is provided between the first and second portions X1 and X2. The first portion X1 is connected to the output terminal o of the word line driver circuit WLD. The second portion X2 is connected to the drain of a P-channel MOS field-effect transistor P12, which serves as a pull-up transistor and is provided in the word line pull-up circuit WLPU. The third portion X3 is connected to the gates of access transistors NA1 and NA2, which are provided in a row of multiple memory cells MC in the memory cell array MCA. Therefore, the third portion X3 can also be considered a memory cell connection area. The gates of the multiple access transistors can be considered as the load capacity of the word line WL.

[0065] When viewing the word line WL from the output terminal o of the word line driver circuit WLD, the first portion X1 can be considered as the proximal end WLA of the word line WL, and the second portion X2 can be considered as the distal end WLB of the word line WL. In other words, the word line WL has a proximal end WLA that is closer to the output terminal o of the word line driver circuit WLD, and a distal end WLB that is farther away from the output terminal o of the word line driver circuit WLD than the proximal end WLA.

[0066] The third portion X3 of the word line WL also includes a fourth portion X4 positioned closest to the first portion X1, and a fifth portion X5 positioned closest to the second portion X2. A plurality of memory cells MC for a row include a first memory cell (MC1) having access transistors NA1 and NA2, whose gates are connected to the fourth portion X4, and a second memory cell (MC2) having access transistors NA1 and NA2, whose gates are connected to the fifth portion X5. The word line WL also includes a sixth portion X6 that is different from the first portion X1 and the fourth portion X4 and is provided between the first portion X1 and the fourth portion X4.

[0067] like Figure 3 As shown, the second wiring L2 includes a first portion Y1 and a second portion Y2, which is different from the first portion Y1. The first portion Y1 is connected to the sixth portion X6. The second portion Y2 is connected to the input terminal of the inverter circuit IV2 in the word line pull-up circuit WLPU. When viewing the second wiring L2 from the output terminal o of the word line driver circuit WLD, the first portion Y1 can be considered the proximal portion of the second wiring L2, and the second portion Y2 can be considered the distal portion of the second wiring L2. The second wiring L2 can be configured from a metal wiring layer different from that of the word line WL. Alternatively, the second wiring L2 can be constructed from the same metal wiring layer as the word line WL. Since the number of transistors connected to the second wiring L2 is small, the load on the second wiring L2 is small compared to the load on the word line WL.

[0068] like Figure 3 As shown, wordline pull-up circuit WLPU includes an inverter circuit IV2 and two P-channel MOS field-effect transistors P11 and P12. Inverter circuit IV2 functions as a waveform shaping circuit. P-channel MOS field-effect transistor P11 functions as an enable switch transistor, controlling the activation and deactivation of wordline pull-up circuit WLPU. P-channel MOS field-effect transistor P12 functions as a pull-up transistor, pulling up the potential of the second portion X2 of wordline WL, or the remote end WLB. The output terminal of inverter circuit IV2 is connected to the gate of P-channel MOS field-effect transistor P12 via wiring (fourth wiring) L2B. The source of P-channel MOS field-effect transistor P11 is connected to a wiring supplied with the output of power supply potential generating circuit VWL. The gate of P-channel MOS field-effect transistor P11 is supplied with a pull-up enable signal WLPUE from wordline pull-up control circuit WLPUC, which controls the operation of wordline pull-up circuit WLPU. The drain of the P-channel MOS field effect transistor P11 is connected to the source of the P-channel MOS field effect transistor P12. The drain of the P-channel MOS field effect transistor P12 is connected to the second portion X2 or the remote end WLB.

[0069] When pull-up enable signal WLPUE is set to an active level, such as a low level, P-channel MOS field-effect transistor P11 turns on. In this case, when the output signal of word line driver circuit WLD transitions from a non-selected level signal (such as a low level) to a selected state signal (such as a high level), first portion X1 of word line WL, or proximal portion WLA, transitions from a low level to a high level, and first portion Y1 of second wiring L2 transitions from a low level to a high level substantially simultaneously. Because the load of second wiring L2 is smaller than that of word line WL, the transition of second portion Y2 of second wiring L2 from a low level to a high level precedes the transition of second portion X2 of word line WL, or distal portion WLB, from a low level to a high level. As a result, the output signal of inverter circuit IV2 transitions from a high level to a low level, P-channel MOS field-effect transistor P12 turns on, and the potential of second portion X2 of word line WL, or distal portion WLB, is pulled up based on the potential generated by power supply potential generating circuit VWL. That is, since the pull-up operation of the second portion X2 of the word line WL or the remote end WLB can be quickly initiated by the word line pull-up circuit WLPU, the potential transition of the second portion X2 of the word line WL or the remote end WLB can be accelerated. Therefore, for example, although the transition from the first memory cell (MC1) connected to the fourth portion X4 of the word line WL to the selected state is slightly delayed, the transition from the second memory cell (MC2) connected to the fifth portion X5 of the word line WL to the selected state can be accelerated, thereby speeding up the overall address access time in read and write operations of the memory device 102.

[0070] (Configuration Example of Power Supply Potential Generating Circuit VWL)

[0071] Figure 5 is a diagram showing a configuration example of a power supply potential generating circuit (VWL Gen.) VWL.

[0072] The power supply potential generating circuit VWL generates a power supply potential for the word line driver circuit WLD. The power supply potential generating circuit VWL is supplied with a first memory power supply potential VDDM1 and a ground potential GND, and is configured to receive a control signal TSNM supplied from the control unit CNT. The power supply potential generating circuit VWL is configured to receive control signals EN1, EN2, and EN3 supplied from the control unit CNT.

[0073] Power supply potential generating circuit VWL includes P-channel MOS field-effect transistors PQ10, PQ11, PQ12, PQ13, and PQ14, and an N-channel MOS field-effect transistor NQ10. The source-drain path of each of P-channel MOS field-effect transistors PQ10, PQ11, and PQ12 is connected in series with the source-drain path of N-channel MOS field-effect transistor NQ10, between a first memory power supply potential VDDM1 and ground potential GND. The source-drain paths of P-channel MOS field-effect transistors PQ13 and PQ14, connected in series, are connected in parallel with the source-drain paths of P-channel MOS field-effect transistors PQ11 and PQ12, connected in series. A control signal EN1 is supplied to the gate of P-channel MOS field effect transistor PQ10, a control signal EN2 is supplied to the gates of P-channel MOS field effect transistors PQ11 and PQ12, and a control signal EN3 is supplied to the gates of P-channel MOS field effect transistors PQ13 and PQ14. A control signal TSNM is supplied to the gate of N-channel MOS field effect transistor NQ10.

[0074] The ratios of the drive capacitance of P-channel MOS field effect transistor PQ10, the drive capacitance of P-channel MOS field effect transistors PQ11 and PQ12, and the drive capacitance of P-channel MOS field effect transistors PQ13 and PQ14 are close to each other. The Vth characteristics of P-channel MOS field effect transistors PQ11 and Q12, the Vth characteristics of P-channel MOS field effect transistors PQ13 and PQ14, and the Vth characteristics of load transistors PQ1 and PQ2 in memory cell MC are the same.

[0075] When the power supply potential generating circuit VWL is used, the control signal EN1 has a signal level such as a low level (EN1 = 0). The control signals EN2 and EN3 are control signals for adjusting the level of the output potential WVDD of the power supply potential generating circuit VWL. When both the control signals EN2 and EN3 are at a signal level such as a low level (EN2 = 0 and EN3 = 0), the read assist function for the memory cell is disabled. When both the control signals EN2 and EN3 are set to a signal level other than a low level, the potential level of the output potential WVDD of the power supply potential generating circuit VWL can be adjusted to, for example, three levels.

[0076] When the control signal TSNM is set to an active level (such as a high level) in synchronization with the internal clock of the memory device 102, the potential level of the output potential WVDD of the power supply potential generating circuit VWL becomes a potential (VDDM1-ΔV) obtained by subtracting the potential difference ΔV from the first memory power supply potential VDDM1. Here, VDDM1-ΔV is the power supply potential WVDDR when reading the word line driver circuit WLD of the memory device 102.

[0077] Specifically, the power supply potential generating circuit VWL reduces the voltage of the first memory power supply potential VDDM1 based on the activation level of the control signal TSNM during a read operation of the memory array MCA to generate a word line power supply potential WVDDR during a read operation. This word line power supply potential WVDDR during a read operation serves to increase the static noise margin (SNM) of the memory cells. On the other hand, when EN1 = 0, during a write operation period excluding a read operation period of the memory array MCA, the power supply potential generating circuit VWL generates a word line power supply potential WVDD based on the potential levels of the control signals EN2 and EN3.

[0078] During reading, the potential relationship between the first memory power supply potential VDDM1, the second memory power supply potential VDDM2, the word line driver circuit WLD, and the power supply potential WVDDR can be VDDM1 = VDDM2 > WVDDR, or can be VDDM1 > VDDM2 > WVDDR, or VDDM2 > WVDDR > VDDM1. That is, if the relationship of VDDM2 > WVDDR can be maintained, the static noise margin (SNM) when reading the memory cell MC can be expanded.

[0079] (Example of operation)

[0080] Figure 6 Is used to explain Figure 3 Flowchart showing the word line potential of a unit circuit during a read operation. Figure 7 It's a picture Figure 6 The waveform diagram of the word line potential of the unit circuit during the read operation. In the following description, Figure 6 Each step will refer to Figure 7 to describe.

[0081] Step S0: At time t1, the pull-up enable signal WLPUE transitions (decreases) from a non-selection level (such as a high level) to a selection level (such as a low level). As a result, the P-channel MOS field effect transistor P11 is turned on.

[0082] Step S1: At time t2, the control signal TSNM transitions (rises) from an inactive level (e.g., a low level) to an active level (e.g., a high level). As a result, the power supply potential generating circuit VWL pulls down (reduces) the first memory power supply potential VDDM1 by a potential difference ΔV to generate a word line power supply potential WVDDR (=VDDM1-ΔV) for reading.

[0083] Step S2: Furthermore, at time t2, the potential level of the wiring WLN connected to the output of the inverter IV1 changes (decreases) from a non-selected level (e.g., a high level) to a selected level (e.g., a low level). This causes the word line WL to be activated at time t3, and the proximal end WLA of the word line WL to change (increase) from a non-selected level (e.g., a low level) to a selected level (e.g., a high level). Note that the potential of the selected level of the word line WL is the word line power supply potential WVDDR during reading.

[0084] The potential at the far end WLB of word line WL slowly rises. On the other hand, because the load on second wiring L2 is smaller than that on word line WL, the potential at the far end Y2 of second wiring L2 rises sharply to the word line power supply potential WVDDR during reading. As a result, the potential level of wiring L2B connected to the output terminal of inverter circuit IV2 transitions (decreases) from a non-selected level (such as a high level) to a selected level (such as a low level), and P-channel MOS field-effect transistor P12 turns on. Therefore, at time t4, the potential at the far end WLB of word line WL rises sharply (Rise) and transitions to a selected level (such as a high level).

[0085] exist Figure 7 , the waveform indicated by the dotted line Z indicates a change in potential of the far end WLB of the word line WL when the auxiliary driver of Japanese Unexamined Patent Application Publication No. 2017-54570 is adopted. Figure 7 It can be seen that compared with the waveform shown by the dotted line Z, the transition of the far-end WLB of this embodiment shown by the solid line to the selection level is completed at an earlier time.

[0086] Step S3: At time t5, the pull-up enable signal WLPUE transitions (rises) from a selection level (such as a low level) to a non-selection level (such as a high level). As a result, the P-channel MOS field effect transistor P11 is turned off.

[0087] Step S4: At time t6, the potential level of the wiring WLN connected to the output of the inverter IV1 changes (increases) from a selected level (such as a low level) to a non-selected level (such as a high level) to deactivate the word line WL. Therefore, at time t7, the proximal end WLA of the word line WL changes (decreases) from a selected level (e.g., a high level) to a non-selected level (e.g., a low level), and the distal end Y2 of the wiring L2 changes (decreases) from a selected level (e.g., a high level) to a non-selected level (e.g., a low level). The distal end WLB of the word line WL then changes (decreases) from a selected level (e.g., a high level) to a non-selected level (e.g., a low level). In addition, the potential level of the wiring L2B connected to the output terminal of the inverter circuit IV2 changes (increases) from a selected level (e.g., a low level) to a non-selected level (e.g., a high level), and the P-channel MOS field effect transistor P12 is turned off (OFF).

[0088] Step S5: At time t8, the control signal TSNM changes from an active level (such as a high level) to an inactive level (such as a low level). As a result, the word line power supply potential WVDDR during reading returns to the first memory power supply potential VDDM1 at the power supply potential level generated by the power supply potential generating circuit VWL.

[0089] Next, a planar layout and a cross-sectional view of the word line WL and the second wiring L2 in the unit circuit 4 will be described with reference to the drawings.

[0090] (Explanation of Planar Layout and Cross-sectional View of Word Line WL and Second Wiring L2)

[0091] Figure 8 4 is a diagram for explaining a schematic planar layout of the unit circuit 4 . Figure 9 Shown along Figure 8 Schematic cross-sectional view of line AA'. Figure 8 In FIG, the via electrodes V11 to V17 and the via electrodes V21 and V22 schematically illustrate the positions where the corresponding via electrodes are formed. Figure 9 In FIG. 1 , a semiconductor chip CHIP schematically represents a semiconductor chip in which field effect transistors constituting a word line driver circuit WLD, a plurality of memory cells MC, and a word line pull-up circuit WLPU are formed.

[0092] Figure 8 The planar layout shows four unit circuits 4 arranged vertically in the Y direction. Each of the four unit circuits 4 includes a word line driver circuit WLD, a memory array MCA, and a word line pull-up circuit WLPU arranged in sequence in the X direction.

[0093] The word line driver circuit WLD includes a first gate electrode G1 and a second gate electrode G2 formed of polycrystalline (POLY) extending in the X direction; an N-type impurity introduction layer (DIFF) N1 into which N-type impurities are introduced; and a P-type impurity introduction layer (DIFF) P1 into which P-type impurities are introduced. The first gate electrode G1 and the second gate electrode G2 form the gate electrodes of an N-channel MOS field-effect transistor NM1 and a P-channel MOS field-effect transistor PM1. The N-type impurity introduction layer N1 forms the source region or drain region of the N-channel MOS field-effect transistor NM1. The P-type impurity introduction layer P1 forms the source region or drain region of the P-channel MOS field-effect transistor PM1. That is, in this embodiment, one word line driver circuit WLD includes two N-channel MOS field-effect transistors NM1 connected in parallel and two P-channel MOS field-effect transistors PM1 connected in parallel.

[0094] The word line WL is formed of a second metal wiring layer (M2) provided to extend in the X direction. Figure 9 As shown, the output terminal o of the word line driver circuit WLD is connected to the first portion X1 of the word line WL or the proximal end WLA of the word line WL via the first metal wiring layer (not shown) and the via electrode V11. Although the second portion X2 of the word line WL or the distal end WLB is not connected to the first portion X1 of the word line WL or the proximal end WLA of the word line WL, Figure 8 As shown in FIG, a second portion X2 or a far end WLB of the word line WL is connected to the drain of the P-channel MOS field effect transistor P12 in the word line pull-up circuit WLPU through a metal wiring layer (not shown), such as a first layer (not shown).

[0095] The memory array MCA includes a plurality of memory cells MC connected to a third portion X3 of a word line WL. The plurality of memory cells of the memory array MCA include a first memory cell (MC1) connected to a fourth portion X4 of the word line WL, and a second memory cell (MC2) connected to a fifth portion X5 of the word line WL. The layout of each of the memory cells MC, MC1 and MC2, can utilize Figure 4 The memory cell MC has a layout configuration MCL. The gates of the access transistors NA1 and NA2 of the memory cells (MC, MC1, MC2) are connected to the nodes ND1 and ND2 via a first metal wiring layer (not shown) and a Figure 9 Via electrodes V12 , V13 , V14 , V15 , and V16 are shown connected to the word line WL.

[0096] The second wiring L2 is formed by the third metal wiring layer M3 provided to extend in the X direction. The second wiring L2 may also be configured by, for example, a fourth metal wiring layer (above M3) above the third metal wiring layer (M3). Figure 9 As shown, second wiring L2 is provided in parallel on the upper side of word line WL in memory array MCA. A first portion Y1 of second wiring L2 is connected to a sixth portion X6 of word line WL via a via electrode V21. A second portion Y2 of second wiring L2 is connected to wiring LIN2 via a via electrode V22. Wiring LIN2 is configured from a second-level metal wiring layer (M2). Wiring LIN2 is further connected to an input terminal of inverter circuit IV2 in word line pull-up circuit WLPU via a via electrode V17 and a first-level metal wiring layer (not shown).

[0097] Inverter circuit IV2 of word line pull-up circuit WLPU includes: a third gate electrode G3 and a fourth gate electrode G4, each composed of polysilicon (POLY) extending in the X direction; an N-type impurity introduction layer (DIFF) N2 into which N-type impurities are introduced; and a P-type impurity introduction layer (DIFF) P2 into which P-type impurities are introduced. The third gate electrode G3 and the fourth gate electrode G4, respectively, constitute the gate electrodes of the N-channel MOS field-effect transistor and the P-channel MOS field-effect transistor that comprise inverter circuit IV2. The N-type impurity introduction layer N2 constitutes the source region or drain region of the N-channel MOS field-effect transistor that comprises inverter circuit IV2. The P-type impurity introduction layer P2 constitutes the source region or drain region of the P-channel MOS field-effect transistor that comprises inverter circuit IV2.

[0098] like Figure 8 and Figure 9 As shown, the second wiring L2 having a load smaller than that of the word line WL may be provided to extend in parallel on an upper side of the word line WL.

[0099] (Modified Example of Layout of Second Wiring L2) Figure 8 and Figure 9 In the embodiment, the second wiring L2 is provided to extend in parallel on the upper side of the word line WL, but the present invention is not limited thereto. The second wiring L2 may be provided to extend along one side of the word line WL. Figure 10 : is a diagram showing a modified example of the layout of the second wiring L2. Figure 10 In, with Figure 8 and Figure 9 Configurations having the same functions are denoted by the same reference numerals, and descriptions thereof are omitted. Figure 8 ,exist Figure 10In FIG. 1 , the first via electrodes V11 to V17 schematically illustrate positions where corresponding via electrodes are formed.

[0100] Figure 10 and Figure 8 and Figure 9 The difference is that in the plan view, Figure 10 The second wiring L2 in the memory array MCA branches upward from the word line WL in the sixth portion X6 of the word line WL and extends in parallel with the word line WL in the memory array MCA. Then, at the second portion Y2 of the second wiring L2, the second wiring L2 bends downward to form a wiring LIN2, and is connected to the input terminal of the inverter circuit IV2 in the word line pull-up circuit WLPU via a via electrode V17 and a first-level metal wiring layer (not shown).

[0101] like Figure 10 As shown, a second wiring L2 having a smaller load than the word line WL may be provided to extend in parallel at one lateral side of the word line WL.

[0102] According to the first embodiment, the following effects can be obtained:

[0103] 1) Because the load on second wiring L2 is smaller than that on word line WL, second portion Y2 of second wiring L2 transitions from low to high before second portion X2 of word line WL or remote portion WLB transitions from low to high. As a result, the output signal of inverter circuit IV2 in word line pull-up circuit WLPU transitions from high to low, turning on P-channel MOS field-effect transistor P12 in word line pull-up circuit WLPU. This pulls up the potential of second portion X2 of word line WL or remote portion WLB based on the potential generated by power supply potential generating circuit VWL.

[0104] 2) Since the pull-up operation of the second portion X2 of the word line WL or the remote end WLB can be quickly initiated by the word line pull-up circuit WLPU, the potential transition in the second portion X2 of the word line WL or the remote end WLB can be accelerated. Therefore, for example, although the transition from the first memory cell (MC1) connected to the fourth portion X4 of the word line WL to the selected state is slightly delayed, the transition from the second memory cell (MC2) connected to the fifth portion X5 of the word line WL to the selected state can be accelerated, thereby speeding up the overall address access time in read and write operations of the memory device 102.

[0105] Next, a second embodiment will be described. In the second embodiment, the same reference numerals are assigned to configurations having the same functions as those of the first embodiment, and descriptions thereof are omitted. In the second embodiment, another exemplary configuration of the unit circuit 4 of the first embodiment will be described.

[0106] Figure 11 is a diagram illustrating an exemplary configuration of a unit circuit 4 according to the second embodiment. Figure 11 and Figure 3 The difference is that in Figure 11 , a first portion (proximal end) Y1 of the second wiring L2 is connected to the output of the inverter IV11, and an input of the inverter IV11 is connected to the output of the inverter IV1 via a wiring WLN. Figure 11 Other configurations and Figure 3 The inverter IV11 is supplied with the first memory power supply potential VDDM1 and the ground potential GND as power supplies.

[0107] exist Figure 11 In the embodiment of the present invention, when the pull-up enable signal WLPUE is set to an active level such as a low level, after the output of the inverter IV1 becomes a low level, the first portion Y1 of the second wiring L2 becomes a high level through the inverter IV11, the second portion Y2 of the second wiring L2 becomes a high level, and the wiring L2B becomes a low level through the inverter IV2. This causes the word line pull-up circuit WLPU to operate.

[0108] (Example of operation)

[0109] Figure 12 is a waveform diagram illustrating the word line potential at the time of the read operation of the unit circuit 4 according to the second embodiment. Figure 12 In FIG. 1 , a dotted line Z1 indicates the potential of the distal end WLB of the word line WL in the first embodiment, and a dotted line ZY2 indicates the potential of the distal end Y2 of the second wiring L2 in the first embodiment.

[0110] At time t1 , the pull-up enable signal WLPUE transitions from a non-selection level (such as a high level) to a selection level (such as a low level) As a result, the P-channel MOS field effect transistor P11 is turned on.

[0111] At time t2, the control signal TSNM changes from an inactive level (such as a low level) to an active level (such as a high level). As a result, the power supply potential generating circuit VWL pulls down the first memory power supply potential VDDM1 by a potential difference ΔV to generate a word line power supply potential WVDDR (=VDDM1-ΔV) during reading.

[0112] At time t2, the potential level of the wiring WLN connected to the output of the inverter IV1 changes from a non-selected level (such as a high level) to a selected level (such as a low level). This causes the word line WL to be activated, and at time t3, the proximal end WLA of the word line WL changes from a non-selected level (such as a low level) to a selected level (such as a high level). Note that the potential of the selected level of the word line WL is the word line power supply potential WVDDR at the time of reading. The potential of the distal end WLB of the word line WL gradually rises. On the other hand, since the load of the second wiring L2 is less than the load of the word line WL, the potential of the distal end Y2 of the second wiring L2 rises sharply to the first memory power supply potential VDDM1. As a result, the potential level of the wiring L2B connected to the output terminal of the inverter circuit IV2 changes from a non-selected level (such as a high level) to a selected level (such as a low level), and the P-channel MOS field effect transistor P12 is turned on. Therefore, at time t4, the potential of the distal end WLB of the word line WL rises sharply and changes to a selected level (such as a high level). At Figure 12 , the waveform represented by the dotted line Z1 indicates the potential change of the far end WLB of the word line WL in the first embodiment. Figure 12 It can be understood that since the load of the word line WL of the second embodiment is smaller than that of the word line WL of the first embodiment, the start time of the transition of the level of the far-end WLB of this embodiment as shown by the solid line and the transition time to the selection level are completed at earlier times compared with the waveform shown by the dotted line Z1.

[0113] At time t5 , the pull-up enable signal WLPUE transitions from a selection level (such as a low level) to a non-selection level (such as a high level) As a result, the P-channel MOS field effect transistor P11 is turned off.

[0114] At time t6, the potential level of the wiring WLN connected to the output of the inverter IV1 changes from a selected level (such as a low level) to a non-selected level (such as a high level) to deactivate the word line WL. As a result, at time t7, the proximal end WLA of the word line WL changes from a selected level (such as a high level) to a non-selected level (such as a low level), and the distal end Y2 of the wiring L2 changes from a selected level (such as a high level) to a non-selected level (such as a low level). Then, the distal end WLB of the word line WL gradually changes from a selected level (such as a high level) to a non-selected level (such as a low level). The potential level of the wiring L2B connected to the output terminal of the inverter circuit IV2 changes from a selected level (such as a low level) to a non-selected level (such as a high level), and the P-channel MOS field effect transistor P12 is turned off.

[0115] At time t8, the control signal TSNM changes from an active level (such as a high level) to an inactive level (such as a low level). As a result, the word line power supply potential WVDDR during reading returns to the first memory power supply potential VDDM1 at the power supply potential level generated by the power supply potential generating circuit VWL.

[0116] According to the second embodiment, the following effects can be obtained.

[0117] The second wiring L2 is driven not by the output signal of the word line driver circuit WLD, but by the inverter IV1, which is the primary circuit of the word line driver circuit WLD, and the inverter IV1 driven by the output signal of the inverter IV1. Therefore, the word line driver circuit WLD drives the word line WL with a smaller load than in the first embodiment. Consequently, the first portion X1 of the word line WL, or the proximal end WLA, can transition from a low level to a high level more quickly than in the first embodiment.

[0118] Additionally, in an advanced process where wiring resistance is high, if the gate width of the transistors (PM1, NM1) constituting the word line driver circuit WLD is increased, the selection operation of the word line WL is generally not accelerated, and in some cases, the operation of selecting the word line WL by the first embodiment is not accelerated. Figure 8 The area occupied by the word line driver circuit WLD shown here cannot be used effectively. In the second embodiment, since an inverter IV11 is required, separate from the word line driver circuit WLD, the gate widths of the transistors PM1 and NM1 that comprise the word line driver circuit WLD are designed to be small, and the inverter IV11 is provided in a vacant area. As a result, the area of ​​the semiconductor chip can be used effectively. Furthermore, since the inverter IV11 does not need to operate at a power supply potential WVDDR lower than the first memory power supply potential VDDM1, the inverter can drive the second wiring L2 at a higher speed.

[0119] Next, some modified examples of the second embodiment will be described.

[0120] (First Modification Example)

[0121] In the first modified example, the same reference numerals are attached to the configuration having the same function as that of the second embodiment, and the description thereof is omitted. Figure 13 is a diagram showing an exemplary configuration of a unit circuit 4 according to a first modified example. Figure 13 and Figure 11 The difference is that in Figure 13 Inverters IV11 and IV2 are deleted. Figure 13 Other configurations and Figure 11 The configuration is the same.

[0122] In the first modification, the first portion (near end) Y1 of the second wiring L2 is directly connected to the wiring WLN connected to the output of the inverter IV1, and the second portion (far end) Y2 of the second wiring L2 is connected to the gate of the P-channel MOS field-effect transistor P12 in the word line pull-up circuit WLPU via the wiring L2B. Therefore, the second wiring L2 is directly driven by the output signal of the inverter IV1.

[0123] According to the first modified example, since the inverters IV11 , IV2 are deleted, the area of ​​the semiconductor chip can be reduced.

[0124] (Second Modification Example)

[0125] In the second modified example, the same reference numerals are attached to the configuration having the same function as that of the second embodiment, and the description thereof is omitted. Figure 14 is a diagram illustrating an exemplary configuration of a unit circuit 4 according to a second modification example. Figure 14 and Figure 11 The difference is that in Figure 14 In FIG, the inverter IV11 is arranged in the word line pull-up circuit WLPU. Figure 14 Other configurations and Figure 11 The configuration is the same.

[0126] In the second modification, the first portion (near end) Y1 of the second wiring L2 is directly connected to the wiring WLN at the output of the inverter IV1, and the second portion (far end) Y2 of the second wiring L2 is connected to the gate of the P-channel MOS field-effect transistor P12 in the word line pull-up circuit WLPU via two inverters IV11 and IV2. The two inverters IV11 and IV2 located in the word line pull-up circuit WLPU have the function of waveform shaping.

[0127] According to the second modification example, the word line pull-up circuit WLPU is capable of a high-speed pull-up operation by waveform-shaping the output of the inverter IV1 using two inverters IV11 and IV2.

[0128] (Third Modification Example)

[0129] In the third modified example, the same reference numerals are attached to the configuration having the same function as that of the second embodiment, and the description thereof is omitted. Figure 15 is a diagram illustrating an exemplary configuration of a unit circuit 4 according to a third modified example. Figure 15 and Figure 11 The difference is that in Figure 15 In the embodiment, a power supply potential generating circuit VWL2 which is different from the power supply potential generating circuit VWL is provided. Figure 15 Other configurations and Figure 11 The configuration is the same.

[0130] The output potential WVDD2 of the power supply potential generating circuit VWL2 is connected to the source of the P-channel MOS field-effect transistor P11 in the word line pull-up circuit WLPU. The configuration and operation of the power supply potential generating circuit VWL2 are identical to those of the power supply potential generating circuit VWL of the first embodiment, and therefore a description thereof will be omitted. Based on the high level of the control signal TSNM, the potential level of the output potential WVDD2 of the power supply potential generating circuit VWL2 becomes the potential (VDDM1-ΔV), which is obtained by subtracting the potential difference ΔV from the first memory power supply potential VDDM1. Here, VDDM1-ΔV becomes the power supply potential WVDDR2 when reading the word line driver circuit WLD of the memory device 102.

[0131] exist Figure 11 In this case, since the output potential WVDD of the power supply potential generating circuit VWL is connected to the word line driver circuit WLD and the word line pull-up circuit WLPU, the load on the power supply potential generating circuit VWL is large. Therefore, the output potential of the word line WL may rise to a high level before the output potential WVDD is pulled down, and the memory cell MC may not operate stably.

[0132] In the third modified example, a power supply potential generating circuit VWL2 is also provided on the word line pull-up circuit WLPU side. On the word line driver circuit WLD side, the power supply potential generating circuit VWL generates the output potential WVDD, and on the word line pull-up circuit WLPU side, the power supply potential generating circuit VWL2 generates the output potential WVDD2. Since the load on the power supply potential generating circuit VWL is reduced, the output potentials WVDD and WVDD2 can be quickly pulled down to the power supply potentials WVDDR and WVDDR2 when reading the word line driver circuit WLD.

[0133] (Fourth Modified Example)

[0134] In the fourth modified example, the same reference numerals are attached to the configuration having the same function as that of the third modified example, and description thereof is omitted. Figure 16 is a diagram illustrating an exemplary configuration of a unit circuit 4 according to a fourth modification example. Figure 17 3 is a waveform diagram illustrating the word line potential of the unit circuit 4 according to the fourth modification example at the time of the read operation. Figure 16 and Figure 15 The difference is that in Figure 16 In , the output potential WVDD2 is generated by simulating the memory cell MC using the parasitic capacitance elements C1 to Cn, and the capacitance elements C1 to Cn are charged by the P-channel MOS field effect transistor P11 which receives the control signal TSNM at its gate. Figure 16Other configurations and Figure 15 The configuration is the same.

[0135] The source of P-channel MOS field-effect transistor P11 is connected to the first memory power supply potential VDDM1, and the gate of P-channel MOS field-effect transistor P11 is connected to receive control signal TSNM. The drain of P-channel MOS field-effect transistor P11 is connected to wiring L10, to which capacitor elements C1 to Cn of analog memory cell MC are connected. Furthermore, the drain of P-channel MOS field-effect transistor P11 is connected to the drain of P-channel MOS field-effect transistor P12 in word line pull-up circuit WLPU using wiring L11. Wiring L10 is provided in parallel with word line WL.

[0136] Next, we will refer to Figure 17 The operation of the fourth modification example will be described.

[0137] When the control signal TSNM is low level, since the P-channel MOS field effect transistor P11 is turned on, the wiring L10 is connected to the first memory power supply potential VDDM1 , and the capacitance elements C1 to Cn are charged.

[0138] At time t1, when the control signal TSNM becomes high level, the P-channel MOS field effect transistor P11 becomes off, and the wiring L10 becomes floating. The power supply potential generating circuit VWL generates an output potential WVDDR.

[0139] When the potential level of wiring WLN connected to the output of inverter IV1 is low, the near end WLA of word line WL is high, the far end Y2 of second wiring L2 is high, and wiring L2B is low, turning on P-channel MOS field-effect transistor P12 in word line pull-up circuit WLPU. Consequently, power supply potential WVDDR2 is generated based on the charge stored in capacitors C1 to Cn, and the far end WLB of word line WL is pulled up using this generated power supply potential WVDDR2. In other words, the far end WLB of word line WL is pulled up by the charge stored in capacitors C1 to Cn.

[0140] At time t2 , when the control signal TSNM transitions from the high level to the low level, the P-channel MOS field effect transistor P11 is turned on, and the capacitance elements C1 to Cn connected to the wiring L10 are charged.

[0141] According to the fourth modified example, since the charge stored in the capacitor elements C1 to Cn is supplied to the word line WL, the word line WL does not rise to the first memory power supply potential VDDM1, so that the memory cell MC can perform stable operation. In addition, since the capacitor elements C1 to Cn simulate a plurality of memory cells MC connected to the word line WL, an equivalent effect can be obtained even when the number of word lines and the number of complementary bit line pairs (BT, / BT) of the memory array MCA are changed.

[0142] (Fifth Modified Example)

[0143] In the fifth modified example, the same reference numerals are attached to configurations having the same functions as those of the fourth modified example, and descriptions thereof are omitted. Figure 18 1 is a diagram showing an exemplary configuration of a memory device according to a fifth modified example. In the fifth modified example, a layout arrangement of the wirings L10_0, L10_1, L10_2, and L10_3 on the memory device 102 is described in the case where the plurality of wirings L10 (wirings L10_0, L10_1, L10_2, and L10_3) described in the fourth modified example are provided. Then, each of the wirings L10_0, L10_1, L10_2, and L10_3 is shared for a plurality of unit circuits 4. Figure 18 In the description, the capacitance element added to each of the wirings L10_0, L10_1, L10_2, and L10_3 is not described. However, similarly to the wiring L10 described in the fourth modified example, the capacitance element is added to each of the wirings L10_0, L10_1, L10_2, and L10_3.

[0144] like Figure 18 As shown, the plurality of unit circuits 4 described in the fourth modified example are arranged in the memory array MCA. In the memory array MCA, in one example, four wirings L10_0, L10_1, L10_2, and L10_3 are provided so as to be connected in parallel in the X direction, which is the same as the direction in which the word lines WL extend. Wiring L10_0 is provided on the lower side of the memory array MCA, wiring L10_3 is provided on the upper side of the memory array MCA, and wirings L10_1 and L10_2 are provided on the memory array MCA between wiring L10_0 and wiring L10_3.

[0145] P-channel MOS field effect transistors P11_0, P11_1, P11_2, and P11_3 corresponding to the P-channel MOS field effect transistor P11 described in the fourth modified example are connected to each of the wirings L10_0, L10_1, L10_2, and L10_3. Wiring L11_0, L11_1, L11_2, and L11_3 correspond to the wiring L11 described in the fourth modified example. In the region where the word line pull-up circuit WLPU is formed, wiring L11_0, L11_1, L11_2, and L11_3 are provided to extend in the Y direction (vertical direction) different from the extension direction of the word line WL. As exemplarily shown in the wiring L11_3 portion, the sources of the plurality of P-channel MOS field effect transistors P12 in the unit circuit 4 described in the plurality of fourth modified examples are connected. Similar to the wiring L11_3 , in the wirings L11_0 , L11_1 , and L11_2 , the sources of the plurality of P-channel MOS field effect transistors P12 in the plurality of unit circuits 4 are connected.

[0146] exist Figure 18 In the figure, the power switch (power SW) represents a switching element (e.g., a MOS transistor) provided to reduce leakage current of the plurality of memory cells MC. The tap (TAP) indicates a region for connecting the N-type well or P-type well in which the plurality of memory cells MC are formed to a desired reference potential (GND, VDDM2).

[0147] In the fifth modified example, each of the wirings (L10_0 and L11_0, L10_1 and L11_1, L10_2 and L11_2, L10_3 and L11_3) can be shared by a plurality of rows of word lines WL. In the fifth modified example, the wiring L11 of the fourth modified example is vertically divided by the word lines WL to have a configuration having a plurality of wirings L10_0, L10_1, L10_2, and L10_3 on the memory array MCA. As shown in the fourth modified example, it is preferable that the wiring L10 has a parasitic capacitance (capacitive element) simulating the parasitic capacitance of the word line WL. ), but when the wiring L10 is shared by a plurality of word lines WL, there is a parasitic capacitance (parasitic capacitance of the wiring L11) perpendicular to the word lines WL. As shown in the fifth modified example, the wiring L11 of the fourth modified example is configured by being divided into wirings L11_0, L11_1, L11_2, and L11_3 in the vertical direction (Y direction) of the word lines WL. Each parasitic capacitance of the wirings (L10_0 and L11_0, L10_1 and L11_1, L10_2 and L11_2, L10_3 and L11_3) becomes stronger in the direction (X direction) in which the word lines WL extend. Therefore, if the number of word lines of the memory array MCA and the number of complementary bit line pairs (BT, / BT) of the memory array MCA are changed, the parasitic capacitance of the wiring (L10_0, L11_0, L10_1, L11_1, L10_2, L11_2, L10_3 and L11_3) can simulate the parasitic capacitance of the word line WL.

[0148] (Sixth Modification Example)

[0149] In the sixth modified example, the same reference numerals are attached to the configuration having the same function as that of the third modified example, and description thereof is omitted. Figure 19 is a diagram illustrating an exemplary configuration of a unit circuit 4 according to a sixth modification example. Figure 19 and Figure 15 The difference is that in Figure 19 In the embodiment of the present invention, the power supply potential generating circuit VWL is deleted, and the first memory power supply potential VDDM1 is used as the power supply potential of the word line driver circuit WLD. The word line driver circuit WLD is provided with a P-channel MOS field effect transistor PM2. The word line driver circuit WLD changes the potential of the word line WL by supplying the first memory power supply potential VDDM1 or the ground potential GND to the output terminal o according to the potential input to the input terminal i. Figure 19 Other configurations and Figure 15 The configuration is the same.

[0150] The source-drain path of the P-channel MOS field-effect transistor PM2 is connected between the word line WL and a wiring supplied with the ground potential GND, and the gate of the P-channel MOS field-effect transistor PM2 is connected to the input terminal i of the word line driver WLD. The source of the P-channel MOS field-effect transistor PM2 is connected to the circuit terminal o of the word line WL or the output terminal o of the word line driver WLD, and the drain of the P-channel MOS field-effect transistor PM2 is connected to the line supplied with the ground potential GND.

[0151] In the sixth modified example, the P-channel MOS field effect transistor PM2 is directly pulled down to the word line WL, and the power supply potential generating circuit VWL2 is provided to the word line pull-up circuit WLPU. The P-channel MOS field effect transistors PM1 and PM2 have a drive capacity ratio such that the same voltage WVDD (WVDDR) as the output potential WVDD2 (WVDDR2) generated by the power supply potential generating circuit VWL2 can be generated.

[0152] When word line WL is at a high level, control signal TSNM needs to be at a high level in order to provide the pulled-down power supply potential WVDDR2. However, in a memory device 102 in which the number of word lines of the memory array MCA and the number of complementary bit line pairs (BT, / BT) of the memory array MCA are different, when power supply control of word line driver circuit WLD is performed by control signal TSNM, it is generally difficult to adjust the timing. Since a P-channel MOS field-effect transistor PM2 is provided for directly pulling down word line WL, timing control is not required in the power supply control of word line driver circuit WLD. On the other hand, power supply potential generating circuit VWL2 of word line pull-up circuit WLPU can relatively easily control the generation timing of power supply potential WVDDR2 using two control signals TSNM and pull-up enable signal WLPUE.

[0153] (Seventh Modification Example)

[0154] In the seventh modified example, the same reference numerals are attached to the configuration having the same function as that of the sixth modified example, and description thereof is omitted. Figure 20 is a diagram illustrating an exemplary configuration of a unit circuit 4 according to a seventh modification example. Figure 21 3 is a waveform diagram illustrating the word line potential of the unit circuit 4 according to the seventh modification example at the time of the read operation. Figure 20 and Figure 19 The difference is that in Figure 20 , an N-channel MOS field effect transistor N12 is provided in the word line pull-up circuit WLPU. Figure 20 Other configurations and Figure 19 The configuration is the same.

[0155] The gate of the N-channel MOS field-effect transistor N12 is connected to the gate of the P-channel MOS field-effect transistor P12, and the source-drain path of the N-channel MOS field-effect transistor N12 is connected between the word line WL and the ground potential GND at the far end X2 (WLB) of the word line WL. The N-channel MOS field-effect transistor N12 pulls down the potential level of the far end X2 (WLB) of the word line WL from a selected level (such as a high level) to a non-selected level (such as a low level) based on the high level of the output signal of the inverter.

[0156] Next, we will refer to Figure 21 The operation of the seventh modification example will be described.

[0157] At time t1 , the pull-up enable signal WLPUE transitions from a non-selection level (such as a high level) to a selection level (such as a low level) As a result, the P-channel MOS field effect transistor P11 is turned on.

[0158] At time t2, the control signal TSNM changes from an inactive level (such as a low level) to an active level (such as a high level). As a result, the power supply potential generating circuit VWL2 pulls down the first memory power supply potential VDDM1 by a potential difference ΔV to generate a word line power supply potential WVDDR2 (=VDDM1-ΔV) during reading.

[0159] Furthermore, the potential level of the wiring WLN connected to the output of the inverter IV1 changes from a non-selected level (such as a high level) to a selected level (such as a low level). This activates the word line WL, and the proximal end WLA of the word line WL changes from a non-selected level (such as a low level) to a selected level (such as a high level). Note that the potential of the selected level of the word line WL is the word line power supply potential WVDDR2 during reading. The potential of the distal end WLB of the word line WL gradually increases.

[0160] On the other hand, since the load on the second wiring L2 is smaller than that on the word line WL, the potential at the distal end Y2 of the second wiring L2 rises sharply to the first memory power supply potential VDDM1. As a result, the potential level of the wiring L2B connected to the output terminal of the inverter circuit IV2 transitions from a non-selected level (such as a high level) to a selected level (such as a low level), turning on the P-channel MOS field-effect transistor P12 and turning off the N-channel MOS field-effect transistor N12. As a result, the potential at the distal end WLB of the word line WL rises sharply and transitions to a selected level (such as a high level).

[0161] At time t3 , the pull-up enable signal WLPUE transitions from a selection level (such as a low level) to a non-selection level (such as a high level) As a result, the P-channel MOS field effect transistor P11 is turned off.

[0162] At time t4, the potential level of the wiring WLN connected to the output of the inverter IV1 changes from a selected level (such as a low level) to a non-selected level (such as a high level) to deactivate the word line WL. As a result, the proximal end WLA of the word line WL changes from a selected level (such as a high level) to a non-selected level (such as a low level), and the distal end Y2 of the wiring L2 changes from a selected level (such as a high level) to a non-selected level (such as a low level). Then, the distal end WLB of the word line WL gradually changes from a selected level (such as a high level) to a non-selected level (such as a low level). The potential level of the wiring L2B connected to the output terminal of the inverter circuit IV2 changes from a selected level (such as a low level) to a non-selected level (such as a high level), the P-channel MOS field effect transistor P12 is turned off, and the N-channel MOS field effect transistor N12 is turned on. As a result, the potential level of the distal end WLB of the word line WL drops sharply (pull-down) and quickly changes to a non-selected level (such as a low level). At Figure 21 , the waveform indicated by the dotted line Z12 indicates the potential change from high level to low level of the far end WLB of the word line WL in the sixth modified example. As described above, in the seventh modified example, the potential change from high level to low level of the far end WLB of the word line WL transitions faster than the waveform indicated by the dotted line Z12.

[0163] At time t5, the control signal TSNM changes from an active level (such as a high level) to an inactive level (such as a low level). As a result, the potential level of the power supply potential generated by the power supply potential generating circuit VWL2 returns to the first memory power supply potential VDDM1 through the word line power supply potential WVDDR2 during reading.

[0164] According to the seventh modification example, since the potential level of the far end WLB of the word line WL quickly transitions to an unselected level such as a low level, the entire address access time in the read operation and the write operation of the memory device 102 can be accelerated.

[0165] In the first embodiment, the second embodiment, and the first to seventh modified examples, the pull-up operation of the far end of the word line WL has been described. In the third embodiment, an exemplary configuration applied to the bit line of the memory device 102 will be described. Figure 22 is a diagram illustrating an exemplary configuration of a unit circuit 5 according to the third embodiment. Figure 23 3 is a diagram for explaining the operation of the unit circuit 5 according to the third embodiment. The third embodiment can be used in combination with any of the first embodiment, the second embodiment, and the first to seventh modified examples.

[0166] Figure 22The unit circuit 5 of the memory device 102 is shown in the column direction. The unit circuit 5 includes two write driver circuits WDC1 and WDC2; two column switches YS1 and YS2; a complementary bit line pair BT and / BT; two wiring lines L20 and L21; a plurality of memory cells MC; a bit line precharge circuit PCC and a bit line potential control circuit BLPD. One bit line BT in the complementary bit line pair BT and / BT can be referred to as a first bit line, and the other bit line / BT in the complementary bit line pair BT and / BT can be referred to as a second bit line. It should be noted that in the unit circuit 5, to simplify the illustration, the word line WL connected to each of the plurality of memory cells MC is not depicted.

[0167] Multiple memory cells MC can be used Figure 4 Configuration of memory cell MC shown. In one memory cell MC, the source or drain of access transistor NA1 is connected to bit line BT, and the source or drain of access transistor NA2 is connected to bit line / BT.

[0168] Each column switch YS1, YS2 has a gate that receives its column select signal YSE1. The source-drain path of column switch YS1 is connected between bit line BT and the output terminal of write driver circuit WDC1. The source-drain path of column switch YS2 is connected between bit line / BT and the output terminal of write driver circuit WDC2. In one example, column switches YS1, YS2 can be formed from N-channel MOS field-effect transistors. Each of column switches YS1, YS2 can be configured as a CMOS switch using an N-channel MOS field-effect transistor and a P-channel MOS field-effect transistor.

[0169] Write driver circuits WDC1 and WDC2 receive write data DTB and DBB and a write enable signal WTE. Each of write driver circuits WDC1 and WDC2 is controlled by the write enable signal WTE. When write data DTB is high and write data DBB is low, and when column switches YS1 and YS2 are on, bit line BT is set high, bit line / BT is set low, and data "1" is written to the selected memory cell. When write data DTB is low and write data DBB is high, and when column switches YS1 and YS2 are on, bit line BT is set low and bit line / BT is set high, and data "0" is written to the selected memory cell. In other words, write driver circuit WDC1 changes the potential of bit line BT by supplying a potential corresponding to write data DTB to the bit line based on the input write enable signal WTE. Write driver circuit WDC2 supplies a potential corresponding to write data DBB to bit line / BT in accordance with write enable signal WTE, thereby changing the potential of bit line / BT.

[0170] When viewed from the output terminal side of write driver circuit WDC1 or the column switch YS1 side, bit line BT has a near end BTA and a far end BTB. Similarly, when viewed from the output terminal side of write driver circuit WDC2 or the column switch YS2 side, bit line / BT has a near end / BTA and a far end / BTB.

[0171] Wiring L20 is a metal wiring provided in parallel with bit line BT and has a proximal end L20A and a distal end L20B. The proximal end BTA of bit line BT is connected to the proximal end L20A of wiring L20 via inverter circuit IB1. Wiring L21 is a metal wiring provided in parallel with bit line / BT and has a proximal end L21A and a distal end L21B. The proximal end / BTA of bit line / BT is connected to the proximal end L21A of wiring L21 via inverter circuit IB2.

[0172] The bitline precharge circuit PCC includes an equalization transistor PC1 and two precharge transistors PC2 and PC3. Transistors PC1, PC2, and PC3 can be formed from P-channel MOS field-effect transistors. Equalization transistor PC1 has a gate for receiving a precharge control signal PC and a source-drain path connected between the proximal end BTA of bitline BT and the proximal end / BTA of bitline / BT. Precharge transistor PC2 has a gate for receiving a precharge control signal PC and a source-drain path connected between a wiring supplied with the first memory power supply potential VDDM1 and the proximal end BTA of bitline BT. Precharge transistor PC3 has a gate for receiving a precharge control signal PC and a source-drain path connected between the wiring supplied with the first memory power supply potential VDDM1 and the proximal end / BTA of bitline / BT.

[0173] When the precharge control signal PC goes high, transistors PC1, PC2, and PC3 are turned off. When the precharge control signal PC goes low, transistors PC1, PC2, and PC3 are turned on. The equalizing transistor PC1 in the on state connects the proximal end BTA of the bit line BT to the proximal end / BTA of the bit line / BT, and equalizes the potential difference between the proximal end BTA of the bit line BT and the proximal end / BTA of the bit line / BT. The potential of the proximal end BTA of the bit line BT and the potential of the proximal end / BTA of the bit line / BT are set to a predetermined precharge potential through the precharge transistors PC2 and PC3 in the on state. As a result, the potential of the bit line BT and the potential of the bit line / BT are set to a predetermined precharge potential from the proximal end (BTA, / BTA) side to the distal end (BTB, / BTB) side.

[0174] The bitline potential control circuit BLPD includes an equalizing transistor PB1, two pull-up transistors PB2 and PB3, an enable transistor NB1, and two pull-down transistors NB2 and NB3. The equalizing transistor PB1 and the pull-up transistors PB2 and PB3 can also be considered as a bitline pull-up circuit for pulling up the bitlines BT and / BT. The enable transistor NB1 and the pull-down transistors NB2 and NB3 can also be considered as a bitline pull-down circuit for pulling down the bitlines BT and / BT. In one example, the equalizing transistor PB1 and the pull-up transistors PB2 and PB3 can be configured using P-channel MOS field-effect transistors. In another example, the enable transistor NB1 and the pull-down transistors NB2 and NB3 can be formed using N-channel MOS field-effect transistors.

[0175] The equalizing transistor PB1 has a gate that receives a control signal BLPDE and a source-drain path connected between the remote BTB of the bit line BT and the remote BTB of the bit line BT. The pull-up transistor PB2 has a gate that receives a control signal BLPDE and a source-drain path connected between a wiring supplied with the first memory power supply potential VDDM1 and the remote BTB of the bit line BT. The pull-up transistor PB3 has a gate that receives a control signal BLPDE and a source-drain path connected between a wiring supplied with the first memory power supply potential VDDM1 and the remote / BTB of the bit line / BT.

[0176] When the control signal BLPDE is at a high level, the equalizing transistor PB1 and the pull-up transistors PB2 and PB3 are turned off. When the control signal BLPDE is at a low level, the equalizing transistor PB1 and the pull-up transistors PB2 and PB3 are turned on. The equalizing transistor PB1, in the on state, connects the remote end BTB of the bit line BT to the remote end / BTB of the bit line BT, equalizing the potential difference between the remote end BTB of the bit line BT and the remote end / BTB of the bit line / BT. The potentials of the remote ends BTB of the bit line BT and / BTB of the bit line / BT are set to a predetermined pull-up potential via the on-state pull-up transistors PB2 and PB3. As a result, the potentials of the bit lines BT and / BT are set to a predetermined pull-up potential from the remote end (BTB, / BTB) to the near end (BTA, / BTA).

[0177] Enable transistor NB1 has a gate that receives a control signal BLPDE and a source-drain path connected to ground potential GND. Pull-down transistor NB2 has a gate connected to the distal end L20B of wiring L20 and a source-drain path provided between the distal end BTB of bit line BT and the source-drain path of enable transistor NB1. The source-drain path of pull-down transistor NB2 and the source-drain path of enable transistor NB1 are connected in series between the distal end BTB of bit line BT and ground potential GND. Pull-down transistor NB3 has a gate connected to the distal end L21B of wiring L21 and a source-drain path provided between the distal end / BTB of bit line / BT and the source-drain path of enable transistor NB1. The source-drain path of pull-down transistor NB3 and the source-drain path of enable transistor NB1 are connected in series between the distal end BTB of bit line BT and ground potential GND.

[0178] Enable transistor NB1 is turned on by a high level control signal BLPDE. When low-level write data DTB is written to the selected memory cell, column switches YS1 and YS2 are turned on, and the bit line BT transitions from a high level to a low level via write driver circuit WDC1. In this example, the potential level at the proximal end BTA of bit line BT transitions from a high level to a low level first. Because multiple memory cells MC are connected to bit line BT, the load capacity of bit line BT is relatively large. Therefore, the potential level at the distal end BTB of bit line BT gradually decreases from a high level. Meanwhile, inverter circuit IB1 transitions the potential level at the proximal end L20A of wiring L20 from a low level to a high level based on the transition from a high level to a low level at the proximal end BTA of bit line BL. Because the load capacity of wiring L20 is smaller than that of the bit line BT to which multiple memory cells MC are connected, the transition from a low level to a high level at the proximal end L20A of wiring L20 is rapidly transmitted to the distal end L20B of wiring L20. As a result, pull-down transistor NB2 changes from an off state to an on state, and the potential level of the far end BTB of bit line BT rapidly changes to a low level. Consequently, writing data to the selected memory cell is accelerated. When high-level write data DTB is written, bit line / BT transitions from a high level to a low level via write driver circuit WDC2. Since those skilled in the art can readily understand the following operations based on the above description, their description will be omitted.

[0179] Here, the bit lines (BT, / BT) and the wirings (L20, L21) will be described. When the bit lines (BT, / BT) are first wirings, the wirings (L20, L21) can be regarded as second wirings.

[0180] like Figure 22 As shown, the bit line (BT, / BT) includes a first portion X1, a second portion X2 different from the first portion X1, and a third portion X3 different from the first portion X1 and the second portion X2, and the third portion X3 is provided between the first portion X1 and the second portion X2. The first portion X1 is connected to the write driver circuit (WDC1, WDC2) via the column switches (YS1, YS2). The second portion X2 is connected to the drain of the pull-down transistors NB2, NB3 provided in the bit line potential control circuit BLPD. The third portion X3 is connected to the source or drain of the access transistors NA1, NA2 in a plurality of memory cells MC provided in a column in the memory cell array MCA. Therefore, the third portion X3 can also be regarded as a memory cell connection area. The source or drain of the plurality of access transistors can be regarded as the load capacity of the bit line (BT, / BT).

[0181] When the bit lines (BT, / BT) are observed from the output terminal side of the write driver circuit (WDC1, WDC2) or the column switch (YS1, YS2) side, the first portion X1 can be regarded as the near end (BTA, / BTA) of the bit lines (BT, / BT), and the second portion X2 can be regarded as the far end (BTB, / BTB) of the bit lines (BT, / BT).

[0182] The third portion X3 of the bit line (BT, / BT) further includes a fourth portion X4 and a fifth portion X5, with the fourth portion X4 positioned closest to the first portion X1 and the fifth portion X5 positioned closest to the second portion X2. A plurality of memory cells MC in a column include a first memory cell (MC1) having access transistors NA1 and NA2 whose sources or drains are connected to the fourth portion X4, and a second memory cell (MC2) having access transistors NA1 and NA2 whose sources or drains are connected to the fifth portion X5. The bit line (BT, / BT) further includes a sixth portion X6, which is different from the first portion X1 and the fourth portion X4 and is provided between the first portion X1 and the fourth portion X4.

[0183] like Figure 22 As shown, the wiring (L20, L21) has a first portion Y1 connected to the sixth portion X6, and a second portion Y2 different from the first portion Y1. The second portion Y2 is connected to the gates of the pull-down transistors NB2 and NB3 in the bit line potential control circuit BLPD. When the bit lines (BT, / BT) are viewed from the output terminal side of the write driver circuit (WDC1, WDC2) or the column switch (YS1, YS2), the first portion Y1 can be regarded as the near end of the wiring (L20, L21), and the second portion Y2 can be regarded as the far end of the wiring (L20, L21). The wiring (L20, L21) can be configured from a different metal wiring layer than the bit lines (BT, / BT). The wiring (L20, L21) can also be composed of a metal wiring layer on the same layer as the bit lines (BT, / BT). Since the number of transistors connected to the wirings ( L20 , L21 ) is small, the load capacity of the wirings ( L20 , L21 ) is smaller than the load capacity of the bit lines (BT, / BT).

[0184] Next, we will refer to Figure 23 The transition of the potential of the bit line BT during writing will be described.

[0185] At time t1, control signal BLPDE transitions from a low level to a high level. As a result, enable transistor NB1 turns on. Write driver circuits WDC1 and WDC2 are activated by write enable signal WTE, and bit line precharge circuit PCC is deactivated by precharge control signal PC. As a result, the near-end BTA of bit line BT transitions sharply to a low level based on write data DTB. The far-end BTB of bit line BT transitions more slowly to a low level.

[0186] At time t2, since the load capacity of wiring L20 is smaller than that of bit lines (BT, / BT), the distal end L20B of wiring L20 abruptly transitions from a low level to a high level. As a result, pull-down transistor NB2 turns on, causing the distal end BTB of bit line BT to quickly transition to a low level.

[0187] At time t3, control signal BLPDE transitions from a high level to a low level. Write driver circuits WDC1 and WDC2 are deactivated by write enable signal WTE, and bit line precharge circuit PCC is activated by precharge control signal PC. As a result, the proximal end BTA of bit line BT transitions sharply from a low level to a high level. The distal end BTB of bit line BT transitions slowly to a high level.

[0188] At time t4 , since the equalization transistor PB1 and the pull-up transistors PB2 , PB3 in the bit line potential control circuit BLPD are set to the on state based on the low level of the control signal BLPDE, the far end BTB of the bit line BT quickly transitions to the high level.

[0189] According to the third embodiment, since the bit line potential control circuit BLPD is provided at the remote ends (BTB, / BTB) of the bit lines (BT, / BT), and the pull-down transistors (NB2, NB3) in the bit line potential control circuit BLPD are controlled by wiring (L20, L21) having a small load capacity, the transition of the potential level at the remote ends of the bit lines can be accelerated. As a result, the address access time of the memory device 102 during a write operation is accelerated, and the overall address access time during a read operation and a write operation of the memory device 102 can be accelerated.

[0190] (Eighth Modification Example)

[0191] Next, an eighth modification example will be described. The eighth modification example describes a signal generation circuit, a row predecoder, a column decoder (such as a control signal (BLPDE, PC, WTE) input to the unit circuit 5 of the third embodiment). In the eighth modification example, the same reference numerals are attached to the configuration having the same functions as the third embodiment, and description thereof is omitted. Figure 24 is a diagram illustrating an exemplary configuration of a memory device 102 according to an eighth modification example. Figure 25 1 is a diagram for explaining the operation of the memory device 102 according to the eighth modification example. Figure 24 In the example, the configuration of unit circuit 5 is similar to Figure 22 The configuration of the unit circuit 5 in is the same, and therefore its description is omitted. Figure 24 In the unit circuit 5, for the purpose of simplifying the drawings, only the Figure 22 Main reference numerals among the reference numerals used in the unit circuit 5 .

[0192] refer to Figure 24 The address signal ADD includes a row address signal and a column address signal. The row address signal is supplied to the row pre-decoder RPDEC1 and the row pre-decoder RPDEC2. The column address signal is supplied to the column decoder CDEC.

[0193] The internal clock signal generating circuit CGEN generates an internal clock pulse TDEC, which is supplied to the row predecoders RPDEC1 and PDEC2 and the column decoder CDEC, and controls the operations of the row predecoders RPDEC1 and PDEC2 and the column decoder CDEC.

[0194] NAND circuits NAND20 to 2n-1 function as row main decoders and word line driver circuits (WLDs). The input terminals of NAND circuits NAND20 to 2n-1 are connected to the outputs of row predecoders RPDEC1 and PDEC2. Row select signals XGN0 to XGNn-1 output from row predecoder RPDEC1 are connected to the input terminals of NAND circuits NAND20 to 2n-1, respectively. The output terminals of NAND circuits NAND20 to 2n-1 are connected to word lines WL0 to WLn-1, respectively. Multiple memory cells MC are connected to word lines WL0 to WLn-1.

[0195] The column select signal YSE1 output from the column decoder CDEC is supplied to the gates of the column switches YS1 and YS2. Figure 24 , only the column selection signal YSE1 is depicted, and other column selection signals output from the column decoder CDEC are not depicted.

[0196] The precharge control circuit PCCNT generates a precharge control signal PC based on the column selection signal YSE1 and supplies the generated precharge control signal PC to each gate of each of the equalization transistor PC1 , precharge transistors PC2 , PC3 in the bit line precharge circuit PCC.

[0197] The write control circuit WCNT receives the internal clock pulse TDEC generated by the internal clock signal generation circuit CGEN, generates a write enable signal WTE, and supplies the generated TDEC to the write driver circuits WDC1 , WDC2 .

[0198] The NAND circuit NAND2 receives an inverted internal clock pulse TDECB obtained by inverting the internal clock pulse TDEC, and receives row select signals XGN0 to XGNn-1 output from the row predecoder RPDEC1, and generates a control signal BLPDE. The generated control signal BLPDE is supplied to the bit line potential control circuit BLPD.

[0199] Next, we will refer to Figure 25 The operation of the memory device 102 is described below.

[0200] At time t1, the internal clock pulse TDEC transitions from low to high, and the inverted internal clock pulse TDECB transitions from high to low. The transition of the internal clock pulse TDEC to high causes the row select signal XGNn-1 to transition from high to low, and causes the column select signal YSE1 to transition from low to high.

[0201] At time t2, the transition of the row select signal XGNn-1 to a low level causes the control signal BLPDE to transition from a low level to a high level, turning on the enable transistor NB1. Furthermore, the word line WLn-1 transitions from a low level to a high level, causing the proximal end BTA of the bit line BT to transition quickly from a high level to a low level, while the distal end BTB of the bit line BT transitions slowly to a low level.

[0202] At time t3, since the load capacity of wiring L20 is smaller than that of bit lines (BT, / BT), the distal end L20B of wiring L20 abruptly transitions from a low level to a high level. As a result, pull-down transistor NB2 turns on, causing the distal end BTB of bit line BT to quickly transition to a low level.

[0203] At time t4, the internal clock pulse TDEC transitions from a high level to a low level, and the inverted internal clock pulse TDECB transitions from a low level to a high level. The transition of the internal clock pulse TDEC to a low level causes the row select signal XGNn-1 to transition from a low level to a high level, and causes the column select signal YSE1 to transition from a high level to a low level. The transition of the row select signal XGNn-1 to a high level causes the control signal BLPDE to transition from a high level to a low level, thereby turning off the enable transistor NB1. Furthermore, the word line WLn-1 transitions from a high level to a low level, the proximal end BTA of the bit line BT transitions quickly from a low level to a high level, and the distal end BTB of the bit line BT transitions slowly to a high level.

[0204] At time t5, the equalization transistor PB1 and the pull-up transistors PB2 and PB3 in the bit line potential control circuit BLPD are turned on based on the low level of the control signal BLPDE, causing the distal end BTB of the bit line BT to rapidly transition to a high level. Because the load capacity of the wiring L20 is smaller than that of the bit lines (BT, / BT), the distal end L20B of the wiring L20 rapidly transitions from a high level to a low level.

[0205] According to the eighth modified example, the control signal BLPDE is generated using the pulse of the internal clock pulse TDEC and the row select signal XGN1 to n-1 generated from the internal clock pulse TDEC and the address signal ADD. The high level (selection level) period of the word lines WL1 to n-1 and the low level period of the bit line BT can be shifted depending on the process, temperature, and voltage of the plurality of transistors constituting the memory device 102. However, since the row select signal XGN1 to n-1 determines the pulse width of the high level period of the word lines WL1 to n-1, the bit line BT is not pulled up during the period in which the word lines WL1 to n-1 are at a high level, and the period in which the bit line BT is at a low level is ensured.

[0206] The fourth embodiment shows an exemplary configuration applied to a search line of a TCAM. Figure 26 is a diagram showing an exemplary configuration of a unit circuit 6 of a TCAM according to the fourth embodiment. Figure 27 It is a diagram illustrating the configuration of the inverter circuit (IV23, IV25). Figure 28 1 is a diagram for explaining the search operation of the unit circuit 6 according to the fourth embodiment.

[0207] TCAM (Ternary Content Addressable Memory) is a content reference memory, and each of the multiple memory cells TCAMMC of the TCAM can store "Don't Care" information in addition to storing information "0" and "1". "Don't Care" means that both "0" and "1" can be used. In the TCAM, the search data (STD, SBD) is input to the search line pair ST, SB, and the data to be stored is compared with the search data (STD, SBD) in the corresponding memory cell TCAMMC. When the search data (STD, SBD) and the stored data are consistent with each other, the consistent result is output to the match line. Figure 26 , a configuration including a search line pair ST and SB of a TCAM is shown as a unit circuit 6. One search line ST of the search line pair ST, SB may be referred to as a first search line, and the other search line SB of the search line pair ST, SB may be referred to as a second search line.

[0208] The unit circuit 6 includes search line driver circuits SD1 and SD2, a search line pair ST and SB, a plurality of memory cells TCAMMC, and wirings L30 and L31. When the search lines (ST and SB) are first wirings, the wirings (L30 and L31) can be regarded as second wirings.

[0209] First, refer to Figure 29 An exemplary configuration of the memory cell TCAMMC is described below. Figure 29 As shown, each of the plurality of memory cells TCAMMC of the TCAM includes a memory cell MC00, MC10 and a data comparison circuit DCMP. Each memory cell MC00, MC10 is a single-port memory cell (6T SP SRAM cell) including six MOS transistors.

[0210] Memory cell MC00 includes a first P-channel MOS transistor PM1 and a second P-channel MOS transistor PM2, and first to fourth N-channel MOS transistors NT1, NT2, ND1, and ND2. The source-drain paths of the P-channel MOS transistors PM1 and PM2, which serve as first and second load transistors, are connected between a supply line for power supply voltage VDD and a first storage node MB1 and a second storage node MT1, respectively. The gates of PM1 and PM2 are connected to the second storage node MT1 and the first storage node MB1, respectively. The source-drain paths of the N-channel MOS transistors ND1 and ND2, which serve as first and second driver transistors, are connected between a supply line for ground potential VSS and the first storage node MB1 and the second storage node MT1, respectively. The gates of ND1 and ND2 are connected to the second storage node MT1 and the first storage node MB1, respectively. N-channel MOS transistors NT1 and NT2, serving as first and second pass transistors, have their source-drain paths connected between first and second storage nodes MB1 and MT1 and bit lines BL1 and BL0, respectively. The gates of NT1 and NT2 are both connected to word line WLe0. MOS transistors PM1 and ND1 form a first inverter, which provides an inverted signal of the signal on second storage node MT1 to first storage node MB1. MOS transistors PM2 and ND2 form a second inverter, which provides an inverted signal of the signal on first storage node MB1 to second storage node MT1. The inputs and outputs of the two inverters are connected in antiparallel between first and second storage nodes MB1 and MT1, forming a latch circuit.

[0211] Memory cell MC10 includes a first P-channel MOS transistor PM3 and a second P-channel MOS transistor PM4, and first to fourth N-channel MOS transistors NT3, NT4, ND3, and ND4. The source-drain paths of the P-channel MOS transistors PM3 and PM4, which serve as first and second load transistors, are connected between a supply line for power supply voltage VDD and the first storage node MB2 and the second storage node MT2, respectively. The gates of PM3 and PM4 are connected to the second storage node MT2 and the first storage node MB2, respectively. The source-drain paths of the N-channel MOS transistors ND3 and ND4, which serve as first and second drive transistors, are connected between a supply line for ground potential VSS and the first storage node MB2 and the second storage node MT2, respectively. The gates of ND3 and ND4 are connected to the second storage node MT2 and the first storage node MB2, respectively. The source-drain paths of N-channel MOS transistors NT3 and NT4 serving as first and second transfer transistors are connected between the first and second storage nodes MB2 and MT2 and the bit lines BL2 and BL1, respectively, and the gates of NT3 and NT4 are both connected to the word line WLo0.

[0212] MOS transistors PM3 and ND3 form a first inverter for providing an inverted signal of the signal on the second storage node MT2 to the first storage node MB2. MOS transistors PM4 and ND4 form a second inverter for providing an inverted signal of the signal on the first storage node MB2 to the second storage node MT2. The inputs and outputs of the two inverters are connected in antiparallel between the first and second storage nodes MB2 and MT2, forming a latch circuit.

[0213] Data comparison circuit DCMP includes four N-channel MOS transistors (NS0-NS3). The source-drain path of N-channel MOS transistor NS0 and the source-drain path of N-channel MOS transistor NS1 are connected in series between match line ML0 and a supply line of ground potential VSS. The gate of N-channel MOS transistor NS0 is connected to one search line (search line ST) of a search line pair (ST, SB). The gate of N-channel MOS transistor NS1 is connected to first storage node MT2 of memory cell MC10. The source-drain path of N-channel MOS transistor NS2 and the source-drain path of N-channel MOS transistor NS3 are connected in series between match line ML0 and a supply line of ground potential VSS. The gate of N-channel MOS transistor NS2 is connected to the other search line (search line SB) of the search line pair (ST, SB). The gate of N-channel MOS transistor NS3 is connected to second storage node MB1 of memory cell MC00.

[0214] One TCAM cell TCEL can store three values ​​"0", "1" and "*" (arbitrary value) as TCAM data using a 2-bit SRAM cell. For example, when "0" is stored in the storage node MB1 of MC00 and "1" is stored in the storage node MT2 of MC10, it is assumed that "0" is stored in the TCAM cell TCEL. When "1" is stored in the storage node MB1 of MC00 and "0" is stored in the storage node MT2 of MC10, it is assumed that "1" is stored in the TCAM cell TCEL. When "0" is stored in the storage node MB1 of MC00 and "0" is stored in the storage node MT2 of MC10, it is assumed that "*" (arbitrary value) is stored in the TCAM cell TCEL. The case in which "1" is stored in the storage node MB1 of MC00 and "1" is stored in the storage node MT2 of MC10 is not used.

[0215] When the search data is "1" (i.e., the search line ST is "1" and the search line SB is "0"), and the TCAM data is "0" (the storage node MB1 is "0" and the storage node MT2 is "1"), MOS transistors NS0 and NS1 become on, so that the pre-charge potential of the matching line ML is pulled down to the ground potential.

[0216] When the search data is "0" (i.e., the search line ST is "0" and the search line SB is "1") and the TCAM data is "1" (the storage node MB1 is "1" and the storage node MT2 is "0"), MOS transistors NS2 and NS3 are turned on, so that the precharge potential of the match line ML is pulled down to the ground potential. That is, when the search data and the TCAM data do not coincide with each other, the potential of the match line ML is pulled down to the ground potential.

[0217] On the contrary, when the input search data is "1" and the TCAM data is "1" or "*", or when the search data is "0" and the TCAM data is "0" or "*" (i.e., when the two are consistent with each other), the precharge potential (power supply potential VDD level) of the match line ML is maintained.

[0218] like Figure 26 As shown, the search line ST includes a first portion X1, a second portion X2 different from the first portion X1, and a third portion X3 different from the first portion X1 and the second portion X2, and the third portion X3 is provided between the first portion X1 and the second portion X2. The first portion X1 of the search line ST is connected to the output terminal of the search line driver circuit SD1. The second portion X2 of the search line ST is connected to the pull-down transistor N26 provided in the inverter circuit IV23 (see FIG. Figure 27 ) and pull-up transistor P26 (see Figure 27). The third portion X3 of the search line ST is connected to the gates of multiple transistors NS0 in the data comparison circuit DCMP provided in the multiple memory cells TCCAMC of a column in the memory cell array MCA. Therefore, the third portion X3 of the search line ST can also be considered a memory cell connection area. The gates of the multiple transistors NS0 can be considered as the load capacity of the search line ST. When viewed from the output terminal side of the search line driver circuit SD1, the first portion X1 of the search line ST can be considered as the near end STA of the search line ST, and the second portion X2 of the search line ST can be considered as the far end STB of the search line ST.

[0219] like Figure 26 As shown, the search line SB includes a first portion X1, a second portion X2 different from the first portion X1, and a third portion X3 different from the first portion X1 and the second portion X2, and the third portion X3 is provided between the first portion X1 and the second portion X2. The first portion X1 of the search line SB is connected to the output terminal of the search line driver circuit SD2. The second portion X2 of the search line SB is connected to the pull-down transistor N26 provided in the inverter circuit IV25 (see FIG. Figure 27 ) and pull-up transistor P26 (see Figure 27 ). The third portion X3 of the search line SB is connected to the gates of multiple transistors NS2 in the data comparison circuit DCMP, which is provided in a plurality of memory cells TCCAMC in a column provided in the memory cell array MCA. Therefore, the third portion X3 of the search line SB can also be considered a memory cell connection area. The gates of the multiple transistors NS2 can be considered as the load capacity of the search line SB. When viewed from the output terminal of the search line driver circuit SD2, the first portion X1 of the search line SB can be considered as the near end SBA of the search line SB, and the second portion X2 of the search line SB can be considered as the far end SBB of the search line SB.

[0220] The third portion X3 of the search line (ST, SB) further includes a fourth portion X4 and a fifth portion X5, with the fourth portion X4 being located closest to the first portion X1 and the fifth portion X5 being located closest to the second portion X2. A column of a plurality of TCAM memory cells TCAMMC includes a first memory cell (MC1) having transistors NS0 and NS2 with their gates connected to the fourth portion X4, and a second memory cell (MC2) having transistors NS0 and NS2 with their gates connected to the fifth portion X5. The search line (ST, SB) further includes a sixth portion X6, which is different from the first portion X1 and the fourth portion X4 and is provided between the first portion X1 and the fourth portion X4.

[0221] Search line driver circuits SD1 and SD2 are connected to the output of inverter circuit IV21, which receives search enable signal STE at its input terminal and outputs an inverted version of search enable signal STE, signal STEN, from its output terminal. Search line driver circuits SD1 and SD2 are controlled by inverted version of search enable signal STE, signal STEN. Search line driver circuit SD1 is adapted to receive search data STD, and its output is connected to the near end STA of search line ST. Search line driver circuit SD2 is adapted to receive search data SBD, and its output is connected to the near end SBA of search line SB. That is, when viewed from the output of search line driver circuit SD1, search line ST has a near end STA and a far end STB. When viewed from the output of search line driver circuit SD2, search line SB has a near end SBA and a far end SBB. Search line driver circuit SD1 changes the potential of search line ST by supplying a potential corresponding to search data STD to search line ST based on an inverted signal STEN of search enable signal STE. Search line driver circuit SD2 changes the potential of search line SB by supplying a potential corresponding to search data SBD to search line SB based on an inverted signal STEN of search enable signal STE. Search enable signal STE can be input to search line drivers SD1 and SD2 without passing through inverter circuit IV21.

[0222] A plurality of memory cells TCAMMC are connected between a search line ST and a search line SB between the near-end STA, SBA and the far-end STB, SBB.

[0223] Wiring L30 is a metal wiring provided in parallel with search line ST. Wiring L30 has a first portion Y1 and a second portion Y2, which is different from the first portion Y1. The first portion Y1 of wiring L30 is connected to the output terminal of inverter circuit IV22. The input terminal of inverter circuit IV22 is connected to the sixth portion X6 of search line ST. The second portion Y2 of wiring L30 is connected to the input terminal of inverter circuit IV23. The output terminal of inverter IV23 is connected to the second portion X2 of search line ST. When viewed from search line driver circuit SD1, the first portion Y1 of wiring L30 can be considered as the proximal end L30A of wiring L30, and the second portion Y2 of wiring L30 can be considered as the distal end L30B of wiring L30. The load capacity of wiring L30 is smaller than that of search line ST, to which multiple memory cells TCAMMC are connected.

[0224] Wiring L31 is a metal wiring provided in parallel with search line SB and includes a first portion Y1 and a second portion Y2, which is different from the first portion Y1. The first portion Y1 of wiring L31 is connected to the output terminal of inverter circuit IV24. The input terminal of inverter circuit IV24 is connected to the sixth portion X6 of search line SB. The second portion Y2 of wiring L31 is connected to the input terminal of inverter circuit IV25. The output terminal of inverter IV25 is connected to the second portion X2 of search line SB. When viewed from the search line driver circuit SD2, the first portion Y1 of wiring L31 can be considered as the proximal end L31A of wiring L31, and the second portion Y2 of wiring L31 can be considered as the distal end L31B of wiring L31. The load capacity of wiring L31 is smaller than that of search line SB, to which multiple memory cells TCAMMC are connected.

[0225] like Figure 27 As shown, each of inverter circuits IV23 and IV25 includes a P-channel MOS field-effect transistor P26 as a pull-up transistor and an N-channel MOS field-effect transistor N26 as a pull-down transistor. P-channel MOS field-effect transistor P26 has a gate connected to input i, a source connected to memory power supply potential VDDM2, and a drain connected to output o. N-channel MOS field-effect transistor N26 has a gate connected to input i, a source connected to ground potential GND, and a drain connected to output o. In inverter circuit IV23, input i is connected to the far end L30B of wiring L30, while output o is connected to the far end STB of search line ST. In inverter circuit IV25, input i is connected to the far end L31B of wiring L31, and output o is connected to the far end SBB of search line SB.

[0226] exist Figure 26 In the embodiment of the present invention, when the search line ST transitions from a low level to a high level based on the search data STD, the potential level of the near end STA of the search line ST rapidly transitions from a low level to a high level. Since the load capacity of the search line ST is large, the potential level of the far end STB of the search line ST gradually rises from a low level to a high level. On the other hand, since the load capacity of the wiring L30 is low, the potential level of the far end L30B of the wiring L30 rapidly transitions from a high level to a low level. Therefore, the output of the inverter circuit IV23 rapidly transitions from a low level to a high level, and the potential level of the far end STB of the search line ST rapidly transitions to a high level. Those skilled in the art will readily understand the transition of the search line SB from a high level to a low level based on the above description, and its description will be omitted.

[0227] Next, we will refer to Figure 28 The operation of the search line ST unit circuit 6 is described below. Figure 28In , the search line ST changes from a low level to a high level based on the search data STD. Figure 28 , the waveform indicated by the dotted line Z27 indicates a waveform in which the wiring L30, the inverter circuits IV22 and IV23 are not provided.

[0228] At time t1, when the search enable signal STE goes to an active level and the search data STD is input, the near end STA of the search line ST quickly transitions from a low level to a high level based on the search data STD. Since the load capacity of the search line ST is large, the potential level of the far end STB of the search line ST gradually rises from a low level to a high level. On the other hand, since the load capacity of the wiring L30 is low, the potential level of the far end L30B of the wiring L30 quickly transitions from a high level to a low level.

[0229] At time t2 , based on the low level of the distal end L30B of the wiring L30 , the output of the inverter circuit IV23 quickly transitions from the low level to the high level, and the potential level of the distal end STB of the search line ST quickly transitions to the high level.

[0230] At time t3, when the search enable signal STE is deactivated, the near end STA of the search line ST quickly transitions from a high level to a low level. As a result, the potential level of the far end STB of the search line ST gradually drops from a high level to a low level. On the other hand, the potential level of the far end L30B of the wiring L30 quickly transitions from a low level to a high level.

[0231] At time t4 , based on the high level of the distal end L30B of the wiring L30 , the output of the inverter circuit IV23 quickly transitions from the high level to the low level, and the potential level of the distal end STB of the search line ST quickly transitions to the low level.

[0232] According to the fourth embodiment, since the rising and falling speeds of the potential level of the distal end STB of the search line ST can be increased, the individual search period of the TCAM can be shortened, and the entire search operation of the TCAM can be made faster.

[0233] Although the invention of the present inventors has been described in detail above based on the embodiments, the present invention is not limited to the above-described embodiments and implementation modes, and various modifications can be made to the present invention of course.

Claims

1. A semiconductor device comprising: The first wiring comprises: Part I; a second portion that is different from the first portion; and a third portion that is different from the first portion and the second portion and is disposed between the first portion and the second portion; a driver circuit connected to the first portion; a plurality of memory cells connected to the third portion; a second wiring connected to the first portion; a potential changing circuit, the potential changing circuit being different from the driver circuit; wherein the first wiring comprises a word line; wherein the driver circuit is supplied with a first power supply potential, and drives the first wiring and the second wiring based on the first power supply potential; wherein the plurality of memory cells are supplied with a second power supply potential, and in a read operation of the plurality of memory cells, the first power supply potential is lower than the second power supply potential; and wherein the potential changing circuit is connected to the second wiring and is configured to be activated so as to pull up the second portion of the word line based on the potential level of the driven second wiring.

2. The semiconductor device according to claim 1, wherein the third portion includes a fourth portion and a fifth portion, the fourth portion is positioned in a portion closest to the first portion, and the fifth portion is positioned in a portion closest to the second portion, wherein the first wiring includes a sixth portion that is different from the first portion and the fourth portion and is positioned between the first portion and the fourth portion, wherein the potential changing circuit includes a field effect transistor having a gate connected to the sixth portion, a source supplied with the first power supply potential, and a drain connected to the second portion.

3. A semiconductor device comprising: a first wiring including a first portion, a second portion different from the first portion, and a third portion different from the first portion and the second portion, the third portion being positioned between the first portion and the second portion; a driver circuit comprising an input terminal, and wherein the first portion is connected to an output terminal of the driver circuit; a plurality of memory cells connected to the third portion; a field effect transistor having a gate and a drain connected to the second portion; A potential generating circuit generates a first power supply potential, a second wiring located in parallel with the first wiring; wherein the third portion includes a fourth portion and a fifth portion, the fourth portion is positioned in a portion closest to the first portion, and the fifth portion is positioned in a portion closest to the second portion, wherein the first wiring includes a sixth portion that is different from the first portion and the fourth portion and is positioned between the first portion and the fourth portion, wherein the plurality of memory cells include a first memory cell connected to the fourth portion, and a second memory cell connected to the fifth portion, and wherein the second wiring is electrically connected between the sixth portion and the gate of the field effect transistor; wherein the first wiring comprises a word line, wherein the plurality of memory cells are supplied with a second power supply potential, wherein the potential generating circuit generates the first power supply potential lower than the second power supply potential in a read operation of the plurality of memory cells; The driver circuit is supplied with the first power supply potential, drives the first wiring and the second wiring based on the first power supply potential, and pulls up the second portion of the word line by turning on the field effect transistor based on the potential level of the driven second wiring. 4 . The semiconductor device according to claim 3 , wherein the field effect transistor comprises a pull-up transistor, and wherein a source of the field effect transistor is connected to a power supply potential.

5. The semiconductor device according to claim 3, wherein the field effect transistor comprises a pull-down transistor, and The source of the field effect transistor is electrically connected to the ground potential. 6 . The semiconductor device according to claim 3 , wherein the first wiring and the second wiring are formed of a metal wiring layer of the same layer.

7. The semiconductor device according to claim 3, wherein the first wiring is formed of a first metal wiring layer, and The second wiring is formed of a second metal wiring layer different from the first metal wiring layer.

8. A semiconductor device comprising: a first wiring including a first portion, a second portion different from the first portion, and a third portion positioned between the first portion and the second portion; a driver circuit comprising an input terminal, and an output terminal connected to the first portion; a plurality of memory cells connected to the third portion; a field effect transistor having a gate and a drain connected to the second portion; a second wiring located in parallel with the first wiring; as well as a third wiring connected to the input terminal of the driver circuit, wherein the second wiring is electrically connected between the third wiring and the gate of the field effect transistor; wherein the first wiring comprises a word line, wherein the field effect transistor comprises a first p-channel field effect transistor, wherein the driver circuit comprises a second p-channel field effect transistor, a first n-channel field effect transistor, and a third p-channel field effect transistor, wherein the second p-channel field effect transistor includes a gate connected to the input terminal of the driver circuit, a drain connected to the output terminal of the driver circuit, and a source connected to a power supply potential, wherein the first n-channel field effect transistor includes a gate connected to the input terminal of the driver circuit, a drain connected to the output terminal of the driver circuit, and a source connected to a ground potential, wherein the third p-channel field effect transistor includes a gate connected to the input terminal of the driver circuit, a source connected to the output terminal of the driver circuit, and a drain connected to the ground potential, wherein the source of the first p-channel field effect transistor is configured to receive a first power supply potential generated by the potential generating circuit, wherein the plurality of memory cells are supplied with a second power supply potential, and In a read operation of the plurality of memory cells, the potential generating circuit generates the first power supply potential lower than the second power supply potential.

9. The semiconductor device according to claim 8, further comprising: a potential generating circuit, wherein the potential generating circuit generates a first power supply potential; wherein the first wiring comprises a word line, wherein the plurality of memory cells are supplied with a second power supply potential, wherein the driver circuit is supplied with the first power supply potential and drives the word line based on the first power supply potential, and In a read operation of the plurality of memory cells, the potential generating circuit generates the first power supply potential lower than the second power supply potential.

10. The semiconductor device according to claim 8, further comprising: a fourth wiring connected to the gate of the field effect transistor; a first inverter circuit including an output and an input connected to the third wiring; a second inverter including an input and an output connected to the fourth wiring; The second wiring connects the output of the first inverter circuit and the input of the second inverter circuit.

11. The semiconductor device according to claim 10, further comprising: a potential generating circuit, wherein the potential generating circuit generates a first power supply potential; wherein the first wiring comprises a word line, wherein the plurality of memory cells are supplied with a second power supply potential, wherein the driver circuit is supplied with the first power supply potential and drives the word line based on the first power supply potential, and In a read operation of the plurality of memory cells, the potential generating circuit generates the first power supply potential lower than the second power supply potential.

12. The semiconductor device according to claim 8, further comprising: a second n-channel field effect transistor having a gate and a source-drain path, wherein the gate of the second n-channel field effect transistor is connected to the gate of the first p-channel field effect transistor, and The source-drain path of the second n-channel field effect transistor is connected between the word line and the ground potential.

13. A method for driving a semiconductor device, the semiconductor device comprising: a first wiring including a first portion, a second portion different from the first portion, and a third portion positioned between the first portion and the second portion; a driver circuit comprising an input terminal, and an output terminal connected to the first portion; a plurality of memory cells connected to the third portion; a field effect transistor having a gate and a drain connected to the second portion, and a second wiring positioned in parallel with the first wiring and electrically connected between the output terminal of the driver circuit and the gate of the field effect transistor, wherein the first wiring comprises a word line, wherein the field effect transistor comprises a first p-channel field effect transistor, wherein the driver circuit comprises a second p-channel field effect transistor, a first n-channel field effect transistor, and a third p-channel field effect transistor, wherein the second p-channel field effect transistor includes a gate connected to the input terminal of the driver circuit, a drain connected to the output terminal of the driver circuit, and a source connected to a power supply potential, wherein the first n-channel field effect transistor includes a gate connected to the input terminal of the driver circuit, a drain connected to the output terminal of the driver circuit, and a source connected to a ground potential, wherein the third p-channel field effect transistor includes a gate connected to the input terminal of the driver circuit, a source connected to the output terminal of the driver circuit, and a drain connected to the ground potential, wherein the source of the first p-channel field effect transistor is configured to receive a first power supply potential generated by the potential generating circuit, wherein the plurality of memory cells are supplied with a second power supply potential, and wherein in a read operation of the plurality of memory cells, the potential generating circuit generates the first power supply potential lower than the second power supply potential; The method comprises the following steps: driving the first wiring and the second wiring by the driver circuit, turning on the field effect transistor based on the potential level of the driven second wiring, and Pull the second portion up or down.

14. The method for driving the semiconductor device according to claim 13, wherein the first wiring comprises a bit line, The method further comprises the following steps: The second portion of the bit line is pulled down by turning on the field effect transistor based on the potential level of the driven second wiring.

15. The method for driving the semiconductor device according to claim 13, wherein the first wiring comprises a search line, The method further comprises the following steps: Based on the potential level of the driven second wiring, the second portion of the bit line is pulled up by turning on the field effect transistor.

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