Non-volatile memory device and method of programming the same

Abstract

A non-volatile memory device and a programming method thereof are disclosed. The non-volatile memory device includes an array of memory cells including a plurality of memory cells connected to a plurality of bit lines, respectively, and a control logic unit configured to control a programming operation with respect to the plurality of memory cells. The control logic unit is configured to, during the programming operation, perform a normal program verify operation with respect to the plurality of memory cells by using a normal program verify condition, and perform an initial program verify operation with respect to the plurality of memory cells by using an initial program verify condition different from the normal program verify condition, based on a suspend command received during the programming operation.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0050453, filed April 30, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device in which a suspend-resume operation is performed during a program operation, and a program method of a nonvolatile memory device. BACKGROUND

[0003] A memory device is used to store data, and is classified into a volatile memory device and a nonvolatile memory device. When a read operation needs to be performed during a program operation of a nonvolatile memory device, a memory controller can suspend a program operation that is currently being performed, perform the read operation, and then can resume the suspended program operation. A time interval between the suspension and the resumption can cause deterioration of a program threshold voltage distribution and / or reliability of the memory device. SUMMARY

[0004] The present inventive concept provides a nonvolatile memory device capable of preventing deterioration of a program threshold voltage distribution during a program suspend-resume operation, and a method of programming the nonvolatile memory device.

[0005] According to an aspect of the present inventive concept, there is provided a nonvolatile memory device including: a memory cell array including a plurality of memory cells respectively connected to a plurality of bit lines; and a control logic unit configured to control a program operation with respect to the plurality of memory cells. The control logic unit is configured to, during the program operation, perform a normal program verify operation with respect to the plurality of memory cells by using a normal program verify condition, and based on a suspend command received during the program operation, perform an initial program verify operation with respect to the plurality of memory cells by using an initial program verify condition different from the normal program verify condition.

[0006] According to another aspect of the present inventive concepts, there is provided a method of programming a non-volatile memory device, the method comprising: in response to a program command, applying a first program voltage to a selected word line to which a plurality of memory cells are connected; in response to a suspend command or a resume command received after the suspend command, performing an initial program verify operation by developing voltage levels of a plurality of sense nodes during an initial development time, the plurality of sense nodes being respectively connected to a plurality of bit lines which are respectively connected to the plurality of memory cells; in response to the resume command, applying a second program voltage to the selected word line; and performing a normal program verify operation by developing voltage levels of the plurality of sense nodes during a normal development time which is different from the initial development time.

[0007] According to another aspect of the present inventive concepts, there is provided a method of programming a non-volatile memory device, the method comprising: in response to a program command, applying a first program voltage to a selected word line to which a plurality of memory cells are connected; in response to a suspend command or a resume command received after the suspend command, performing an initial program verify operation by developing voltage levels of a plurality of sense nodes during an initial development time, the plurality of sense nodes being respectively connected to a plurality of bit lines which are respectively connected to the plurality of memory cells; in response to the resume command, applying a second program voltage to the selected word line; and performing a normal program verify operation by developing voltage levels of the plurality of sense nodes during a normal development time which is different from the initial development time. BRIEF DESCRIPTION OF DRAWINGS

[0008] Exemplary embodiments of the present inventive concepts will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a memory system according to some embodiments of the present inventive concepts;

[0010] Figure 2 is a block diagram of a memory system according to some embodiments of the present inventive concepts; Figure 1 is a block diagram of a non-volatile memory device (NVM) according to some embodiments of the present inventive concepts;

[0011] Figure 3 is a circuit diagram of a memory block according to some embodiments of the present inventive concepts;

[0012] Figure 4 shows a program operation including a plurality of program loops according to some embodiments of the present inventive concepts;

[0013] Figure 5 is a flowchart of operations between a memory controller and an NVM according to some embodiments of the present inventive concepts;

[0014] Figure 6 shows a suspend-resume operation during a program operation according to some embodiments of the present inventive concepts;

[0015] Figure 7A and Figure 7B are graphs showing degradation of threshold voltage distribution due to suspend-resume operation according to some embodiments of the inventive concept;

[0016] Figure 8 showing suspend-resume operation during a program operation according to some embodiments of the inventive concept;

[0017] Figure 9 is a flowchart of a method of programming NVM according to some embodiments of the inventive concept;

[0018] Figure 10 showing normal program verify operation and initial program verify operation according to some embodiments of the inventive concept;

[0019] Figure 11A and Figure 11B are block diagrams of a page buffer according to embodiments of the inventive concept, respectively;

[0020] Figure 12 showing latch values according to thresholds of memory cells during a program operation according to some embodiments of the inventive concept;

[0021] Figure 13 showing voltages of selected word lines and selected bit lines during a program operation according to some embodiments of the inventive concept;

[0022] Figure 14 is a graph showing variation of a sense node voltage according to normal program verify operation according to some embodiments of the inventive concept;

[0023] Figure 15A and Figure 15B is a graph showing variation of a sense node voltage according to initial program verify operation according to embodiments of the inventive concept;

[0024] Figure 16 is a circuit diagram of a part of a page buffer according to some embodiments of the inventive concept;

[0025] Figure 17 showing control signals applied to first to fourth transistors included in a page buffer of Figure 16 during a program verify operation according to some embodiments of the inventive concept;

[0026] Figure 18A showing threshold voltage distribution due to suspend-resume operation according to a comparative example of the inventive concept, Figure 18B showing threshold voltage distribution due to suspend-resume operation according to some embodiments of the inventive concept;

[0027] Figure 19 and Figure 20 is a flowchart of a method of programming an NVM according to embodiments of the inventive concept;

[0028] Figure 21A and Figure 21B is a graph showing a change in word line voltage over time during a program verify operation according to some embodiments of the inventive concept;

[0029] Figure 22 is a flowchart of a method of programming an NVM according to some embodiments of the inventive concept;

[0030] Figure 23 is a block diagram of a memory system according to some embodiments of the inventive concept; and

[0031] Figure 24 is a block diagram of a solid state drive (SSD) system having applied a memory device according to embodiments of the inventive concept. DETAILED DESCRIPTION

[0032] Embodiments will now be described more fully with reference to the accompanying drawings.

[0033] Figure 1 is a block diagram of a memory system 10 according to some embodiments of the inventive concept.

[0034] Referring to Figure 1 , the memory system 10 can include a non-volatile memory device (NVM) 100 and a memory controller 200. The NVM 100 can include a memory cell array 110, a page buffer unit 120, and a control logic unit 130. The memory cell array 110 can include a plurality of memory cells, and the page buffer unit 120 can include a plurality of page buffers.

[0035] In response to a write / read request from a host HOST, the memory controller 200 can control the NVM 100 so that data is read from or programmed to the NVM 100. Specifically, the memory controller 200 can control a program operation, a read operation, and an erase operation with respect to the NVM 100 by providing a command CMD, an address ADDR, and a control signal CTRL to the NVM 100. Data DATA to be programmed and read data DATA can be transmitted or received between the memory controller 200 and the NVM 100.

[0036] The memory controller 200 can generate a suspend command SUS_CMD and a resume command RES_CMD, and can transmit the suspend command SUS_CMD and the resume command RES_CMD to the NVM 100. For example, while the NVM 100 is performing a program operation, the memory controller 200 can receive a read request from the host HOST. At this time, the memory controller 200 can transmit the suspend command SUS_CMD to the NVM 100, and can control a read operation with respect to the NVM 100. When the read operation is completed, the memory controller 200 can transmit the resume command RES_CMD to the NVM 100. Now, a suspend-resume operation during a program operation of the NVM 100 will be mainly described by way of example. However, the inventive concept is not limited thereto. For example, embodiments of the inventive concept are equally applicable to a suspend-resume operation during an erase operation of the NVM 100.

[0037] In detail, the memory controller 200 can include a suspend / resume controller 210, and the suspend / resume controller 210 can control a suspend operation and a resume operation with respect to the NVM 100. According to some embodiments, the suspend / resume controller 210 can be implemented as software or firmware, and a processor included in the memory controller 200 can execute instructions for performing a function of the suspend / resume controller 210. According to some embodiments, the suspend / resume controller 210 can be implemented as hardware.

[0038] The control logic unit 130 can receive a program command PGM_CMD from the memory controller 200, and can control a program operation with respect to a memory cell included in the memory cell array 110 in response to the received program command PGM_CMD. At this time, the control logic unit 130 can sequentially perform a plurality of program loops during the program operation, and each of the plurality of program loops can include a normal program verify operation to which a normal program verify condition is applied. For example, the normal program verify condition can include a normal development time and a normal program verify voltage.

[0039] The control logic unit 130 can receive a suspend command SUS_CMD from the memory controller 200 during the program operation, and perform an initial program verify operation in response to the suspend command SUS_CMD. The control logic unit 130 can receive a resume command RES_CMD from the memory controller 200 after the suspend command SUS_CMD, and perform an initial program verify operation in response to the resume command RES_CMD. The initial program verify operation is a program verify operation to which an initial program verify condition different from the normal program verify condition is applied, and can be referred to as a "suspend program verify operation" or a "resume program verify operation". For example, the initial program verify condition can include an initial development time different from the normal development time, and an initial program verify voltage different from the normal program verify voltage.

[0040] Figure 2 is a block diagram of an NVM 100 according to some embodiments of the inventive concepts. Figure 1

[0041] Referring to Figure 2 , the NVM 100 can include a memory cell array 110, a page buffer unit 120, a control logic unit 130, a voltage generator 140, and a row decoder 150. The NVM 100 can also include a data input / output (I / O) circuit or I / O interface. The NVM 100 can also include a column logic unit, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0042] The memory cell array 110 can be connected to the page buffer unit 120 via bit lines BL and can be connected to the row decoder 150 via word lines WL, string select lines SSL, and ground select lines GSL. The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz can include a plurality of memory cells. For example, the plurality of memory cells can be flash memory cells. Embodiments of the inventive concepts will now be described in detail with reference to the case where the plurality of memory cells are NAND flash memory cells. However, the inventive concepts are not limited thereto. For example, in some embodiments, the plurality of memory cells can be resistive memory cells (such as resistive random access memory (ReRAM)), phase change RAM (PRAM), or magnetic RAM (MRAM).

[0043] According to some embodiments, the memory cell array 110 can include a three-dimensional (3D) memory cell array, which can include a plurality of NAND strings, and each of the plurality of NAND strings can include memory cells vertically stacked on a base, each connected to a word line. This will be described with reference to Figure 3 Appropriate configurations of three-dimensional memory arrays, which are configured as a plurality of layers having word lines and / or bit lines shared between the plurality of layers, are described in the following patent documents, which are incorporated herein by reference: US 7,679,133, US 8,553,466, US 8,654,587, US 8,559,235, and US 2011 / 0233648. According to some embodiments, the memory cell array 110 can include a two-dimensional (2D) memory cell array, which can include a plurality of NAND strings arranged in a column direction and a row direction.

[0044] ​The page buffer unit 120 can include a plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn can be connected to the memory cells via a plurality of bit lines BL, respectively. The page buffer unit 120 can select some of the plurality of bit lines BL in response to a column address Y-ADDR. In detail, the page buffer unit 120 operates as a write driver or a sense amplifier according to an operation mode.

[0045] Based on the command CMD, the address ADDR, and the control signal CTRL, the control logic unit 130 can output various control signals (e.g., a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR) for programming data to the memory cell array 110, reading data from the memory cell array 110, or erasing data from the memory cell array 110. Accordingly, the control logic unit 130 can control various operations of the NVM 100.

[0046] The control logic unit 130 can differently control a normal program verify operation and an initial program verify operation. The normal program verify operation can be performed in a program cycle before a suspend command SUS_CMD is received or when the suspend command SUS_CMD is not received, or in a program cycle after the initial program verify operation is performed. The initial program verify operation can be performed in response to the suspend command SUS_CMD or in response to a resume command RES_CMD received after the suspend command SUS_CMD.

[0047] The control logic unit 130 can selectively perform the initial program verify operation (using an initial development time) and the normal program verify operation (using a normal development time) according to a program cycle, a program state, etc. For example, when a current program cycle at a time when the suspend command SUS_CMD is received is less than N, the control logic unit 130 can perform the normal program verify operation instead of the initial program verify operation in response to the suspend command SUS_CMD or the resume command RES_CMD, where N can be a natural number greater than or equal to 2. The control logic unit 130 can vary an offset between the initial program verify condition and the normal program verify condition (such as a development time and / or a program verify voltage) according to a program cycle, a program state, etc. The term "and / or" can be used herein to include any and all combinations of one or more associated listed items.

[0048] The initial program verify operations can include first through Mth initial program verify operations for detecting whether the programming of the first through Mth program states has been completed, where M is a natural number greater than or equal to 2. According to some embodiments, the control logic unit 130 can independently control initial program verify conditions of the first through Mth initial program verify operations. For example, the control logic unit 130 can apply a normal progression time during the first and second initial program verify operations, a longer initial progression time than the normal progression time during the third and fourth initial program verify operations, and a shorter initial progression time than the normal progression time during the fifth and sixth initial program verify operations.

[0049] According to some embodiments, the control logic unit 130 can independently control a forcing development time and a main development time. For example, the control logic unit 130 can determine the forcing development time to be equal to a normal forcing development time, and can determine the main development time to be different from a normal main development time. For example, the control logic unit 130 can determine the forcing development time to be longer than the normal forcing development time, and can determine the main development time to be shorter than the normal main development time.

[0050] According to some embodiments, the control logic unit 130 can differently control a normal progression time applied to a normal program verify operation and an initial progression time applied to an initial program verify operation. The control logic unit 130 can increase or decrease the initial progression time compared to the normal progression time according to a program cycle, a program state, etc. The control logic unit 130 can change an offset of the initial progression time with respect to the normal progression time according to the program cycle, the program state, etc.

[0051] According to some embodiments, the control logic unit 130 can differently control a normal program verify voltage applied to a normal program verify operation and an initial program verify voltage applied to an initial program verify operation. The control logic unit 130 can increase or decrease the initial program verify voltage compared to the normal program verify voltage according to a program cycle, a program state, etc. The control logic unit 130 can change an offset of the initial program verify voltage with respect to the normal program verify voltage according to the program cycle, the program state, etc.

[0052] The voltage generator 140 can generate various types of voltages for performing program operations, read operations, and erase operations with respect to the memory cell array 110 based on a voltage control signal CTRL_vol. In detail, the voltage generator 140 can generate a word line voltage VWL (e.g., a program voltage, a read voltage, and a program verify voltage). The program verify voltage can include a normal program verify voltage and an initial program verify voltage.

[0053] In response to the row address X-ADDR, the row decoder 150 can select one memory block from the plurality of memory blocks BLK1 to BLKz, select one word line from the plurality of word lines WL of the selected memory block, and select one string selection line from the plurality of string selection lines SSL. The row decoder 150 can apply a normal program verify voltage to the selected word line during a normal program verify operation, and apply an initial program verify voltage to the selected word line during an initial program verify operation.

[0054] Figure 3 is a circuit diagram of a memory block BLK according to some embodiments of the inventive concepts.

[0055] Referring to Figure 3 , the memory block BLK can include NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33, word lines WL1 to WL8, first to third bit lines BL1 to BL3, ground selection lines GSL1 to GSL3, string selection lines SSL1 to SSL3, and a common source line CSL. The memory block BLK can correspond to one of the memory blocks BLK1 to BLKz of Figure 2 The number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines can be variously changed according to embodiments. Also, the terms "first", "second", and the like can be used herein to distinguish one element from another element, but the elements should not be limited by the terms.

[0056] The NAND strings NS11, NS21, and NS31 are disposed between the first bit line BL1 and the common source line CSL, the NAND strings NS12, NS22, and NS32 are disposed between the second bit line BL2 and the common source line CSL, and the NAND strings NS13, NS23, and NS33 are disposed between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., the NAND string NS11) can include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST connected in series.

[0057] The string selection transistor SST is connected to a corresponding one of the string selection lines SSL1 to SSL3. The memory cells MC are connected to the word lines WL1 to WL8, respectively. The ground selection transistor GST is connected to a corresponding one of the ground selection lines GSL1 to GSL3. The string selection transistor SST is connected to a corresponding one of the first to third bit lines BL1 to BL3, and the ground selection transistor GST is connected to the common source line CSL.

[0058] Figure 4 shows a program operation including a plurality of program loops according to some embodiments of the inventive concepts.

[0059] Referring to Figure 1 and Figure 4 , the programming operation can include a plurality of programming loops (e.g., a first programming loop PL1 to a twenty-first programming loop PL21), and each of the plurality of programming loops can include a program execution operation (or, a program execution part) PE and a program verify operation (or, a program verify part) VFY. For example, when the memory cells are three-level cells (TLC) each capable of storing 3-bit data, the memory cells can be programmed to one of a first program state P1 to a seventh program state P7. The program verify operation VFY can include one or more of a first program verify operation VFY1 to a seventh program verify operation VFY7, the first program verify operation VFY1 corresponding to the first program state P1, and the seventh program verify operation VFY7 corresponding to the seventh program state P7.

[0060] When the plurality of programming loops are performed, the memory cells are gradually programmed through. Being programmed through means that the memory cells enter a target threshold voltage interval. For example, the memory cells targeting the first program state P1 having the lowest target threshold voltage can all be programmed through in the seventh programming loop PL7. After the seventh program state P7 having the highest target threshold voltage interval is programmed through, the programming operation is finally ended.

[0061] During the programming operation, when the NVM 100 receives a suspend command SUS_CMD from the memory controller 200, the programming operation can be suspended. Although in Figure 4 , the programming operation is suspended in the eleventh programming loop PL11, this is merely an example, the programming operation can be suspended in any one of the first programming loop PL1 to the twenty-first programming loop PL21.

[0062] Figure 5 is a flowchart of operations between the memory controller 200 and the NVM 100 according to some embodiments of the inventive concepts. Figure 6 suspended-resume operations during a programming operation according to some embodiments of the inventive concepts are shown.

[0063] Referring to Figure 5 and Figure 6 , in operation S100, the memory controller 200 sends a program command PGM_CMD to the NVM 100. In operation S110, the NVM 100 performs a program execution operation in response to the program command PGM_CMD. For example, operation S110 can correspond to an Nth programming loop PL_N. In the program execution part of the Nth programming loop PL_N, a first program voltage VPGM1 can be applied to a selected word line WLsel. Here, N can be a positive integer.

[0064] In operation S120, the memory controller 200 transmits a suspend command SUS_CMD to the NVM 100. Accordingly, the programming operation of the NVM 100 can be suspended. According to some embodiments, when the suspend command SUS_CMD is received during the programming execution of the Nth programming loop PL_N, the NVM 100 can complete the programming execution operation that is currently being executed, and then can enter the suspend. In operation S130, the NVM 100 transmits a response message indicating that the programming operation has been suspended to the memory controller 200.

[0065] In operation S140, the memory controller 200 transmits a read command READ_CMD to the NVM 100. In operation S150, the NVM 100 performs a read operation. In operation S155, the NVM 100 transmits the read data to the memory controller 200. However, the inventive concept is not limited thereto, and the memory controller 200 can transmit another command or a plurality of commands between the suspend command SUS_CMD and the resume command RES_CMD, and accordingly, the NVM 100 can perform an operation corresponding to the received command.

[0066] In operation S160, the memory controller 200 transmits a resume command RES_CMD to the NVM 100. When the NVM 100 receives the resume command RES_CMD, the programming operation can be resumed. The time between the suspend time point and the resume time point can be referred to as a "suspend-resume time tRES". According to some embodiments, the suspend-resume time tRES can correspond to a time interval from a time point at which the suspend command SUS_CMD is received to a time point at which the resume command RES_CMD is received. According to some embodiments, the suspend-resume time tRES can correspond to a time interval from a time point at which the programming operation has been actually suspended to a time point at which the programming operation has been actually resumed.

[0067] Figure 7A and Figure 7B is a graph showing the deterioration of the threshold voltage distribution due to the suspend-resume operation according to some embodiments of the inventive concept.

[0068] Referring to Figure 7A , the horizontal axis indicates the threshold voltage Vth, and the vertical axis indicates the number of memory cells. The first distribution 71 can correspond to the distribution at the time of entering the suspend, and can be one of a plurality of program states (for example, the first program state P1 to the seventh program state P7 of Figure 4 ). The second distribution 72 can correspond to the distribution after the suspend-resume time tRES elapses, that is, the distribution at the resume time point. The charge loss phenomenon in which the charge escapes from the charge storage layer of the memory cell can occur during the suspend-resume time tRES, and accordingly, the threshold voltage of the memory cell can be lowered.

[0069] When the threshold voltage of the memory cell is increased by the program execute operation of the Nth program loop PL_N to be greater than the program verify voltage Vvfy as in the first distribution 71, and when the program verify operation is performed immediately after the program execute operation without any suspend-resume operation, it can be determined that the memory cell is programmed through. However, when the program suspend is entered according to the suspend command SUS_CMD, the threshold voltage of the memory cell can be decreased by the suspend-resume time tRES as in the second distribution 72, and the memory cell can be determined as a program failure by the program verify operation after the program resume. The memory cell determined as the program failure can undergo the program execute operation in the (N+1)th program loop PL_N+1, and thus, as in the third distribution 73, the threshold voltage of the memory cell can be greater than the threshold voltage of the target interval TG, and the read error of the NVM 100 can occur.

[0070] Referring to Figure 7B , the horizontal axis indicates the threshold voltage Vth, the vertical axis indicates the number of memory cells, and E indicates the erased state. The first distribution 74 indicates the threshold voltage distribution of the memory cells when the program operation is performed without any suspend-resume operation, and the second distribution 75 indicates the threshold voltage distribution of the memory cells when the suspend-resume operation is performed during the program operation. When the suspend-resume operation is performed during the program operation, the program threshold voltage distribution can be widened to the right as in the second distribution 75 by an over-program operation. This deterioration of the program threshold voltage distribution can cause a read failure during a read operation after the program operation ends, thereby degrading the reliability of the NVM.

[0071] Referring back to Figure 5 and Figure 6 , in operation S170, the NVM 100 performs an initial program verify operation INT_VFY in an initial program verify condition. The initial program verify condition can be different from a normal program verify condition applied to a normal program verify operation performed in a program loop before the suspend command SUS_CMD is received or after the resume command RES_CMD is received. For example, the verify condition can include a development time and a program verify voltage. This will be described in more detail with reference to Figure 9 to Figure 23 . According to some embodiments, operation S170 can be performed between operations S120 and S130 or between operations S130 and S140. This will be described in more detail below with reference to Figure 8 .

[0072] In operation S180, the NVM 100 performs a program execute operation. For example, operation S180 can correspond to the (N+1)th program loop PL_N+1. The second program voltage VPGM2 can be applied to the selected word line WLsel in the program execute part of the (N+1)th program loop PL_N+1, and the second program voltage VPGM2 can have a voltage level that is greater than the first program voltage VPGM1 by an incremental step pulse program (ISPP) level.

[0073] In operation S190, the NVM 100 performs a normal program verify operation under normal program verify conditions. For example, operation S190 can correspond to the (N+1)th program loop PL_N+1. The normal program verify operation N_VFY can be performed in the program verify part of the (N+1)th program loop PL_N+1. In the normal program verify operation N_VFY, the program verify operation can be performed according to the normal program verify conditions. This will be described in more detail with reference to Figure 9 to Figure 23

[0074] Figure 8 A suspend-resume operation during a program operation according to some embodiments of the inventive concept is shown.

[0075] Figure 8 The present embodiment can correspond to a modification of the operations shown in Figure 5 and Figure 6 . According to the present embodiment, the initial program verify operation INT_VFY can be performed after the suspend command SUS_CMD is received and before the resume command RES_CMD is received. In this case, the initial program verify operation INT_VFY can be performed using initial program verify conditions that are different from the normal program verify conditions. As such, in the various embodiments described herein, the initial program verify operation INT_VFY can be performed after the suspend command SUS_CMD is received or after the resume command RES_CMD is received.

[0076] Figure 9 is a flowchart of a method of programming an NVM according to some embodiments of the inventive concept.

[0077] Referring to Figure 9 , the programming method according to the present embodiment can correspond to a method of operating an NVM when a suspend-resume operation is performed during a program operation of the NVM. For example, the programming method according to the present embodiment can be performed in the NVM 100 of Figure 2 . The description given above with reference to Figure 1 to Figure 8 applies to the present embodiment, and repeated descriptions thereof will be omitted.

[0078] ​In operation S210, in response to the program command PGM_CMD, the NVM 100 applies the first program voltage VPGM1 to the selected word line WLsel. Operation S210 corresponds to a program execute operation. For example, operation S210 can correspond to a program execute operation in an Nth program loop PL_N of Figure 6 In operation S230, in response to the suspend command SUS_CMD or the resume command RES_CMD, the NVM 100 performs an initial program verify operation INT_VFY by developing the voltage level of the sense node during an initial development time. According to some embodiments, as shown in Figure 5 and Figure 6 Operation S230 can be performed after the resume command RES_CMD is received. According to some embodiments, as shown in Figure 8 Operation S230 can be performed after the suspend command SUS_CMD is received but before the resume command RES_CMD is received.

[0079] In operation S250, in response to the resume command RES_CMD, the NVM 100 applies the second program voltage VPGM2 to the selected word line WLsel. Operation S250 corresponds to a program execute operation. For example, operation S250 can correspond to a program execute operation in an (N+1)th program loop PL_N+1 of Figure 6 In operation S270, the NVM 100 performs a normal program verify operation N_VFY by developing the voltage level of the sense node during a normal development time.

[0080] Figure 10 A normal program verify operation 101 and initial program verify operations 102 and 103 according to some embodiments of the inventive concepts are shown.

[0081] Referring to Figure 10 , the normal program verify operation 101 can correspond to a program verify operation that is typically performed during a program operation, and can include a pre-charge portion 1011, a development portion 1012, and a sense portion 1013. The pre-charge portion 1011 can correspond to a portion in which an operation of pre-charging a voltage of a bit line BL or a sense node (e.g., the sense node SO of Figure 11A ) to a pre-charge voltage is performed. The development portion 1012 can correspond to a time portion between the pre-charge portion 1011 and the sense portion 1013, and can correspond to a portion in which an operation of developing a voltage of the sense node SO by electrically connecting the bit line BL to the sense node SO is performed. The sense portion 1013 can correspond to a portion in which an operation of sensing the voltage of the sense node SO is performed.

[0082] The initial program verify operation 102 can correspond to an example of a program verify operation when a suspend-resume operation is performed during a program operation, and can include a pre-charge portion 1021, a develop portion 1022, and a sense portion 1023. The pre-charge portion 1021, the develop portion 1022, and the sense portion 1023 can correspond to the pre-charge portion 1011, the develop portion 1012, and the sense portion 1013, respectively. The length of the develop portion 1022 of the initial program verify operation 102 can be less than the length of the develop portion 1012 of the normal program verify operation 101.

[0083] The initial program verify operation 103 can correspond to another example of a program verify operation when a suspend-resume operation is performed during a program operation, and can include a pre-charge portion 1031, a develop portion 1032, and a sense portion 1033. The pre-charge portion 1031, the develop portion 1032, and the sense portion 1033 can correspond to the pre-charge portion 1011, the develop portion 1012, and the sense portion 1013, respectively. The length of the develop portion 1032 of the initial program verify operation 103 can be greater than the length of the develop portion 1012 of the normal program verify operation 101.

[0084] Figure 11A and Figure 11B are block diagrams of page buffers according to embodiments of the inventive concepts, respectively.

[0085] Referring to Figure 11A , the page buffer 121 can include a sense latch (S-Latch) 1211 connected to the sense node SO, a force latch (F-Latch) 1212, a high bit latch (e.g., M-Latch) 1213, a low bit latch (e.g., L-Latch) 1214, and a cache latch (C-Latch) 1215. The page buffer 121 can also include a first transistor TR1 connected between the bit line BL and the sense node SO.

[0086] During a read operation or a program verify operation, the sense latch 1211 can store a sense result of data stored in a memory cell or a threshold voltage of the memory cell. During a program execution operation, the sense latch 1211 can be used to apply a program bit line voltage (e.g., Vprogram BL of Figure 13 ) or a program inhibit voltage (e.g., Vinhibit of Figure 13 ) to the bit line BL. The force latch 1212 can be used to improve a threshold voltage distribution during a program operation. A value stored in the force latch 1212 can change according to a threshold voltage of a memory cell during a program operation, and a voltage applied to the bit line BL can change according to the value stored in the force latch 1212 during a program execution operation. This will be described with reference to FIGS. 2A and 2B.Figure 13 Described in more detail.

[0087] The high latch 1213, the low latch 1214, and the cache latch 1215 can be used to store externally input data during a program operation, and can be referred to as data latches. When 3-bit data is programmed to a single memory cell, the 3-bit data can be stored in each of the high latch 1213, the low latch 1214, and the cache latch 1215. The high latch 1213, the low latch 1214, and the cache latch 1215 can maintain the stored data until the program operation of the memory cell is completed. The cache latch 1215 can receive data read from the memory cell during a read operation from the sense latch 1211, and can output the received data to the outside via the data output line DOUT.

[0088] The first transistor TR1 can be driven by a bit line shutdown signal BLSHF that controls a connection between the bit line BL and the sense node SO, and thus, the first transistor TR1 can be referred to as a "bit line shutdown transistor." For example, when data is read from the memory cell, the first transistor TR1 is turned on to electrically connect the bit line BL to the sense latch 1211. When the data stored in the sense latch 1211 is transmitted to the cache latch 1215 or the data stored in the cache latch 1215 is transmitted to the force latch 1212, the first transistor TR1 can be shut off.

[0089] Referring to Figure 11B In comparison with the page buffer 121 of Figure 11A The page buffer 121a can further include a suspend-resume latch (SR-Latch) 1217. When a suspend is entered during a program operation, the data stored in the cache latch 1215 can be transmitted to the SR-Latch 1217, and then the cache latch 1215 can become available. Thereafter, a requested read operation can be performed, the sense latch 1211 can store read data, and the read data stored in the sense latch 1211 can be transmitted to the cache latch 1215 and output to the outside via the data output line DOUT. Thereafter, the data stored in the SR-Latch 1217 can be retransmitted to the cache latch 1215, and the suspended program operation can be resumed.

[0090] Figure 12 Illustrating latch values according to threshold voltages of memory cells during a program operation according to some embodiments of the inventive concept.

[0091] Referring to Figure 11A and Figure 12The 3-bit program data received from the memory controller 200 can be stored in the high-bit latch 1213, the low-bit latch 1214, and the cache latch 1215, such that the 3 bits of the 3-bit program data are stored in the high-bit latch 1213, the low-bit latch 1214, and the cache latch 1215, respectively. For example, when the 3-bit program data is "110", the target program state can be the first program state PI, "1" can be stored in the high-bit latch 1213, "1" can be stored in the low-bit latch 1214, and "0" can be stored in the cache latch 1215.

[0092] The values stored in the high-bit latch 1213, the low-bit latch 1214, and the cache latch 1215 can hold the externally input program data values before the threshold voltage of the memory cell enters the target interval, and then when the threshold voltage of the memory cell has entered the target interval, the values stored in the high-bit latch 1213, the low-bit latch 1214, and the cache latch 1215 can all change to "1". For example, when the 3-bit program data is "110" and the threshold voltage of the memory cell has entered the first interval Rl or the second interval R2, the values stored in the high-bit latch 1213, the low-bit latch 1214, and the cache latch 1215 hold "110" as the original program data values. When the threshold voltage of the memory cell has entered the third interval R3, the values stored in the high-bit latch 1213, the low-bit latch 1214, and the cache latch 1215 can all change to "1".

[0093] The force latch 1212 stores force data. After the force data is initially set to "1", the force data can be inverted to "0" when the threshold voltage of the memory cell has not reached the target interval but has entered the force interval or the force range. For example, when the program data is "110" and the threshold voltage of the memory cell has entered the second interval R2, the value stored in the force latch 1212 is inverted from "1" to "0". The force data can be used to control the bit line voltage and form a narrow program threshold voltage distribution during the program execution operation. Although the first interval Rl to the third interval R3 for the first program state PI are shown in Figure 12 The first interval to the third interval can be distinguished based on target intervals for other program states as well.

[0094] Figure 13 Voltages of selected word lines and selected bit lines during a program operation are shown according to some embodiments of the inventive concepts.

[0095] Referring to Figure 12 and Figure 13During the program execution operation of the (N-1)th program loop PL_N-1, the program voltage VPGM can be applied to the selected word line WLsel. When the threshold voltage of the selected memory cell is in the first interval Rl, the high bit latch 1213, the low bit latch 1214, and the cache latch 1215 can maintain the initial program data, and the value of the force latch 1212 can be "1". As a result, the program bit line voltage Vprogram BL can be applied to the selected bit line BLsel. The program bit line voltage Vprogram BL is typically a ground voltage. Thereafter, the program verify operation can be performed, which can include at least one of the first program verify operation VFYl to the seventh program verify operation VFY7, and the program verify voltage Vvfy can be applied to the selected word line WLsel.

[0096] During the program execution operation of the Nth program loop PL_N, the voltage VPGM+ISPP, which is larger than the program voltage VPGM of the (N-1)th program loop PL_N-1 by the ISSP level, can be applied to the selected word line WLsel. When the threshold voltage of the selected memory cell is in the second interval R2, the value of the force latch 1212 can be the value inverted from the initial value, i.e., "0", and thus the program force voltage VFORCE can be applied to the selected bit line BLsel. The program force voltage VFORCE can be higher than the ground voltage and lower than the program inhibit voltage Vinhibit. By using this program force voltage VFORCE, the program threshold voltage distribution can be controlled to have a small width.

[0097] During the program execution operation of the (N+1)th program loop PL_N+1, the voltage VPGM+2ISSP, which is larger than the program voltage VPGM of the (N-1)th program loop PL_N-1 by 2ISSP, can be applied to the selected word line WLsel. When the threshold voltage of the selected memory cell is in the third interval R3, the data latches of the page buffer 121 corresponding to the selected memory cell can all have the value "1", and thus the program inhibit voltage Vinhibit can be applied to the selected bit line BLsel. The program inhibit voltage Vinhibit can typically be the internal power supply voltage VCC.

[0098] Figure 14 is a graph showing the change of the sense node voltage according to the normal program verify operation according to some embodiments of the present inventive concepts.

[0099] Referring to Figure 14 , the horizontal axis represents time, and the vertical axis represents the voltage V_SO of the sense node SO. The normal program verify operation according to the present embodiment can correspond to Figure 10embodiments, the normal program verify operation can be a 2-step verify operation including a forced sense portion 141 and a main sense portion 142. In the forced sense portion 141, forced sensing or pre-verify can be performed. In the main sense portion 142, main sensing or main verify can be performed. However, the inventive concept is not limited thereto, and the normal program verify operation can be a 1-step verify operation including only the main sense portion 142.

[0100] The forced sense portion 141 can include a first pre-charge portion 1411, a first development portion 1412, and a first sense portion 1413. In the first development portion 1412, a voltage level of the sense node SO is changed according to a voltage level of the bit line. In this case, a length of the first development portion 1412 can correspond to a normal forced development time Tf. The main sense portion 142 can include a second pre-charge portion 1421, a second development portion 1422, and a second sense portion 1423. In this case, a length of the second development portion 1422 can correspond to a normal main development time Tm. The normal main development time Tm can be longer than the normal forced development time Tf.

[0101] Figure 15A and Figure 15B is a graph showing a change in a voltage of a sense node according to an initial program verify operation according to an embodiment of the inventive concept.

[0102] Referring to Figure 14 and Figure 15A , the initial program verify operation according to the present embodiment can correspond to an embodiment of the initial program verify operation 103 of Figure 10 The forced sense portion 151 can include a first pre-charge portion 1511, a first development portion 1512, and a first sense portion 1513. A length of the first development portion 1512 can correspond to a first forced development time Tf', and the first forced development time Tf' can be longer than the normal forced development time Tf. The main sense portion 152 can include a second pre-charge portion 1521, a second development portion 1522, and a second sense portion 1523. A length of the second development portion 1522 can correspond to a first main development time Tm', and the first main development time Tm' can be longer than the normal main development time Tm.

[0103] Referring to Figure 14 and Figure 15B , the initial program verify operation according to the present embodiment can correspond to an embodiment of the initial program verify operation 103 of Figure 10embodiment of the initial program verify operation 102 of FIG. 1. The forced sensing portion 151' can include a first pre-charge portion 1511, a first development portion 1512', and a first sense portion 1513. The length of the first development portion 1512' can correspond to a second forced development time Tf", and the second forced development time Tf" can be shorter than the normal forced development time Tf. The main sensing portion 152' can include a second pre-charge portion 1521, a second development portion 1522', and a second sense portion 1523. The length of the second development portion 1522' can correspond to a second main development time Tm", and the second main development time Tm" can be shorter than the normal main development time Tm.

[0104] Figure 16 is a circuit diagram of a portion of a page buffer PB according to some embodiments of inventive concepts.

[0105] Referring to Figure 16 , the page buffer PB can include first to fourth transistors TR1-TR4 and a sense latch 1211. The page buffer PB can be one of a plurality of page buffers PB1-PBn of Figure 1 , and can correspond to an embodiment of the page buffer 121 of Figure 11A , or an embodiment of the page buffer 121a of Figure 11B . For example, the first sense node SO1 can correspond to the sense node SO of the page buffer 121 of Figure 11A . Although not shown in Figure 16 , the first sense node SO1 can also be connected to a forced latch 1212, a high bit latch 1213, a low bit latch 1214, and a cache latch 1215.

[0106] The first transistor TR1 can be connected between the bit line BL and the sense node SO2, and can be driven by a bit line shut-off signal BLSHF. The second transistor TR2 can be connected between the first sense node SO1 and the second sense node SO2, and can be driven by a bit line connection control signal CLBLK. The third transistor TR3 can be connected to the second sense node SO2, and can be driven by a bit line clamp signal BLCLAMP. When the bit line clamp signal BLCLAMP is activated, the third transistor TR3 can clamp the voltage of the second sense node SO2. For example, the first to third transistors TR1-TR3 can be implemented by using NMOS transistors.

[0107] The fourth transistor TR4 can be connected to the first sense node SO1, and can be driven by a bit line set-up signal BLSETUP. When the bit line set-up signal BLSETUP is activated, the fourth transistor TR4 can pre-charge the voltage of the bit line BL or the first sense node SO1 to a pre-charge level. For example, the fourth transistor TR4 can be implemented by using a PMOS transistor.

[0108] Figure 17 shows control signals applied to the first to fourth transistors TR1 to TR4 included in a page buffer PB during a program verify operation according to some embodiments of the inventive concepts. Figure 16

[0109] Referring to Figure 1 , Figure 16 and Figure 17 , the program verify operation can include, for example, a first program verify operation VFY1 and a second program verify operation VFY2. The first program verify operation VFY1 denotes an operation of verifying whether programming of the memory cell to a first program state P1 has been completed, and the second program verify operation VFY2 denotes an operation of verifying whether programming of the memory cell to a second program state P2 has been completed. However, the program verify operation can include more than two program verify operations to verify whether programming to more than two program states has been completed.

[0110] The first program verify operation VFY1 can include a first forced sensing portion FS1 and a first main sensing portion MS1. The first forced sensing portion FS1 can include a first pre-charge portion PRE11, a first development portion DEV11, and a first sensing portion SEN11. The first pre-charge portion PRE11 can be defined as an active portion of the bit line set signal BLSETUP, i.e., a time portion from a point in time at which the bit line set signal BLSETUP transitions to logic low to a point in time at which the bit line set signal BLSETUP transitions to logic high.

[0111] The first development portion DEV11 can be defined as a time portion from a point in time at which the bit line set signal BLSETUP is deactivated to a point in time at which the bit line connection control signal CLBLK is deactivated. In other words, the first development portion DEV11 can be defined as a time portion from a point in time at which the bit line set signal BLSETUP transitions to logic high to a point in time at which the bit line connection control signal CLBLK transitions to logic low.

[0112] ​According to some embodiments, the length of the first development portion DEV11 can be changed according to whether the program verify operation is a normal program verify operation or an initial program verify operation. Accordingly, the control logic unit 130 can control the point in time at which the bit line setup signal BLSETUP is deactivated or the point in time at which the bit line connection control signal CLBLK is deactivated according to the type of the program verify operation. In detail, during the initial program verify operation, the control logic unit 130 can control the point in time at which the bit line setup signal BLSETUP is deactivated or the point in time at which the bit line connection control signal CLBLK is deactivated differently from the normal program verify operation.

[0113] The first sensing portion SEN11 can be defined as a deactivation portion of the bit line connection control signal CLBLK, i.e., a time portion from the point in time at which the bit line connection control signal CLBLK is transitioned to a logic low to the point in time at which the bit line connection control signal CLBLK is transitioned to a logic high. When the length of the first development portion DEV11 is changed, the point in time at which the first sensing portion SEN11 starts can be changed. Accordingly, the control logic unit 130 can control the point in time at which the bit line connection control signal CLBLK is deactivated according to the type of the program verify operation.

[0114] The first main sensing portion MS1 can include a second pre-charge portion PRE12, a second development portion DEV12, and a second sensing portion SEN12. The second pre-charge portion PRE12 can be defined as a time portion from the point in time at which the bit line connection control signal CLBLK is activated to the point in time at which the bit line setup signal BLSETUP is deactivated. The second development portion DEV12 can be defined as a time portion from the point in time at which the bit line setup signal BLSETUP is deactivated to the point in time at which the bit line connection control signal CLBLK is deactivated. The second sensing portion SEN12 can be defined as a deactivation portion of the bit line connection control signal CLBLK.

[0115] According to some embodiments, the length of the second development portion DEV12 can be changed according to whether the program verify operation is a normal program verify operation or an initial program verify operation. Accordingly, the control logic unit 130 can control the point in time at which the bit line setup signal BLSETUP is deactivated or the point in time at which the bit line connection control signal CLBLK is deactivated according to the type of the program verify operation. In detail, during the initial program verify operation, the control logic unit 130 can control the point in time at which the bit line setup signal BLSETUP is deactivated or the point in time at which the bit line connection control signal CLBLK is deactivated differently from the normal program verify operation. The control logic unit 130 can control the point in time at which the bit line connection control signal CLBLK is deactivated according to the type of the program verify operation.

[0116] The second program verify operation VFY2 can include a second forced sensing part FS2 and a second main sensing part MS2. The second forced sensing part FS2 can include a first pre-charge part PRE21, a first development part DEV21, and a first sensing part SEN21. The first pre-charge part PRE21, the first development part DEV21, and the first sensing part SEN21 can correspond to the first pre-charge part PRE11, the first development part DEV11, and the first sensing part SEN11, respectively, and thus a repeated description thereof will be omitted. The second main sensing part MS2 can include a second pre-charge part PRE22, a second development part DEV22, and a second sensing part SEN22. The second pre-charge part PRE22, the second development part DEV22, and the second sensing part SEN22 can correspond to the second pre-charge part PRE12, the second development part DEV12, and the second sensing part SEN12, respectively, and thus a repeated description thereof will be omitted.

[0117] Figure 18A a threshold voltage distribution due to a suspend-resume operation according to a comparative example of the present inventive concept is shown, Figure 18B a threshold voltage distribution due to a suspend-resume operation according to some embodiments of the present inventive concept is shown.

[0118] Referring to Figure 18A , a first distribution 181 represents a target distribution, a second distribution 182 represents an initial distribution at a time of entering a suspend, a third distribution 183 represents a changed distribution due to charge loss after a suspend-resume time tRES elapses, and a fourth distribution 184 represents a distribution due to a re-program operation after a program resume. A first forced interval or a first forced range FR can correspond to a certain interval lower than a program verify voltage Vvfy. In this case, the first forced interval FR can be a forced interval used during a normal program verify operation, and can correspond to, for example, a second interval R2 of Figure 12 .

[0119] When a threshold voltage of the first memory cell is lower than the first forced range FR, and a normal program verify operation is performed after the resume command RES_CMD is received, the first memory cell can be determined as a program failure. At this time, when the first memory cell is re-programmed to a program voltage obtained by increasing the program voltage by ISPP (e.g., a voltage VPGM+ISPP of Figure 13 ), the threshold voltage of the first memory cell can be greater than the target distribution 181. Thus, an error bit can be generated, and a read error can occur.

[0120] Referring to Figure 18BAccording to the present embodiment, during the initial program verify operation after the suspend command SUS_CMD or the resume command RES_CMD is received, the first force region FR can be changed to the second force region FR' by distinguishing the development time from the normal development time. Accordingly, the first memory cell not included in the first force region FR can be included in the second force region FR', and the value of the force latch included in the page buffer connected to the first memory cell can be changed from "1" to "0". Accordingly, in the program cycle after the program operation is resumed, the force voltage VFORCE can be applied to the bit line connected to the first memory cell, and the threshold voltage of the first memory cell can increase more than the threshold voltage of the second memory cell included in the second force region FR'. Figure 18A Accordingly, by preventing the over-program operation of the first memory cell, the difference between the upper voltage level of the first distribution 181 and the upper voltage level of the fourth distribution 184' can be reduced.

[0121] Figure 19 is a flowchart of a method of programming an NVM according to some embodiments of the inventive concept.

[0122] Referring to Figure 1 and Figure 19 In operation S310, the NVM 100 receives a program command PGM_CMD. In operation S320, the NVM 100 performs at least one program cycle in response to the program command PGM_CMD. In operation S330, the NVM 100 receives a suspend command SUS_CMD. In operation S340, the NVM 100 receives a resume command RES_CMD.

[0123] In operation S350, the NVM 100 determines whether the current program cycle is greater than or equal to N. Here, N can be a natural number greater than or equal to 2. When it is determined in operation S350 that the current program cycle is greater than or equal to N, in operation S360, the NVM 100 performs an initial program verify operation by using an initial development time. On the other hand, when it is determined in operation S350 that the current program cycle is less than N, in operation S370, the NVM 100 performs a normal program verify operation by using a normal development time. However, the inventive concept is not limited thereto. For example, according to some embodiments, operations S350 to S370 can be performed between operations S330 and S340. In operation S380, the NVM 100 sequentially performs the next program cycle in response to the resume command RES_CMD.

[0124] In the programming method of the NVM according to some embodiments, the NVM can determine whether the programming to the Mth programming state has been completed, instead of performing operation S350, where M can be a natural number greater than or equal to 2. In this case, when the programming to the Mth programming state has been completed, the NVM can perform the initial program verify operation in operation S360, and when the programming to the Mth programming state has not been completed, the NVM can perform the normal program verify operation in operation S370.

[0125] Figure 20 is a flowchart of a method of programming an NVM according to some embodiments of the inventive concepts.

[0126] Referring to Figure 20 , the programming method according to the present embodiment can correspond to a modification of the programming method of Figure 9 , and the description given above with reference to Figure 9 may apply to the present embodiment. For example, the programming method according to the present embodiment can include operations performed in a time-sequential manner in the NVM 100 of Figure 2

[0127] In operation S410, in response to a program command PGM_CMD, the NVM 100 applies a first program voltage VPGM1 to the selected word line WLsel. Operation S410 corresponds to a program execute operation. For example, operation S410 can correspond to a program execute operation in an Nth program loop PL_N of Figure 6 , where N can be a positive integer. In operation S430, in response to a suspend command SUS_CMD or a resume command RES_CMD, the NVM 100 performs an initial program verify operation INT_VFY by applying an initial program verify voltage to the selected word line WLsel. According to some embodiments, as shown in Figure 5 and Figure 6 , operation S430 can be performed after the resume command RES_CMD is received. According to some embodiments, as shown in Figure 8 , operation S430 can be performed after the suspend command SUS_CMD is received.

[0128] In operation S450, in response to the resume command RES_CMD, the NVM 100 applies a second program voltage VPGM2 to the selected word line WLsel. Operation S450 corresponds to a program execute operation. For example, operation S450 can correspond to a program execute operation in an (N+1)th program loop PL_N+1 of Figure 6 . In operation S470, the NVM 100 performs a normal program verify operation N_VFY by applying a normal program verify voltage to the selected word line WLsel. The normal program verify voltage can be different from the initial program verify voltage. ​

[0129] Figure 21A and Figure 21B are graphs showing word line voltage as a function of time during program verify operations according to some embodiments of the inventive concepts.

[0130] Referring to Figure 21A , according to a first program verify sequence, program verify operations can be performed from lower program states to higher program states. For example, a first program verify operation VFY1 can be performed with respect to a first program state PI, and then a second program verify operation VFY2 can be performed with respect to a second program state P2.

[0131] When the program verify operation is a normal program verify operation (e.g., N_VFY of Table 200), the voltage of the selected word line WLsel can correspond to a normal program verify voltage 211. The normal program verify voltage 211 during the first program verify operation VFY1 can correspond to a first normal program verify voltage Vvfy1, and the normal program verify voltage 211 during the second program verify operation VFY2 can correspond to a second normal program verify voltage Vvfy2. The voltage of the unselected word line WLunsel can correspond to a read inhibit voltage Vr. For example, the read inhibit voltage Vr can be greater than the seventh normal program verify voltage Vvfy7. Figure 6 When the program verify operation is an initial program verify operation (e.g., INT_VFY of Table 200), the voltage of the selected word line WLsel can correspond to an initial program verify voltage 212a or an initial program verify voltage 212b. When the voltage of the selected word line WLsel is the initial program verify voltage 212a, the initial program verify voltage 212a during the first program verify operation VFY1 can be greater than the first normal program verify voltage Vvfy1, and the initial program verify voltage 212a during the second program verify operation VFY2 can be greater than the second normal program verify voltage Vvfy2. When the voltage of the selected word line WLsel is the initial program verify voltage 212b, the initial program verify voltage 212b during the first program verify operation VFY1 can be less than the first normal program verify voltage Vvfy1, and the initial program verify voltage 212b during the second program verify operation VFY2 can be less than the second normal program verify voltage Vvfy2.

[0132] Figure 6 Referring to , according to a second program verify sequence, program verify operations can be performed from higher program states to lower program states. For example, a seventh program verify operation VFY7 can be performed with respect to a seventh program state P7 (e.g., having a highest target threshold voltage), and then a sixth program verify operation VFY6 can be performed with respect to a sixth program state P6.

[0133] Figure 21B ​​

[0134] When the program verify operation is a normal program verify operation (e.g., N_VFY), the voltage of the selected word line WLsel can correspond to a normal program verify voltage 214. The normal program verify voltage 214 during the seventh program verify operation VFY7 can correspond to a seventh normal program verify voltage Vvfy7, and the normal program verify voltage 214 during the sixth program verify operation VFY6 can correspond to a sixth normal program verify voltage Vvfy6. The voltage of the unselected word line WLunsel can correspond to a read inhibit voltage Vr. For example, the read inhibit voltage Vr can be greater than the seventh normal program verify voltage Vvfy7. Figure 6

[0135] When the program verify operation is an initial program verify operation (e.g., INT_VFY), the voltage of the selected word line WLsel can correspond to an initial program verify voltage 215a or an initial program verify voltage 215b. When the voltage of the selected word line WLsel is the initial program verify voltage 215a, the initial program verify voltage 215a during the seventh program verify operation VFY7 can be greater than the seventh normal program verify voltage Vvfy7, and the initial program verify voltage 215a during the sixth program verify operation VFY6 can be greater than the sixth normal program verify voltage Vvfy6. When the voltage of the selected word line WLsel is the initial program verify voltage 215b, the initial program verify voltage 215b during the seventh program verify operation VFY7 can be less than the seventh normal program verify voltage Vvfy7, and the initial program verify voltage 215b during the sixth program verify operation VFY6 can be less than the sixth normal program verify voltage Vvfy6. Figure 6

[0136] Figure 22 is a flowchart of a method of programming an NVM according to some embodiments of the inventive concepts.

[0137] Referring to Figure 1 and Figure 22 In operation S510, the NVM 100 receives a program command PGM_CMD. In operation S520, the NVM 100 performs at least one program cycle in response to the program command PGM_CMD. In operation S530, the NVM 100 receives a suspend command SUS_CMD. In operation S540, the NVM 100 receives a resume command RES_CMD.

[0138] ​​In operation S550, the NVM 100 can determine whether programming of the memory cell to the Mth programming state has been completed, where M can be a natural number greater than or equal to 2. When it is determined in operation S550 that programming of the memory cell to the Mth programming state has been completed, the NVM 100 performs an initial program verify operation by using an initial program verify voltage in operation S560. When it is determined in operation S550 that programming of the memory cell to the Mth programming state has not been completed, the NVM 100 performs a normal program verify operation by using a normal program verify voltage in operation S570. However, the inventive concept is not limited thereto. For example, according to some embodiments, operations S550 to S570 can be performed between operations S530 and S540. In operation S580, the NVM 100 sequentially performs the next program loop in response to a resume command RES_CMD.

[0139] In a program method of the NVM according to some embodiments, the NVM 100 can determine whether the current program loop is greater than or equal to N instead of performing operation S550, where N can be a natural number greater than or equal to 2. When it is determined that the current program loop is greater than or equal to N, the NVM 100 can perform an initial program verify operation by using an initial program verify voltage different from a normal program verify voltage in operation S560. On the other hand, when it is determined that the current program loop is less than N, the NVM 100 can perform a normal program verify operation by using a normal program verify voltage in operation S570.

[0140] Figure 23 is a block diagram of a memory system 10a according to some embodiments of the inventive concept. The memory system 10a can correspond to a modification of the memory system 10 of Figure 1 and the description given above with reference to Figure 1 to Figure 22 may be applied to the present embodiment.

[0141] Referring to Figure 23 , the memory system 10a can include an NVM 100a and a memory controller 200a. The memory controller 200a can include a suspend / resume controller 210a and a temperature sensor 220. The NVM 100a can include a memory cell array 110, a page buffer unit 120, a control logic unit 130a, and a temperature sensor 160. However, the inventive concept is not limited thereto, and the memory system 10a can include only one of the temperature sensor 220 and the temperature sensor 160.

[0142] The temperature sensor 220 can sense a temperature of the memory system 10a, and can provide the sensed temperature TP to the suspend / resume controller 210a. The suspend / resume controller 210a can control a suspend / resume operation based on the sensed temperature TP. In detail, the suspend / resume controller 210a can control an initial program verify condition of the initial program verify operation according to the sensed temperature TP, and can transmit the controlled initial program verify condition to the NVM 100a.

[0143] The temperature sensor 160 can sense a temperature of the NVM 100a, and can provide the sensed temperature TP' to the control logic unit 130a. The control logic unit 130a can control an initial program verify condition of the initial program verify operation based on the sensed temperature TP'. For example, when the sensed temperature TP' is greater than or equal to a reference temperature, the control logic unit 130a can perform the initial program verify operation during the suspend-resume operation. For example, when the sensed temperature TP' increases, the control logic unit 130a can increase or decrease an offset between the initial program verify condition and the normal program verify condition.

[0144] Figure 24 is a block diagram of a solid state drive (SSD) system 1000 of a memory device to which an embodiment according to the inventive concept has been applied.

[0145] Referring to Figure 24 , the SSD system 1000 can include a host (HOST) 1100 and an SSD 1200. The SSD 1200 communicates with the host 1100 based on signals transmitted / received via a signal connector (SIG), and receives power via a power connector (PWR). The SSD 1200 can include an SSD controller 1210, an auxiliary power supply 1220, and memory devices (MEM) 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 can be implemented using the embodiments described above with reference to Figure 1 to Figure 23 In some example embodiments, the SSD controller 1210 can exchange data with the memory devices 1230, 1240, and 1250 through channels Ch1, Ch2, …, Chn, where n is a natural number greater than or equal to 3.

[0146] Although the inventive concept has been particularly shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A nonvolatile memory device comprising: an array of memory cells including a plurality of memory cells connected to a plurality of bit lines, respectively; and control logic configured to control a program operation with respect to the plurality of memory cells, wherein the control logic is further configured to: perform, during the program operation, a normal program verify operation with respect to the plurality of memory cells by using a normal program verify condition; and perform, based on a suspend command received during the program operation, an initial program verify operation with respect to the plurality of memory cells by using an initial program verify condition different from the normal program verify condition, wherein the normal program verify condition includes a normal progression time, and the initial program verify condition includes an initial progression time different from the normal progression time.

2. The nonvolatile memory device of claim 1, wherein, the initial program verify operation is performed in response to the suspend command or a resume command received after the suspend command.

3. The nonvolatile memory device of claim 1, wherein, the normal program verify operation is performed in a program cycle before the suspend command is received or in a program cycle after the initial program verify operation.

4. The nonvolatile memory device according to claim 1, wherein the normal progression time corresponds to a time portion between a precharge portion of the plurality of bit lines and a sense portion of a plurality of sense nodes connected to the plurality of bit lines, respectively, during the normal program verify operation, and the initial progression time corresponds to a time portion between the precharge portion of the plurality of bit lines and the sense portion of the plurality of sense nodes during the initial program verify operation.

5. The nonvolatile memory device according to claim 1, further comprising: a page buffer unit including a plurality of page buffers connected to the plurality of bit lines, respectively, wherein a first page buffer among the plurality of page buffers includes: a first transistor connected to a first sense node and driven by a bit line set signal, the first sense node being connected to a first bit line among the plurality of bit lines; and a second transistor connected between the first bit line and the first sense node and driven by a bit line connection control signal, and each of the initial progression time and the normal progression time corresponds to a time portion from a time point at which the bit line set signal is deactivated to a time point at which the bit line connection control signal is deactivated.

6. The nonvolatile memory device of claim 1, wherein, the suspend command is received after an Nth program cycle of the program operation, where N is a natural number greater than or equal to 2.

7. The nonvolatile memory device of claim 6, wherein, the suspend command is a first suspend command, wherein based on a second suspend command being received in one of a first program cycle to an N-1th program cycle of the program operation, the control logic is further configured to perform, in response to the second suspend command or a resume command received after the second suspend command, the normal program verify operation with respect to the plurality of memory cells by using the normal program verify condition.

8. The nonvolatile memory device of claim 1, wherein, the suspend command is received after programming the plurality of memory cells to an Mth program state has been completed, where M is a natural number greater than or equal to 2.

9. The nonvolatile memory device of claim 8, wherein, the suspend command is a first suspend command, wherein based on the second suspend command being received prior to completion of programming the plurality of memory cells to the Mth program state, the control logic unit is configured to perform a normal program verify operation with respect to the plurality of memory cells by using normal program verify conditions in response to the second suspend command or a resume command received after the second suspend command.

10. The nonvolatile memory device of claim 1, wherein, The initial development time includes a forced development time, and the initial program verify operation includes: pre-charging voltages of the plurality of bit lines to a pre-charge level during a first pre-charge portion; developing voltages of a plurality of sense nodes during a forced development time; and sensing the voltages of the plurality of sense nodes during a first sense portion, wherein the forced development time is different from a normal forced development time of the normal program verify operation.

11. The nonvolatile memory device of claim 10, wherein, The initial development time also includes a main development time, and the initial program verify operation also includes: pre-charging the voltages of the plurality of bit lines to the pre-charge level during a second pre-charge portion after the first sense portion; developing the voltages of the plurality of sense nodes during the main development time; and sensing the voltages of the plurality of sense nodes during a second sense portion, wherein the main development time is different from a normal main development time of the normal program verify operation.

12. A method of programming a non-volatile memory device, the method comprising: applying a first program voltage to a selected word line to which a plurality of memory cells are connected in response to a program command; performing an initial program verify operation by developing voltage levels of a plurality of sense nodes that are respectively connected to a plurality of bit lines that are respectively connected to the plurality of memory cells during an initial development time in response to a suspend command or a resume command received after the suspend command; applying a second program voltage to the selected word line in response to the resume command; and performing a normal program verify operation by developing the voltage levels of the plurality of sense nodes during a normal development time that is different from the initial development time.

13. The method of claim 12, wherein the initial development time corresponds to a portion of time between a pre-charge portion of the plurality of bit lines and a sense portion of the plurality of sense nodes during the initial program verify operation, and the normal development time corresponds to a portion of time between a pre-charge portion of the plurality of bit lines and a sense portion of the plurality of sense nodes during the normal program verify operation. The step of performing the normal program verify operation is performed after applying the first program voltage or applying the second program voltage.

14. The method of claim 12, wherein, The initial development time includes a forced development time, and the step of performing the initial program verify operation includes:

15. The method of claim 12, wherein, pre-charging voltages of the plurality of bit lines to a pre-charge level during a first pre-charge portion; developing voltages of a plurality of sense nodes during a forced development time; and sensing the voltages of the plurality of sense nodes during a first sense portion, wherein the forced development time is different from a normal forced development time of the normal program verify operation. The initial development time also includes a main development time, and the step of performing the initial program verify operation also includes:

16. The method of claim 15, wherein, pre-charging the voltages of the plurality of bit lines to the pre-charge level during a second pre-charge portion after the first sense portion; developing the voltages of the plurality of sense nodes during the main development time; and sensing the voltages of the plurality of sense nodes during a second sense portion, wherein the main development time is different from a normal main development time of the normal program verify operation. precharging the voltages of the plurality of bit lines to a precharge level during a second precharge portion following the first sense portion; developing the voltages of the plurality of sense nodes during a main development time; and sensing the voltages of the plurality of sense nodes during a second sense portion, wherein the main development time is different from a normal main development time of a normal program verify operation.

17. The method of claim 12, wherein, the suspend command is received after an Nth program loop of the program operation, or after the programming of the plurality of memory cells to an Mth program state has completed, where N and M are natural numbers greater than or equal to 2.

18. The method of claim 17, wherein, the suspend command is a first suspend command, wherein the method further comprises: based on a second suspend command being received in one of a first program loop to an N-1th program loop of the program operation, performing a normal program verify operation with respect to the plurality of memory cells by using normal program verify conditions in response to the second suspend command or a resume command received after the second suspend command.

19. The method of claim 17, wherein, the suspend command is a first suspend command, wherein the method further comprises: based on a second suspend command being received before the programming of the plurality of memory cells to an Mth program state is completed, performing a normal program verify operation with respect to the plurality of memory cells by using normal program verify conditions in response to the second suspend command or a resume command received after the second suspend command.

20. The method of claim 12, wherein, the normal program verify operation is performed in a program loop before the suspend command is received or in a program loop after an initial program verify operation.

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