An enhanced device and a method of fabricating the same

Abstract

The application discloses an enhanced device and a preparation method thereof. The enhanced device adopts a vertical or semi-vertical structure, and a nitride heterojunction of a non-polar surface or a semi-polar surface is prepared, so that a two-dimensional electron gas is interrupted at the position, and the enhanced device is obtained.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to an enhanced device and its fabrication method. Background Technology

[0002] In applications of RF / microwave power amplifiers and power switching devices, high electron mobility transistors (HEMTs) based on gallium nitride (GaN) have significant advantages over silicon and gallium arsenide (GaAs) devices in high-temperature, high-frequency, high-voltage, and high-power applications. This is due to the characteristics of gallium nitride materials, such as a large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity.

[0003] Gallium nitride (GaN)-based HEMTs typically utilize the two-dimensional electron gas (2EG) in an AlGaN / GaN heterojunction as the conductive channel. Due to the spontaneous polarization and piezoelectric polarization effects in AlGaN and GaN materials, the 2EG is in a conducting state at zero bias, resulting in a depletion-mode device. However, depletion-mode (normally on) devices require a negatively biased gate in the off state, increasing system circuit complexity and cost. Enhancement-mode (normally off) devices, on the other hand, are in a closed state when power is off, eliminating the need for a negative bias power supply and improving system safety, thus offering greater practicality. Implementing enhancement-mode GaN HEMTs requires specialized design of materials and device structure (especially the gate region) to reduce the 2EG concentration in the gate region at zero gate voltage.

[0004] Several common approaches exist for realizing gallium nitride-based enhancement devices. Figure 1 The corresponding solution is to locally thin the aluminum gallium nitride layer beneath the gate. For example... Figure 1 As shown, buffer layer 1, gallium nitride channel layer 2, and aluminum gallium nitride barrier layer 3 are located on substrate 10, while gate 4, source 5, and drain 6 are located on aluminum gallium nitride layer 3. The aluminum gallium nitride layer below gate 4 is locally etched, thereby thinning the aluminum gallium nitride layer thickness in the gate region. However, the thickness of this aluminum gallium nitride layer generally needs to be reduced to below 3nm to 5nm to achieve a good depletion effect, which places high demands on the precision of the etching process. Another approach is to implant fluorine ions into the epitaxial layer below the gate. Because fluorine ions carry a negative charge, after implantation, they will pull the conduction band to deplete the two-dimensional electron gas below the gate, forming an enhancement-mode device structure. Figure 2 The corresponding device structure includes an aluminum gallium nitride layer 7 below the gate 4, which is a fluorine ion implantation region. However, fluorine ion implantation causes lattice damage to the nitride material. Lattice defect scattering reduces the channel carrier mobility, lowers the saturation current, and limits the device's performance. All of the above methods damage the gate material, affecting the device's reliability.

[0005] Therefore, in view of the above technical problems, it is necessary to provide an enhancement mode device and a preparation method thereof. SUMMARY

[0006] The enhancement mode device prepared based on the nitride polarization effect principle has small process damage and more reliable performance, and the vertical structure device can further improve the ability of the device to withstand high current. The purpose of the present application is to provide an enhancement mode device and a preparation method thereof, which includes a vertical structure and a semi-vertical structure. By forming a trench in the gate region, a non-polar surface or semi-polar surface of nitride is obtained, so that the two-dimensional electron gas at the heterojunction is interrupted, and the enhancement mode characteristics are realized. In order to achieve the above purpose, the technical scheme provided by the embodiments of the present application is as follows:

[0007] An enhancement mode device, which is a multilayer epitaxial structure, sequentially includes:

[0008] A highly doped n-type nitride layer;

[0009] A lowly doped n-type nitride layer arranged on the highly doped n-type nitride layer;

[0010] An isolation layer arranged on the lowly doped n-type nitride layer, and a trench is arranged between the isolation layers;

[0011] A nitride channel layer arranged on the surface and sidewall of the isolation layer;

[0012] A nitride barrier layer arranged on the surface and sidewall of the nitride channel layer;

[0013] A gate structure arranged between the sidewalls of the nitride barrier layer;

[0014] A source electrode arranged on the surface of the nitride barrier layer;

[0015] A drain electrode arranged in contact with the highly doped n-type nitride layer.

[0016] Further, the gate structure includes a gate electrode.

[0017] As a further improvement of the present application, the gate structure includes a p-type semiconductor and a gate electrode located on the p-type semiconductor, wherein the p-type semiconductor of the gate region includes a p-type GaN-based material.

[0018] As a further improvement of the present application, the gate structure includes a gate electrode and a dielectric layer, wherein the dielectric layer is arranged between the gate electrode and the nitride barrier layer, and between the gate electrode and the lowly doped n-type nitride layer.

[0019] As a further improvement of the present application, the surface of the gate structure is exposed to form a T-shaped structure.

[0020] As a further improvement of the present application, the gate structure is covered by a dielectric layer, thereby forming a buried gate, and a surface of the dielectric layer is covered by a source electrode.

[0021] As a further improvement of the present application, the dielectric layer is one or a combination of SiN, SiCN, SiO2, SiAlN, Al2O3, AlON, SiON, HfO2.

[0022] As a further improvement of the present application, the isolation layer comprises a semi-insulating layer, wherein the semi-insulating layer is realized by one or more of unintentional doping, carbon doping, iron doping, magnesium doping of the nitride layer.

[0023] As a further improvement of the present application, the high-doped n-type nitride layer, the low-doped n-type nitride layer, the isolation layer, the nitride channel layer and the nitride barrier layer are one or a combination of gallium nitride layer, indium gallium nitride layer, aluminum gallium nitride layer, aluminum indium nitride layer, aluminum indium gallium nitride layer.

[0024] As a further improvement of the present application, the multi-layer epitaxial structure further comprises a nitride cap layer formed on the nitride barrier layer, and the nitride cap layer is a gallium nitride layer or an aluminum gallium nitride layer.

[0025] As a further improvement of the present application, an aluminum nitride layer is arranged between the nitride barrier layer and the nitride channel layer.

[0026] As a further improvement of the present application, the cross-sectional shape of the trench is one or a combination of U-shaped, V-shaped, rectangular, triangular, trapezoidal, polygonal, semicircular.

[0027] Correspondingly, a preparation method of an enhanced device, the preparation method comprises:

[0028] S1, epitaxially growing a low-doped n-type nitride layer on a high-doped n-type nitride layer;

[0029] S2, forming an isolation layer on the low-doped n-type nitride layer, and the isolation layer is provided with a trench;

[0030] S3, forming a nitride channel layer on a surface and a side wall of the isolation layer, and forming a nitride barrier layer on a surface and a side wall of the nitride channel layer, the nitride channel layer and the nitride barrier layer have non-polar surfaces or semi-polar surfaces, and at least part of the two-dimensional electron gas is interrupted;

[0031] S4, forming a gate structure between side walls of the nitride barrier layer;

[0032] S5, forming a source electrode on a surface of the nitride barrier layer;

[0033] S6, forming a drain electrode in contact with the highly doped n-type nitride layer.

[0034] Further, the gate structure is a gate electrode.

[0035] As a further improvement of the present application, the gate structure comprises a p-type semiconductor and a gate electrode on the p-type semiconductor, wherein the p-type semiconductor of the gate region comprises a p-type GaN-based material.

[0036] As a further improvement of the present application, the gate structure comprises a gate electrode and a dielectric layer, wherein the dielectric layer is arranged between the gate electrode and the nitride barrier layer and between the gate electrode and the lowly doped n-type nitride layer.

[0037] As a further improvement of the present application, the dielectric layer is one or a combination of SiN, SiCN, SiO2, SiAlN, Al2O3, AlON, SiON, HfO2.

[0038] As a further improvement of the present application, the highly doped n-type nitride layer is a substrate.

[0039] As a further improvement of the present application, the step S1 further comprises providing a substrate and growing a highly doped n-type nitride layer on the substrate.

[0040] The step S6 further comprises etching or peeling off the substrate until the highly doped n-type nitride layer is exposed, and preparing a drain electrode on the back of the highly doped n-type nitride layer.

[0041] The step S6 further comprises etching from the side of the nitride barrier layer away from the highly doped n-type nitride layer until the highly doped n-type nitride layer is exposed, and forming a drain electrode on the front of the highly doped n-type nitride layer.

[0042] As a further improvement of the present application, the substrate is one or a combination of sapphire, diamond, silicon carbide, silicon, lithium niobate, insulating substrate silicon, gallium nitride or aluminum nitride.

[0043] As a further improvement of the present application, the step S4 further comprises:

[0044] growing a nitride cap layer on the nitride barrier layer, the nitride cap layer being a gallium nitride layer or an aluminum gallium nitride layer.

[0045] As a further improvement of the present application, the step S4 further comprises:

[0046] growing an aluminum nitride layer between the nitride barrier layer and the nitride channel layer.

[0047] Compared with the existing enhancement mode device technology, the present application has the advantages that:

[0048] In the present application, the nitride heterojunction of non-polar or semi-polar surface is prepared, so that the two-dimensional electron gas is interrupted there, and an enhancement-mode device is obtained. Compared with the method of etching the nitride barrier layer or fluorine ion implantation in the gate region, the present application can avoid the device performance degradation caused by the damage of the active region, such as the current density reduction, and is easier to implement in the process.

[0049] In the present application, the vertical structure device is realized by forming a good ohmic contact between the back drain electrode and the highly doped n-type nitride layer; and the semi-vertical structure device is realized by forming a good ohmic contact between the front drain electrode and the highly doped n-type nitride layer. The low-doped n-type nitride layer has the functions of conducting and bearing voltage. The heterojunction composed of the nitride channel layer and the nitride barrier layer has a two-dimensional electron gas as a conductive channel, a part of which is interrupted due to the non-polar or semi-polar surface, and the gate mainly controls the on-off of this part of the conductive channel. The isolation layer is used to isolate the heterojunction from the low-doped n-type nitride layer, and only the heterojunction with the non-polar or semi-polar surface in the gate region is exposed as the conductive channel. The dielectric layer is prepared between the gate electrode and the nitride barrier layer and between the gate electrode and the low-doped n-type nitride layer, so as to reduce the gate leakage current; if the surface of the gate electrode is covered with a dielectric layer, the source electrode located in the nitride barrier layer can also cover the gate region, so that the source electrode pattern can be simplified. The structure design realizes the enhancement-mode device of nitride material, and has the advantages of smaller on-resistance, higher current-carrying capacity and higher wafer area utilization rate. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0051] Figure 1 It is a schematic diagram of the enhancement-mode device structure in the prior art in which the thickness of the aluminum gallium nitride layer is locally thinned at the gate.

[0052] Figure 2 It is a schematic diagram of the enhancement-mode device structure in the prior art in which fluorine ions are implanted below the gate.

[0053] FIGS. 3-8 are state diagrams of the preparation method steps of the enhancement-mode device of the present application. DETAILED DESCRIPTION

[0054] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0055] Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are merely for the purpose of clearly and simply describing the invention and do not imply any connection between the different embodiments and / or structures discussed.

[0056] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0057] This application provides a method for fabricating an enhanced device, the specific steps of which are as follows:

[0058] S1, such as Figure 3A As shown, a low-doped n-type nitride layer 22 is epitaxially grown on a highly doped n-type nitride layer 21.

[0059] In this embodiment, the highly doped n-type nitride layer 21 indicates that the concentration of n-type impurities in the nitride layer is greater than or equal to 5E17cm. -3 The low-doped n-type nitride layer 22 indicates that the concentration of n-type impurities in the nitride layer is less than or equal to 5E16cm. -3 .

[0060] In this embodiment, the highly doped n-type nitride layer 21 serves directly as the substrate, and the lightly doped n-type nitride layer 22 is directly epitaxially grown on the highly doped n-type nitride layer substrate. In other embodiments, such as... Figure 3B As shown, a highly doped n-type nitride layer can also be grown on the substrate 10, and then the substrate can be etched or stripped until the highly doped n-type nitride layer is exposed. The substrate 10 includes sapphire, diamond, silicon carbide, silicon, lithium niobate, insulating substrate silicon, gallium nitride, or aluminum nitride, etc.

[0061] S2, such as Figure 4 As shown, an isolation layer 23 is formed on a lightly doped n-type nitride layer 22, and the isolation layer has trenches.

[0062] In this embodiment, the trenches can be formed by selectively epitaxially growing isolation layers 23 on the lightly doped n-type nitride layer 22, creating rectangular trenches between the isolation layers 23; alternatively, isolation layers 23 can be epitaxially grown on the lightly doped n-type nitride layer 22 first, and then etched, specifically, starting from the side of the isolation layer 23 away from the lightly doped n-type nitride layer 22 and stopping at the lightly doped n-type nitride layer 22, thus forming trenches between the isolation layers 23. This embodiment does not impose specific limitations on the method of trench formation.

[0063] Furthermore, the cross-sectional shape of the groove is a combination of one or more shapes selected from U-shape, V-shape, rectangle, triangle, trapezoid, polygon, and semicircle.

[0064] S3, such as Figure 5 As shown, a nitride channel layer 24 is formed on the surface and sidewalls of the isolation layer 23, and a nitride barrier layer 25 is formed on the surface and sidewalls of the nitride channel layer 24. The nitride channel layer 24 and the nitride barrier layer 25 have non-polar or semi-polar surfaces, and at least part of the two-dimensional electron gas is interrupted.

[0065] It is understood that the formation method of the nitride channel layer 24 and the nitride barrier layer 25 can be a selective epitaxial growth method, where the nitride channel layer 24 is formed only on the surface and sidewalls of the isolation layer 23, and then the nitride barrier layer 25 is formed only on the surface and sidewalls of the nitride channel layer 24. Alternatively, after forming the nitride channel layer 24 on the isolation layer 23 and in the trench, the nitride channel layer 24 in the trench is etched, and then the nitride barrier layer 25 is formed on the nitride channel layer 24 and in the trench, and the nitride barrier layer 25 in the trench is etched to ensure that the bottom of the trench is not filled with the nitride channel layer 24 or the nitride barrier layer 25, thus forming... Figure 5 The structure shown is an example of a non-polar or semi-polar orientation formed on the trench sidewalls that is inconsistent with the polar plane orientation of the nitride crystal. This interrupts the two-dimensional electron gas at the nitride heterojunction with this crystal orientation, thereby realizing an enhancement-mode device.

[0066] S4, such as Figures 6A-6D As shown, a gate structure is formed between the sidewalls of the nitride barrier layer;

[0067] The gate structure may consist of only the gate electrode 27, such as... Figure 6A As shown.

[0068] The gate structure may include a gate electrode 27 and a p-type semiconductor 30, such as Figure 6B As shown; the p-type semiconductor 30 fills the region between the sidewalls of the nitride barrier layer 25, forming a gate electrode 27 on the p-type semiconductor 30. The p-type semiconductor material includes a p-type GaN-based material to realize a p-GaN gate structure. A GaN-based material is a compound containing at least Ga and N atoms, such as GaN, AlGaN, InGaN, AlInGaN, etc.

[0069] The gate structure may include a gate structure 27 and a dielectric layer 26, such as Figure 6CAs shown; the dielectric layer is disposed between the gate electrode and the nitride barrier layer, and between the gate electrode and the lightly doped n-type nitride layer, and the dielectric layer is one or more of SiN, SiCN, SiO2, SiAlN, Al2O3, AlON, SiON, and HfO2. In other embodiments, the gate electrode 27 may be exposed to form a T-shaped structure, such as... Figure 6D As shown.

[0070] S5, such as Figures 7A-7H As shown, a source electrode 28 is formed on the surface of the nitride barrier layer 25;

[0071] The source electrode 28 can be distributed on both sides of the gate structure, and the source electrode is directly formed on the surface of the nitride barrier layer 25. Corresponding to the 6A-6D embodiments, the source electrode 28 is arranged as follows: Figures 7A-7D As shown.

[0072] The source electrode 28 can also be formed on the gate structure and the nitride barrier layer 25. Corresponding to the 6A-6D embodiments, the source electrode 28 is configured as follows: Figures 7E-7H As shown, a buried gate structure is formed. Specifically, a dielectric layer 26 is then covered on the gate structure, and the source electrode 28 is further covered with a dielectric layer 26 to form a buried gate.

[0073] S6, such as Figures 8A-8I As shown, a drain electrode 29 is formed in contact with the highly doped n-type nitride layer 21.

[0074] Corresponding to embodiments 7A-7H, a drain electrode 29 is formed on the back side of the highly doped n-type nitride layer 21, such as... Figures 8A-8H As shown, the drain electrode 29 contacts the heavily doped n-type nitride layer 21 to form a vertical enhancement-mode device. The back side of the heavily doped n-type nitride layer 21 is the side of the heavily doped n-type nitride layer 21 that is away from the lightly doped n-type nitride layer 22. It can be understood that when the heavily doped n-type nitride layer 21 is formed on the substrate 10, as... Figure 3B In this embodiment, before forming the drain electrode 29, the substrate 10 should be stripped first, and then the drain electrode 29 should be formed on the back side of the highly doped n-type nitride layer 21.

[0075] The drain electrode 29 can also be formed on the front side of the highly doped n-type nitride layer 21, such as... Figure 8I As shown, this is an enhancement-mode device forming a semi-vertical structure. The front side of the highly doped n-type nitride layer 21 is the side of the highly doped n-type nitride layer 21 that is close to the less doped n-type nitride layer 22. Specifically, Figure 8IThe structure shown is the embodiment corresponding to 6A. After forming the gate structure, a source electrode 28 is formed on the nitride barrier layer 25 on one side of the gate structure, a recess is formed on the other side of the gate structure, the recess is etched from the nitride barrier layer 25 until the highly doped n-type nitride layer 21 is exposed, and a drain electrode 29 is formed on the front surface of the highly doped n-type nitride layer 21. The remaining embodiments form the drain electrode 29 on the front surface of the highly doped n-type nitride layer 21 in the same way as the 6A embodiment, and will not be described again here.

[0076] Further, the highly doped n-type nitride layer, the low-doped n-type nitride layer, the isolation layer, the nitride channel layer, and the nitride barrier layer are one or a combination of gallium nitride layer, indium gallium nitride layer, aluminum gallium nitride layer, aluminum indium nitride layer, and aluminum indium gallium nitride layer.

[0077] In this embodiment, the isolation layer 23 includes a semi-insulating layer, wherein the semi-insulating layer is realized by one or more of unintentional doping, carbon doping, iron doping, and magnesium doping of the nitride layer. The isolation layer is mainly to isolate the heterojunction formed by the nitride channel layer and the nitride barrier layer from the low-doped n-type nitride layer, and only the heterojunction of the non-polar surface or semi-polar surface exposed by the gate structure serves as a vertical conductive channel. The so-called semi-insulating is a relative concept, and in this application, it means that the isolation layer has a high resistivity (for example, the resistivity is not less than 10 4 Ω·cm at room temperature).

[0078] The application also provides an enhanced device, which is a multilayer epitaxial structure, as shown, comprising in order: Figure 8A

[0079] a highly doped n-type nitride layer 21;

[0080] a low-doped n-type nitride layer 22 arranged on the highly doped n-type nitride layer 21;

[0081] an isolation layer 23 arranged on the low-doped n-type nitride layer 22, and a groove is arranged between the isolation layer 23;

[0082] a nitride channel layer 24 arranged on the surface and sidewall of the isolation layer 23;

[0083] a nitride barrier layer 25 arranged on the surface and sidewall of the nitride channel layer 24;

[0084] a gate structure arranged between the sidewalls of the nitride barrier layer 25;

[0085] a source electrode 28 arranged on the surface of the nitride barrier layer 25;

[0086] a drain electrode 29 arranged in contact with the highly doped n-type nitride layer 21.​

[0087] In this embodiment, the gate structure is a gate electrode 27.

[0088] As a further improvement of the present application, the gate structure comprises a p-type semiconductor 30 and a gate electrode 27 on the p-type semiconductor 30, as shown in Figure 8B wherein the p-type semiconductor 30 of the gate region comprises a p-type GaN-based material.

[0089] As a further improvement of the present application, the gate structure comprises a gate electrode 27 and a dielectric layer 26, wherein the dielectric layer 26 is disposed between the gate electrode 27 and the nitride barrier layer 25, and between the gate electrode 27 and the low-doped n-type nitride layer 22, as shown in Figure 8C .

[0090] As a further improvement of the present application, the gate structure is exposed on the surface to form a T-shaped structure, as shown in Figure 8D .

[0091] As a further improvement of the present application, the gate structure is covered by a dielectric layer 26 to form a buried gate, as shown in Figures 8E-8H wherein the surface of the dielectric layer is covered by a source electrode 28.

[0092] The enhancement-mode devices shown in FIGS. 8A-8H are all vertical structures, wherein the drain electrode is formed on the back surface of the high-doped n-type nitride layer 21. As a further improvement of the present application, the enhancement-mode device further comprises a semi-vertical structure, as shown in Figure 8I wherein the drain electrode is formed on the front surface of the high-doped n-type nitride layer 21.

[0093] As a further improvement of the present application, the dielectric layer 26 is one or a combination of SiN, SiCN, SiO2, SiAlN, Al2O3, AlON, SiON, and HfO2.

[0094] As a further improvement of the present application, the isolation layer 23 comprises a semi-insulating layer, wherein the semi-insulating layer is realized by one or more of unintentional doping, carbon doping, iron doping, and magnesium doping of the nitride layer.

[0095] As a further improvement of the present application, the high-doped n-type nitride layer 21, the low-doped n-type nitride layer 22, the isolation layer 23, the nitride channel layer 24, and the nitride barrier layer 25 are one or a combination of gallium nitride layer, indium gallium nitride layer, aluminum gallium nitride layer, aluminum indium nitride layer, and aluminum indium gallium nitride layer.

[0096] As a further improvement of the present application, the multi-layer epitaxial structure further comprises a nitride cap layer formed on the nitride barrier layer 25, wherein the nitride cap layer is a gallium nitride layer or an aluminum gallium nitride layer.

[0097] As a further improvement of the present application, an aluminum nitride layer is arranged between the nitride barrier layer 25 and the nitride channel layer 24.

[0098] As a further improvement of the present application, the cross-sectional shape of the trench is one or a combination of U-shaped, V-shaped, rectangular, triangular, trapezoidal, polygonal, and semicircular.

[0099] Compared with the existing enhancement device technology, the present application has the following advantages:

[0100] In the present application, the nitride heterojunction with a non-polar or semi-polar surface is prepared to interrupt the two-dimensional electron gas, thereby obtaining an enhancement device. Compared with the method of etching a nitride barrier layer or injecting fluorine ions into a gate region, the present application can avoid the performance degradation of the device caused by the damage to the active region, such as the reduction of current density, and is easier to implement in the process.

[0101] In the present application, the back surface of the highly doped n-type nitride layer forms a good ohmic contact with the drain electrode to realize a vertical structure device; the front surface of the highly doped n-type nitride layer forms a good ohmic contact with the drain electrode to realize a semi-vertical structure device. The lowly doped n-type nitride layer has the functions of conducting electricity and bearing voltage. The heterojunction composed of the nitride channel layer and the nitride barrier layer has a two-dimensional electron gas as a conductive channel, which is interrupted due to the non-polarity or semi-polarity, and the gate mainly controls the on-off of this part of the conductive channel.

[0102] In the present application, the isolation layer is used to isolate the heterojunction from the lowly doped n-type nitride layer, and only the heterojunction with a non-polar or semi-polar surface in the gate structure region is exposed as a vertical conductive channel. The isolation layer includes a semi-insulating nitride layer. A dielectric layer can be prepared between the gate electrode and the nitride barrier layer, and between the gate electrode and the lowly doped n-type nitride layer, to reduce the gate leakage current; if the gate surface is covered with a dielectric layer, the source electrode located in the nitride barrier layer can also cover the gate region, thereby simplifying the source electrode pattern; the source electrode is formed on one side of the gate structure, and a recess is etched on the other side until the highly doped n-type nitride layer is exposed, and a drain electrode is formed, thereby realizing a semi-vertical structure enhancement device.

[0103] The structure design of the present application realizes the vertical structure and semi-vertical structure enhancement devices of nitride materials, and has the advantages of smaller on-resistance, higher current-carrying capacity, and higher wafer area utilization rate.

[0104] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0105] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. An enhanced device, said enhanced device being a multilayer epitaxial structure, characterized in that, The enhanced device comprises in sequence: a high-doped n-type nitride layer; a low-doped n-type nitride layer arranged on the high-doped n-type nitride layer; an isolation layer arranged on the low-doped n-type nitride layer, and a groove is arranged between the isolation layer; a nitride channel layer directly formed on the surface and sidewall of the isolation layer; a nitride barrier layer arranged on the surface and sidewall of the nitride channel layer; the nitride channel layer and the nitride barrier layer have a non-polar surface, and at least part of the two-dimensional electron gas is interrupted; the surface of the nitride channel layer corresponding to the non-polar surface is arranged in parallel with the surface of the nitride barrier layer corresponding to the non-polar surface and away from the surface of the isolation layer; a gate structure arranged between the sidewalls of the nitride barrier layer; a source electrode arranged on the surface of the nitride barrier layer; a drain electrode arranged in contact with the high-doped n-type nitride layer; The gate structure exposes the heterojunction of the non-polar surface as a vertical conductive channel, the isolation layer includes a semi-insulating layer, the isolation layer has a resistivity of not less than 10 4 Ω·cm at room temperature, and the semi-insulating layer is realized by one or more of unintentional doping, carbon doping, and iron doping of a nitride layer.

2. The enhanced device of claim 1, wherein, The gate structure comprises a gate electrode.

3. The enhanced device of claim 1, wherein, The gate structure comprises a p-type semiconductor and a gate electrode arranged on the p-type semiconductor.

4. The enhanced device of claim 1, wherein, The gate structure comprises a gate electrode and a dielectric layer arranged between the gate electrode and the nitride barrier layer and between the gate electrode and the low-doped n-type nitride layer.

5. The enhanced device of claim 1, wherein, The surface of the gate structure is exposed to form a T-shaped structure.

6. The enhanced device of claim 1, wherein, The gate structure is covered by a dielectric layer, and the surface of the dielectric layer is covered by a source electrode to form a buried gate.

7. The enhanced device of claim 1, wherein, The drain electrode is arranged on the back surface of the high-doped n-type nitride layer.

8. The enhanced device of claim 1, wherein, The drain electrode is arranged on the front surface of the high-doped n-type nitride layer.

9. The enhanced device of claim 1, wherein, The high-doped n-type nitride layer, the low-doped n-type nitride layer, the isolation layer, the nitride channel layer and the nitride barrier layer are one or a combination of gallium nitride layer, indium gallium nitride layer, aluminum gallium nitride layer, aluminum indium nitride layer and aluminum indium gallium nitride layer.

10. The enhanced device of claim 1, wherein, The multilayer epitaxial structure further comprises a nitride cap layer formed on the nitride barrier layer, and the nitride cap layer is a gallium nitride layer or an aluminum gallium nitride layer.

11. The enhanced device of claim 1, wherein, An aluminum nitride layer is arranged between the nitride barrier layer and the nitride channel layer.

12. The enhanced device of claim 1, wherein, The cross-sectional shape of the groove between the isolation layers is one or a combination of U-shaped, V-shaped, rectangular, triangular, trapezoidal, polygonal and semicircular.

13. A method for manufacturing an enhanced device, characterized by, The preparation method comprises: S1, forming a low-doped n-type nitride layer on a high-doped n-type nitride layer; S2, forming an isolation layer on the low-doped n-type nitride layer, and the isolation layer is provided with a groove; S3, directly forming a nitride channel layer on the surface and sidewall of the isolation layer, and forming a nitride barrier layer on the surface and sidewall of the nitride channel layer; the nitride channel layer and the nitride barrier layer have a non-polar surface, and at least part of the two-dimensional electron gas is interrupted; the surface of the nitride channel layer corresponding to the non-polar surface is arranged in parallel with the surface of the nitride barrier layer corresponding to the non-polar surface and away from the surface of the isolation layer; S4, forming a gate structure between the sidewalls of the nitride barrier layer, wherein the gate structure exposes the heterojunction of the non-polar surface as a vertical conductive channel; S5, forming a source electrode on the surface of the nitride barrier layer; S6, forming a drain electrode in contact with the highly doped n-type nitride layer, the isolation layer including a semi-insulating layer, the isolation layer having a resistivity no less than 10 4 Ω-cm at room temperature, the semi-insulating layer being realized by one or more of unintentional doping, carbon doping, iron doping of the nitride layer.

14. The method of claim 13, wherein, The gate structure comprises a gate electrode.

15. The method of claim 13, wherein, The gate structure comprises a p-type semiconductor and a gate electrode arranged on the p-type semiconductor.

16. The method of claim 13, wherein, The gate structure comprises a gate electrode and a dielectric layer, wherein the dielectric layer is arranged between the gate electrode and the nitride barrier layer, and between the gate electrode and the low-doped n-type nitride layer.

17. The method of claim 13, wherein, The high-doped n-type nitride layer is a substrate.

18. The method of claim 13, wherein, Before the step S1, the method further comprises: providing a substrate, and growing a high-doped n-type nitride layer on the substrate. Before the step S6, the method further comprises: etching or peeling off the substrate until the high-doped n-type nitride layer is exposed, and forming a drain electrode on the back of the high-doped n-type nitride layer.

19. The method of claim 13, wherein, Before the step S6, the method further comprises: etching from the side of the nitride barrier layer away from the high-doped n-type nitride layer until the high-doped n-type nitride layer is exposed, and forming a drain electrode on the front of the high-doped n-type nitride layer.

20. The method of claim 18, wherein, The substrate is one or a combination of sapphire, diamond, silicon carbide, silicon, lithium niobate, insulating substrate silicon, gallium nitride, or aluminum nitride.

21. The method of claim 13, wherein, The step S4 further comprises: growing a nitride cap layer on the nitride barrier layer, wherein the nitride cap layer is a gallium nitride layer or an aluminum gallium nitride layer.

22. The method of claim 13, wherein, The step S4 further comprises: growing an aluminum nitride layer between the nitride barrier layer and the nitride channel layer. The step S4 further comprises: growing an aluminum nitride layer between the nitride barrier layer and the nitride channel layer.

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