Time-interleaved analog-to-digital converter device and control method thereof

Abstract

The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number signal generator, a plurality of ADCs and an output circuit. The random number signal generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive analog input signals respectively to generate a plurality of digital signals, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the plurality of digital signals according to the plurality of selection signals generated by the plurality of ADCs to generate a digital output signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 839,822 filed on April 29, 2019, the entire contents of which are hereby incorporated by reference. Technical Field

[0003] The present invention generally relates to an analog-to-digital conversion technique, and more particularly, to a time-interleaved analog-to-digital converter device and a control method thereof. Background Art

[0004] In order to make analog-to-digital converters (ADCs) suitable for high-speed applications, a time-interleaved ADC device with multiple ADCs has been developed to increase the overall system sampling rate. Since ADCs may be mismatched due to semiconductor processes, if the ADCs are always used sequentially to generate digital output signals, the digital output signals of the time-interleaved ADC device may have spurs. In order to solve the spurious problem of the digital output signal, conventional technology uses more ADCs and a timing controller to select one of the ADCs to generate the digital output signal. However, this conventional technology requires many main wires to be connected between the timing controller and the ADCs, which brings difficulties to the wiring within the chip. Summary of the invention

[0005] In view of this, one of the objectives of the present invention is to provide a time-interleaved analog-to-digital converter device, which has simpler wiring in the chip and can solve the spurious problem of the digital output signal.

[0006] According to one embodiment of the present invention, a time-interleaved analog-to-digital converter device is disclosed, wherein the time-interleaved analog-to-digital converter device includes a random number signal generator, a plurality of ADCs and an output circuit. The random number signal generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive analog input signals respectively to generate a plurality of digital signals, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the plurality of digital signals according to the plurality of selection signals generated by the plurality of ADCs to generate a digital output signal (according to the selected digital signal).

[0007] In some embodiments, only one of the multiple selection signals generated by the multiple ADCs has an enabled state at the same time, and the output circuit selects the digital signal generated by the ADC whose selection signal has an enabled state.

[0008] In some embodiments, if a selection signal generated by one of the multiple ADCs has an enabled state when receiving a first random number of the random number sequence, then the one of the multiple ADCs generates a selection signal that does not have an enabled state when receiving a second random number immediately following the first random number.

[0009] In some embodiments, each of the plurality of ADCs decodes the same random number sequence to determine whether to generate a selection signal having an enabled state.

[0010] In some embodiments, the time-interleaved analog-to-digital converter device further includes: a clock signal generator for generating a clock signal; wherein each of the plurality of ADCs includes a timing controller, and the timing controller receives the clock signal and the random number sequence and generates the selection signal.

[0011] In some embodiments, the random number signal generator outputs the random number sequence via one or more main conductors, and the number of the main conductors is less than the number of the plurality of ADCs.

[0012] In some embodiments, the random number sequence is represented by the random number signal generator generating a pulse width modulation signal with different pulse widths.

[0013] In some embodiments, the timing controller of at least one of the multiple ADCs includes: a plurality of delay components connected in series; and a selection circuit configured to select one of the plurality of output signals of the plurality of delay components according to the random number sequence to generate the selection signal.

[0014] In some embodiments, each of the plurality of delay elements is a flip-flop, and the plurality of delay elements are controlled by the clock signal.

[0015] According to another embodiment of the present invention, a control method of a time-interleaved analog-to-digital converter device is disclosed. The control method comprises the following steps: generating a random number sequence; using a plurality of ADCs to respectively receive analog input signals to generate a plurality of digital signals; using each ADC to generate a selection signal according to the random number sequence; and selecting one of the plurality of digital signals of the plurality of ADCs according to the plurality of selection signals generated by the plurality of ADCs to generate a digital output signal.

[0016] In some embodiments, only one of the multiple selection signals generated by the multiple ADCs has an enabled state at the same time, and the step of selecting one of the multiple digital signals of the multiple ADCs according to the multiple selection signals generated by the multiple ADCs includes: selecting the digital signal generated by the ADC whose selection signal has an enabled state.

[0017] In some embodiments, the control method further includes: if the selection signal generated by one of the multiple ADCs has an enabled state when receiving the first random number of the random number sequence, then the one of the multiple ADCs generates a selection signal that does not have an enabled state when receiving a second random number immediately following the first random number.

[0018] In some embodiments, the random number sequence is represented by generating a pulse width modulated signal having different pulse widths.

[0019] According to another embodiment of the present invention, a time-interleaved analog-to-digital converter device is disclosed, comprising: a random number signal generator, configured to generate a random number sequence; a plurality of analog-to-digital converters (ADCs), coupled to the random number signal generator, wherein each of the plurality of ADCs is configured to generate a selection signal according to the random number sequence, and is enabled or disabled by the selection signal generated by each ADC to determine whether to perform analog-to-digital conversion; an output circuit, coupled to the plurality of ADCs, and configured to generate a digital output signal according to a digital signal generated by an enabled ADC among the plurality of ADCs.

[0020] In some embodiments, only one of the multiple selection signals generated by the multiple ADCs has an enabled state at the same time, and, if the selection signal generated by one of the multiple ADCs has an enabled state when receiving a first random number of the random number sequence, then the one of the multiple ADCs generates a selection signal that does not have an enabled state when receiving a second random number immediately following the first random number.

[0021] In some embodiments, the random number sequence is represented by generating a pulse width modulated signal having different pulse widths.

[0022] Those skilled in the art will no doubt understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention may be more fully understood by reading the following detailed description and by referring to the examples given in the accompanying drawings, in which:

[0024] Figure 1 FIG. 4 is a schematic diagram of a time-interleaved analog-to-digital converter device according to an embodiment of the present invention.

[0025] Figure 2 The timing diagram of the clock signal and the selection signal is marked.

[0026] Figure 3 FIG. 4 is a schematic diagram of a timing controller according to an embodiment of the present invention.

[0027] Figure 4 4 is a flow chart of a control method of a time-interleaved analog-to-digital converter device according to an embodiment of the present invention.

[0028] In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can more thoroughly understand the embodiments of the present invention. However, it is apparent that one or more embodiments may be implemented without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments listed in the accompanying drawings. DETAILED DESCRIPTION

[0029] The following description is a preferred embodiment of the present invention, which is only used to illustrate the technical features of the present invention, and is not used to limit the scope of the present invention. Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different names to refer to the same components. Therefore, the present specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as a basis for distinction. The terms "component", "system" and "device" used in the present invention can be entities related to computers, wherein the computer can be hardware, software, or a combination of hardware and software. The terms "including" and "comprising" mentioned in the following description and claims are open-ended terms, so they should be interpreted as "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0030] Corresponding numbers and symbols in the various figures of the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0031] The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the technical effect to be achieved. For example, "approximately equal to" means that a certain error from "completely equal to" is acceptable to a person skilled in the art without affecting the correctness of the result.

[0032] Figure 1 FIG. 1 is a schematic diagram of a time-interleaved analog-to-digital converter device 100 according to an embodiment of the present invention. Figure 1 As shown, the time-interleaved analog-to-digital converter device 100 includes a plurality of ADCs 110_1 to 110_N, a random number signal generator 120, a clock signal generator 130 and an output circuit 140, wherein the ADCs 110_1 to 110_N include timing controllers (TCs) 112_1 to 112_N, that is, each ADC includes a corresponding timing controller (TC), for example, the ADC 110_1 includes the timing controller (TC) 112_1, the ADC 110_2 includes the timing controller (TC) 112_2, and the ADC 110_N includes the timing controller (TC) 112_N.

[0033] In the operation of the time-interleaved analog-to-digital converter device 100, the clock signal generator 130 generates a clock signal CLK to the ADCs 110_1 to 110_N, and the ADCs 110_1 to 110_N respectively receive the analog input signal Vin to generate a plurality of digital signals D1-DN. In the embodiment of the present invention, the clock signal CLK is the fastest clock signal in the system including the time-interleaved analog-to-digital converter device 100, but the present invention does not impose any limitation on this. At the same time, the random number signal generator 120 generates a random number sequence RN to the timing controllers 112_1 to 112_N, and the timing controllers 112_1 to 112_N respectively refer to the random number sequence RN to generate the selection signals P1-PN. In this embodiment, only one of the selection signals P1-PN has an enablement state at the same time, and the output circuit 140 selects the digital signal generated by the ADC whose selection signal has an enablement state to generate the digital output signal Dout. For example, if the selection signal P2 has an enablement state, and the other selection signals P1 and P3-PN do not have an enablement state, the output circuit 140 can directly use the digital signal D2 as the digital output signal Dout, or the output circuit 140 processes the digital signal D2 to generate the digital output signal Dout.

[0034] In this embodiment, the timing controllers 112_1 to 112_N have similar circuit structures, and each of the timing controllers 112_1 to 112_N decodes the same random number sequence RN to determine whether to generate a selection signal having an enabled state. Figure 2 And it is assumed that the random number sequence RN sequentially represents random numbers (random bit streams) B0, B1, B2, B3, ... First, each of the timing controllers 112_1 to 112_N refers to the value of the first random number B0 to determine which of the ADCs 110_1 to 110_N should be applied to generate the digital output signal Dout (i.e., determine which of the digital signals D1 to DN should be referenced to generate the digital output signal Dout). Figure 2 In the example shown, in the first frequency cycle of the clock signal CLK, ADC 110_1 is selected, and the timing controller 112_1 generates a selection signal P1 having an enabled state (e.g., a high voltage level, a logical value "1"), and the output circuit 140 refers to the selection signal P1 to generate a digital output signal Dout based on the digital signal D1 output by ADC 110_1; at the same time, all selection signals P2-PN do not have an enabled state (e.g., a low voltage level, a logical value "0"), that is, the digital signal D2-DN is not used for the output circuit 140 to generate the digital output signal Dout. Then, each of the timing controllers 112_1 to 112_N refers to the value of the second random number B1 to determine which of the ADCs 110_1 to 110_N should be applied to generate the digital output signal Dout in the next cycle. Figure 2 In the example shown, in the second frequency cycle of the clock signal CLK, ADC 110_3 is selected, and the timing controller 112_3 generates a selection signal P3 having an enabled state, and the output circuit 140 refers to the selection signal P3 to generate a digital output signal Dout based on the digital signal D3 output by ADC 110_3; at the same time, all the selection signals P1, P2 and P4-PN do not have an enabled state, that is, the digital signals D1, D2 and D4-DN are not used for the output circuit 140 to generate the digital output signal Dout. Then, each of the timing controllers 112_1 to 112_N refers to the value of the third random number B2 to determine which of the ADCs 110_1 to 110_N should be applied to generate the digital output signal Dout in the next cycle. Figure 2In the example shown, in the third frequency cycle of the clock signal CLK, the ADC 110_2 is selected, and the timing controller 112_2 generates a selection signal P2 having an enabled state, and the output circuit 140 refers to the selection signal P2 to generate a digital output signal Dout based on the digital signal D2 output by the ADC 110_2; at the same time, all the selection signals P1 and P3-PN do not have an enabled state, that is, the digital signals D1 and D3-DN are not used for the output circuit 140 to generate the digital output signal Dout. Similar to the above steps, for each random number, one of the digital signals D1-DN generated by the ADCs 110_1 to 110_N is selected respectively, so that the output circuit 140 generates the digital output signal Dout according to the selected corresponding digital signal.

[0035] In addition, since each of the ADCs 110_1 to 110_N requires a stabilization time (e.g., several cycles of the clock signal CLK) to generate reliable digital signals D1-DN, the timing controllers 112_1 to 112_N have a mechanism for avoiding using the same ADC within the stabilization time. For example, assuming that the stabilization time is four cycles of the clock signal CLK, once the ADC 110_1 is selected while receiving the first random number B0, the ADC 110_1 cannot be selected while receiving the random numbers B1-B3. In addition, in order to more effectively improve the spurious of the digital output signal Dout and improve the spurious free dynamic range (SFDR), the number of the ADCs 110_1 to 110_N can be designed to be greater than the number of cycles of the clock signal CLK corresponding to the stabilization time. For example, if the settling time is four cycles of the clock signal CLK, the number of ADCs 110_1 to 110_N may be any integer greater than four, such as five, six, seven, or eight (ie, N=5, 6, 7, or 8).

[0036] In some exemplary embodiments, the random number sequence RN can be represented by a single signal (or unit signal) capable of carrying different information. In this exemplary implementation, for the signal used to control / select which ADC, the random number signal generator 120 only requires one wire source or only one main wire, overcoming the wiring difficulty defect caused by using N main wires or N wire sources in the conventional solution. Among them, the different information carried by this single signal is used to represent different values in the random number sequence RN, and this single signal will be decoded by the timing controllers (TC) 112_1 to 112_N in the ADCs 110_1 to 110_N respectively. That is to say, the timing controllers (TC) 112_1 to 112_N in the ADCs 110_1 to 110_N determine whether the output of the ADC where they are located is used to generate the final digital output signal Dout according to the same single signal. For example, the random number sequence RN is represented by a Pulse Width Modulation (PWM) signal. Generally, the PWM signal consists of a series of pulses. Therefore, different random numbers can be indicated by using different widths / duty cycles of the pulses (for example, N widths / duty cycles correspond to N ADCs / timing controllers (TC) / random numbers). For example, each of the timing controllers (TC) 112_1 to 112_N decodes the same Pulse Width Modulation (PWM) signal. If it is decoded that the pulse has a first width / first duty cycle, only the timing controller 112_1 generates a selection signal with an enable state (for example, a high voltage level, logical value "1"), while other timing controllers generate selection signals without an enable state; correspondingly, if it is decoded that the pulse has a second width / second duty cycle, only the timing controller 112_2 generates a selection signal with an enable state (for example, a high voltage level, logical value "1"), while other timing controllers generate selection signals without an enable state; and so on. It should be noted by the applicant that this is not a limitation of the present invention. For example, the single signal can also carry different information by using different voltage potentials to indicate different random numbers. In some other exemplary embodiments, the random number sequence RN can be represented by using M data signals less than the number of ADCs (for example, each data signal can be 0 or 1 in a clock cycle to indicate different random numbers through different combinations), where M < N. For example, if N is 16, M can be set to 4. Thus, the random number signal generator 120 only requires 4 wire sources or only 4 main wires to output the signal used to control / select which ADC. For the sake of brevity, other similar descriptions are omitted in this exemplary implementation.

[0037] In Figure 1 and Figure 2In the illustrated embodiment, since the mechanism for selecting the ADCs 110_1-110_N is based on the timing controllers 112_1-112_N inside the ADCs 110_1-110_N, and only the random number sequence RN and the clock signal CLK are needed to generate the selection signals P1-PN, the wiring between the ADCs 110_1 to 110_N and the random number signal generator 120 and the clock signal generator 130 can be effectively reduced to simplify the wiring of the chip. In one embodiment, the signal generator 120 outputs the random number sequence RN via one or more main wires, and the number of main wires is less than the number of ADCs 110_1 to 110_N. It should be noted that the main wire is a description corresponding to the source of the wire. For example, to output the unit cell signal to N ADCs 110_1-110_N, only one main wire and N bridge wires branched from the main wire are needed, wherein the bridge wire is easily implemented from the main wire. The conventional technology directly outputs N control signals P1 to PN to ADCs 110_1-110_N. Therefore, the device for outputting control signals P1 to PN requires N wire sources, and N main wires are required to be connected to ADCs 110_1-110_N. Specifically, assuming that the number of ADCs 110_1-110_N is five (i.e., N=5), the conventional technology needs to control / select ADCs 110_1-110_5 by using five different control signals via five different main wires. However, Figure 1 and Figure 2 The embodiment shown can achieve the same purpose by using less than five main wires (eg, 1 or 3), and in fact only one main wire is sufficient to transmit the random number sequence. Therefore, the embodiment does have a simple chip wiring design.

[0038] In another variant implementation, the selection signal generated by the timing controllers 112_1 to 112_N inside the ADCs 110_1 to 110_N can be used to enable or disable the corresponding ADC to determine whether to perform analog-to-digital conversion. Specifically, the timing controllers 112_1 to 112_N refer to the same random number sequence RN to generate a selection signal with an enabled state. If the timing controller 112_i (i is any integer from 1 to N) generates a selection signal Pi with an enabled state, ADC_i is enabled to perform analog-to-digital conversion, so that ADC_i generates a digital signal Di according to the analog input signal Vin, and other ADC_j (j is any integer from 1 to N that is not equal to i) is disabled, so that analog-to-digital conversion is not performed (for example, the digital signal Dj outputted by it can be represented as 0) to save power consumption. Therefore, the digital output signal of the output circuit 140 is generated according to the digital signal generated by the enabled ADC. For example, the output circuit 140 may be a multiplexer or an additional processing circuit, so that the output circuit 140 outputs the digital signal corresponding to the selection signal according to the selection signal with an enabled state or processes the corresponding digital signal before outputting it. Specifically, the embodiment of the present invention does not impose any restrictions on how the digital signal generated by the enabled ADC is used to generate the final output digital output signal. For the sake of brevity, other similar descriptions are omitted here.

[0039] Figure 3 is a schematic diagram of a timing controller 300 according to an embodiment of the present invention, wherein the timing controller 300 is Figure 1 Each of the timing controllers 112_1 to 112_N shown. Figure 3 As shown, the timing controller 300 includes a plurality of delay elements (in this embodiment, flip-flops 310_1 to 310_N are taken as examples) and a selection circuit 320. In this embodiment, the flip-flops 310_1 to 310_N are connected in series and controlled by a clock signal CLK, and the output signal of the last flip-flop 310_N is input to the first flip-flop 310_1. The flip-flops 310_1 to 310_N are configured to generate output signals Q1 to QN, and the selection circuit 320 refers to a random number sequence RN to select one of the output signals Q1 to QN to generate a selection signal Pj (j=1, 2, ..., N).

[0040] Figure 4FIG. 1 is a flow chart of a control method of a time-interleaved analog-to-digital converter device according to an embodiment of the present invention. Referring to the above embodiment, the flow chart of the control method is described as follows.

[0041] Step 400: The process starts.

[0042] Step 402: Generate a random number sequence.

[0043] Step 404: Use a plurality of ADCs to respectively receive analog input signals to generate a plurality of digital signals.

[0044] Step 406: Use each ADC to generate a selection signal according to the random number sequence.

[0045] Step 408: Select one of the multiple digital signals of the multiple ADCs according to the multiple selection signals generated by the multiple ADCs to generate a digital output signal. Optionally, the multiple ADCs are enabled or disabled by the multiple selection signals, wherein the enabled ADC performs analog-to-digital conversion to convert the analog input signal into a digital signal.

[0046] To summarize briefly, in the present invention, a distributed timing controller is designed in the ADC (i.e., a timing controller is separately provided inside each ADC, rather than providing controllers outside multiple ADCs to provide different control signals to the multiple ADCs) to receive a random number sequence to generate a selection signal, so that the output circuit selects one of the multiple digital signals generated by the multiple ADCs, thereby effectively simplifying the wiring design between the ADC and the surrounding circuits.

[0047] Although the present invention has been described by way of example and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. Instead, it is intended to cover various modifications and similar structures (as will be apparent to those skilled in the art), for example, combinations or replacements of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A time-interleaved analog-to-digital converter device, comprising: A random number signal generator is configured to generate a random number sequence; a plurality of analog-to-digital converters ADC, coupled to the random number signal generator and respectively configured to receive analog input signals to generate a plurality of digital signals, wherein each of the plurality of ADCs is further configured to generate a selection signal according to the random number sequence; and an output circuit coupled to the plurality of ADCs and configured to select one of the plurality of digital signals according to a plurality of selection signals generated by the plurality of ADCs to generate a digital output signal; Among them, only one of the multiple selection signals generated by the multiple ADCs has an enabled state at the same time, and the output circuit selects the digital signal generated by the ADC whose selection signal has an enabled state.

2. The time-interleaved analog-to-digital converter device according to claim 1, wherein: If the selection signal generated by one of the plurality of ADCs has an enabled state when receiving a first random number of the random number sequence, the one of the plurality of ADCs generates a selection signal not having an enabled state when receiving a second random number immediately following the first random number.

3. The time-interleaved analog-to-digital converter device according to claim 1, wherein: Each of the plurality of ADCs decodes the same random number sequence to determine whether to generate a selection signal having an enabled state.

4. The time-interleaved analog-to-digital converter device according to claim 3, wherein: Also includes: A clock signal generator, used for generating a clock signal; Each of the plurality of ADCs includes a timing controller, and the timing controller receives the clock signal and the random number sequence and generates the selection signal.

5. The time-interleaved analog-to-digital converter device according to claim 4, wherein: The random number signal generator outputs the random number sequence via one or more main wires, and the number of the main wires is less than the number of the plurality of ADCs.

6. The time-interleaved analog-to-digital converter device according to claim 1, wherein: The random number sequence is represented by the random number signal generator by generating a pulse width modulation signal with different pulse widths.

7. The time-interleaved analog-to-digital converter device according to claim 4, wherein: The timing controller of at least one of the plurality of ADCs comprises: Multiple delay components connected in series; The selection circuit is configured to select one of the multiple output signals of the multiple delay components according to the random number sequence to generate the selection signal.

8. The time-interleaved analog-to-digital converter device according to claim 7, wherein: Each of the plurality of delay elements is a flip-flop, and the plurality of delay elements are controlled by the clock signal.

9. A control method for a time-interleaved analog-to-digital converter device, comprising: Generate a random number sequence; Using a plurality of analog-to-digital converters ADC to respectively receive analog input signals to generate a plurality of digital signals; using each ADC to generate a selection signal according to the random number sequence; as well as, Selecting one of the plurality of digital signals of the plurality of ADCs according to the plurality of selection signals generated by the plurality of ADCs to generate a digital output signal; Among them, only one of the multiple selection signals generated by the multiple ADCs has an enabled state at the same time, and the step of selecting one of the multiple digital signals of the multiple ADCs according to the multiple selection signals generated by the multiple ADCs includes: The digital signal generated by the ADC whose selection signal has an enabled state is selected.

10. The control method according to claim 9, characterized in that: The control method further comprises: If the selection signal generated by one of the plurality of ADCs has an enabled state when receiving a first random number of the random number sequence, the one of the plurality of ADCs generates a selection signal not having an enabled state when receiving a second random number immediately following the first random number.

11. The control method according to claim 9, characterized in that: The random number sequence is represented by generating a pulse width modulated signal with different pulse widths.

12. A time-interleaved analog-to-digital converter device, comprising: A random number signal generator is configured to generate a random number sequence; A plurality of analog-to-digital converters ADCs coupled to the random number signal generator, wherein each of the plurality of ADCs is configured to generate a selection signal according to the random number sequence, and is enabled or disabled by the respective generated selection signal to determine whether to perform analog-to-digital conversion; an output circuit coupled to the plurality of ADCs and configured to generate a digital output signal according to a digital signal generated by an enabled ADC among the plurality of ADCs; Among them, only one of the multiple selection signals generated by the multiple ADCs is in an enabled state at the same time.

13. The time-interleaved analog-to-digital converter device according to claim 12, wherein: If the selection signal generated by one of the plurality of ADCs has an enabled state when receiving a first random number of the random number sequence, the one of the plurality of ADCs generates a selection signal not having an enabled state when receiving a second random number immediately following the first random number.

14. The time-interleaved analog-to-digital converter device according to claim 12, wherein: The random number sequence is represented by generating a pulse width modulated signal with different pulse widths.

Images