Sidewall Passivation for HEMT Devices

Abstract

Some embodiments of the present invention relate to a high electron mobility transistor (HEMT) including a heterojunction structure disposed above a semiconductor substrate. The heterojunction structure includes a binary III / V semiconductor layer made of a first III-nitride material serving as a channel region of an e-HEMT and a ternary III / V semiconductor layer made of a second III-nitride material disposed above the binary III / V semiconductor layer and serving as a barrier layer. A source region and a drain region are disposed above the ternary III / V semiconductor layer and are laterally spaced apart from each other. A gate structure is disposed above the heterojunction structure and is disposed between the source region and the drain region. The gate structure is made of a third III-nitride material. A first passivation layer is disposed around sidewalls of the gate structure and is made of a fourth III-nitride material. Embodiments of the present invention also relate to sidewall passivation for HEMT devices.

Description

[0001] This application is a divisional application of the patent application titled "Sidewall Passivation for HEMT Devices" with the patent application number 201510212686.5, filed on April 29, 2015. Technical Field

[0002] Embodiments of the present invention relate to integrated circuit devices, and more particularly, to sidewall passivation for HEMT devices. Background Art

[0003] A high electron mobility transistor (HEMT), also known as a heterostructure FET (HFET) or a modulation-doped FET (MODFET), is a type of field effect transistor. Given that a conventional n-type MOSFET includes a gate electrode disposed above a p-type doped channel region that separates n-type source / drain regions, for example, an HEMT device uses a heterojunction as the channel instead of a doped region as the channel. This heterojunction is defined by an interface at which two materials with different bandgaps contact each other. III-N (ternary nitride) devices are a type of HEMT, where the heterojunction is composed of a group III material (e.g., Al, Ga, In) and a nitride (N) material. These III-N devices exhibit very promising performance in high-power and high-frequency applications. For example, III-N devices can be used in high-power - high-frequency applications such as transmitters for mobile phone base stations, direct broadcast satellite (DBS) receivers, electronic countermeasure systems, etc. Summary of the Invention

[0004] Embodiments of the present invention provide a high electron mobility transistor (HEMT), comprising: a heterojunction structure disposed above a semiconductor substrate, the heterojunction structure including: a binary III / V semiconductor layer made of a first III-nitride material serving as the channel region of the HEMT and a ternary III / V semiconductor layer made of a second III-nitride material disposed above the binary III / V semiconductor layer and serving as a barrier layer; a source region and a drain region disposed above the ternary III / V semiconductor layer and laterally spaced apart from each other; a gate structure disposed above the heterojunction structure and between the source region and the drain region, wherein the gate structure is made of a third III-nitride material; and a first passivation layer disposed around the sidewalls of the gate structure and made of a fourth III-nitride material.

[0005] According to another embodiment of the present invention, a method of forming an enhancement-mode, high electron mobility transistor (e-HEMT) on a substrate is provided, including: forming a binary III-nitride channel layer over the substrate; forming a ternary III-nitride barrier layer over the binary III-nitride channel layer, wherein the ternary III-nitride barrier layer contacts the binary III-nitride channel layer at a heterojunction interface; forming a binary III-nitride gate layer over the ternary III-nitride barrier layer and doping the binary III-nitride gate layer with donor or acceptor impurities; removing a selected portion of the doped binary III-nitride gate layer to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate sidewalls, and exposing an upper surface region of the ternary III-nitride barrier layer; and forming a first conformal passivation layer over the gate upper surface, gate sidewalls, and exposed upper surface region of the ternary III-nitride barrier layer.

[0006] According to yet another embodiment of the present invention, an enhancement-mode high electron mobility transistor (HEMT) formed on a substrate is provided, including: an AlN buffer layer over the substrate; an AlGaN buffer layer over the AlN buffer layer; a GaN channel layer over the AlGaN buffer layer; an AlGaN barrier layer over the GaN channel layer; a GaN gate structure over the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and gate structure sidewalls; and an AlN or BN conformal passivation layer over the gate structure upper surface and adjacent to the gate structure sidewalls. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 Some embodiments of cross-sectional views of HEMT devices in accordance with some embodiments of the present invention are shown.

[0009] Figure 2 A flowchart of a method of manufacturing an e-HEMT device in accordance with some embodiments of the present invention is shown.

[0010] Figures 3 to 11 A series of cross-sectional views in accordance with some embodiments of the present invention are shown, which together illustrate a method of manufacturing a HEMT device. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] HEMT devices use a heterojunction between two materials with different bandgaps as the channel. For example, in some III-N HEMT devices, a wide-bandgap AlGaN layer may form a heterojunction with a narrow-bandgap GaN layer. The lattice constants of these two materials are usually slightly different. The difference in the lattice structures of these types of materials creates strain, which can cause piezoelectric-induced polarization and form band bending at the heterojunction interface. For example, GaN HEMTs typically have strong surface polarization that causes them to operate in a normally-on (depletion mode) state. To overcome the surface polarization and control the flow of charge carriers in enhancement-mode devices, a gate of p-GaN material with a high work function may be formed directly on top of the AlGaN layer.

[0014] However, GaN HEMTs with AlGaN / GaN as the Schottky barrier and p-GaN gates as the control gates result in large gate leakage. In addition, in order to form an enhancement-mode device structure, many III-N surfaces are subject to process-induced traps or damage. These traps or damage mainly lead to gate leakage or device leakage current that degrades device performance. In an attempt to limit the number of traps (and thus improve device performance), the present invention describes a technique for forming a passivation layer on the III-N surface (e.g., the sidewalls of p-GaN). The passivation layer terminates and passivates the dangling bonds on the surface of the gate sidewall surface to limit the number of interface traps and thus helps improve device performance. Therefore, gate leakage can be reduced by introducing such a passivation layer.

[0015] Figure 1 Some embodiments of a cross-sectional view of a HEMT device 100 according to the present invention are shown. The HEMT device 100 includes a heterojunction structure 102 disposed above a semiconductor substrate 104. The heterojunction structure 102 is composed of a binary III / V semiconductor layer 106 and a ternary III / V semiconductor layer 108 disposed above the binary III / V semiconductor layer 106. The binary III / V semiconductor layer 106 is made of a first III-nitride material and serves as the channel region of the e-HEMT. The ternary III / V semiconductor layer 108 is made of a second III-nitride layer and serves as a barrier layer somewhat similar to the gate dielectric for a conventional MOSFET. In some embodiments, the binary III / V semiconductor layer 106 is made of gallium nitride (GaN), and the ternary III / V semiconductor layer 108 is made of aluminum gallium nitride (Al x Ga 1-x GaN, where 0 < x < 1).

[0016] One or more buffer layers 110 may be disposed between the heterostructure 102 and the substrate 104. These buffer layers 110 can help gradually distribute the strain over their thickness, where the strain is caused by the lattice mismatch between the substrate 104 and the binary III / V layer 106. By distributing the strain, these buffer layers 110 can help avoid the formation of traps in some respects. The illustrated buffer layers 110 include an uppermost buffer layer 112 adjacent to the binary III / V layer 106 and a lower buffer layer 114 located between the uppermost buffer layer 112 and the substrate 104. In some embodiments, the uppermost buffer layer 112 may be made of AlGaN, and the lower buffer layer 114 may be made of AlN. In other embodiments, more than two buffer layers may be included between the heterostructure 102 and the substrate 104.

[0017] The conductive source region 116 and drain region 118 are disposed above the ternary III / V semiconductor layer 108 and are laterally spaced apart from each other. The conductive source region 116 and drain region 118 have respective lower regions that are adjacent to and ohmically connected to the ternary III / V semiconductor layer 108. In some embodiments, the source region 116 / drain region 118 is directly located on and adjacent to the ternary III / V semiconductor layer 108 and is spaced apart from the binary III / V semiconductor layer 106. However, in other embodiments, the source region 116 / drain region 118 extends through the ternary III / V semiconductor layer 108 and is adjacent to the binary III / V semiconductor layer 106.

[0018] The gate structure 120 is disposed above the heterojunction structure 102 and is laterally disposed between the conductive source region 116 and drain region 118. The gate structure 120 is made of a third III-nitride material. For example, in some embodiments, the gate structure 120 may be made of GaN that has been doped with donor impurities to form an n-type gate structure or has been doped with acceptor impurities to form a p-type gate structure. These dopants help the resulting HEMT device 100 to operate in an enhancement mode as opposed to a depletion mode.

[0019] A first conformal passivation layer 122 is disposed around the sidewalls 120A, 120B of the gate structure and above the upper surface 120C of the gate structure. The first conformal passivation layer 122 is also disposed above the upper surface 108A of the ternary III / V semiconductor layer 108. In some embodiments, the first conformal passivation layer 122, which may be made of aluminum nitride (AlN) or boron nitride (BN), may be a high-quality thin film to prevent current leakage from the gate structure 120. Thus, in some embodiments, the first conformal passivation layer 122 is grown by atomic layer deposition (ALD) techniques, which, although time-consuming, produce very high-quality films. In some embodiments, the first conformal passivation layer 122 may have a thickness between about 5 angstroms and about 500 angstroms. In addition to providing high-quality films, ALD techniques are advantageous because they can be implemented at relatively low temperatures, e.g., between 200 °C and 500 °C, which helps to limit thermal budget issues, and because ALD techniques provide good step coverage compared to PVD.

[0020] A second conformal passivation layer 124 is disposed above the first conformal passivation layer 122. The second conformal passivation layer 124 may help protect the first conformal passivation layer 122 during processing. In some embodiments, the second conformal passivation layer 124 may be made of a nitride (e.g., SiN) or an oxide (e.g., SiO 2) It is made. The thickness of the second conformal passivation layer 124 can be greater than the thickness of the first conformal passivation layer 122, and the second conformal passivation layer 124 can be formed by a technique different from the technique used to form the first conformal passivation layer 122. For example, in some embodiments, the second conformal passivation layer 124 can have a thickness of about 50 nanometers to about 500 nanometers. Additionally, for example, in some embodiments, the second conformal passivation layer 124 can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0021] The conductive source region 116 / drain region 118 extends downward through the first passivation layer 122 and the second passivation layer 124 to make an ohmic connection to the ternary III / V semiconductor layer 108. For example, the conductive source region 116 / drain region 118 can be a metal such as copper, aluminum, tungsten, nickel, iron, cobalt, silver, gold, or platinum.

[0022] A conformal dielectric overlay 126 is located over the conductive source region 116 / drain region 118. For example, in some embodiments, the conformal dielectric overlay 126 is a nitride (e.g., SiN) or an oxide (e.g., SiO 2 ). In some embodiments, the thickness of the conformal dielectric overlay 126 is greater than or equal to the thickness of the second conformal passivation layer 124.

[0023] A metal electrode pad or a metal electrode contact 128 extends downward through the dielectric overlay 126 and through the first passivation layer 122 and the second passivation layer 124 to make an ohmic connection with the gate structure 120. In some embodiments, the metal electrode pad or the metal electrode contact 128 is formed by PVD or CVD. The metal electrode pad or the metal electrode contact 128 can extend downward along the sidewalls of the overlay 126 and the sidewalls of the first passivation layer 122 and the second passivation layer 124 before making an ohmic contact with the upper surface region of the gate structure 120.

[0024] Due to the difference in bandgap between the binary III / V layer 106 and the ternary III-V layer 108, highly mobile charge carriers in the form of a two-dimensional electron gas (2DEG) are established at the interface between the layers 106, 108. Thus, during operation, the voltage applied to the gate electrode 120 controls the number of carriers (e.g., 2DEG) that can flow from the source 116 through the channel region in the layer 106 to the drain 118 (or vice versa). Thus, the HEMT 100 can be controlled to be in a conductive state or a resistive state by controlling the 2DEG with the help of the gate electrode 120. In many cases, the HEMT device 100 is an enhancement-mode device that operates similar to a silicon MOSFET device by typically being in a non-conductive state (normally off). Due to the nature of the heterojunction interface between 106 / 108 and the formation of the 2DEG at this heterojunction interface in the HEMT, such devices formed in the III-N material system tend to be normally on or are depletion-mode devices. The high electron mobility of the 2DEG at the interface of the AlGaN / GaN layer allows III-N devices such as HEMT devices to conduct electricity without applying a gate potential.

[0025] In the off state, conventional enhancement-mode HEMT (e-HEMT) devices may exhibit current leakage from their gate structures. In some cases, the passivation layer 122 can help limit this current leakage by about an order of magnitude.

[0026] Figure 2 A flowchart of some embodiments of a method of manufacturing a HEMT device in accordance with some embodiments of the present invention is shown. Although the method is shown and described below as a series of steps or events, it will be understood that the order of the steps or events shown should not be construed in a limiting sense. For example, some steps may be performed in a different order and / or concurrently with other steps or events other than those shown and / or described herein. Additionally, not all of the steps shown may be necessary to implement one or more aspects or embodiments described herein. Further, one or more of the steps shown herein may be implemented in one or more separate steps and / or phases.

[0027] In step 202, a first buffer layer made of a first III-nitride material is formed over the substrate. In step 204, a second buffer layer is formed over the first buffer layer, wherein the second buffer layer is made of a second III-nitride material different from the first III-nitride material. In step 206, a binary III-nitride channel layer is formed over the second buffer layer. In step 208, a ternary III-nitride barrier layer is formed over the binary III-nitride channel layer. The ternary III-nitride barrier layer contacts the binary III-nitride channel layer at the heterojunction interface. In step 210, a binary III-nitride gate layer is formed over the ternary III-nitride barrier layer, and the binary III-nitride gate layer is doped with donor or acceptor impurities. In step 212, selected portions of the doped binary III-nitride gate layer are removed to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate sidewalls. Removal of these selected portions exposes the upper surface region of the ternary III-nitride barrier layer. In step 214, a first conformal passivation layer is formed over the gate upper surface, gate sidewalls, and exposed upper surface region of the ternary III-nitride barrier layer. The first conformal passivation layer can help reduce gate sidewall traps and thus help limit current leakage from the gate structure during operation of the device.

[0028] Turning now to Figures 3 to 11 , a series of cross-sectional views according to some embodiments are shown, which together illustrate the formation of a HEMT device. It will be understood that while specific structural components are disclosed in these cross-sectional views, these specific structural components are not required in all embodiments.

[0029] Figure 3 Consistent with some embodiments of the structure formed by reference numerals 202 to 210 of Figure 2 . Figure 3The structure includes a substrate 302 that can take various different forms. In some embodiments, the substrate 302 is a silicon substrate, a silicon carbide (SiC) substrate, or a sapphire substrate. Then, a first buffer layer 304 is formed over the substrate 302, for example, by an epitaxial growth technique. In some cases, the first buffer layer 304 can be referred to as the lower buffer layer. In some cases, the first buffer layer 304 is an aluminum nitride (AlN) layer. Then, a second buffer layer 306 is formed over the first buffer layer 304, for example, by an epitaxial growth technique. In some cases, the second buffer layer 306 can be referred to as the uppermost buffer layer. In some cases, the second buffer layer 306 is an AlGaN layer. Then, a binary III-nitride channel layer 308 is formed over the second buffer layer 306, for example, by an epitaxial growth technique. In some cases, the binary III-nitride channel layer 308 is a GaN layer. A ternary III-nitride barrier layer 310 is formed over the binary III-nitride channel layer 308, for example, by an epitaxial growth technique. In some embodiments, the ternary III-nitride barrier layer 310 is an Al x Ga 1- x N layer, where 0 < x < 1. A binary III-nitride gate layer 312 is formed over the ternary III-nitride barrier layer 310, for example, by an epitaxial growth technique, and the binary III-nitride gate layer 312 is doped with donor or acceptor impurities. In some embodiments, the binary III-nitride gate layer 312 is an n-type or p-type GaN layer.

[0030] In Figure 4 , a gate structure mask layer is formed and patterned over the binary III-nitride gate layer. The gate structure mask layer can be a photoresist layer, a hard mask layer such as a nitride layer, and / or other individual layers or a combination of layers. With the patterned gate structure mask 402 in place, etching is performed to selectively remove the exposed portions of the binary III-nitride gate layer 312, leaving a gate structure 312' having the gate structure mask 402 over it. Then, the patterned gate structure mask 402 is removed.

[0031] In Figure 5 , a first conformal passivation layer 502 is formed by atomic layer deposition (ALD). In some embodiments, the first conformal passivation layer 502 is AlN or BN and is deposited to have a thickness between about 5 angstroms and 500 angstroms. To limit gate sidewall traps, the first conformal passivation layer 502 directly abuts the sidewalls and the upper surface of the gate electrode 312'.

[0032] In Figure 6In [the above], a second conformal passivation layer 602 is formed over the first conformal passivation layer 502 to protect the first conformal passivation layer 502 during processing. In some embodiments, the second conformal passivation layer is a nitride such as, for example, SiN or an oxide such as, for example, SiO 2 In some embodiments, the second conformal passivation layer 602 is formed by a technique different from that used to form the first conformal passivation layer 502. For example, the second conformal passivation layer 602 can be formed by CVD, PECVD, or PVD having a deposition rate faster than that of ALD to keep the process throughput at a good level. To help protect the first conformal passivation layer 502, the thickness of the second passivation layer 602 can be in the range of about 50 nm and about 500 nm.

[0033] In Figure 7 [the above], a source / drain mask 700 has been formed over the second conformal passivation layer. With the source / drain mask 700 in place, an etch such as, for example, a dry etch is performed to form source / drain openings 702 that extend through the first conformal passivation layer 502 and the second conformal passivation layer 602 and terminate on the ternary III-nitride barrier layer 310. Some portions of the ternary III-nitride barrier layer 310 can be removed / consumed during this etch, and other portions can remain below the source / drain openings 702 that are located over the ternary III-nitride barrier layer 310. In Figure 8 [the above], the source / drain mask 700 is removed, and the source / drain openings are filled with a conductive material such as metal. The initially formed metal extends over the entire exposed surface of the second conformal passivation layer. Subsequently, a mask such as a photoresist mask (not shown) is formed over the source / drain regions, and an etch such as a dry etch is performed to form the illustrated conductive source / drain regions 802.

[0034] In Figure 9 [the above], a conformal dielectric overlay 902 is formed. In some embodiments, the conformal dielectric overlay is a nitride such as, for example, SiN or an oxide such as, for example, SiO 2 In some embodiments, the conformal dielectric overlay is a nitride such as, for example, SiN or an oxide such as, for example, SiO

[0035] In Figure 10 [the above], a gate electrode mask 1000 is formed over the dielectric overlay. With the gate electrode mask in place, an etch such as a dry etch is performed to form a gate electrode opening 1002. The gate electrode opening extends through the dielectric overlay, the first conformal passivation layer, and the second conformal passivation layer. The gate electrode opening terminates on the patterned doped binary III-nitride gate structure.

[0036] In Figure 11In [the figure], a conductive gate electrode pad 1100 is formed in the gate electrode opening. In some embodiments, the conductive gate electrode pad is deposited by PVD or CVD. For example, the conductive gate electrode layer may include a metal such as aluminum, copper, tungsten, or nickel or may include other conductive materials such as doped polysilicon.

[0037] As can be understood from the above, the present invention describes a technique of forming a passivation layer above the sidewall of a gate electrode to limit interface traps. The passivation layer terminates and passivates the dangling bonds on the surface of the gate sidewall surface to limit the number of interface traps and helps to improve device performance. Specifically, the passivation layer reduces the gate leakage current.

[0038] Accordingly, some embodiments of the present invention relate to a high electron mobility transistor (HEMT) including a heterojunction structure disposed above a semiconductor substrate. The heterojunction structure includes a binary III / V semiconductor layer made of a first III-nitride material serving as a channel region of the e-HEMT and a ternary III / V semiconductor layer made of a second III-nitride material disposed above the binary III / V semiconductor layer and serving as a barrier layer. A source region and a drain region are disposed above the ternary III / V semiconductor layer and are laterally spaced apart from each other. A gate structure is disposed above the heterojunction structure and is disposed between the source region and the drain region. The gate structure is made of a third III-nitride material. A first conformal passivation layer is disposed around the sidewall of the gate structure and is made of a fourth III-nitride material.

[0039] In the above HEMT, wherein the third III-nitride material of the gate structure is a binary III / V semiconductor material and has the same binary semiconductor composition as the first III-nitride material, and the fourth III-nitride material of the first passivation layer is a binary III / V semiconductor material and has a binary semiconductor composition different from that of the first III-nitride material and the second III-nitride material.

[0040] In the above HEMT, wherein the gate structure is a doped n-type or doped p-type gate structure, and wherein the binary III / V semiconductor layer is an intrinsic semiconductor material.

[0041] In the above HEMT, wherein the first passivation layer is conformal and has a thickness between 5 angstroms and 500 angstroms.

[0042] In the above HEMT, further comprising: a second passivation layer having a thickness of 50 nm to 500 nm and conformally covering the first passivation layer, wherein the material composition of the second passivation layer is different from that of the first passivation layer.

[0043] In the above HEMT, there is also included: one or more buffer layers located under the binary III / V semiconductor layer, wherein the uppermost buffer layer is made of the second III-nitride material, and wherein the lower buffer layer located under the uppermost buffer layer is made of the first III-nitride material.

[0044] In the above HEMT, there is also included: one or more buffer layers located under the binary III / V semiconductor layer, wherein the uppermost buffer layer is made of the second III-nitride material, and wherein the lower buffer layer located under the uppermost buffer layer is made of the first III-nitride material, wherein the first passivation layer is made of the same material as the lower buffer layer.

[0045] In the above HEMT, there is also included: one or more buffer layers located under the binary III / V semiconductor layer, wherein the uppermost buffer layer is made of the second III-nitride material, and wherein the lower buffer layer located under the uppermost buffer layer is made of the first III-nitride material, wherein the first passivation layer is made of the same material as the lower buffer layer, wherein the first III-nitride material of the binary III / V semiconductor layer is GaN; the second III-nitride material of the ternary III / V semiconductor layer is Al x Ga 1-x N; the third III-nitride material of the gate structure is n-type GaN or p-type GaN; and the fourth III-nitride material of the first passivation layer is AlN or BN.

[0046] In the above HEMT, there is also included: a second passivation layer conformally disposed above the first passivation layer and having a second thickness greater than the first thickness of the first passivation layer; a capping layer conformally disposed above the upper surface region of the second passivation layer; and a metal gate electrode including an edge located above the upper surface region of the capping layer and including an inner sidewall that extends downward along the sidewall of the opening through the capping layer, through the second passivation layer, and through the first passivation layer to be directly electrically connected to the upper surface of the gate structure.

[0047] Other embodiments of the present invention relate to a method of forming an enhancement-mode, high electron mobility transistor (e-HEMT) on a substrate. In this method, a binary III-nitride channel layer is formed over the substrate. A ternary III-nitride barrier layer is formed over the binary III-nitride channel layer. The ternary III-nitride barrier layer contacts the binary III-nitride channel layer at a heterojunction interface. A binary III-nitride gate layer is formed over the ternary III-nitride barrier layer and the binary III-nitride gate layer is doped with donor or acceptor impurities. A selected portion of the doped binary III-nitride gate layer is removed to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate outer sidewalls. Removing the selected portion of the gate layer exposes an upper surface region of the ternary III-nitride barrier layer. A first conformal passivation layer is formed over the gate upper surface of the ternary III-nitride barrier layer, over the gate outer sidewalls, and over the exposed upper surface region.

[0048] In the above method, wherein the first conformal passivation layer is formed by atomic layer deposition (ALD).

[0049] In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer.

[0050] In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer, wherein the first conformal passivation layer is formed by ALD and has a thickness between about 5 angstroms and about 500 angstroms, and wherein the second conformal passivation layer is formed by CVD, PECVD or PVD and has a thickness between about 50 nm and about 500 nm to protect the first conformal passivation layer during processing.

[0051] In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer, wherein the method further comprises: forming a source / drain mask over the second conformal passivation layer; with the source / drain mask in place, performing an etch to form source / drain openings that extend through the first conformal passivation layer and the second conformal passivation layer and terminate on the ternary III-nitride barrier layer; and filling the source / drain openings with a conductive material.

[0052] In the above method, it further includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer, and the method further includes: forming a source / drain mask above the second conformal passivation layer; performing etching to form a source / drain opening when the source / drain mask is in place, the source / drain opening extending through the first conformal passivation layer and the second conformal passivation layer and terminating on the ternary III-nitride blocking layer; filling the source / drain opening with a conductive material, and the method further includes: patterning the conductive material to form a source / drain conductive body; forming a dielectric covering layer above the source / drain conductive body; forming a gate electrode mask above the dielectric covering layer; performing etching to form a gate electrode opening extending through the dielectric covering layer, the first conformal passivation layer, and the second conformal passivation layer when the gate electrode mask is in place, wherein the gate electrode opening terminates on the patterned doped binary III-nitride gate structure; and forming a conductive gate electrode liner in the gate electrode opening.

[0053] In the above method, it further includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer, and the method further includes: forming a source / drain mask above the second conformal passivation layer; performing etching to form a source / drain opening when the source / drain mask is in place, the source / drain opening extending through the first conformal passivation layer and the second conformal passivation layer and terminating on the ternary III-nitride blocking layer; filling the source / drain opening with a conductive material, and the method further includes: patterning the conductive material to form a source / drain conductive body; forming a dielectric covering layer above the source / drain conductive body; forming a gate electrode mask above the dielectric covering layer; performing etching to form a gate electrode opening extending through the dielectric covering layer, the first conformal passivation layer, and the second conformal passivation layer when the gate electrode mask is in place, wherein the gate electrode opening terminates on the patterned doped binary III-nitride gate structure; and forming a conductive gate electrode liner in the gate electrode opening, wherein the binary III-nitride channel layer is made of GaN; the ternary III-nitride blocking layer is made of Al x Ga 1-x N; the patterned doped binary III-nitride gate structure is n-type GaN or p-type GaN; the first conformal passivation layer is AlN or BN; the second conformal passivation layer is SiO 2or SiN; and the dielectric capping layer is SiN or SiO 2 .

[0054] In the above method, it further includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer, and wherein the method further includes: forming a first buffer layer before forming the binary III-nitride channel layer above the substrate; and forming a second buffer layer above the first buffer layer before forming the binary III-nitride channel layer above the substrate.

[0055] In the above method, it further includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that for forming the first conformal passivation layer, and wherein the method further includes: forming a first buffer layer before forming the binary III-nitride channel layer above the substrate; and forming a second buffer layer above the first buffer layer before forming the binary III-nitride channel layer above the substrate, wherein the first conformal passivation layer is made of the same material as the first buffer layer.

[0056] Yet other embodiments relate to a high electron mobility transistor (HEMT) formed on a substrate. The HEMT includes an AlN buffer layer located above the substrate. An AlGaN buffer layer is disposed above the AlN buffer layer. A GaN channel layer is disposed above the AlGaN buffer layer. An AlGaN barrier layer is disposed above the GaN channel layer. A GaN gate structure is disposed above the AlGaN barrier layer. The GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and gate structure outer sidewalls. An AlN or BN conformal passivation layer is disposed above the gate structure upper surface and adjacent to the gate structure outer sidewalls.

[0057] In the above HEMT, the HEMT further includes: a second passivation layer having a thickness of 50 nm to 500 nm and conformally covering the AlN or BN conformal passivation layer, wherein the material composition of the second passivation layer is different from that of the AlN or BN conformal passivation layer.

[0058] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A high electron mobility transistor, comprising: a heterojunction structure disposed on a semiconductor substrate, the heterojunction structure comprising: a channel layer including a first III-nitride material and a barrier layer including a second III-nitride material; a source region and a drain region in direct contact with an upper surface of the heterojunction structure and laterally spaced apart from each other; a gate structure disposed above the heterojunction structure and between the source region and the drain region, wherein the gate structure includes a third III-nitride material in direct contact with the upper surface of the heterojunction structure, and the gate structure has etched sidewalls; a first passivation layer conformally disposed over all sidewall surfaces and an upper surface of the etched sidewalls of the gate structure and including a fourth III-nitride material; and a second passivation layer conformally disposed over the first passivation layer; wherein the first passivation layer has a first thickness and the second passivation layer has a second thickness greater than the first thickness, wherein, in a lateral direction, a portion of the etched sidewalls of the gate structure, a portion of the first passivation layer, and a portion of the second passivation layer are adjacent to and overlap each other; a capping layer conformally disposed over the second passivation layer; a metal gate electrode including an edge covering an upper surface of the capping layer and including an inner sidewall extending downward along sidewalls of an opening passing through the capping layer, the second passivation layer, and the first passivation layer, a bottom surface of the metal gate electrode being lower than a top surface of the gate structure to extend into the gate structure, thereby electrically connecting to the gate structure.

2. The high electron mobility transistor according to claim 1, wherein, the fourth III-nitride material of the first passivation layer is a binary III / V semiconductor material and has a binary semiconductor composition different from that of the first III-nitride material and the second III-nitride material.

3. The high electron mobility transistor according to claim 1, further comprising: one or more buffer layers below the channel layer, wherein the uppermost buffer layer is made of the second III-nitride material, and a lower buffer layer below the uppermost buffer layer is made of the fourth III-nitride material.

4. The high electron mobility transistor according to claim 3, wherein, the first passivation layer is made of the same material as the lower buffer layer.

5. The high electron mobility transistor according to claim 1, wherein: the first III-nitride material includes GaN; The second III-nitride material includes Al x Ga 1-x N; and the fourth III-nitride material includes AlN or BN.

6. The high electron mobility transistor according to claim 1, wherein the source region and the drain region extend through the first passivation layer and the second passivation layer and terminate on the barrier layer.

7. A method of forming a high electron mobility transistor, comprising: forming a heterojunction structure on a semiconductor substrate; forming a gate layer on the heterojunction structure and etching the gate layer to form a gate structure having etched sidewalls; Form a first passivation layer that is conformally disposed on all sidewall surfaces of the etched sidewalls of the gate structure and extends above the upper surface of the gate structure; Form a second passivation layer that conformally covers the first passivation layer, wherein the material composition of the second passivation layer is different from that of the first passivation layer, and wherein, in the lateral direction, a portion of the etched sidewalls of the gate structure, a portion of the first passivation layer, and a portion of the second passivation layer are adjacent to and overlap each other; Etch source / drain openings through the first passivation layer and the second passivation layer located on opposite sides of the gate structure; and Fill the source / drain openings with a conductive material to form a source conductor and a drain conductor on opposite sides of the gate structure.

8. The method of forming a high electron mobility transistor according to claim 7, wherein forming the heterojunction structure comprises: Forming a binary III / V semiconductor layer made of a first III-nitride material, the first III-nitride material serving as the channel region of the high electron mobility transistor; and Forming a ternary III / V semiconductor layer, the ternary III / V semiconductor layer being disposed above the binary III / V semiconductor layer and made of a second III-nitride material serving as a barrier layer.

9. The method of forming a high electron mobility transistor according to claim 8, wherein, The third III-nitride material of the gate structure is a binary III / V semiconductor material and has the same binary semiconductor composition as the first III-nitride material, and the third III-nitride material of the gate structure is in direct contact with the upper surface of the ternary III / V semiconductor layer.

10. The method of forming a high electron mobility transistor according to claim 8, wherein, The binary III / V semiconductor material of the first passivation layer has a binary semiconductor composition different from that of the first III-nitride material and the second III-nitride material.

11. The method of forming a high electron mobility transistor according to claim 10, wherein, The gate structure is a doped n-type or doped p-type gate structure, and wherein the binary III / V semiconductor layer is an intrinsic semiconductor material.

12. The method of forming a high electron mobility transistor according to claim 8, wherein, The source conductor and the drain conductor are formed to be in ohmic contact with the upper surface of the ternary III / V semiconductor layer and are laterally spaced apart from each other.

13. The method of forming a high electron mobility transistor according to claim 7, wherein, The second passivation layer is formed to have a thickness of 50 nm to 500 nm.

14. The method of forming a high electron mobility transistor according to claim 13, wherein, The first passivation layer has a thickness between 5 angstroms and 500 angstroms.

15. The method of forming a high electron mobility transistor according to claim 7, wherein, The second thickness of the second passivation layer is greater than the first thickness of the first passivation layer, and further includes: Conformally disposing a capping layer over the second passivation layer; and A metal gate electrode, the metal gate electrode includes an edge covering the upper surface of the capping layer, and includes an inner sidewall extending downward along the sidewall of an opening passing through the capping layer, the second passivation layer, and the first passivation layer, and the metal gate electrode is electrically connected to the upper surface of the gate structure.

16. A method of forming a high electron mobility transistor, Comprising: Forming an AlN buffer layer over a substrate; Forming an AlGaN buffer layer over the AlN buffer layer; Forming a GaN channel layer over the AlGaN buffer layer; Forming an AlGaN barrier layer over the GaN channel layer; Forming a GaN gate structure in direct contact with the upper surface of the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and an etched outer sidewall of the gate structure; Forming an AlN or BN conformal passivation layer in direct contact with the AlGaN barrier layer, extending over the upper surface of the GaN gate structure, and extending over all sidewall surfaces of the etched outer sidewall of the gate structure; Conformally forming a second passivation layer over the AlN or BN conformal passivation layer, wherein the material composition of the second passivation layer is different from the material composition of the AlN or BN conformal passivation layer, and in the lateral direction, a portion of the etched outer sidewall of the gate structure, a portion of the AlN or BN conformal passivation layer, and a portion of the second passivation layer are adjacent to and overlap each other; Forming source / drain openings through the AlN or BN conformal passivation layer and the second passivation layer; and Forming conductive source and drain regions in the source / drain openings to directly contact the upper surface of the AlGaN barrier layer.

17. The method of forming a high electron mobility transistor according to claim 16, further Comprising: Forming a capping layer conformally disposed on the upper surface of the second passivation layer, wherein the capping layer is conformally disposed along the outer sidewall of the second passivation layer and on the upper surface of the second passivation layer; Forming an opening in the capping layer between the source / drain openings and forming a metal gate electrode, the metal gate electrode includes an edge covering the upper surface of the capping layer, and includes an inner sidewall extending downward along the sidewall of an opening passing through the capping layer, the second passivation layer, and the AlN or BN conformal passivation layer, and the metal gate electrode is electrically connected to the gate structure.

18. The method of forming a high electron mobility transistor according to claim 16, Wherein, The AlN or BN conformal passivation layer is a BN conformal passivation layer, and the second passivation layer is made of SiO 2 fabricated.

Images