Semiconductor device including LDMOS transistor

Abstract

The present invention relates to a semiconductor device including an LDMOS transistor. In an embodiment, a semiconductor device includes: a semiconductor substrate having a body resistivity ρ ≥ 100 Ohm.cm, a front surface and a rear surface; at least one LDMOS transistor located in the semiconductor substrate; and a RESURF structure. The RESURF structure includes a doped buried layer, which is arranged in the semiconductor substrate, separated from the front surface and the rear surface by a certain distance, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

Description

Background Art

[0001] There is a continuing need for solid-state circuits adapted to operate at increasingly higher frequencies, including microwave frequencies. As used herein, the term "microwave" is intended to mean frequencies at or above about 300 MHz (e.g., between 300 MHz and 3 GHz). Various transistor structures have been created that can provide gain in this frequency range. The LDMOS (laterally diffused metal oxide semiconductor) transistor is an example of such a transistor structure.

[0002] For power amplifier circuits with faster switching speeds, LDMOS transistors with high breakdown voltage and low on-resistance are desired. However, these parameters are affected in opposite ways. For example, by increasing the drift length, the breakdown voltage is increased, but the on-resistance is increased.

[0003] Therefore, further improvements are desired for providing transistor devices with increased performance at higher frequencies. Summary of the invention

[0004] In an embodiment, a semiconductor device includes: a semiconductor substrate having a bulk resistivity p ≥ 100 Ohm.cm, a front surface and a back surface; at least one LDMOS transistor located in the semiconductor substrate; and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, separated from the front surface and the back surface by a certain distance, and coupled to at least one of a channel region and a body contact region of the LDMOS transistor.

[0005] In an embodiment, a semiconductor device includes: a semiconductor substrate having a bulk resistivity ρ ≥ 100 Ohm.cm, a front surface, and a rear surface; at least one LDMOS transistor located in the semiconductor substrate, the LDMOS transistor including a source region, a drain region, a channel region, a drift region, and a body contact region, wherein the source region is coupled to a conductive layer on the rear surface of the substrate; a doped buried layer arranged in the substrate, separated from the front surface and the rear surface by a certain distance, and coupled to the body contact region of the LDMOS transistor; a gate shield extending from the gate toward the source region of the LDMOS transistor; and a field plate extending from the gate toward the drain region of the LDMOS transistor.

[0006] In an embodiment, a method includes: implanting a self-depletion layer having a dopant concentration of a first conductivity type in a semiconductor substrate having a bulk resistivity ρ ≥ 100 Ohm.cm; and forming an LDMOS transistor in a front surface of the substrate so that a source region, a channel region, a drift region, and a drain region are separated from the self-depletion layer by a portion of the substrate, wherein the body contact region extends to the self-depletion layer and is coupled to the self-depletion layer.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements of the drawings are not necessarily drawn to scale relative to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and detailed in the following description.

[0009] Figure 1 FIG. 1 shows a semiconductor device including an LDMOS transistor having a RESURF structure.

[0010] Figure 2 FIG. 1 shows a semiconductor device including an LDMOS transistor having a RESURF structure.

[0011] Figure 3 FIG. 1 shows a semiconductor device including an LDMOS transistor having a RESURF structure.

[0012] Figure 4 FIG. 1 shows a semiconductor device including an LDMOS transistor having a RESURF structure.

[0013] Figure 5 FIG. 1 shows a semiconductor device including an LDMOS transistor having a RESURF structure.

[0014] Figure 6 FIG. 1 shows a semiconductor device including an LDMOS transistor having a RESURF structure.

[0015] Figure 7 A flow chart illustrating a method for processing an LDMOS transistor having a RESURF structure. DETAILED DESCRIPTION

[0016] In the detailed description below, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific embodiments of the present invention are shown as illustrations. In this respect, directional terms such as "top", "bottom", "front", "back", "head", "tail", etc. are used with reference to the orientation of the (one or more) accompanying drawings being described. Because the parts of the embodiments can be located in many different orientations, directional terms are used for illustrative purposes and are by no means restrictive. It should be understood that other embodiments may be used and structural or logical changes may be realized without departing from the scope of the present invention. The following detailed description should not be understood in a restrictive sense, and the scope of the present invention is defined by the appended claims.

[0017] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference numerals in the accompanying drawings. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or extent extending substantially parallel to the lateral extent of the semiconductor material or semiconductor carrier. The lateral direction therefore extends substantially parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction extending substantially perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. The vertical direction therefore extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0018] As used in this specification, when an element (such as a layer, region or substrate) is referred to as being “on” or “extending onto” another element, it can be directly on or directly extend onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “extending directly onto” another element, there are no intervening elements present.

[0019] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0020] As used herein, various device types and / or doped semiconductor regions may be identified as having n-type or p-type, but this is merely for convenience of description and is not intended to be limiting, and such identification may be replaced by a more general description of having a "first conductivity type" or a "second, opposite conductivity type," where the first type may be n or p-type and the second type may be p or n-type.

[0021] Those skilled in the art will appreciate that the active device(s) (such as LDMOS transistors) may be formed on or above a substrate or completely within a substrate or partially within a substrate and partially on or above a substrate, depending on the nature of the device(s). Thus, as used herein with respect to the active device(s), the terms "in a substrate," "in a semiconductor substrate," and equivalents are intended to include all such variations.

[0022] Figure 1 A semiconductor device 10 according to an embodiment is illustrated. The semiconductor device 10 includes a semiconductor substrate 11 having a front surface 12 and a back surface 13. The semiconductor substrate 11 has a bulk resistivity p, which is greater than or equal to 100 Ohm.cm. The semiconductor device 10 includes at least one LDMOS (laterally diffused metal oxide semiconductor) transistor 14 located in the semiconductor substrate 11. The semiconductor device 10 also includes a RESURF structure 15, which includes a doped buried layer 16 arranged in the semiconductor substrate 11. The doped buried layer 16 is separated from the front surface 12 by a certain distance and is separated from the back surface 13 of the semiconductor substrate 11 by a certain distance. The doped buried layer 16 is coupled to a channel region 17 and / or a body contact region 18 of the LDMOS transistor 14.

[0023] The RESURF structure 15 (Reduced Surface Field Structure) in the LDMOS transistor serves to reduce the electric field at the front surface 12 of the semiconductor substrate 11 and to achieve an improved compromise between high breakdown voltage and low on-resistance.

[0024] The semiconductor substrate 11 has a bulk resistivity p greater than or equal to 100 Ohm.cm and may be described as having a high resistance. In some embodiments, the semiconductor substrate 11 includes silicon and may include a silicon single crystal.

[0025] When the bulk resistivity of the semiconductor substrate is equal to or greater than a predetermined level, substrate-related inductance and capacitance parasitics can be reduced. The desired predetermined level is beneficially equal to or greater than 100 Ohm.cm resistivity, conveniently equal to or greater than about 500 Ohm.cm resistivity, and more conveniently equal to or greater than about 1000 Ohm.cm resistivity. As used herein, the term "bulk resistivity" refers to those portions of the substrate 60 that are located outside the device region (e.g., outside the doped regions of the LDMOS transistor and any associated RESURF structures).

[0026] The doped buried layer 16 of the RESURF structure 15 is provided to reduce the electric field at the front surface 12 of the semiconductor substrate 11 and, in particular, at the drain side edge 28 of the gate 21 and in the region starting from the drain side edge 28 of the gate 21 in the direction of the drain region 20. The doped buried layer 16 can also be configured to be self-depleted and source-grounded. The doped buried layer 16 is used to limit drain-source leakage by making the drain junction less abrupt and to help deplete the drift region during biasing of the drain junction.

[0027] As used herein, the term "LDMOS transistor" refers to a single LDMOS transistor structure including a source, a gate, and a drain. The single LDMOS transistor structure may also be referred to as a primitive or a fragment. The LDMOS transistor 14 includes: a source region 19, which is highly doped with a second conductivity type (e.g., n+); and a drain region 20, which is highly doped with a second conductivity type (e.g., n+). The source region 19 and the drain region 20 are asymmetrically arranged around a gate 21 at the front surface 12 of the semiconductor substrate 11, and the gate 21 is arranged on the front surface 12.

[0028] The drift region 22 extends from the gate 21 into the front surface 12 in the direction of the drain region 20 and may be doped with a second conductivity type (e.g., n). The drift region 22 extends deeper into the semiconductor substrate 11 than the drain region 20. The drift region is doped with the second conductivity type (e.g., n) and has a dopant concentration that is less than the dopant concentrations of the drain region 20 and the source region 19. The drift region 22 extends a greater distance in the semiconductor substrate 11 than the channel region 17, but is separated from the doped buried layer 16 by a portion of the semiconductor substrate 11.

[0029] The LDMOS transistor 14 further includes a channel region 17 extending from the drift region 22 below the source region 19, and a body contact region 18 doped with the first conductivity type and extending deeper into the semiconductor substrate 11 from the front surface 12 than the channel region 17. The body contact region 18 is provided by a highly doped well of the second conductivity type extending to and overlapping the doped buried layer 16.

[0030] In some embodiments, the semiconductor substrate 11 may include silicon lightly doped with a first conductivity type (e.g., p-). The buried doped layer 16 may be doped with the first conductivity type (e.g., p), the channel layer 17 may be doped with the first conductivity type (e.g., p), and the body contact region 18 may be highly doped with the first conductivity type (e.g., p+).

[0031] The LDMOS transistor 14 is one of a plurality of transistor cells or segments, whereby the same electrodes of the transistor cells are electrically coupled together to form a single switching device by a metallization structure, not shown, arranged on the front surface 12. In a symmetrical structure, the drain region 20 is provided around the center line 23, and a common drain region 20 is provided for two adjacent transistor cells or segments. However, an asymmetrical arrangement may also be used.

[0032] The drain region 20 advantageously has a thickness of at least 5.10 19 cm -3 The doping concentration is conveniently at least 1.10 20 cm -3 The doping concentration is more conveniently at least 3.10 20 cm -3 The drift region 22 is laterally adjacent to the drain region 20 in a symmetrical structure and has a doping concentration that is advantageously between 1.10 and 1.20. 16 cm -3 To 1.10 18 cm -3 range, conveniently at 7.10 16 cm -3 To 3.10 17 cm -3 and more conveniently around 1.10 17 cm -3 To 2.10 17 cm -3 The doping concentration of the drift region 22 is preferably in the range of 1.10 Å, but higher or lower doping concentrations may also be used. Laterally outward of the drift region 22 relative to the center line 23 is the channel region 17, which is located under at least a portion of the gate 21. The channel region 17 has a doping concentration that is advantageously in the range of 1.10 Å. 17 cm -3 To 2.10 18 cm -3 range, conveniently around 3.10 17 cm -3 To 1.10 18 cm -3 range, and more conveniently at 5.10 17 cm -3 to 9.10 17 cm -3 The doping concentration may be in the range of 5.10 Å, but higher or lower doping concentrations may also be used. Laterally outside the channel region 17 is the source region 19. The source region 19 advantageously has a doping concentration of at least 5.10 Å. 19 cm -3 , conveniently at least 1.1020 cm -3 , and more conveniently at least 3.10 20 cm -3 The doping concentration of the source region 19 is preferably 1.10, but higher or lower doping concentrations may also be used. Laterally outward of the source region 19 is the body contact region 18. The body contact region 18 has a doping concentration that is advantageously at 1.10 18 cm -3 To 1.10 20 cm -3 range, conveniently around 2.10 18 cm -3 To 7.10 19 cm -3 range, and more conveniently at 5.10 18 cm -3 To 5.10 19 cm -3 The substrate 11 may have a doping concentration in the range of 1.10 17 cm -3 To 2.10 18 cm -3 The doped buried layer may have a doping concentration in the range of 1.10 13 cm -3 To 2.10 15 cm -3 The doping concentration is in the range of .

[0033] When the gate 21 is appropriately biased, a conductive channel 17 is formed between the source region 19 and the drain region 20. The exemplary conductivity types presented above are suitable for forming an N-channel structure, but those skilled in the art will appreciate that a P-channel structure can also be formed by appropriate interchange of the conductivity types of the various doping regions and appropriate modification of the bias on the gate 21.

[0034] The source region 19 of the LDMOS transistor 14 may be coupled to the back surface 13 of the semiconductor substrate 11. The conductive path between the source region 19 and the back surface 13 may have different forms.

[0035] In some embodiments, a conductive via is provided that extends from the front surface 12 through the semiconductor substrate 11 to the back surface 13. The conductive via can be positioned so that the body contact area 18 surrounds the upper portion of the conductive via. The conductive via can be lined with a metal (such as tungsten or copper). In some embodiments, the bottom of the conductive via is filled with high purity copper, and the upper portion of the via includes a high purity copper cladding sidewall surrounding the void. The top of the via can be sealed to provide a cavity or gap within the upper portion of the substrate via.

[0036] A contact structure including one or more metal layers may extend substantially over the entire back surface 13 of the semiconductor substrate 11. The contact structure on the back surface 13 may be electrically coupled to a source region 19 in the opposite front surface 12 of the semiconductor substrate 11 by, for example, conductive vias.

[0037] By ion implantation through the front surface 12 of the semiconductor substrate 11 using an appropriately constructed mask and dopant ions and by subsequent diffusion of the implanted areas, a doped buried layer 16, a channel region 17, a body contact region 18, a drift region 22, a source region 19 and a drain region 20 may be formed.

[0038] In some embodiments (such as, Figure 2 In the embodiment shown in FIG. 1 , the source region 19 comprises a double well structure, and the drain region 20 comprises a double well structure. The second well 23 of the drain 20 may surround the more highly doped well 24, whereby both wells are doped with the second conductivity type.

[0039] The more highly doped well 25 of the source region 19 may extend to the source side 26 of the gate 21 and beyond the lateral extent of the body contact region 18. The more lightly doped well 27 of the source region 19 extends deeper into the substrate 11 than the more highly doped well 25 and extends a slightly lesser distance than the channel region 17 and may be located entirely within the body contact region 18. The rest of the LDMOS transistor 14 and the RESURF structure 15 are similar to Figure 1 The same as the embodiment shown in .

[0040] exist Figure 1 and 2 In the embodiment shown in FIG. 1 , the doped buried layer 16 of the RESURF structure 15 continuously extends through the lateral regions of the semiconductor substrate 11 and continuously extends under the source region 19, the gate 21, and the drain region 20 of the LDMOS transistor 14. The doped buried layer 16 is separated from the drift region 22 and the channel region 17 by a portion of the semiconductor substrate 11. The doped buried layer 16 has a dopant concentration that is greater than the dopant concentration of the semiconductor substrate 11 and less than the dopant concentration of the channel region 17.

[0041] The RESURF structure 15 is provided to reduce the electric field at the front surface 12 of the semiconductor substrate 11 and in particular, the electric field at the front surface 12 of the semiconductor substrate 11 at the drain side edge 28 of the gate 21 and in the direction of the drain region 20. The RESURF structure 15 can be used to increase the breakdown voltage of the transistor while maintaining a low on-resistance.

[0042] In addition to the doped buried layer 16, the RESURF structure 15 may include additional features to reduce the electric field at the front surface 12 of the semiconductor substrate 11. In some embodiments, the RESURF structure includes at least one field plate. The field plate may extend from the gate 21 toward the drain region 20. The field plate, the size and position of the doped buried layer 16, the doping level and profile of the doped buried layer 16 and the drift region 22 may be selected to produce an electric field at the front surface 12 that is below a desired threshold (e.g., 0.5 MV / cm).

[0043] Figure 3 The semiconductor device 10 is shown with a RESURF structure 15, which includes a doped buried layer 16 and further includes a field plate 33. The semiconductor device 10 includes a first dielectric layer 30 (e.g., a TEOS layer) located on the front surface 12 of the semiconductor substrate 11. The first dielectric layer 30 is structured and has: an opening located above the drain contact region 23, in which a drain metal contact 31 is formed; and an opening located above the source region 25, in which a source metal contact 32 is formed. The first dielectric layer 30 covers the gate 21 and extends between the source-side gate edge 26 and the source metal contact 32 and between the drain-side gate edge 28 and the drain metal contact 31.

[0044] The RESURF structure includes a field plate 33 , which is located on the first dielectric layer 30 above the gate 21 and extends on the first dielectric layer 30 in the direction of the drain metal contact 31 .

[0045] The second dielectric layer 34 is deposited so that it extends over the source metal contact 32, the portion of the first dielectric layer 30 between the source metal contact 32 and the field plate 33, over the gate 21, over the field plate 33, the portion of the first dielectric layer 30 extending between the field plate 33 and the drain metal contact 31, and over the drain metal contact 31. The second dielectric layer 34 may include two or more sublayers, such as a first sublayer of silicon oxynitride (SiON) and a second sublayer of silicon dioxide (SiO2) on the first sublayer.

[0046] The gate shield 35 is arranged on the second dielectric layer 34 above the gate 21 and extends in the direction of the source region 19 . The gate shield 35 may be conformally deposited on the second dielectric layer 34 and may partially overlap the gate-side end of the field plate 33 .

[0047] In this embodiment, the RESURF structure 15 includes a doped buried layer 16 , a lightly doped drain region 22 , and a field plate 33 . Figure 4The dimensions of the RESURF structure 15 and the LDMOS transistor structure are shown, which dimensions may be optimized to reduce the electric field at the front surface 12 , in particular, at the drain-side edge 28 of the gate 21 .

[0048] In order to reduce the front surface 12 and in particular at the drain side edge 28 of the gate 21 for a given transistor structure (such as Figure 2 The length L of the field plate between the drain side edge 28 of the gate 21 and the drain side edge 36 of the field plate 33 is FP , the length L of the gate 21 G , the length L of the drift region between the drain side edge 28 of the gate 21 and the gate side edge 37 of the drain metal contact 31 LDD , the height D of the field plate above the drift region FP , the depth D of the drift region relative to the front surface 12 LDD The depth D of the doped buried layer 16 relative to the front surface 12 may be appropriately selected and optimized.

[0049] The appropriate dimensions of the transistor structure may vary depending on the voltage level of the transistor device. For a voltage level of 28 V to 30 V, the length L FP The length L can be in the range of 0.8 μm to 1.2 μm. G It can be in the range of 0.2 μm to 0.5 μm, and the length L LDD It can be in the range of 2.5 μm to 3.2 μm, with a height D FP The depth D can be in the range of 0.1 μm to 0.2 μm. LDD The Å may be in the range of 0.1 μm to 0.5 μm, and the depth D of the doped buried layer may be in the range of 0.5 μm to 2.5 μm.

[0050] For a voltage level of 18V, the length L FP The length L can be in the range of 0.4 μm to 1.0 μm. G It can be in the range of 0.15 μm to 0.3 μm, and the length L LDD It can be in the range of 0.8 μm to 2.5 μm, with a height D FP The depth D can be in the range of 0.05 μm to 0.15 μm. LDD The Å may be in the range of 0.1 μm to 0.5 μm, and the depth D of the doped buried layer may be in the range of 0.3 μm to 2.0 μm.

[0051] For a voltage level of 50V, the length L FP The length L can be in the range of 0.8 μm to 2.0 μm.G It can be in the range of 0.3 μm to 0.8 μm, and the length L LDD It can be in the range of 3.0 μm to 8.0 μm, with a height D FP The depth D can be in the range of 0.15 μm to 0.35 μm. LDD The Å may be in the range of 0.1 μm to 1.0 μm, and the depth D of the doped buried layer may be in the range of 0.5 μm to 3.0 μm.

[0052] The semiconductor device can exhibit a breakdown voltage of at least 60 volts while supporting a saturation current of at least 0.15 A / mm.

[0053] The source region 19 may be coupled to the back surface 13 of the semiconductor substrate 11, and in particular, to a conductive layer 37 disposed on the back surface 13. The conductive layer 37 may provide a contact pad for mounting the semiconductor device 10 to a ground plane of a substrate and / or package. In some embodiments, the connection between the source region 19 and the back surface 13 of the semiconductor substrate 11 is provided by a conductive path at least partially located within the semiconductor substrate 11. Figure 5 and 6 Examples of conductive paths that may be used are shown.

[0054] Figure 5 The illustrated embodiment provides a through substrate via (TSV) 40 extending from the front surface 12 of the semiconductor substrate 11 to the back surface 13 of the semiconductor substrate 11. The TSV 40 may include a conductive material 41 (such as tungsten) filling the TSV 40. The TSV 40 may include an outermost dielectric liner to electrically insulate the conductive path within the TSV 40 from the doped regions of the semiconductor substrate 11. One or more liner layers, diffusion barrier layers, and / or seed layers that provide adhesion promotion are disposed between the material of the semiconductor substrate 11 that defines the sidewalls of the TSV 40 and the conductive material 41. The conductive material 41 may be electrically coupled to the source region 19 through a portion of a metallization structure 42 disposed on the front surface 12 of the substrate 11. TSV 40 extends through dielectric layer 43 disposed on front surface 12 and is coupled to metal layer 44 disposed on dielectric layer 43, which in turn is coupled to source region 19 through another conductive via 45 extending through dielectric layer 43 to source metal contact 32. Metal layer 44 may include aluminum.

[0055] Figure 6 The structure of a through substrate via (TSV) 50 is illustrated according to another embodiment, the TSV 50 extending from the front surface 12 of the semiconductor substrate 11 to the back surface 13 of the semiconductor substrate 11. The inset shows an enlarged view of the LDMOS transistor 14 and the electrical connection to the TSV 50.

[0056] The TSV 50 includes a first conductive portion 51 at its bottom, the first conductive portion 51 including a conductive material (such as high purity copper). At the bottom, the conductive material fills the volume of the TSV 50 and forms a portion of the rear surface 13 so that it is in direct contact with the conductive layer 37 located on the rear surface 13 of the semiconductor substrate 11. The TSV 50 also includes a conformal conductive layer 52, which is arranged on the sidewalls of the through hole and at least arranged on the perimeter of the upper surface of the conductive portion 51 located at the bottom of the through hole. The conformal conductive layer 52 may also include high purity copper. The conductive layer 52 may define a void 53 in the upper portion of the TSV 50, and the void 53 may be sealed at the top by, for example, a conductive layer or a semiconductor layer or a dielectric layer 54 to form a gap 55 in the upper portion of the TSV 50.

[0057] The upper region of TSV 50 is surrounded by body contact region 17. TSV 50 may be one of a plurality of TSVs arranged in a row or array in a region of a substrate between adjacent LDMOS transistors. The TSV or TSVs may be coupled to source regions of two adjacent LDMOS transistors.

[0058] Conformal conductive layer 52 may also extend over front surface 12 of semiconductor substrate 11 and may be disposed directly on and electrically coupled with conductive layer 56 that is coupled to source metal contact 32 adjacent source region 19 .

[0059] One or more additional layers may be arranged on the wall of TSV 50 to serve as adhesion promoting layers, diffusion barriers and / or seed layers, for example, Ti, TiN and Cu seed layers may be deposited using physical vapor deposition and / or chemical vapor deposition techniques, and first portion 51 and conformal conductive layer 52 may be deposited by electrodeposition techniques.

[0060] In this embodiment, a dual damascene technique may be used to form conformal conductive layer 52. Electroplating techniques may be used to form conformal conductive layer 52 and conductive portion 51. For example, the conditions for electrodepositing first conductive portion 51 may be different from those for electrodepositing conformal conductive layer 52 over first conductive portion 51.

[0061] The first conductive portion 51 and the conformal conductive layer 52 may have different microstructures, such as different average grain sizes.

[0062] Figure 7 A flow chart 80 illustrates a method for processing a LDMOS transistor having a RESURF structure including a doped buried layer according to one or more embodiments described herein.

[0063] In block 81, the method includes: implanting a self-depletion layer having a dopant concentration of a first conductivity type in a semiconductor substrate having a bulk resistivity ρ ≥ 100 Ohm.cm; and in block 82, forming an LDMOS transistor in a front surface of the substrate so that a source region, a channel region, a drift region, and a drain region are separated from the self-depletion layer by a portion of the substrate and a body contact region extends to the self-depletion layer and is coupled to the self-depletion layer.

[0064] The self-depletion layer may be implanted so that it extends continuously through the lateral region of the substrate. The substrate, the channel layer and the self-depletion layer are doped with a first conductivity type so that the dopant concentration of the self-depletion layer is greater than the dopant concentration of the substrate and less than the dopant concentration of the channel region. The body contact region is doped with the first conductivity type and has a dopant concentration greater than the dopant concentration of the channel region. The channel layer and the body contact region may be formed by implantation from the front surface and subsequent diffusion. The drift region may be formed by implantation from the front surface and subsequent diffusion.

[0065] The source region, the drift region and the drain region have a dopant concentration of a second conductivity type, which is opposite to the first conductivity type. The source region and the drain region are more highly doped than the drift region. The source region, the drift region and the drain region may also be formed by implantation from the front surface.

[0066] After forming the LDMOS transistor, the method may further proceed to block 83 and include inserting a blind via or a closed via into the front surface of the substrate such that the body contact region surrounds the via, in block 84, inserting a conductive material into the blind via, and in block 85, electrically coupling the conductive material to the source region.

[0067] In some embodiments, inserting the conductive material into the through hole includes inserting the conductive material into the through hole and forming a first portion filling the through hole at the bottom of the through hole, and inserting the conductive material into the upper portion of the through hole, the conductive material lining the sidewalls of the through hole to surround the void. The method can further proceed to block 86 and include removing a portion of the rear surface of the substrate to expose the conductive material within the through hole at the rear surface, and in block 87, applying a conductive layer to the rear surface and the conductive material.

[0068] One or more semiconductor devices including one or more LDMOS transistors according to any one of the embodiments described herein may be used in high-frequency power amplifier circuits, such as RF power amplifier circuits for cellular communications operating at frequencies in the range of 700 MHz to 3.6 GHz, power conversion in cellular communication networks, and Doherty configuration amplifier circuits.

[0069] Spatially relative terms (such as "below," "beneath," "below," "above," "on," etc.) are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device in addition to those depicted in the drawings. In addition, terms such as "first," "second," etc. are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. The same terms refer to the same elements throughout the description.

[0070] As used herein, the terms "having", "containing", "comprising", "including", etc. are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0071] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to include any modifications or variations of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a bulk resistivity ρ ≥ 100 Ohm.cm, a front surface and a back surface; A laterally diffused metal oxide semiconductor (LDMOS) transistor in a semiconductor substrate; and A reduced surface field (RESURF) structure comprising a doped buried layer arranged in a semiconductor substrate, The LDMOS transistor includes: a body contact region doped with a first conductivity type; and a source region disposed in the body contact region and doped with a second conductivity type opposite to the first conductivity type, The source region includes a first well and a second well of the same second conductivity type, wherein the first well is more highly doped than the second well, The first well extends from the inside of the body contact region to the outside of the lateral extent of the body contact region in a direction toward the source side of the gate of the LDMOS transistor.

2. The semiconductor device of claim 1 , wherein the doped buried layer is spaced a distance from the front surface and the back surface and is coupled to at least one of a channel region and a body contact region of the LDMOS transistor, and wherein the RESURF structure further comprises: A lightly doped region extending from the gate toward the drain region of the LDMOS transistor; and At least one field plate. 3 . The semiconductor device according to claim 1 , wherein the doped buried layer continuously extends through a lateral region of the semiconductor substrate. 4 . The semiconductor device of claim 1 , wherein the doped buried layer extends continuously under a drain region, a source region, and a gate of the LDMOS transistor. 5 . The semiconductor device of claim 1 , wherein the second well extends farther into the substrate than the first well by a distance less than a distance a channel region of the LDMOS transistor extends, and is completely located within the body contact region.

6. The semiconductor device according to claim 1 further comprises a first dielectric layer on the front surface of the substrate, the first dielectric layer having: an opening above the drain region of the LDMOS transistor, a drain metal contact being formed in the opening; and an opening above the source region of the LDMOS transistor, a source metal contact being formed in the opening. 7 . The semiconductor device of claim 6 , wherein the first dielectric layer covers the gate of the LDMOS transistor and extends between a source-side edge of the gate and the source metal contact and between a drain-side edge of the gate and the drain metal contact.

8. The semiconductor device according to claim 6, further comprising: A field plate is located on the first dielectric layer above the gate and extends on the first dielectric layer in the direction of the drain metal contact portion.

9. The semiconductor device according to claim 8, further comprising: A second dielectric layer extends over the source metal contact, over a portion of the first dielectric layer between the source metal contact and the field plate, over the gate, over the field plate, over a portion of the first dielectric layer extending between the field plate and the drain metal contact, and over the drain metal contact. 10 . The semiconductor device of claim 9 , wherein the second dielectric layer comprises a first sublayer of silicon oxynitride and a second sublayer of silicon dioxide on the first sublayer. 11 . The semiconductor device according to claim 9 , further comprising a gate shield arranged on the second dielectric layer above the gate and extending in the direction of the source region. 12 . The semiconductor device of claim 11 , wherein the gate shield is conformally deposited on the second dielectric layer and partially overlaps a gate-side end of the field plate.

13. The semiconductor device according to claim 1 further includes a conductive via extending from the front surface of the substrate to the rear surface, wherein the conductive via includes a first conductive portion adjacent to the rear surface filling a lower portion of the conductive via and a second conductive portion arranged on the first conductive portion lining a sidewall of the via and surrounding a void, wherein the void is sealed at a top to form a gap within an upper portion of the conductive via.

14. The semiconductor device of claim 13, wherein the second conductive portion extends over the front surface of the substrate and is directly disposed on and electrically coupled to a conductive layer coupled to a source metal contact at a position adjacent to a source region of the LDMOS transistor.

15. The semiconductor device according to claim 1 further includes a conductive via extending from the front surface to the rear surface through the semiconductor substrate and through a dielectric layer formed on the front surface, wherein the conductive via electrically connects the conductive layer arranged on the rear surface with a metal layer arranged on the dielectric layer, and wherein the metal layer is electrically connected to the source region through the conductive via extending through the dielectric layer to the source metal contact portion.

16. The semiconductor device according to claim 1, further comprising: A conductive via extends through the semiconductor substrate from the front surface to the back surface, including through the body contact region.

17. A high frequency amplifier circuit, comprising: An RF power amplifier circuit formed on a semiconductor substrate, wherein the semiconductor substrate has a bulk resistivity ρ ≥ 100 Ohm.cm, a front surface and a rear surface; The RF power amplifier circuit includes: a laterally diffused metal oxide semiconductor (LDMOS) transistor in a semiconductor substrate; and a reduced surface field (RESURF) structure, the structure including a doped buried layer arranged in the semiconductor substrate, The LDMOS transistor includes: a body contact region doped with a first conductivity type; and a source region disposed in the body contact region and doped with a second conductivity type opposite to the first conductivity type, wherein the source region includes a first well and a second well of the same second conductivity type, wherein the first well is more highly doped than the second well, The first well extends from the inside of the body contact region to the outside of the lateral extent of the body contact region in a direction toward the source side of the gate of the LDMOS transistor.

18. The high frequency amplification circuit of claim 17, wherein the RF power amplification circuit is configured for cellular communication within an operating frequency range of 700 MHz to 3.6 GHz.

19. The high frequency amplification circuit according to claim 17, wherein the RF power amplification circuit is configured for power conversion in a cellular communication network.

20. The high frequency amplifying circuit according to claim 17, wherein the RF power amplifying circuit is a Doherty amplifying circuit.

21. A semiconductor device comprising: a semiconductor substrate having a bulk resistivity ρ ≥ 100 Ohm.cm, a front surface and a back surface; A laterally diffused metal oxide semiconductor (LDMOS) transistor in a semiconductor substrate; A reduced surface field (RESURF) structure comprising a doped buried layer disposed in a semiconductor substrate; a first dielectric layer on the front surface of the substrate, the first dielectric layer having: an opening above the drain region of the LDMOS transistor, a drain metal contact formed in the opening; and an opening above the source region of the LDMOS transistor, a source metal contact being formed in the opening, the first dielectric layer covering the gate of the LDMOS transistor and extending between a source-side gate edge and the source metal contact and between a drain-side gate edge and the drain metal contact; a field plate, located on the first dielectric layer above the gate and extending on the first dielectric layer in the direction of the drain metal contact; a second dielectric layer extending over the source metal contact, over a portion of the first dielectric layer between the source metal contact and the field plate, over the gate, over the field plate, over a portion of the first dielectric layer extending between the field plate and the drain metal contact, and over the drain metal contact; as well as A gate shield is arranged on the second dielectric layer above the gate and extends in the direction of the source region. 22 . The semiconductor device of claim 21 , wherein the gate shield is conformally deposited on the second dielectric layer and partially overlaps a gate-side end of the field plate.

23. A high-frequency amplifier circuit comprising the semiconductor device according to claim 21.

24. The high frequency amplification circuit of claim 23, wherein the high frequency amplification circuit comprises an RF power amplification circuit configured for cellular communications operating in a frequency range of 700 MHz to 3.6 GHz.

25. The high frequency amplification circuit of claim 23, wherein the high frequency amplification circuit comprises an RF power amplification circuit configured for power conversion in a cellular communication network. 26 . The high-frequency amplification circuit according to claim 23 , wherein the high-frequency amplification circuit comprises an RF power amplification circuit configured for a Doherty amplification circuit.

27. A semiconductor device comprising: a semiconductor substrate having a bulk resistivity ρ ≥ 100 Ohm.cm, a front surface and a back surface; A laterally diffused metal oxide semiconductor (LDMOS) transistor in a semiconductor substrate; and A reduced surface field (RESURF) structure comprising a doped buried layer arranged in a semiconductor substrate, wherein the doped buried layer of the RESURF structure has the same conductivity type as the channel region and / or the body contact region of the LDMOS transistor, wherein the doped buried layer of the RESURF structure is coupled to at least one of a channel region and a body contact region of the LDMOS transistor, The doped buried layer of the RESURF structure is separated from the channel region and the drift region of the LDMOS transistor by a portion of the semiconductor substrate.

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