Multithreaded self-scheduling reconfigurable computing architecture

Abstract

Representative apparatus, method, and system embodiments for configurable computing are disclosed. A representative system includes an interconnect network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes: a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes: a configurable computing circuit; and a configuration memory having: a first instruction memory storing a plurality of datapath configuration instructions for configuring a datapath of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and datapath configuration instruction indexes for selection of a master synchronization input, a current datapath configuration instruction, and a next datapath configuration instruction of a next configurable computing circuit.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application of and claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 651,128, filed on March 31, 2018, entitled “Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric,” whose inventor is Tony M. Brewer, which is commonly assigned herewith, and the entire contents of which are hereby incorporated by reference herein in their entirety with the same full force and effect as if set forth as a whole herein (hereinafter referred to as the “Related Application”). Technical Field

[0003] The present invention relates generally to configurable computing circuitry, and more particularly to heterogeneous computing systems including configurable computing circuitry with embedded interconnect networks, dynamic reconfiguration, and dynamic control of energy or power consumption. Background Art

[0004] Many existing computing systems have reached significant limits in computing processing capabilities in terms of computing speed, energy (or power) consumption, and associated heat dissipation. For example, as the demand for advanced computing technologies grows, existing computing solutions are increasingly inadequate to accommodate, for example, artificial intelligence and other important computing applications.

[0005] Therefore, there is a continuing need for a computing architecture that can provide high-performance and energy-efficient solutions for compute-intensive cores, such as the computation of Fast Fourier Transforms (FFTs) and Finite Impulse Response (FIR) filters used in sensing, communication, and analysis applications (synthetic aperture radar, 5G base stations) and graph analysis applications (such as graph clustering using spectroscopy techniques, machine learning, 5G networking algorithms, and large template codes), to name but not limited.

[0006] There is also a continuing need for a configurable computing architecture that can be configured for any of these various applications, but most importantly, is also capable of dynamically self-configuring and self-reconfiguring. Summary of the invention

[0007] As discussed in more detail below, representative devices, systems, and methods provide a computing architecture capable of providing high-performance and energy-efficient solutions for compute-intensive cores for computation of fast Fourier transforms (FFTs) and finite impulse response (FIR) filters used in sensing, communication, and analysis applications (synthetic aperture radar, 5G base stations) and graph analysis applications (e.g., graph clustering using spectroscopy techniques, machine learning, 5G networking algorithms, and large template codes), for example and without limitation.

[0008] Notably, the various representative embodiments provide a multi-threaded coarse-grained configurable computing architecture that is capable of being configured for any of these various applications, but most importantly, is also capable of self-scheduling, dynamic self-configuration and self-reconfiguration, conditional branching, backpressure control for asynchronous signaling, ordered thread execution and loop thread execution (including in data dependencies), automatic start of thread execution after data dependencies and / or ordering are completed, providing loop access to private variables, using re-entrant queues to provide fast execution of loop threads, and using various thread identifiers for advanced loop execution (including nested loops).

[0009] In a representative embodiment, a configurable circuit may include: a configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a configuration memory coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs, and the synchronization network outputs, wherein the configuration memory includes: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indexes for selection of a master synchronization input of the synchronization network inputs.

[0010] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; and a configuration memory coupled to the configurable computing circuit, a control circuit system, a synchronization network input, and the synchronization network output, the configuration memory including: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and a data path configuration instruction index for selection of a current data path configuration instruction of the configurable computing circuit.

[0011] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; and a configuration memory coupled to the configurable computing circuit, a control circuit system, a synchronization network input, and a synchronization network output, the configuration memory including: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and a data path configuration instruction index for selection of a next data path configuration instruction of a next configurable computing circuit.

[0012] In another representative embodiment, the configurable circuit may include: a configurable computing circuit; a control circuit coupled to the configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs coupled to the configurable computing circuit; a plurality of synchronous network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, the control circuit system, the synchronous network inputs and the synchronous network outputs, the configuration memory circuit including: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indexes for selection of a master synchronous input of the synchronous network input.

[0013] In yet another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs, and the synchronization network outputs; and a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a thread control circuit; and a plurality of control registers.

[0014] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; a configuration memory coupled to the configurable computing circuit, a control circuit system, a synchronous network input and a synchronous network output, the configuration memory including: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indexes for selecting a next data path instruction or a next data path instruction index for a next configurable computing circuit; and a conditional logic circuit coupled to the configurable computing circuit, wherein depending on an output from the configurable computing circuit, the conditional logic circuit is suitable for providing a conditional branch by modifying the next data path instruction or the next data path instruction index provided on a selected output of the plurality of synchronous network outputs.

[0015] In another representative embodiment, the configurable circuit may include: a configurable computing circuit; a control circuit coupled to the configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs coupled to the configurable computing circuit; a plurality of synchronous network outputs coupled to the configurable computing circuit; an asynchronous network input queue coupled to an asynchronous packet network and the first memory circuit; an asynchronous network output queue; and a flow control circuit coupled to the asynchronous network output queue, the flow control circuit being adapted to generate a stop signal when a predetermined threshold has been reached in the asynchronous network output queue.

[0016] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs, and the synchronization network outputs; and a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a thread control circuit; and a plurality of control registers, wherein the plurality of control registers store a loop table having a plurality of thread identifiers and, for each thread identifier, a next thread identifier for execution after execution of a current thread to provide in-order thread execution.

[0017] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs, and the synchronization network outputs; and a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a first data completion count; and a thread control circuit adapted to queue a thread for execution when its completion count has been decremented to zero for its thread identifier.

[0018] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs and outputs coupled to the configurable computing circuit; and an asynchronous network input queue and an asynchronous network output queue; a second configuration memory circuit coupled to the configurable computing circuit, the control circuit system, the synchronous network inputs, and the synchronous network outputs, the second configuration memory including: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing: a plurality of data path configuration instructions for configuring the synchronous network inputs and outputs of the configurable computing circuit; and a plurality of data path configuration instructions for configuring the synchronous network outputs of the configurable computing circuit. a plurality of spoke instructions and datapath configuration instruction indexes for selecting a master synchronization input of a network input, selecting a current datapath configuration instruction for the configurable computing circuit, and selecting a next datapath instruction or a next datapath instruction index for a next configurable computing circuit; and the configurable circuit further comprises: a control circuit coupled to the configurable computing circuit, the control circuit comprising: a memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a first data completion count; and a thread control circuit adapted to queue a thread for execution when its completion count has been decremented to zero for its thread identifier.

[0019] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs, and the synchronization network outputs; and a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a first data completion count; and a thread control circuit adapted to queue a thread for execution when its completion count has been decremented to zero for its thread identifier and its thread identifier is a next thread.

[0020] In yet another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs, and the synchronization network outputs; and the configurable circuit further includes: a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a thread control circuit; and a plurality of control registers storing a completion table having a plurality of types of thread identifiers, wherein each type of thread identifier indicates a loop stage for loop and nested loop execution, and wherein the plurality of control registers further store a top of a thread identifier stack to allow each type of thread identifier to access private variables of a selected loop.

[0021] In another representative embodiment, the configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronization network inputs coupled to the configurable computing circuit; a plurality of synchronization network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronization network inputs and the synchronization network outputs; and a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a plurality of control registers; and a thread control circuit including: a continuation queue storing one or more thread identifiers of computing threads having a completion count allowed to execute but not yet having an assigned thread identifier; and a reentry queue storing one or more thread identifiers of computing threads having a completion count allowed to execute and having an assigned thread identifier to provide execution of the threads in the reentry queue after a specified spoke count.

[0022] In another representative embodiment, a configurable circuit may include: a configurable computing circuit; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs coupled to the configurable computing circuit; a plurality of synchronous network outputs coupled to the configurable computing circuit; and a second configuration memory circuit coupled to the configurable computing circuit, a control circuit system, the synchronous network inputs and the synchronous network outputs; and a control circuit coupled to the configurable computing circuit, the control circuit including: a memory control circuit; a plurality of control registers storing a thread identifier pool and a completion table having a loop count of a valid number of loop threads; and a thread control circuit, wherein in response to receipt of an asynchronous fabric message that returns a thread identifier to the thread identifier pool, the control circuit decrements the loop count and transmits an asynchronous fabric completion message when the loop count reaches zero.

[0023] In a representative embodiment, a system is disclosed that may include: an asynchronous packet network; a synchronous network; and a plurality of configurable circuits arranged in an array, each of the plurality of configurable circuits being coupled to both the synchronous network and the asynchronous packet network, the plurality of configurable circuits being adapted to perform a plurality of calculations using the synchronous network to form a plurality of synchronization domains, and the plurality of configurable circuits being further adapted to generate and transmit a plurality of control messages through the asynchronous packet network, the plurality of control messages including one or more completion messages and continue messages.

[0024] In another representative embodiment, a system may include: a plurality of configurable circuits arranged in an array; a synchronous network coupled to each of the plurality of configurable circuits of the array; and an asynchronous packet network coupled to each of the plurality of configurable circuits of the array.

[0025] In another representative embodiment, a system may include: an interconnect network; a processor coupled to the interconnect network; and a plurality of configurable circuit clusters coupled to the interconnect network.

[0026] In a representative embodiment, a system may include: an interconnection network; a processor coupled to the interconnection network; a host interface coupled to the interconnection network; and a plurality of configurable circuit clusters coupled to the interconnection network, each of the plurality of configurable circuit clusters comprising: a plurality of configurable circuits arranged in an array; a synchronous network coupled to each of the plurality of configurable circuits in the array; an asynchronous packet network coupled to each of the plurality of configurable circuits in the array; a memory interface coupled to the asynchronous packet network and the interconnection network; and a dispatch interface coupled to the asynchronous packet network and the interconnection network.

[0027] In another representative embodiment, a system may include: a hierarchical interconnection network comprising a first plurality of crossbar switches having a Folded Clos configuration and a plurality of direct mesh connections at interfaces with endpoints; a processor coupled to the interconnection network; a host interface coupled to the interconnection network; and a plurality of configurable circuit clusters coupled to the interconnection network, each of the plurality of configurable circuit clusters comprising: a plurality of configurable circuits arranged in an array; a synchronous network coupled to each of the plurality of configurable circuits of the array and providing a plurality of direct connections between adjacent configurable circuits of the array; an asynchronous packet network comprising a second plurality of crossbar switches, each crossbar switch coupled to at least one of the plurality of configurable circuits of the array and another crossbar switch of the second plurality of crossbar switches; a memory interface coupled to the asynchronous packet network and the interconnection network; and a dispatch interface coupled to the asynchronous packet network and the interconnection network.

[0028] In another representative embodiment, a system may include: an interconnection network; a processor coupled to the interconnection network; a host interface coupled to the interconnection network; and a plurality of configurable circuit clusters coupled to the interconnection network, each of the plurality of configurable circuit clusters comprising: a synchronous network; an asynchronous packet network; a memory interface coupled to the asynchronous packet network and the interconnection network; a dispatch interface coupled to the asynchronous packet network and the interconnection network; and a plurality of configurable circuits arranged in an array, each configurable circuit comprising: a configurable computing circuit; a control circuit coupled to the configurable computing circuit, the control circuit comprising: a memory control circuit; a thread control circuit; and a plurality of control registers; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs and outputs coupled to the configurable computing circuit and the synchronous network; an asynchronous network input queue and an asynchronous network output queue; a second configuration memory circuit coupled to the configurable computing circuit, the control circuit system, the synchronous network input and the synchronous network output, the configuration memory circuit comprising: a first instruction memory storing a plurality of data path configuration instructions for configuring the data path of the configurable computing circuit; and a second instruction and instruction index memory storing: a plurality of spoke instructions and data path configuration instruction indexes for selection of a master synchronous input of the synchronous network input.

[0029] In any of the various representative embodiments, the second instruction and instruction index memory may further store a plurality of spoke instructions and data path configuration instruction indexes for selection of a current data path configuration instruction for the configurable computing circuit.

[0030] In any of the various representative embodiments, the second instruction and instruction index memory may further store a plurality of spoke instructions and data path configuration instruction indexes for selection of a next data path configuration instruction for a next configurable computing circuit.

[0031] In any of the various representative embodiments, the second instruction and instruction index memory may further store a plurality of spoke instructions and data path configuration instruction indexes for selection of a synchronous network output among the plurality of synchronous network outputs.

[0032] In any of the various representative embodiments, the configurable circuit or system may further include: a configuration memory multiplexer coupled to the first instruction memory and the second instruction and instruction index memory.

[0033] In any of the various representative embodiments, when a select input of the configuration memory multiplexer has a first setting, the current datapath configuration instruction may be selected using an instruction index from a second instruction and instruction index memory.

[0034] In any of the various representative embodiments, when the select input of the configuration memory multiplexer has a second setting different than the first setting, the current datapath configuration instruction may be selected using an instruction index from a master synchronization input.

[0035] In any of the various representative embodiments, the second instruction and instruction index memory may further store a plurality of spoke instructions and datapath configuration instruction indexes for configuring portions of the configurable circuitry independently of the current datapath instruction.

[0036] In any of the various representative embodiments, the selected spoke instruction and data path configuration instruction index of the plurality of spoke instructions and data path configuration instruction indexes may be selected according to a modulo spoke count.

[0037] In any of the various representative embodiments, the configurable circuit or system may further include: a conditional logic circuit coupled to the configurable computation circuit.

[0038] In any of the various representative embodiments, depending on an output from the configurable computation circuit, the conditional logic circuit may be adapted to modify a next datapath instruction index provided on a selected one of the plurality of synchronous network outputs.

[0039] In any of the various representative embodiments, depending on an output from the configurable computation circuit, the conditional logic circuit may be adapted to provide conditional branching by modifying a next data path instruction or a next data path instruction index provided on a selected output of the plurality of synchronous network outputs.

[0040] In any of the various representative embodiments, the conditional logic circuit, when enabled, may be adapted to provide conditional branching by ORing the least significant bits of the next datapath instruction with the output from the configurable computation circuit to specify a next datapath instruction or a datapath instruction index.

[0041] In any of the various representative embodiments, the conditional logic circuit, when enabled, may be adapted to provide conditional branching by ORing a least significant bit of the next datapath instruction with an output from the configurable computation circuit to specify a next datapath instruction index.

[0042] In any of the various representative embodiments, the plurality of synchronous network inputs may include: a plurality of input registers coupled to a plurality of communication lines of a synchronous network; and an input multiplexer coupled to the plurality of input registers and the second instruction and instruction index memory for selection of the master synchronous input.

[0043] In any of the various representative embodiments, the plurality of synchronous network outputs may include: a plurality of output registers coupled to a plurality of communication lines of the synchronous network; and an output multiplexer coupled to the configurable computing circuit for selection of outputs from the configurable computing circuit.

[0044] In any of the various representative embodiments, the configurable circuit or system may further include: an asynchronous network input queue coupled to an asynchronous packet network and the memory circuit; and an asynchronous network output queue coupled to the output multiplexer.

[0045] In any of the various representative embodiments, the configurable circuit or system may further include: an asynchronous architecture state machine, which is coupled to the asynchronous network input queue and the asynchronous network output queue, and the asynchronous architecture state machine is suitable for decoding input data packets received from the asynchronous packet network and assembling output data packets for transmission on the asynchronous packet network.

[0046] In any of the various representative embodiments, the asynchronous packet network may include a plurality of crossbar switches, each crossbar switch coupled to a plurality of configurable circuits and at least another crossbar switch.

[0047] In any of the various representative embodiments, the configurable circuit or system may further include: an array of multiple configurable circuits, wherein: each configurable circuit is coupled to the synchronous network through the multiple synchronous network inputs and the multiple synchronous network outputs; and each configurable circuit is coupled to the asynchronous packet network through the asynchronous network input and the asynchronous network output.

[0048] In any of the various representative embodiments, the synchronization network may include a plurality of direct point-to-point connections coupling adjacent configurable circuits of the array of the plurality of configurable circuits.

[0049] In any of the various representative embodiments, each configurable circuit may include: a direct transfer connection between the plurality of input registers and the plurality of output registers. In any of the various representative embodiments, the direct transfer connection may provide a direct point-to-point connection for data transmission from a second configurable circuit received on the synchronous network to a third configurable circuit transmitted on the synchronous network.

[0050] In any of the various representative embodiments, the configurable computing circuitry may include arithmetic, logical, and bitwise operations suitable for performing at least one integer operation selected from the group consisting of signed and unsigned addition, absolute value, negation, logical NOT, addition and negation, subtraction AB, inverse subtraction BA, signed and unsigned greater than, signed and unsigned greater than or equal to, signed and unsigned less than, signed and unsigned less than or equal to, comparison of equal to or not equal to, logical AND operation, logical OR operation, logical XOR operation, logical NAND operation, logical NOR operation, logical NOT XOR operation, logical AND NOT operation, logical OR NOT operation, and conversion between integer and floating point.

[0051] In any of the various representative embodiments, the configurable computing circuit may include arithmetic logic and bit operations, which are suitable for performing at least one floating-point operation selected from the group consisting of: signed and unsigned addition, absolute value, negation, logical NOT, addition and negation, subtraction AB, reverse subtraction BA, signed and unsigned greater than, signed and unsigned greater than or equal to, signed and unsigned less than, signed and unsigned less than or equal to, comparison of equality or inequality, logical AND operation, logical OR operation, logical XOR operation, logical NAND operation, logical NOR operation, logical NOTXOR operation, logical AND NOT operation, logical OR NOT operation, conversion between integer and floating point, and combinations thereof.

[0052] In any of the various representative embodiments, the configurable computing circuit may include multiplication and shift operation circuitry adapted to perform at least one integer operation selected from the group consisting of: multiplication, shift, pass input, signed and unsigned multiplication, signed and unsigned right shift, signed and unsigned left shift, bit order reversal, permutation, conversion between integer and floating point, and combinations thereof.

[0053] In any of the various representative embodiments, the configurable computing circuit may include multiplication and shift operation circuitry adapted to perform at least one floating-point operation selected from the group consisting of: multiplication, shift, pass input, signed and unsigned multiplication, signed and unsigned right shift, signed and unsigned left shift, bit order reversal, permutation, conversion between integer and floating point, and combinations thereof.

[0054] In any of the various representative embodiments, the array of the plurality of configurable circuits may be further coupled to a first interconnect network. In any of the various representative embodiments, the array of the plurality of configurable circuits may further include: a third system memory interface circuit; and a dispatch interface circuit. In any of the various representative embodiments, the dispatch interface circuit may be adapted to receive a work descriptor packet through the first interconnect network, and in response to the work descriptor packet, generate one or more data and control packets to the plurality of configurable circuits to configure the plurality of configurable circuits for performance of a selected computation.

[0055] In any of the various representative embodiments, the configurable circuit or system may further include: a flow control circuit coupled to the asynchronous network output queue, the flow control circuit being adapted to generate a stop signal when a predetermined threshold has been reached in the asynchronous network output queue. In any of the various representative embodiments, in response to the stop signal, each asynchronous network output queue stops outputting data packets on the asynchronous packet network. In any of the various representative embodiments, in response to the stop signal, each configurable computing circuit stops executing after its current execution is completed.

[0056] In any of the various representative embodiments, a first plurality of configurable circuits of the array of the plurality of configurable circuits may be coupled in a first predetermined order through the synchronization network to form a first synchronization domain; and wherein a second plurality of configurable circuits of the array of the plurality of configurable circuits may be coupled in a second predetermined order through the synchronization network to form a second synchronization domain. In any of the various representative embodiments, the first synchronization domain may be adapted to generate a continuation message transmitted to the second synchronization domain through the asynchronous packet network. In any of the various representative embodiments, the second synchronization domain may be adapted to generate a completion message transmitted to the first synchronization domain through the asynchronous packet network.

[0057] In any of the various representative embodiments, the plurality of control registers may store a completion table having a first data completion count. In any of the various representative embodiments, the plurality of control registers may further store a completion table having a second iteration count. In any of the various representative embodiments, the plurality of control registers may further store a loop table having a plurality of thread identifiers and, for each thread identifier, a next thread identifier for execution after execution of a current thread. In any of the various representative embodiments, the plurality of control registers may further store an identification of a first iteration and an identification of a last iteration in the loop table.

[0058] In any of the various representative embodiments, the control circuitry may be adapted to queue a thread for execution when its completion count has been decremented to zero for its thread identifier and its thread identifier is the next thread.

[0059] In any of the various representative embodiments, the control circuitry may be adapted to queue a thread for execution when its completion count for its thread identifier indicates completion of any data dependencies. In any of the various representative embodiments, the completion count may indicate a predetermined number of completion messages to be received for each of the plurality of threads before the selected thread executes.

[0060] In any of the various representative embodiments, the plurality of control registers may further store a completion table having a plurality of types of thread identifiers, wherein each type of thread identifier indicates a loop stage for loop and nested loop execution.

[0061] In any of the various representative embodiments, the plurality of control registers may further store a completion table having loop counts of a valid number of loop threads, and wherein in response to receipt of an asynchronous architecture message that returns a thread identifier to a thread identifier pool, the control circuit decrements the loop count and transmits an asynchronous architecture completion message when the loop count reaches zero. In any of the various representative embodiments, the plurality of control registers may further store a top of a thread identifier stack to allow each type of thread identifier to access private variables of a selected loop.

[0062] In any of the various representative embodiments, the control circuitry may further include: a continuation queue; and a reentry queue. In any of the various representative embodiments, the continuation queue stores one or more thread identifiers of computing threads that have completion counts that allow execution but do not yet have assigned thread identifiers. In any of the various representative embodiments, the reentry queue may store one or more thread identifiers of computing threads that have completion counts that allow execution and have assigned thread identifiers. In any of the various representative embodiments, any thread with a thread identifier in the reentry queue may be executed before the execution of any thread with a thread identifier in the continuation queue.

[0063] In any of the various representative embodiments, the control circuitry may further include: a priority queue, wherein any thread having a thread identifier in the priority queue may be executed before execution of any thread having a thread identifier in the continuation queue or the reentry queue.

[0064] In any of the various representative embodiments, the control circuitry may further include: a run queue, wherein once the spoke count of the thread identifier occurs, any thread having a thread identifier in the run queue may be executed.

[0065] In any of the various representative embodiments, the second configuration memory circuit may include: a first instruction memory storing a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and a second instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indexes for selection of a master synchronization input of the synchronization network input.

[0066] In any of the various representative embodiments, the control circuitry may be adapted to self-schedule computing threads for execution.

[0067] In any of the various representative embodiments, the conditional logic circuitry may be adapted to branch to a different second next instruction for execution by the next configurable circuitry.

[0068] In any of the various representative embodiments, the control circuitry may order sequential computing threads for execution. In any of the various representative embodiments, the control circuitry may be adapted to order cyclic computing threads for execution. In any of the various representative embodiments, the control circuitry may be adapted to start execution of computing threads in response to one or more completion signals from data dependencies.

[0069] Various method embodiments for configuring a configurable circuit are also disclosed. A representative method embodiment may include: using a first instruction memory to provide a plurality of data path configuration instructions for configuring a data path of the configurable computing circuit; and using a second instruction and instruction index memory to provide a plurality of spoke instructions and data path configuration instruction indexes for selecting a master synchronization input from a plurality of synchronization network inputs.

[0070] In any of the various representative embodiments, a method for configuring a configurable circuit may include: using a first instruction memory, providing a plurality of datapath configuration instructions for configuring a datapath of the configurable computing circuit; and using a second instruction and instruction index memory, providing a plurality of spoke instructions and datapath configuration instruction indexes for selection of a current datapath configuration instruction of the configurable computing circuit.

[0071] In any of the various representative embodiments, a method for configuring a configurable circuit may include: using a first instruction memory, providing a plurality of datapath configuration instructions for configuring a datapath of the configurable computing circuit; using a second instruction and instruction index memory, providing a plurality of spoke instructions and datapath configuration instruction indexes for selecting a next datapath configuration instruction for a next configurable computing circuit.

[0072] A method of controlling thread execution of a multithreaded configurable circuit is also disclosed, wherein the configurable circuit has a configurable computation circuit. A representative method embodiment may include: using a conditional logic circuit to provide a conditional branch by modifying the next data path instruction or the next data path instruction index provided to the next configurable circuit, depending on an output from the configurable computation circuit.

[0073] Another representative method embodiment of controlling thread execution of a multi-threaded configurable circuit may include generating, using a flow control circuit, a stall signal when a predetermined threshold has been reached in an asynchronous network output queue.

[0074] Another representative method embodiment of controlling thread execution of a multithreaded configurable circuit may include using a plurality of control registers to store a loop table having a plurality of thread identifiers and, for each thread identifier, a next thread identifier for execution after execution of a current thread to provide in-order thread execution.

[0075] Another representative method embodiment of controlling thread execution of a multi-threaded configurable circuit may include: using a plurality of control registers to store a completion table having a first data completion count; and using the thread control circuit, queuing a thread for execution when its completion count for its thread identifier has been decremented to zero.

[0076] A method of configuring and controlling thread execution of a multithreaded configurable circuit having a configurable computing circuit is disclosed, wherein a representative method embodiment includes: using a first instruction memory, providing a plurality of data paths using configuration instructions for configuring the data paths of the configurable computing circuit; using a second instruction and instruction index memory, providing a plurality of spoke instructions and data path configuration instruction indexes for selection of a master synchronization input among a plurality of synchronization network inputs, selection of a current data path configuration instruction for the configurable computing circuit, and selection of a next data path instruction or a next data path instruction index for a next configurable computing circuit; using a plurality of control registers, providing a completion table having a first data completion count; and using a thread control circuit, queuing a thread for execution when its completion count has been decremented to zero for its thread identifier.

[0077] Another method of configuring and controlling thread execution of a multi-threaded configurable circuit may include: using a first instruction memory, providing a plurality of data paths using configuration instructions for configuring the data paths of the configurable computing circuit; using a second instruction and instruction index memory, providing a plurality of spoke instructions and data path configuration instruction indexes for selection of a master synchronization input among a plurality of synchronization network inputs, selection of a current data path configuration instruction for the configurable computing circuit, and selection of a next data path instruction or a next data path instruction index for a next configurable computing circuit; using a plurality of control registers, providing a completion table having a first data completion count; and using a thread control circuit, queuing a thread for execution when its completion count has been decremented to zero for its thread identifier and its thread identifier is the next thread.

[0078] Another method of controlling thread execution of a multi-threaded configurable circuit may include: using a plurality of control registers, storing a completion table having a plurality of types of thread identifiers, wherein each type of thread identifier indicates a loop stage for loop and nested loop execution, and wherein the plurality of control registers further store a top of a thread identifier stack; and allowing each type of thread identifier to access private variables of a selected loop.

[0079] Another method of controlling thread execution of a multi-threaded configurable circuit may include: using multiple control registers to store a completion table with data completion counts; using thread control circuitry to provide a continuation queue that stores one or more thread identifiers of computing threads that have completion counts that allow execution but do not yet have assigned thread identifiers; and using thread control circuitry to provide a re-entry queue that stores one or more thread identifiers of computing threads that have completion counts that allow execution and have assigned thread identifiers to provide execution of the threads in the re-entry queue after a specified spoke count.

[0080] Another method of controlling thread execution of a multi-threaded configurable circuit may include: using multiple control registers to store a thread identifier pool and a completion table having loop counts of a valid number of loop threads; and using thread control circuitry to decrement the loop count in response to receipt of an asynchronous architecture message that returns a thread identifier to the thread identifier pool, and transmitting an asynchronous architecture completion message when the loop count reaches zero.

[0081] In any of the various representative embodiments, the method may further include providing, using the second instruction and instruction index memory, a plurality of spoke instructions and datapath configuration instruction indexes for selection of a current datapath configuration instruction for the configurable computing circuit.

[0082] In any of the various representative embodiments, the method may further include providing, using the second instruction and instruction index memory, a plurality of spoke instructions and datapath configuration instruction indexes for selection of a next datapath configuration instruction for a next configurable computing circuit.

[0083] In any of the various representative embodiments, the method may further include providing, using the second instruction and instruction index memory, a plurality of spoke instructions and datapath configuration instruction indexes for selection of a synchronous network output of the plurality of synchronous network outputs.

[0084] In any of the various representative embodiments, the method may further include: using a configuration memory multiplexer, providing a first selection setting to select a current datapath configuration instruction using an instruction index from the second instruction and instruction index memory.

[0085] In any of the various representative embodiments, the method may further include using a configuration memory multiplexer to provide a second selection setting to select a current datapath configuration instruction using an instruction index from a master synchronization input, the second setting being different from the first setting.

[0086] In any of the various representative embodiments, the method may further include: using the second instruction and instruction index memory, providing a plurality of spoke instructions and datapath configuration instruction indexes for configuring portions of the configurable circuitry independently of the current datapath instruction.

[0087] In any of the various representative embodiments, the method may further include selecting, using a configuration memory multiplexer, a spoke instruction and datapath configuration instruction index of the plurality of spoke instructions and datapath configuration instruction indexes according to a modulo spoke count.

[0088] In any of the various representative embodiments, the method may further include modifying a next data path instruction or a next data path instruction index using a conditional logic circuit and depending on an output from the configurable computation circuit.

[0089] In any of the various representative embodiments, the method may further include providing conditional branching by modifying a next data path instruction or a next data path instruction index using conditional logic circuitry and depending on an output from the configurable computation circuitry.

[0090] In any of the various representative embodiments, the method may further include: enabling a conditional logic circuit; and using the conditional logic circuit and depending on the output from the configurable computation circuit, providing a conditional branch by ORing the least significant bits of the next data path instruction with the output from the configurable computation circuit to specify a next data path instruction or a data path instruction index.

[0091] In any of the various representative embodiments, the method may further include: selecting a master synchronization input using an input multiplexer. In any of the various representative embodiments, the method may further include: selecting an output from the configurable computing circuit using an output multiplexer.

[0092] In any of the various representative embodiments, the method may further include: using an asynchronous fabric state machine coupled to an asynchronous network input queue and an asynchronous network output queue, decoding input data packets received from the asynchronous packet network and assembling output data packets for transmission on the asynchronous packet network.

[0093] In any of the various representative embodiments, the method may further include providing, using the synchronization network, a plurality of direct point-to-point connections coupling adjacent configurable circuits of the array of the plurality of configurable circuits.

[0094] In any of the various representative embodiments, the method may further include: providing a direct transfer connection between a plurality of input registers and a plurality of output registers using the configurable circuit. In any of the various representative embodiments, the direct transfer connection provides a direct point-to-point connection for data transmission from a second configurable circuit received on the synchronous network to a third configurable circuit transmitted on the synchronous network.

[0095] In any of the various representative embodiments, the method may further include: using the configurable computing circuit, performing at least one integer or floating-point operation selected from the group consisting of: signed and unsigned addition, absolute value, negation, logical NOT, addition and negation, subtraction AB, reverse subtraction BA, signed and unsigned greater than, signed and unsigned greater than or equal to, signed and unsigned less than, signed and unsigned less than or equal to, comparison of equal or not equal to, logical AND operation, logical OR operation, logical XOR operation, logical NAND operation, logical NOR operation, logical NOT XOR operation, logical AND NOT operation, logical OR NOT operation and conversion between integer and floating point.

[0096] In any of the various representative embodiments, the method may further include: using the configurable computing circuit, performing at least one integer or floating point operation selected from the group consisting of: multiplication, shift, pass input, signed and unsigned multiplication, signed and unsigned right shift, signed and unsigned left shift, bit order reversal, permutation, conversion between integer and floating point, and combinations thereof.

[0097] In any of the various representative embodiments, the method may further include: using a dispatch interface circuit, receiving a work descriptor packet through the first interconnect network, and in response to the work descriptor packet, generating one or more data and control packets to the plurality of configurable circuits to configure the plurality of configurable circuits for performance of the selected computation.

[0098] In any of the various representative embodiments, the method may further include: using the flow control circuit to generate a stop signal when a predetermined threshold has been reached in the asynchronous network output queue. In any of the various representative embodiments, in response to the stop signal, each asynchronous network output queue stops outputting data packets on the asynchronous packet network. In any of the various representative embodiments, in response to the stop signal, each configurable computing circuit stops executing after its current execution is completed.

[0099] In any of the various representative embodiments, the method may further include: coupling a first plurality of configurable circuits of an array of a plurality of configurable circuits through the synchronization network in a first predetermined order to form a first synchronization domain; and coupling a second plurality of configurable circuits of an array of a plurality of configurable circuits through the synchronization network in a second predetermined order to form a second synchronization domain.

[0100] In any of the various representative embodiments, the method may further include generating a connection message from the first synchronization domain to the second synchronization domain for transmission over an asynchronous packet network.

[0101] In any of the various representative embodiments, the method may further include: generating a completion message from the second synchronization domain to the first synchronization domain for transmission over an asynchronous packet network. In any of the various representative embodiments, the method may further include storing a completion table with a first data completion count in the plurality of control registers.

[0102] In any of the various representative embodiments, the method may further include storing a completion table having a second iteration count in the plurality of control registers.

[0103] In any of the various representative embodiments, the method may further include: storing a loop table having a plurality of thread identifiers in the plurality of control registers; and for each thread identifier, storing a next thread identifier to execute after the current thread executes.

[0104] In any of the various representative embodiments, the method may further include storing an identification of a first iteration and an identification of a last iteration in a loop table in the plurality of control registers.

[0105] In any of the various representative embodiments, the method may further include, using the control circuitry, queuing a thread for execution when its completion count for its thread identifier has been decremented to zero.

[0106] In any of the various representative embodiments, the method may further include, using the control circuitry, queuing the thread for execution when its completion count has been decremented to zero for its thread identifier and its thread identifier is the next thread.

[0107] In any of the various representative embodiments, the method may further include: using the control circuitry, queuing a thread for execution when its completion count for its thread identifier indicates completion of any data dependencies. In any of the various representative embodiments, the completion count may indicate a predetermined number of completion messages to be received for each selected thread of the plurality of threads before the selected thread executes.

[0108] In any of the various representative embodiments, the method may further include storing a completion table having a plurality of types of thread identifiers in the plurality of control registers, wherein each type of thread identifier indicates a loop stage for loop and nested loop execution.

[0109] In any of the various representative embodiments, the method may further include storing a completion table having a loop count of a valid number of loop threads in the plurality of control registers, and wherein in response to receipt of an asynchronous architecture message that returns a thread identifier to a thread identifier pool, decrementing the loop count using the control circuit, and transmitting an asynchronous architecture completion message when the loop count reaches zero.

[0110] In any of the various representative embodiments, the method may further include storing a top of a thread identifier stack in the plurality of control registers to allow each type of thread identifier to access private variables of the selected loop.

[0111] In any of the various representative embodiments, the method may further include: using a continuation queue, storing one or more thread identifiers of computing threads that have completion counts that allow execution but do not yet have assigned thread identifiers.

[0112] In any of the various representative embodiments, the method may further include: using a reentrant queue, storing one or more thread identifiers of computing threads having completion counts allowed to execute and having assigned thread identifiers.

[0113] In any of the various representative embodiments, the method may further include executing any thread having a thread identifier in the reentry queue prior to execution of any thread having a thread identifier in the continuation queue.

[0114] In any of the various representative embodiments, the method may further include executing any thread having a thread identifier in a priority queue before execution of any thread having a thread identifier in the continuation queue or the reentry queue.

[0115] In any of the various representative embodiments, the method may further include executing any thread in the run queue upon occurrence of the spoke count for the thread identifier.

[0116] In any of the various representative embodiments, the method may further include: using the control circuit to self-scheduling the computing thread for execution.

[0117] In any of the various representative embodiments, the method may further include: using the conditional logic circuit, branching to a different second next instruction to be executed by the next configurable circuit.

[0118] In any of the various representative embodiments, the method may further include ordering computing threads for execution using the control circuitry.

[0119] In any of the various representative embodiments, the method may further include ordering, using the control circuit, the loop computation threads for execution.

[0120] In any of the various representative embodiments, the method may further include, using the control circuitry, starting execution of the computing thread in response to one or more completion signals from the data dependencies.

[0121] Numerous other advantages and features of the present invention will be readily apparent from the following detailed description of the invention and its embodiments, from the claims and from the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0122] Objects, features, and advantages of the present invention will be more readily understood after reference to the following disclosure when considered in conjunction with the accompanying drawings, wherein like reference numerals are used to identify identical components in the various figures, and wherein reference numerals with alphabetical characters are used to identify additional types, instantiations, or variations of selected component embodiments in the various figures, wherein:

[0123] FIG. 1 is a block diagram of a representative first embodiment of a hybrid computing system.

[0124] Figure 2 is a block diagram of a representative second embodiment of a hybrid computing system.

[0125] Figure 3 is a block diagram of a representative third embodiment of a hybrid computing system.

[0126] Figure 4 is a block diagram of a representative embodiment of a hybrid threading architecture having configurable computing circuitry coupled to a first interconnect network.

[0127] Figure 5 A high-level block diagram of a portion of a representative embodiment of a hybrid threading architecture circuit cluster.

[0128] Figure 6 is a high-level block diagram of a second interconnect network within a hybrid threading architecture circuit cluster.

[0129] Figure 7 is a detailed block diagram of a representative embodiment of a hybrid threading architecture circuit cluster.

[0130] Figure 8 is a detailed block diagram of a representative embodiment of a hybrid thread architecture configurable computing circuit (block).

[0131] Fig. 9 , 9A and 9B (of which Fig. 9 Divided into Fig. 9A and 9B (collectively referred to as Fig. 9 )) are collectively detailed block diagrams of representative embodiments of hybrid thread architecture configurable computing circuits (blocks).

[0132] Fig.10 is a detailed block diagram of a representative embodiment of a memory control circuit for a hybrid threaded architecture configurable computing circuit (tile).

[0133] Fig.11 is a detailed block diagram of a representative embodiment of a thread control circuit for a hybrid threaded architecture configurable computing circuit (tile).

[0134] Fig.12 is a diagram of representative hybrid threaded architecture configurable computing circuits (tiles) forming a synchronization domain and representative asynchronous packet network messaging.

[0135] Fig.13 is a block diagram of a representative embodiment of a memory interface.

[0136] Fig.14 is a block diagram of a representative embodiment of a dispatch interface.

[0137] Fig.15 is a block diagram of a representative embodiment of an optional first network interface.

[0138] Fig.16 is a diagram of representative hybrid threaded architecture configurable computing circuits (tiles) forming a synchronization domain and representative asynchronous packet network messaging for performing computations by a cluster of hybrid threaded architecture circuits.

[0139] Fig.17A , 17B and 17C (collectively referred to as FIG. 17 ) are for use by a hybrid thread architecture circuit cluster to execute Fig.16 Flowchart of representative asynchronous packet network messaging and execution of computations performed by a hybrid threaded architecture configurable computing circuit (tile).

[0140] Fig.18 is a diagram of representative hybrid threaded architecture configurable computing circuits (tiles) forming a synchronization domain and representative asynchronous packet network messaging for performing computations by a cluster of hybrid threaded architecture circuits.

[0141] Fig.19A and 19B (collectively referred to as FIG. 19 ) is for use by a hybrid thread architecture circuit cluster to execute Fig.18 Flowchart of representative asynchronous packet network messaging and execution of computations performed by a hybrid threaded architecture configurable computing circuit (tile).

[0142] Fig. 20A diagram of a representative hybrid threaded architecture configurable computing circuit (block) forming a synchronization domain and a representative asynchronous packet network message passing for executing loops in a computation by a cluster of hybrid threaded architecture circuits

[0143] Fig.21 is used by the hybrid thread architecture circuit cluster in Fig. 20 Flowchart of representative asynchronous packet network message passing and execution of a computational loop by a hybrid threaded architecture configurable computing circuit (block).

[0144] Fig. 22 is a block diagram of a representative flow control circuit.

[0145] Fig.23 is a diagram of representative hybrid threaded architecture configurable computing circuits (tiles) forming a synchronization domain and representative asynchronous packet network messaging and synchronization messaging for executing loops in a computation by a cluster of hybrid threaded architecture circuits.

[0146] Fig.24 is a block diagram and circuit diagram of a representative embodiment of a conditional branching circuit system. DETAILED DESCRIPTION

[0147] Although the present invention may have embodiments in many different forms, specific exemplary embodiments of the present invention are shown in the figures and will be described in detail herein, it should be understood that the present invention should be regarded as an example of the principles of the present invention and it is not desired to limit the present invention to the specific embodiments described. In this regard, before explaining in detail at least one embodiment consistent with the present invention, it should be understood that the present invention is not limited to the construction details and component arrangements stated above and below, illustrated in the figures, or as described in the examples in its application. Methods and devices consistent with the present invention can have other embodiments and can be practiced and implemented in various ways. Moreover, it should be understood that the wording and terminology used in the abstract description herein and contained below are for descriptive purposes and should not be considered to be limiting.

[0148] Figure 1 , 2 3 are block diagrams of representative first, second, and third embodiments of hybrid computing systems 100A, 100B, 100C (collectively referred to as system 100). Figure 4 is a block diagram of a representative embodiment of a hybrid threading architecture (“HTF”) 200 having configurable computing circuitry coupled to a first interconnect network 150 . Figure 5 A high-level block diagram of a portion of a representative embodiment of a hybrid thread architecture cluster 205 . Figure 6 is a high-level block diagram of a second interconnect network within the hybrid thread architecture cluster 205 . Figure 7 is a detailed block diagram of a representative embodiment of a hybrid threading architecture (HTF) cluster 205 .

[0149] Figure 8 is a high-level block diagram of a representative embodiment of a hybrid threaded architecture configurable computing circuit 210 referred to as a “tile” 210 . Fig. 9 , 9A and 9B (of which Fig. 9 Divided into Fig. 9A and 9B (collectively referred to as Fig. 9 )) are collectively a detailed block diagram of a representative embodiment of a hybrid thread architecture configurable computing circuit 210A referred to as a "tile" 210A (as a specific representative instantiation of the tile 210). Unless explicitly referred to as the tile 210A, references to the tile 210 shall represent and refer to the tile 210 and the tile 210A individually and collectively. The hybrid thread architecture configurable computing circuit 210 is referred to as a "tile" 210 because in a representative embodiment all such hybrid thread architecture configurable computing circuits 210 are identical to each other and can be arranged and connected in any order, i.e., each hybrid thread architecture configurable computing circuit 210 can be "tiled" to form a hybrid thread architecture cluster 205.

[0150] refer to Figures 1 to 9 , the hybrid computing system 100 includes a hybrid thread processor ("HTP") 300 coupled to one or more hybrid thread fabric ("HTF") circuits 200 via a first interconnect network 150. It should be understood that the term "fabric" as used herein means and includes an array of computing circuits, which in this case are reconfigurable computing circuits. Figure 1 , 2 3 show different system 100A, 100B, and 100C arrangements, including additional components forming relatively larger and smaller systems 100, any and all of which are within the scope of the present invention. Figure 1 and 2 , by way of example and without limitation, the hybrid computing systems 100A, 100B may also optionally include a memory controller 120 that may be coupled to a memory 125 (which may also be a separate integrated circuit), any of the various communication interfaces 130 (e.g., a PCIe communication interface), one or more host processors 110, and a host interface ("HIF") 115 in the various combinations described. Each of the arrangements may be suitable for a "chiplet" configuration on a common substrate 101. Figure 3As shown in , by way of example and without limitation, hybrid computing system 100C may also optionally include communication interface 130, with or without these other components. Any and all of these arrangements are within the scope of the present invention and are collectively referred to herein as system 100. Any of these hybrid computing systems 100 may also be considered a "node" operating under a single operating system ("OS"), and likewise may also be coupled to other such local and remote nodes.

[0151] As used herein, hybrid threading refers to the ability to derive multiple computational fibers and threads across different heterogeneous types of processing circuits (hardware), such as across HTF circuits 200 (as a reconfigurable computing architecture) and across processors, such as RISC-V processors. Hybrid threading also refers to a programming language / style in which worker threads transition from one computational element to the next to move computations to where data is located, which is also implemented in a representative embodiment. Moreover, in a representative embodiment, HTP 300 is a multi-threaded processor based on RISC-V ISA. HTP 300 provides barrel-style loop instantaneous thread switching to maintain a higher per-clock instruction rate. Host processor 110 is typically a multi-core processor that may be embedded within hybrid computing system 100, or it may be an external host processor coupled to hybrid computing system 100 via communication interface 130 (e.g., a PCIe-based interface). These processors, such as HTP 300 and one or more host processors 110, are described in more detail below.

[0152] The memory controller 120 may be implemented as is or becomes known in the electronic arts. Alternatively, in a representative embodiment, the memory controller 120 may be implemented as described in the related applications. The memory 125 may also be implemented as is or becomes known in the electronic arts, and as described in more detail below.

[0153] For purposes herein, the HIF 115 provides the host processor 110 to send work to the HTP 300 and HTF circuit 200, and provides the HTP 300 to send work to the HTF circuit 200, both as work descriptor packets transmitted over the first interconnect network 150. The HIF 115 includes a dispatch circuit and queue (referred to as a "dispatch queue" 105 for short), which also provides management functionality for monitoring the load provided to the HTF circuit 200 and / or HTP 300 and the availability of resources for the HTF circuit 200 and / or HTP 300. When resources are available on the HTF circuit 200 and / or HTP 300, the dispatch queue 105 determines the least loaded HTF circuit 200 and / or HTP 300. In the case of multiple HTF circuit clusters 205 with the same or similar work load, it selects the HTF circuit cluster 205 that is currently executing the same kernel, if possible (to avoid having to load or reload the kernel configuration). Similar functionality of HIF 115 may also be included in HTP 300, for example, particularly for arrangements of system 100 that may not include a separate HIF 115. Other HIF 115 functions are described in more detail below. HIF 115 may be implemented as is or becomes known in the electronics art, for example, as one or more state machines with registers (forming FIFOs, queues, etc.).

[0154] The first interconnection network 150 is a packet-based communication network that provides data packet routing between and among the HTF circuit 200, the hybrid thread processor 300, and other optional components such as the memory controller 120, the communication interface 130, and the host processor 110. Depending on the embodiment of the system 100, the first interconnection network 150 is typically embodied as a plurality of crossbar switches having a folded Claus configuration and typically having a mesh network for additional connections. For purposes of the present invention, the first interconnection network 150 forms part of an asynchronous switching architecture ("AF"), meaning that data packets may be routed along any of a variety of paths such that, depending on the routing, the arrival of any selected data packet at an addressed destination may occur at any of a number of different times. This is in contrast to the synchronous mesh communication network 275 of the second interconnection network 250 discussed in more detail below.

[0155] The HTF circuit 200 typically includes a plurality of HTF circuit clusters 205, each of which is coupled to a first interconnection network 150 for data packet communication. Each HTF circuit cluster 205 can operate independently of each of the other HTF circuit clusters 205. Each HTF circuit cluster 205 includes an array of a plurality of HTF reconfigurable computing circuits 210, equivalently referred to herein as "tiles" 210, and a second interconnection network 250. The tiles 210 are embedded in or otherwise coupled to the second interconnection network 250, which includes two different types of networks discussed in more detail below. In a representative embodiment, each HTF circuit cluster 205 also includes a memory interface 215, an optional first network interface 220 (which provides an interface for coupling to the first interconnection network 150), and a dispatch interface 225. The various memory interfaces 215, dispatch interface 225, and optional first network interface 220 may be implemented using any suitable circuitry, such as one or more state machine circuits, to perform the functionality specified in more detail below.

[0156] As an overview, the HTF circuit 200 is a coarse-grained reconfigurable computing architecture composed of interconnected computing tiles 210. The tiles 210 are interconnected with a synchronization architecture called a synchronous mesh communication network 275, allowing data to traverse from one tile 210 to another tile 210 without queuing. This synchronous mesh communication network 275 allows many tiles 210 to be pipelined together to produce a continuous data flow through arithmetic operations, and each such pipeline of tiles 210 connected by the synchronous mesh communication network 275 for executing one or more computing threads is referred to herein as a "synchronization domain", which can have serial connections, parallel connections, and potentially also branch connections. The first tile 210 of a synchronization domain is referred to herein as a "base" tile 210.

[0157] The tiles 210 are also interconnected with an asynchronous architecture called an asynchronous packet network 265 that allows synchronous domains of computation to be bridged by asynchronous operations, where in a representative embodiment all packets on the asynchronous packet network 265 can be transferred in a single clock cycle. These asynchronous operations include initiating synchronous domain operations, transferring data from one synchronous domain to another, accessing the system memory 125 (reading and writing), and performing branch and loop constructs. The synchronous architecture together with the asynchronous architecture allows the tiles 210 to efficiently execute high-level language constructs. The asynchronous packet network 265 differs from the first interconnect network 150 in many ways, including, by way of example and without limitation, requiring less addressing, being single-channel, queuing under depth-based backpressure, and utilizing packed data operands (e.g., having a 128-bit data path). It should be noted that, also by way of example and without limitation, the internal data path of each tile 210 is also 128 bits. By way of example and without limitation, in Fig.16, 18 20 illustrates an example of synchronization domains and an example of synchronization domains communicating with each other through an asynchronous packet network 265.

[0158] In a representative embodiment, in most cases, thread (e.g., kernel) execution and control signaling are separated between these two different networks, where thread execution occurs using the synchronous mesh communication network 275 to form multiple synchronization domains for each tile 210, and control signaling occurs using message passing packets transmitted between and among the various tiles 210 through the asynchronous packet network 265. For example, the plurality of configurable circuits are adapted to perform a plurality of computations using the synchronous mesh communication network 275 to form a plurality of synchronization domains, and the plurality of configurable circuits are further adapted to generate and transmit a plurality of control messages through the asynchronous packet network 265, for example and without limitation, where the plurality of control messages include one or more completion messages and continue messages.

[0159] In a representative embodiment, the second interconnection network 250 generally includes two different types of networks, each of which provides data communication between and among the tiles 210, a first asynchronous packet network 265 superimposed or combined with a second synchronous mesh communication network 275, such as Figure 6 and 7 . The asynchronous packet network 265 is comprised of a plurality of AF switches 260, which are typically implemented as crossbar switches (which may or may not additionally or optionally have a Claus or Folded Claus configuration, by way of example and without limitation); and a plurality of communication lines (or wires) 280, 285, which connect the AF switches 260 to the tiles 210, providing data packet communications between and among the tiles 210 and other described components discussed below. The synchronous mesh communication network 275 provides a plurality of direct (i.e., unswitched point-to-point) connections between and among the tiles 210 via communication lines (or wires) 270, which may be register-staged at the inputs and outputs of the tiles 210, but otherwise do not require queuing between the tiles 210 and do not require the formation of data packets. (In Figure 6 In order to better illustrate the superposition of the two networks with the block 210 embedded in the second interconnect network 250, the block 210 is represented as a vertex of the synchronous mesh communication network 275, and the AF switch 260 is illustrated as an "X", as indicated.)

[0160] refer to Figure 8, block 210 includes one or more configurable computing circuits 155, control circuit system 145, one or more memories 325, configuration memory (e.g., RAM) 160, synchronous network input 135 (which is coupled to synchronous mesh communication network 275), synchronous network output 170 (which is also coupled to synchronous mesh communication network 275), asynchronous (packet) network input 140 (which is coupled to asynchronous packet network 265), and asynchronous (packet) network output 165 (also coupled to asynchronous packet network 265). Each of these various components is shown coupled to each other by buses 180, 185 in the various combinations illustrated. Those skilled in the art of electronics will recognize that fewer or more components and any of the various coupling combinations may be included in block 210, any and all of which are considered equivalent and within the scope of the present invention.

[0161] References below Fig. 9 Representative examples of each of these various components are illustrated and discussed. For example, in a representative embodiment, one or more configurable computation circuits 155 are embodied as multiplication and shift operation circuits ("MS Op") 305 and arithmetic logic and bitwise operation circuits ("ALB Op") 310, for example and without limitation, with associated configuration capabilities (e.g., through intermediate multiplexers 365) and associated registers (e.g., registers 312). Also, in a representative embodiment, also for example and without limitation, one or more configurable computation circuits 155 may include a write mask generator 375 and conditional (branch) logic circuitry 370. Also in a representative embodiment, for example and without limitation, control circuitry 145 may include memory control circuitry 330, thread control circuitry 335, and control registers 340, such as those elements illustrated for block 210A. Continuing with the example, the synchronous network input 135 may consist of an input register 350 and an input multiplexer 355, the synchronous network output 170 may consist of an output register 380 and an output multiplexer 395, the asynchronous (packet) network input 140 may consist of an AF input queue 360, and the asynchronous (packet) network output 165 may consist of an AF output queue 390 and may also include or share an AF message state machine 345.

[0162] Notably, and as discussed in more detail below, the configuration memory (e.g., RAM) 160 is comprised of configuration circuitry (e.g., configuration memory multiplexer 372) and two different configuration memories that perform different configuration functions: a first instruction RAM 315 (which is used to configure the internal data paths of tile 210) and a second instruction (and index) RAM 320, referred to herein as the “spoke” RAM 320 (which is used for a variety of purposes, including, among other things, configuring portions of tile 210 that are independent of the current instruction, selecting the current instruction and instruction for the next tile 210, and selecting a master synchronization input, all as discussed in more detail below).

[0163] like Figure 8 and Fig. 9 3, the communication lines (or wires) 270 are illustrated as communication lines (or wires) 270A and 270B, such that communication line (or wire) 270A is the "input" (input communication line (or wire)) that feeds data into input register 350, and communication line (or wire) 270B is the "output" (output communication line (or wire)) that moves data from output register 380. In a representative embodiment, there are multiple sets or buses of communication lines (or wires) 270 to and from each tile 210, to and from each adjacent tile (e.g., the uplink, downlink, left link, and right link of the synchronous mesh communication network 275), and to and from other components for distribution of various signals (e.g., data write masks, stop signals, and instructions or instruction indexes provided from one tile 210 to another tile 210), as discussed in more detail below. Alternatively, and not separately illustrated, there may also be various dedicated communication lines, such as for asserting a stop signal, so that a stop signal generated from any tile 210 in the HTF circuit cluster 205 can be quickly received by all other tiles 210 in the HTF circuit cluster 205 within a limited number of clock cycles.

[0164] It should be noted that there are various fields in each set or bus of communication lines that form the synchronous mesh communication network 275. For example, Figure 8 and Fig. 9 Four buses are illustrated for incoming and outgoing communication lines (or wires) 270A and 270B, respectively. Each of the sets of these communication lines (or wires) 270A and 270B may carry different information, such as data, instruction index, control information, and thread information (such as TID, XID, loop dependency information, write mask bits for selecting valid bits, etc.). One of the inputs may also be labeled as a master synchronization input, including an input internal to the tile 210 (feedback from the output), which may be different for each time slice of the tile 210, for example and without limitation, which may have data for the instruction index of that tile 210 for the synchronization domain, discussed in more detail below.

[0165] Additionally, as discussed in more detail below, for any input received on the synchronous mesh communication network 275 and held in one or more input registers 350 (of the synchronous network input 135), each tile 210 may communicate the input directly to one or more output registers 380 (of the synchronous network output 170) for output (typically on a single clock cycle) to another location on the synchronous mesh communication network 275, thereby allowing a first tile 210 to communicate with any other third tile 210 within the HTF circuit cluster 205 via one or more intermediate second tiles 210. This synchronous mesh communication network 275 enables configuration (and reconfiguration) of statically scheduled synchronous pipelines between and among tiles 210 so that once a thread is initiated along a selected data path between and among tiles 210 (as a synchronization domain), completion of data processing will occur within a fixed period of time. Additionally, the synchronous mesh communication network 275 is used to minimize the number of any required accesses to the memory 125 , since accesses to the memory 125 may not be required to complete computations for the threads executing along the selected data paths between and among the tiles 210 .

[0166] In the asynchronous packet network 265, each AF switch 260 is typically coupled to a plurality of tiles 210 and one or more other AF switches 260 via a communication line (or wire) 280. In addition, one or more selected AF switches 260 are also coupled to one or more of a memory interface 215, an optional first network interface 220, and a dispatch interface 225 (via a communication line (or wire) 285). As illustrated, as an example and without limitation, the HTF circuit cluster 205 includes a single dispatch interface 225, two memory interfaces 215, and two optional first network interfaces 220. Also as illustrated, as an example and without limitation, in addition to being coupled to the other AF switches 260, one of the AF switches 260 is further coupled to a memory interface 215, an optional first network interface 220, and a dispatch interface 225, while another of the AF switches 260 is further coupled to a memory interface 215 and an optional first network interface 220.

[0167] Depending on the selected embodiment, each of the memory interface 215 and the dispatch interface 225 may also be directly connected to the first interconnection network 150, have the ability to receive, generate, and transmit data packets through both the first interconnection network 150 and the asynchronous packet network 265, and the first network interface 220 is not used or included in the HTF circuit cluster 205. For example, the dispatch interface 225 may be used by any of the various tiles 210 to transmit data packets to and from the first interconnection network 150. In other embodiments, any of the memory interface 215 and the dispatch interface 225 may utilize the first network interface 220 to receive, generate, and transmit data packets through the first interconnection network 150, such as using the first network interface 220 to provide additional addressing required by the first interconnection network 150.

[0168] Those skilled in the art of electronics will recognize that the connections between and among the AF switch 260, tile 210, optional first network interface 220, memory interface 215, and dispatch interface 225 can occur with any selected number of components and with any selected combination of any selection of all such components and combinations that are considered equivalent and within the scope of the present invention. Those skilled in the art of electronics will recognize that the division of the HTF circuit 200 into multiple HTF clusters 205 is not required and that the conceptual division is only provided to facilitate the description of the various components and the connections between and among the various components. For example, although the HTF circuit cluster 205 is illustrated as having 16 tiles 210, having 4 AF switches 260, a single dispatch interface 225, 2 memory interfaces 215, and 2 first network interfaces 220 (optional), more or less of any of these components may be included in either or both of the HTF circuit cluster 205 or the HTF circuit 200, and as described in more detail below, for any selected embodiment, the HTF circuit cluster 205 may be partitioned to change the number and type of components that may be active (e.g., powered on and functioning) at any selected time.

[0169] The synchronous mesh communication network 275 allows multiple tiles 210 to be pipelined without the need for data queuing. All tiles 210 participating in the synchronization domain are used as a single pipelined data path. The first tile in this sequence of tiles 210 that forms a single pipelined data path is referred to herein as the "base" tile 210 of the synchronization domain, and this base tile 210 starts the work thread through the pipelined tile 210. The base tile 210 is responsible for starting work at a predefined rhythm, referred to herein as the "spoke count". As an example, if the spoke count is 3, then the base tile 210 can start work every three clocks. It should also be noted that the calculations within each tile 210 can also be pipelined so that parts of different instructions can be executed while other instructions are being executed, such as inputting data for the next operation while the current operation is being executed.

[0170] Each of the tiles 210, memory interfaces 215, and dispatch interface 225 has a distinct or unique address (e.g., as a 5-bit wide endpoint ID) as a destination or endpoint within any selected HTF circuit cluster 205. For example, tile 210 may have endpoint IDs 0-15, memory interfaces 215 (0 and 1) may have endpoint IDs 20 and 21, and dispatch interface 225 may have endpoint ID 18 (with no address provided to the optional first network interface 220 unless it is included in selected embodiments). Dispatch interface 225 receives data packets containing work to be performed by one or more of tiles 210, called work descriptor packets, which have been configured for various operations, as discussed in more detail below. The work descriptor packet will have one or more arguments, which the dispatch interface 225 will then provide or distribute to the various tiles as a packet or message (AF message) transmitted to the selected addressed tile 210 through the AF switch 260, and will further typically include an identification of the area in the tile memory 325 used to store the data (the arguments) and a thread identifier ("ID") for tracking and identifying the associated computation and its completion.

[0171] Messages are routed from source endpoints to destination endpoints through the asynchronous packet network 265. Messages from different sources to the same destination take different paths and may encounter different levels of congestion. Messages may arrive in a different order than when they were sent out. The message delivery mechanism is constructed to work properly with a non-deterministic arrival order.

[0172] Fig.13 is a block diagram of a representative embodiment of memory interface 215. Fig.13 , each memory interface 215 includes a state machine (and other logic circuitry) 480, one or more registers 485, and optionally one or more queues 474. The state machine 480 receives, generates, and transmits data packets on the asynchronous packet network 265 and the first interconnection network 150. The registers 485 store addressing information, such as the virtual address of the tile 210, the physical address within a given node, and various tables used to translate virtual addresses into physical addresses. The optional queues 474 store messages waiting to be transmitted on the first interconnection network 150 and / or the asynchronous packet network 265.

[0173] The memory interface 215 allows the tiles 210 within the HTF circuit cluster 205 to make requests to the system memory 125 (e.g., DRAM memory). The memory request types supported by the memory interface 215 are load, store, and atomic. From the perspective of the memory interface 215, a load sends an address to the memory 125 and the data is returned. A write sends both the address and data to the memory 125 and a completion message is returned. An atomic operation sends both the address and data to the memory 125 and the data is returned. It should be noted that atoms that only receive data from memory (i.e., extract and increment) will be handled by the memory interface 215 as load requests. All memory interface 215 operations require a single 64-bit virtual address. The data size for the operation can be changed from a single byte to 64 bytes. Larger data payload sizes are more efficient for the device and can be used; however, the data payload size will be governed by the ability of the high-level language compiler to detect access to large data blocks.

[0174] Fig.14 is a block diagram of a representative embodiment of the dispatch interface 225. Fig.14 , the dispatch interface 225 includes a state machine (and other logic circuitry) 470, one or more registers 475, and one or more dispatch queues 472. The state machine 470 receives, generates, and transmits data packets over the asynchronous packet network 265 and the first interconnect network 150. The registers 475 store addressing information, such as the virtual addresses of the tiles 210 and various tables that track the configuration and workload distributed to each tile, as discussed in more detail below. The dispatch queues 472 store messages waiting to be transmitted over the first interconnect network 150 and / or the asynchronous packet network 265.

[0175] As mentioned above, the dispatch interface 225 receives work descriptor call packets (messages) over the first interconnect network 150, for example, from the host interface 115. The work descriptor call packet will have various information, such as a payload (e.g., configuration, argument values, etc.), a call identifier (ID), and return information (e.g., for providing results to that endpoint). The dispatch interface 225 will create various AF data messages for transmission to the tile 210 over the asynchronous packet network 265, including writing data into the memory 325, which will be the base tile 210 (base tile ID, used for transmission of AF completion messages), the thread ID (thread identifier or "TID"), and sending continuation messages to the base tile 210 (e.g., with completion counts and other counts per TID) so that once the base tile 210 has received enough completion messages it can begin execution. The dispatch interface 225 maintains various tables in registers 475 that track what has been transmitted to which tile 210 per thread ID and XID. As results are generated or execution completes, the dispatch interface 225 will receive either an AF data message (indicating completion and with data) or an AF completion message (indicating completion but without data). The dispatch interface 225 also maintains (in registers 475) various counts of the number of completion and data messages it will need to receive to know that kernel execution has completed, and will then assemble and transmit the work descriptor return data packet with the resulting data, call ID, return message (e.g., address of the requester), and release TID over the first interconnect network 150. Additional features and functionality of the dispatch interface 225 are described in more detail below.

[0176] It should be noted that, as mentioned above, multiple layers (or types) of TIDs can be utilized and are typically utilized. For example, the dispatch interface 225 allocates a first type of TID from a TID pool, and the dispatch interface 225 will transmit the first type of TID to the base tile 210. For example and without limitation, the base tile 210 may in turn allocate additional TIDs (such as second and third types of TIDs), such as to track threads utilized in loops and nested loops. These different TIDs may then also be used to access variables that are private to a given loop. For example, a first type of TID may be used for an outer loop, and a second and third type of TID may be used to track iterations of a nested loop.

[0177] It should also be noted that separate transaction IDs are used to track the various memory requests through the first interconnect network 150 .

[0178] Fig.15 is a block diagram of a representative embodiment of an optional first network interface. Fig.15, when included, each memory interface 220 includes a state machine (and other logic circuitry) 490 and one or more registers 495. The state machine 490 receives, generates, and transmits data packets over the asynchronous packet network 265 and the first interconnect network 150. The registers 495 store addressing information, such as the virtual address of the tile 210, the physical address within a given node, and various tables used to translate virtual addresses into physical addresses.

[0179] Reference again Fig. 9 , the representative HTF reconfigurable computing circuit (tile) 210A includes at least one multiplication and shift operation circuit ("MS Op") 305, at least one arithmetic logic and bit operation circuit ("ALB Op") 310, a first instruction RAM 315, a second instruction (and index) RAM 320 referred to herein as a "spoke" RAM 320, one or more tile memory circuits (or memories) 325 (illustrated as memory "0" 325A, memory "1" 325B to memory "N" 325C, and individually and collectively referred to as memory 325 or tile memory 325). In addition, as previously mentioned, the representative tile 210A also typically includes input registers 350 and output registers 380 coupled to the asynchronous mesh communication network 275 through communication lines (or wires) 270A, 270B, and AF input queues 360 and AF output queues 390 coupled to the AF switch 260 through the communication lines (or wires) 280 of the asynchronous packet network 265. Control circuitry 145 is also typically included in block 210, such as memory control circuitry 330, thread control circuitry 335, and control registers 340 illustrated for block 210A. To decode and prepare (assemble) data packets received from or provided to asynchronous packet network 265, an AF message state machine 345 is also typically included in block 210. As part of the configurability of block 210, one or more multiplexers are typically included, illustrated as input multiplexer 355, output multiplexer 395, and one or more intermediate multiplexers 365 for selecting inputs to MS Op 305 and ALBOp 310. Optionally, other components may also be included in block 210, such as conditional (branch) logic circuitry 370, write mask generator 375, and flow control circuitry 385 (which is illustrated as being included as part of AF output queue 390, and which may equivalently be provided as a separate flow control circuit). The capabilities of MS Op 305 and ALB Op 310 are described in more detail below.

[0180] The synchronous mesh communication network 275 transmits the information required to make the synchronization domain function. The synchronous mesh communication network 275 includes the fields specified below. In addition, many parameters used in these fields are also stored in the control register 340 and assigned to the threads that will be executed in the synchronization domain formed by multiple tiles 210. The specified fields of the synchronous mesh communication network 275 include:

[0181] 1. Data, typically having a field width of 64 bits and comprising calculated data that is transferred from one tile 210 to the next tile 210 in the sync domain.

[0182] 2. Instruction RAM 315 address, referred to as "INSTR", typically has a field width of 8 bits and includes the instruction RAM 315 address of the next tile 210. The base tile 210 specifies the instruction RAM 315 address of the first tile 210 in the domain. Subsequent tiles 210 may pass the instructions through without modification, or may conditionally change the instructions for the next tile 210 to allow conditional execution (i.e., if-then-else or switch statements) as described in more detail below.

[0183] 3. A thread identifier, referred to herein as a "TID", typically has a field width of 8 bits and comprises a unique identifier for a thread of a kernel, of which a predetermined number of TIDs (the "TID pool") are stored in the control register 340 and potentially available for use by a thread (if not already ready for use by another thread). The TID is allocated at the base tile 210 of a sync domain and can be used as a read index into the tile memory 325. The TID can be passed from one sync domain to another over the asynchronous packet network 265. Because there is a finite number of available TIDs to perform other functions or calculations, eventually the TID should be released back to the TID pool of the allocated base tile for subsequent reuse. The release is accomplished using an asynchronous architecture message transmitted over the asynchronous packet network 265.

[0184] 4. A transfer identifier, referred to as an "XID", typically has a field width of 8 bits and comprises a unique identifier for transferring data from one synchronization domain to another, where a predetermined number of XIDs (the "XID pool") are stored in the control register 340 and potentially available for use by one thread (if not already ready for use by another thread). A transfer may be a direct data write from one domain to another, as an "XID_WR", or it may be the result of a memory 125 read (as an "XID_RD"), where the source domain sends a virtual address to the memory 125 and the destination domain receives the memory read data. The XID_WR is allocated at the base tile 210 of the source domain. The XID_WR in the source domain becomes the XID_RD in the destination domain. The XID_WR may be used as a write index to the tile memory 325 in the destination domain. The XID_RD is used as a tile memory 325 read index in the destination domain. Because there are a finite number of XIDs available for use, the final XID should be released back to the XID pool of the allocated base tile for subsequent reuse in order to perform other functions or calculations. The destination domain should release the XID by sending an asynchronous message to the base tile 210 of the source domain also over the asynchronous packet network 265 .

[0185] The asynchronous mesh communication network 275 provides both data and control information. The control information (INSTR, XID, TID) is used to set up the data path, and the DATA field can be selected as the source of the configured data path. Note that the control field is needed earlier (to configure the data path) than the data field. In order to minimize the synchronous domain pipeline delay through the tile 210, the control information arrives at the tile 210 a few clock cycles earlier than the data.

[0186] A particular inventive feature of the architecture of the HTF circuit 200 and its composite HTF circuit cluster 205 and its composite tile 210 is the use of two different configuration RAMs: an instruction RAM 315 for datapath configuration and a spoke RAM 320 for a number of other functions, including configuration of portions of the tile 210 independent of any selected or given datapath, selection of datapath instructions from the instruction RAM 315, selection of a master sync input (among available inputs) for each clock cycle, etc. As discussed in more detail below, this novel use of both the instruction RAM 315 and the independent spoke RAM 320 enables, among other things, dynamic self-configuration and self-reconfiguration of the HTF circuit cluster 205 and the HTF circuit 200 as a whole.

[0187] Each tile has an instruction RAM 315 containing configuration information used to set up the tile 210 data path for a particular operation, i.e., for example, data path instructions that determine whether a multiplication, shift, addition, etc. is to be performed in a given time slice of the tile 210 and with which data (e.g., data from memory 325 or data from input registers 350). The instruction RAM 315 has multiple entries that allow the tile 210 to be time sliced ​​to perform multiple different operations in the pipelined synchronization domain, where Fig. 9 210. Any given instruction may also specify which inputs will have data and / or control information to be utilized by the instruction. Additionally, each time slice may depend on a reference Fig.24 The previously discussed tile 210 time slice data dependency conditional operations conditionally execute different instructions. The number of entries within the instruction RAM 315 will typically be about 256. The number may change depending on experience gained from porting kernels to the HTF 200.

[0188] The support instruction set should match the needs of the target application, such as applications with data types of 32 and 64 bit integer and floating point values. Additional applications such as machine learning, image analysis, and 5G wireless processing can be executed using HTF 200. This entire set of applications will require 16, 32 and 64 bit floating point and 8, 16, 32 and 64 bit integer data types. The support instruction set needs to support these data types for load, store and arithmetic operations. The supported operations need to allow the compiler to efficiently map high-level language source to tile 210 instructions. In a representative embodiment, tile 210 supports the same instruction set as a standard high-performance processor, including single instruction multiple data (SIMD) instruction variants.

[0189] The spoke RAM 320 has multiple functions, and in a representative embodiment, one of the functions is to be used to configure a portion of the (time slice) of the tile 210 that is independent of the current instruction of the datapath, i.e., the tile 210 configuration maintained in the spoke RAM 320 can be used to configure the invariant portions of the configuration of the tile 210, such as those settings of the tile 210 that remain the same across different datapath instructions. For example, the spoke RAM 320 is used to specify which input of the tile 210 (e.g., one of the sets of input communication lines 270A or input registers 350) is the master sync input for each clock cycle as a selection control for the input multiplexer 355. This is important because the instruction index used to select the instruction for a given time slice of the tile 210 (from the instruction RAM 315) and the thread ID (TID) are provided on the master sync input. Thus, even the actual instruction index provided on the input to a given tile 210 may be variable (as referenced in the example of FIG. 1 ). Fig.24 Description), which set of inputs will have that selected instruction index will also not change, so that any given tile 210 knows in advance which input it will use to receive the selected instruction index independently of the instruction specified by that selected instruction index. The configuration maintained in the spoke RAM 320 also typically specifies which outputs 270B will be used for the selected instruction (or time slice). The spoke RAM 320 reads the address input (i.e., spoke index) from a counter that counts from zero (modulo) to the spoke count minus 1. All tiles 210 within the HTF circuit cluster 205 should typically have the same spoke RAM input value per clock to have proper synchronization domain operation. The spoke RAM 320 also stores the instruction index and is also used to select instructions from the instruction RAM 315, so that as the count of the spoke RAM 320 changes for the base tile 210 of the synchronization domain, a series of instructions can be selected for the tile 210 to execute. For subsequent tiles in the synchronization domain, the instruction index can be provided by the previous tile 210 of the synchronization domain. This aspect of the spoke RAM 320 also refers to Fig.24 This is discussed because the spoke RAM 320 is highly dense, thereby enabling dynamic self-configuration and reconfiguration of the HTF circuit cluster 205 .

[0190] The spoke RAM 320 also specifies when synchronous inputs are written to the tile memory 325. This situation may occur if a tile instruction requires multiple inputs and one of the inputs arrives early. The early arriving input may be written to the tile memory 325 and then read from the memory 325 later when the other inputs have arrived. For this situation, the tile memory 325 is accessed like a FIFO. The FIFO read and write pointers are stored in the tile memory area ram.

[0191] For example, each tile 210 contains one or more memories 325, and typically each is the width of the datapath (64 bits), and the depth will be in the range of 512 to 1024 elements. The tile memories 325 are used to store data needed to support datapath operations. The stored data may be constants loaded as part of the cluster 205 configuration of the kernel or variables calculated as part of the dataflow. The tile memories 325 may be written from the synchronous mesh communication network 275 as a result of a data transfer from another synchronization domain or a load operation initiated by another synchronization domain. Reading of the tile memories is performed only via synchronous datapath instructions.

[0192] The tile memory 325 is typically partitioned into multiple regions. The small tile memory region RAM stores the information required for memory region access. Each region represents a different variable in the kernel. The region can store shared variables (i.e., variables shared by all execution threads). Scalar shared variables have an index value of 0. The shared variable array has a variable index value. The region can store thread-private variables indexed by the TID identifier. Variables can be used to transfer data from one synchronization domain to the next synchronization domain. For this case, the variable is written using the XID_WR identifier in the source synchronization domain and read using the XIN_RD identifier in the destination domain. Finally, the region can be used to temporarily store data previously generated by the tile 210 in the synchronization data path until other tile data inputs are ready. For this case, the read and write indexes are FIFO pointers. The FIFO pointers are stored in the tile memory region RAM.

[0193] The tile memory area RAM typically contains the following fields:

[0194] 1. Region Index High, which is the high bit of the tile memory region index. The low index bits are obtained from an asynchronous architecture message, TID, XID_WR or XID_RD identifier or from a FIFO read / write index value. The region index high bit is ORed with the low index bit to generate the tile memory 325 index.

[0195] 2. Region SizeW, which is the width of the low index of the memory region. The size of the memory region is 2 SizeW elements.

[0196] 3. Region FIFO Read Index, which is the read index of the memory region used as FIFO.

[0197] 4. Region FIFO Write Index, which is the write index of the memory region used as FIFO. The tile performs the calculation operation of the HTF 200.

[0198] Computational operations are performed by configuring data paths within tile 210. There are two functional blocks that perform all computations for tile 210: multiplication and shift operation circuitry ("MS Op") 305 and arithmetic logic and bitwise operation circuitry ("ALB Op") 310. MS Op 305 and ALB Op 310 are controlled by instructions from instruction RAM 315 and can be configured to perform two pipelined operations, such as, for example and without limitation, multiplication and addition, or shift and addition. (In a representative embodiment, all devices supporting HTF200 will have a full support instruction set. This will provide binary compatibility across all devices. However, it may be necessary to have a set of base functionality and optional instruction set classes to meet die size tradeoffs. This approach is similar to how the RISC-V instruction set has a base and multiple optional instruction subsets.) Fig. 9 As illustrated in FIG. 3 , the outputs of MS Op 305 and ALB Op 310 may be provided to register 312 , or directly to other components such as output multiplexer 395 , conditional logic circuitry 370 , and / or write mask generator 375 .

[0199] The various operations performed by MS Op 305 include, by way of example and without limitation: integer and floating point multiplication, shifts, passing any input, signed and unsigned integer multiplication, signed and unsigned right shifts, signed and unsigned left shifts, bit order reversal, permutations, any and all of these operations as floating point operations, and conversions between integer and floating point, such as double precision floor operations or converting floating point to integer. The various operations performed by ALB Op 310 include, by way of example and without limitation: signed and unsigned addition, absolute value, negation, logical NOT, addition and negation, subtraction AB, inverse subtraction BA, signed and unsigned greater than, signed and unsigned greater than or equal to, signed and unsigned less than, signed and unsigned less than or equal to, comparisons (equal to or not equal to), logical operations (AND, OR, XOR, NAND, NOR, NOTXOR, AND NOT, OR NOT), any and all of these operations as floating point operations, and conversions between integers and floating points, such as floor operations or converting floating point to integer.

[0200] Inputs to ALB Op 310 and MS Op 305 are either from synchronous tile inputs (held in registers 350), from internal tile memory 325, or from small constant values ​​provided in instruction RAM 315. Table 1 below, showing tile 210 datapath input resources, lists typical inputs to ALB Op 310 and MS Op 305.

[0201] Table 1:

[0202]

[0203]

[0204] Each of the outputs 270B of the block 210 are individually enabled as part of the communication line 270 of the synchronous mesh communication network 275, allowing clock gating of disabled outputs. The outputs of the ALB Op 310 can be sent to a number of destinations shown in Table 2.

[0205] Table 2:

[0206]

[0207]

[0208] At a high level, and all as representative examples (without limitation), the general operation of the block 210 is as follows. As part of the program compilation and when the configuration is loaded into the system, the synchronous mesh communication network 275 and synchronization domains of each block 210 are all scheduled. Unless paused or stopped, the block 210 can perform its operation when all required inputs are ready, for example, data variables are in the input registers 350 or memory 325 and can be read or obtained from the registers or memory and used, as described in more detail below. In a representative embodiment, each pipeline stage can operate in a single clock cycle, while in other representative embodiments, each pipeline stage can utilize additional clock cycles. In the first pipeline stage 304, data is input, for example, into the AF input queue 360 ​​and input registers 350, and optionally directly into the memory 325. In the next pipeline stage 306, for example, the AF message is decoded by the AF state machine 345 and moved into the memory 325; the AF state machine 345 reads data from the memory 325 or reads data received from the output multiplexer 395 and generates a data packet for transmission over the asynchronous packet network 265; the data in the input register 350 is moved into the memory 325 or selected as operand data (using the input multiplexer 355 and the intermediate multiplexer 365) or directly passed to the output register 380 for output on the synchronous mesh communication network 275. In one or more of the next pipeline stages 307 and 308, calculations are performed by the ALB Op 310 and / or the MS Op 305, a write mask may be generated by the write mask generator 375, and an instruction (or instruction index) may be selected based on a test condition in the conditional (branch) logic circuitry 370. In the next pipeline stage 309, the output is selected using the output multiplexer 395, and the output message (which may have been stored in the AF output queue 390) is transmitted over the asynchronous packet network 265, and the output data in any of the output registers 380 is transmitted over the synchronous mesh communication network 275.

[0209] Fig.10 is a detailed block diagram of a representative embodiment of a memory control circuit 330 (with associated control registers 340 ) of a hybrid threaded architecture configurable compute circuit (tile) 210 . Fig.10A diagram showing the tile memory 325 read index logic of the memory control circuit 330 is shown and is replicated for each memory 325 (not illustrated separately). The instruction RAM 315 has a field that specifies which region of the tile memory 325 is being accessed and a field that specifies the access index mode. The memory region RAM 405 (part of the control register 340) specifies a region read mask that provides the high memory address bits of a particular region. The mask is ORed with the low address bits supplied by the read index selection multiplexer 403 (OR gate 408). When the tile memory 325 is accessed in FIFO mode, the region RAM 405 also contains a read index value. The read index value in the RAM 405 is incremented and written back when accessed in FIFO mode. In various embodiments, the memory region RAM 405 can also maintain the top of the TID stack through nested loops, described below.

[0210] Fig.10 Also shown is the need for control information (INSTR, XID, TID) for the synchronous mesh communication network 275 several clocks ahead of the data input. For this reason, the control information is sent out from the previous tile 210 several clocks before the data is sent. This staging of the synchronous mesh communication network 275 information reduces the overall pipeline stages per tile 210, but it can make it challenging to use calculated values ​​as indexes into the tile memory 325. Specifically, the synchronous mesh communication network 275 data may arrive too late to be used as an index into the tile memory 325. The architected solution to this problem is to provide the calculated index from the previous tile 210 in the variable index register of the control register 340. Later, another input causes the variable index register to be used as the tile memory 325 index.

[0211] The asynchronous packet network 265 is used to perform operations that occur asynchronously with the synchronous domain. Each block 210 contains an interface to the asynchronous packet network 265, such as Fig. 9 . The inbound interface (from communication line 280A) is an AF input queue 360 ​​(as a FIFO) used to provide storage for messages that cannot be processed immediately. Similarly, the outbound interface (to communication line 280B) is an AF output queue 390 (as a FIFO) used to provide storage for messages that cannot be sent out immediately. Messages passing through the asynchronous packet network 265 can be classified as data messages or control. Data messages contain a 64-bit data value that is written to one of the tile memories 325. Control messages are used to control thread creation, release resources (TID or XID), or issue external memory references. Table 3 below lists the asynchronous packet network 265 outbound message operations:

[0212] Table 3:

[0213]

[0214]

[0215] The asynchronous packet network 265 allows messages to be sent and received from tiles 210 in different sync domains. These are the few cases where it makes sense for a sync domain to send a message to itself, such as when a sync domain's base tile 210 allocates a TID and the TID is to be released by the same sync domain.

[0216] If the synchronous domains of the various tiles 210 generate and send messages faster than the messages can be received, routed and processed by the asynchronous packet network 265 or receiving endpoints, the asynchronous packet network 265 may become congested. In this case, a back pressure mechanism is provided to alleviate any such congestion. Fig. 22 385. In general, there is at least one flow control circuit 385 per HTF circuit cluster 205. The tile 210 asynchronous fabric output queue 390 will hold messages as they wait to be sent over the asynchronous packet network 265. A predetermined threshold is provided for the output queue 390 which, when reached, will cause the output queue 390 of the tile 210 to generate an indicator, such as a set bit, which is asserted as a "stop" signal 382 on a communication line 384 provided to the flow control circuit 385. Each communication line 384 from a tile 210 in an HTF circuit cluster 205 is provided to the flow control circuit 385. The flow control circuit 385 has one or more OR gates 386 which will continue to assert the stop signal 382 on the communication line 388 distributed to all tiles 210 within the affected HTF circuit cluster 205 as long as any of the tiles 210 are generating a stop signal 382.

[0217] The stop signal 382 may be distributed over a dedicated communication line 388 that is not part of the illustrated synchronous mesh communication network 275 or asynchronous packet network 265 or distributed over the synchronous mesh communication network 275. In a representative embodiment, there is a single stop signal 382 so that all tile output queues 390 within the HTF circuit cluster 205 may be asserted, and all tiles 210 within the HTF circuit cluster 205 are held (paused or stopped) when the stop signal 382 is asserted. This stop signal 382 continues to allow all AF input queues 360 to receive AF messages and packets, thereby avoiding deadlock, but also causes all synchronous domain pipelines to be held or paused (which also prevents additional AF data packets from being generated). The stop signal 382 allows the asynchronous packet network 265 to drain the tile 210 output queue 390 to a point where the number of messages in the output queue 390 (triggering the output queue 390) has dropped below a threshold level. Once the size of the output queue 390 has dropped below the threshold level, the signal through the communication line 384 is returned to 0 (the stop signal 382 is no longer generated) for that tile 210. When this has occurred for all tiles 210 in the HTF circuit cluster 205, the signal on the communication line 388 also returns to 0, meaning that the stop signal is no longer asserted, and the stop or pause on the tile 210 ends.

[0218] The first or "base" tile 210 of the synchronization domain has the responsibility to start the worker thread through the multi-tile 210 synchronization pipeline. New threads can be started at a predetermined rhythm. The rhythm interval is referred to in this article as the "spoke count" mentioned above. For example, if the spoke count is 3, then a new worker thread can be started on the base tile 210 every three clocks. If starting a new thread is skipped (for example, no thread is ready to start), then a full spoke count must be waited before another thread can be started. A spoke count greater than 1 allows each physical tile 210 to be used multiple times within the synchronization pipeline. As an example, if the synchronization domain is executed on a single physical tile and the spoke count is 1, then the synchronization domain may contain a single tile time slice. If the spoke count is 4 for this example, then the synchronization domain may contain 4 tile time slices. Typically, the synchronization domain is executed by multiple tiles 210 interconnected by synchronization links of the synchronous mesh communication network 275. Sync domains are not limited to a subset of tiles 210 within a cluster 205, i.e., multiple sync domains may share a tile 210 of a cluster 205. A single tile 210 may participate in multiple sync domains, e.g., spoke 0, tile 210 operates on sync domain "A"; spoke 1, tile 210 operates on sync domain "B"; spoke 2, tile 210 operates on sync domain "A"; and spoke 3, tile 210 operates on sync domain "C". Thread control of tiles is described below with reference to Fig.11 describe.

[0219] Fig.11is a detailed block diagram of a representative embodiment of a thread control circuit 335 (with associated control registers 340) of a hybrid threaded architecture configurable computing circuit (tile) 210. Fig.11 , several registers are included in the control register 340, namely, TID pool register 410, XID pool register 415, pause table 420 and completion table 422. In various embodiments, the data of completion table 422 may be equally maintained in pause table 420, and vice versa. Thread control circuit system 335 includes continuation queue 430, reentry queue 445, thread control multiplexer 435, run queue 440, iteration increment 447, iteration index 460 and loop iteration count 465. Alternatively, continuation queue 430 and run queue 440 may be equally embodied in control register 340.

[0220] Fig.12 is a diagram of tiles 210 and representative asynchronous packet network messaging forming first and second synchronization domains 526, 538. One difficulty with an asynchronous packet network 265 is that required data may arrive at tiles 210 at different times, which may make it difficult to ensure that an initiated thread can run to completion with a fixed pipeline delay. In a representative embodiment, tiles 210 forming a synchronization domain do not execute a compute thread until all resources are ready, such as by having available required data, any required variables, etc., all of which have been distributed to the tiles via the asynchronous packet network 265, and thus may have arrived at a given tile 210 at any one of various times. Additionally, data may have to be read from system memory 125 and transmitted via the asynchronous packet network 265, and thus may also have arrived at a given tile 210 at any one of various times.

[0221] In order to run a thread to completion at a fixed pipeline latency, a representative embodiment provides a completion table 422 (or pause table 420) indexed by the TID of the thread at the base tile 210 of the synchronization domain. The completion table 422 (or pause table 420) maintains a dependency completion count that must be received before the execution of the thread is initiated. The completion table 422 (or pause table 420) contains a field named "Completion Count" that is initialized to 0 at reset. Two types of AF messages are used to modify the count field. The first message type is a thread start or continue message and increments the field by a count of the number of dependencies that must be observed before the thread can be initiated in the synchronization domain. The second AF message type is a completion message and decrements the count field by 1 indicating that a completion message was received. Once a thread start message is received and the completion count field reaches 0, the thread is ready to be initiated.

[0222] like Fig.12293, which is also included in the AF Continue message 291. Fig.12 ) and a completion count of 1, which indicates that the base tile 210D of the second synchronization domain 538 will wait to start a thread on the second synchronization domain 538 until it has received a completion message.

[0223] Therefore, when, for example Fig.12 When the tile 210 of the tile 210E in receives this data, it acknowledges the receipt by sending a completion message (with the thread ID (TID)) back to the base tile 210 (here, the base tile 210D of the second synchronization domain 538). As part of the configuration provided to the base tile 210 (at the initial configuration or as part of the continue message) and stored in the completion table 422 (or pause table 420) as the completion count, the base tile 210D knows how many such completion messages the base tile 210 must receive in order to begin execution by the tile 210 of the synchronization domain (in this case, the second synchronization domain 538). As completion messages are received by the base tile 210, the completion count of the pause table is decremented for the particular thread with that TID and when it reaches 0 for that thread (indicating that all required completion messages have been received), the base tile 210 can begin execution of the thread. To begin execution, the thread's TID is passed to the continuation queue 430 from which the thread is selected to run (at the appropriate spoke count of the appropriate time slice of the tile 210). It should be noted that data determined during execution of a thread and that may be transmitted between tiles 210 of a synchronization domain over the synchronous mesh communication network 275 does not require a completion message.

[0224] There are several advantages to this type of thread control. This thread control waits for all dependencies to complete before starting a thread, allowing the started thread to have a fixed synchronous execution time. The fixed execution time allows register levels to be used throughout the pipeline instead of FIFOs. In addition, while one thread of a tile 210 may be waiting to execute, other threads may be executing on that tile 210, providing much higher overall throughput and minimizing idle time and minimizing unused resources.

[0225] Similar control is provided when crossing sync domains, such as to execute multiple threads (e.g., for related compute threads forming a compute fiber). For example, a first sync domain will notify the base tile 210 of the next sync domain in a continuation message transmitted over the asynchronous packet network 265 of how many completion messages it will need to receive in order for it to start execution of the next thread. Also, for example, for an iterative loop across sync domains, the first sync domain will notify the base tile 210 of the next sync domain in a loop message (with a loop count and the same TID) transmitted over the asynchronous packet network 265 of how many completion messages it will need to receive in order for it to start execution of the next thread.

[0226] It should also be mentioned that various delays may need to be implemented, for example when first data from a first tile 210 is available while second data is still being determined by the second tile 210, both of which will be needed in the next calculation by the third tile 210. For such cases, delays may be introduced at the output register 380 at the first tile 210 that created the first data or in the tile memory 325 of the third tile 210. This delay mechanism also applies to data that can be transferred from the first tile 210 to the third tile 210 using the second tile 210 as a pass-through.

[0227] The pause table 420 is used to hold or pause the creation of a new synchronization thread in the tile 210 until all required completion messages have been received. A thread from the previous synchronization domain sends a message to the base tile 210 containing the number of completion messages expected for the new synchronization thread and the action to be taken when all completion messages have been received. The action includes: call, continue, or loop. Many pause operations are usually valid at the same time. All messages for a specific pause operation (i.e., a set of pause and completion messages) will have the same pause index within the corresponding message. The pause index is the TID from the sending tile 210. The pause table 420 entry is initialized to be invalid if the completion delta count is 0. Receiving a pause message increments the delta count by the number of required completion counts and sets the pause table 420 entry to valid. Receiving a completion message decrements the delta count by 1. It should be noted that a completion message may arrive before the associated pause message, resulting in a negative delta count. When a suspend table 420 entry is valid with a delta count of 0, then the associated activity (eg, a new thread) is initialized (and the suspend table 420 entry is deactivated).

[0228] The continuation (or call) queue 430 holds threads that are ready to be started on the synchronization domain. When all completions of the call operations are received, the threads are pushed into the continuation queue 430. It should be noted that the threads in the continuation queue 430 may need to be assigned a TID and / or XID before the threads can be started on the synchronization domain, for example, if all TIDs are in use, then once the TID is released and available (i.e., the thread can wait until the TID and / or XID is available), the threads in the continuation queue 430 can be started.

[0229] The reentry queue 445 holds threads ready to be started on the synchronization domain while executing those threads with priority over the threads in the continuation queue 430. When all completions of the continuation operation are received and the thread already has a TID, the thread is pushed into the reentry queue 445. It should be noted that the threads in the reentry queue 445 may not require the allocation of a TID. A separate reentry queue 445 and continuation (or continuation) queue 430 are provided to avoid deadlock situations. A special type of continuation operation is a loop. The loop message contains a loop iteration count. The count is used to specify the number of times the thread will be started once the pause operation is completed.

[0230] Optional priority queue 425 may also be implemented so that any thread having a thread identifier in priority queue 425 is executed before any thread having a thread identifier in continuation queue 430 or reentry queue 445 is executed.

[0231] The iteration index 460 state is used when starting a thread of a loop operation. The iteration index 460 is initialized to 0 and incremented for each thread start. The iteration index 460 is pushed into the run queue 440 along with the thread information from the continuation queue 430. The iteration index 460 can be used as a selection for the data path input multiplexer 365 within the first tile (base tile) 210 of the synchronization domain.

[0232] The loop iteration count 465 is received as part of the loop message, saved in the pause table 420, pushed into the continue queue 430, and then used to determine when the appropriate number of threads are started for the loop operation.

[0233] Run queue 440 holds ready-to-run threads that have assigned TIDs and / or XIDs and can be executed when the appropriate spoke count clock has occurred. TID pool 410 provides a unique thread identifier (TID) to a thread as it starts on a synchronization domain. Only threads within continuation queue 430 can obtain a TID. XID pool 415 provides a unique transfer identifier (XID) to a thread as it starts on a synchronization domain. Threads from continuation queue 430 can obtain an XID. The assigned XID becomes the XID_WR of the started thread.

[0234] For any given or selected program to be executed, code or instructions written or generated for that program in any appropriate or selected programming language are compiled for the system 100 and loaded into the system 100, including instructions for the HTP 300 and HTF circuits 200, and either of which may be applicable to the host processor 110 to provide the selected configuration to the system 100. Thus, the various instruction sets for one or more selected calculations are loaded into the instruction RAM 315 and spoke RAM 320 of each tile 210, and into any of the various registers maintained in the memory interface 215 and dispatch interface 225 of each tile 210, thereby providing the configuration for the HTF circuits 200, and depending on the program, also loaded into the HTP 300.

[0235] By way of example and not limitation, a kernel is initiated with a work descriptor message containing zero or more arguments, typically generated by a host processor 110 or HTP 300, for execution by one or more HTF circuits 200. The arguments are sent within the work descriptor AF message to the dispatch interface 225. These arguments provide thread specific input values. The host processor 110 or HTP 300, using its respective operating system ("OS"), may send a "host" message to the kernel that initializes tile memory 325 locations, where such host messages provide non-thread specific values. A typical example is a host message that sends the base address of a data structure used by all kernel threads.

[0236] Host messages sent to a kernel are sent to all HTF circuit clusters 205 that load the kernel. In addition, the order of sending host messages and sending kernel dispatches is maintained. Sending a host message causes the kernel to essentially idle before sending the message. The completion message ensures that tile memory 325 writes have completed before starting a new synchronization thread.

[0237] Control messaging over the asynchronous packet network 265 is as follows:

[0238] (1) The dispatch interface 225 receives the host message and sends the AF data message to the destination tile 210. The destination tile 210 writes the data of the AF data message to the selected memory.

[0239] (2) The destination tile 210 sends an AF completion message to the dispatch interface 225 confirming that the tile writing is complete.

[0240] (3) The dispatch interface 225 keeps all new kernel threads started until all message writes have been confirmed. Once confirmed, the dispatch interface 225 transmits the AF call message to the basic tile of the synchronization domain to start the thread.

[0241] The dispatch interface 225 is responsible for managing the HTF circuit cluster 205, including: (1) interacting with the system 100 software to prepare the HTF circuit cluster 205 for use by the process; (2) dispatching work to the tiles 210 of the HTF circuit cluster 205, including loading the HTF circuit cluster 205 with one or more kernel configurations; (3) saving and restoring the context of the HTF circuit cluster 205 to the memory 125 for breakpoints and exceptions. As mentioned above, the registers 475 of the dispatch interface 225 can include a variety of tables to track what has been dispatched to any of the tiles 210 and what has been received from any of the tiles 210, such as tracking any of the message passing utilized in the representative embodiment. The dispatch interface 225 primitive operations used to perform these operations are listed in Table 4.

[0242] Table 4:

[0243]

[0244]

[0245] Fig.16 17 provides an example of message passing and thread control within the system 100, wherein an example calculation is provided to demonstrate how the synchronous mesh communication network 275 and the asynchronous packet network 265 work together to execute a simple kernel, where a simple expression R=*A+B is solved. To demonstrate this message passing, the calculation has been divided across two different synchronization domains 526 and 538. The variable B is passed as a host message to all HTF circuit clusters 205, and the address A is passed as an argument to the call in the work descriptor packet. The result R is passed back in the return data packet through the first interconnect network 150. The example does almost no calculations, so the number of messages per calculation performed is quite high. The HTF circuit 200 has much higher performance when a large number of calculations are performed within a loop so that the number of messages per calculation is low.

[0246] Fig.16 FIG. 17 is a diagram of a representative hybrid threaded architecture configurable computing circuit (tile) 210 forming a synchronization domain and a representative asynchronous packet network message passing for computing performed by the HTF circuit cluster 205. Fig.16 Flowchart of representative asynchronous packet network message passing and execution of computations by hybrid threaded architecture configurable computing circuits (blocks). First, the host processor 110 sends a message 504 to all HTF circuit clusters 205 within the node (step 506). The message is the value of variable B. The message is contained in a single data packet, commonly referred to as a work descriptor packet, which is written to the dispatch queue 105 of the HIF 115 associated with the process (in Figure 1 and2 105). HIF 115 reads the message from dispatch queue 105 and sends a copy of the packet to each HTF circuit cluster 205 assigned to the process. The dispatch interface 225 of the assigned HTF circuit cluster 205 receives the packet. It should also be noted that HIF 115 performs various load balancing functions across all HTP 300 and HTF 200 resources.

[0247] The host processor 110 sends a call message 508 to one of the HTF circuit clusters 205 assigned to the process (step 510). The host processor 110 can manually specify a particular HTF circuit cluster 205 on which to execute the kernel, or allow the HTF circuit cluster 205 to be automatically selected. The host processor 110 writes the call parameters to the dispatch queue associated with the process. The call parameters include the kernel address, the start instruction, and a single argument (the address of variable A). The host interface (HIF) 115 reads the queued message and forwards the message as a data packet on the first interconnect network 150 to the assigned HTF circuit cluster 205, typically the HTF circuit cluster 205 with the least load.

[0248] The dispatch interface 225 receives the host message (the value of variable B), waits until all previous calls to the HTF circuit cluster 205 have completed, and sends the value to the first selected destination tile 210H using an AF message 512 over the asynchronous packet network 265 (step 514). The dispatch interface 225 has an information table stored in registers 475 for each possible host message indicating the destination tile 210H, the tile memory 325, and the memory area (in RAM 405) of that tile 210H. The tile 210H writes the value to the memory 325 in the tile 210H using the message information, and once the value is written to the tile memory, a write complete AF message 516 is sent back to the dispatch interface 225 via the asynchronous packet network 265 (step 518).

[0249] The dispatch interface 225 waits for all message completion messages to arrive (in this case, only a single message). Once all completion messages have arrived, the dispatch interface 225 sends the call argument (the address of variable A) in an AF message 520 to the second selected destination tile 210B to write the value into the tile memory 325 (step 522). The dispatch interface 225 has a call argument table stored in registers 475 indicating the destination tile 210B, the tile memory 325, and the memory area (in RAM 405) of that tile 210B.

[0250] The dispatch interface 225 then sends an AF call message 524 to the base tile 210A of the first synchronization domain 526 (step 528). The AF call message indicates that a single completion message should be received before the call can initiate execution through the synchronization tile 210 pipeline. The required completion message has not arrived, so the call is suspended.

[0251] Once the value is written to the tile memory 325 of that tile 210B, a write completion message 530 is sent by the tile 210B to the base tile 210A of the first synchronization domain 526 via the asynchronous packet network 265 (step 532).

[0252] The base tile 210A has received both the call message 524 and the required completion message 530 and is now ready to start execution on the synchronization domain 526 (tile pipeline). The base tile 210A starts execution by providing an initial instruction and a valid signal 534 to the tile 210B via the synchronization mesh communication network 275 (step 536). The base tile 210A allocates an XID value from the XID pool 415 for use in the first synchronization domain 526. If the XID pool 415 is empty, the base tile 210A must wait to start the synchronization pipeline until an XID is available.

[0253] As execution proceeds, tile 210B or another tile 210E within the first sync domain 526 sends an AF Continue message 540 to the base tile 210C of the second sync domain 538 (step 542). The Continue message contains the number of required Completion messages (in this case, a single Completion message) that must arrive before the second sync domain 538 can start execution. The Continue message also includes a Transfer ID (XID). The XID is used as a write index in one sync domain 526 and then as a read index in the next sync domain 538. The XID provides a common tile memory index from one sync domain to the next sync domain.

[0254] Tile 210B or another tile 210F within first sync domain 526 sends AF memory load message 544 to memory interface 215 of HTF circuit cluster 205 (step 546). The message contains request ID, virtual address and XID to be used as index for writing load data to destination tile 210G memory 325.

[0255] The memory interface 215 receives the AF load message and translates the virtual address into a node local physical address or a remote virtual address. The memory interface 215 uses the request ID of the AF message to index into a request table stored in registers 485 containing parameters of the memory request. The memory interface 215 issues a load memory request packet 548 to the first interconnection network 150 with the translated address and size information from the request table (step 550).

[0256] The memory interface 215 then receives a memory response packet 552 with the load data (the value of variable A) through the first interconnect network 150 (step 554). The memory interface 215 sends an AF message 556 to the tile 210G within the second synchronization domain 538 (step 558). The AF message contains the value of variable A and writes the value to the tile memory using the parameters from the request table stored in registers 485.

[0257] Once the values ​​are written to the tile memory, an AF write complete message 560 is sent to the base tile 210C of the second synchronization domain 538 via the asynchronous packet network 265 (step 562).

[0258] The base tile 210C of the second sync domain 538 receives both the continue message 540 and the required completion message 560 and is ready to start execution on the second sync domain 538 (tile pipeline). The base tile 210C starts execution by providing an initial instruction and a valid signal 564 to a tile 210 (e.g., tile 210H) of the second sync domain 538 (step 566). The base tile 210C also allocates an XID value from the XID pool for use in the second sync domain 538.

[0259] Block 210H in the second synchronization domain performs an addition operation (step 568) of the B value passed in from the host message and the A value read from the system memory 125. The resulting value is the R value of the expression.

[0260] The tile 210J in the second synchronization domain sends an AF message 570 containing the R value to the dispatch interface 225 (step 572). The AF message contains the assigned XID value from the base tile 210A. The XID value is used as an index within the dispatch interface 225 to a table stored in register 475, which holds the return parameter until the value is read and the return message has been generated for transmission over the first interconnect network 150.

[0261] The AF message 574 from the second sync domain (tile 210K) sends the XID value allocated in the first sync domain back to the base tile 210A to be transferred back to the XID pool (step 576). The first interconnect network 150 message 578 from the dispatch interface 225 is sent to the HIF 115 (step 580). The HIF writes the return work descriptor to the dispatch return queue. Once the first interconnect network 150 has sent the return packet, the XID value is sent by the dispatch interface 225 in an AF message 582 to the base tile 210C of the second sync domain 538 to be transferred back to the XID pool (step 584).

[0262] It should be noted that Fig.16In this example of FIG. 17 , many tiles 210 have been utilized in order to show the variety of AF messages that can be used for thread control. In practice, especially for this simple calculation, significantly fewer tiles 210 may be utilized, for example to perform the calculation entirely within a single synchronization domain.

[0263] exist Fig.18 Another example of message passing for thread control across multiple synchronization domains is provided in 19, which also uses AF completion and continue messages over the asynchronous packet network 265. Fig.18 FIG. 19 is a diagram of a representative hybrid threaded architecture configurable computing circuit (block) forming a synchronization domain and a representative asynchronous packet network message passing for computing performed by a hybrid threaded architecture circuit cluster. Fig.18 Flowchart of representative asynchronous packet network messaging and execution of computations performed by a hybrid threaded architecture configurable computing circuit (tile).

[0264] For this example, the dispatch interface 225 sends a message to the base tile 210A of the first synchronization domain 526. The message starts the thread on the first synchronization domain 526. The thread sends a thread continue message to the second synchronization domain 538. The continue message indicates that the thread will be started on the second synchronization domain 538 when a certain number of completion messages have been received. The first synchronization domain 526 sends a completion message to the second synchronization domain 538 that causes a pause to complete and start synchronizing the second thread. The second thread sends a completion message back to the dispatch interface 225 indicating that the second synchronization thread is complete, thereby completing the dispatched kernel. An additional message to release the TID and XID identifiers is in Fig.18 Displayed in.

[0265] The dispatch interface 225 has received the work descriptor packet 602, ensured that the correct kernel configuration is loaded, determined that the XID and TID pools are not empty, and thus obtains the XID and TID values ​​of the new work thread from the TID and XID pools stored in registers 475 within the dispatch interface 225 (step 604). The dispatch interface 225 initiates kernel execution by sending an AF call message 606 (with the assigned XID and TID values, e.g., XID=3 and (first type of) TID=11) to the base tile 210A of the first synchronization domain 526 (step 608). The base tile 210A receives the AF call message 606, determines that the TID and XID pools 410, 415 are not empty, assigns TID and XID values ​​(e.g., XID_WR=7 and (second type) TID=1), and the spoke Ram 320 is selecting the base tile as the input to the tile data path (step 610), so that it begins execution with the first specified instruction indicated by the instruction index held in its spoke Ram 320, rather than potentially executing instructions from an instruction index that may have been provided by a previous tile 210 (e.g., as discussed in more detail below with respect to conditional execution).

[0266] The base tile 210A starts the first thread 612 through the first synchronization domain 526 with an assigned TID value (e.g., (second type) TID=1), an XID_RD assigned a value from the AF call message 606 (e.g., XID_RD=3), an XID_WR assigned a value obtained from the XID pool (e.g., XID_WR=7), and a TID from the AF call message 606 (e.g., (first type) TID=11) (step 614).

[0267] As the computation proceeds in the first synchronization domain 526, another tile 210B within the first synchronization domain 526 sends an AF continue message 616 to the base tile 210D of the second synchronization domain 538 (step 618). The AF continue message 616 provides the information necessary to start the second thread on the second synchronization domain 538 when the appropriate number of completion messages have arrived. The AF continue message 616 includes a completion count field with a value specifying the number of completion messages required. One of the tiles 210C in the first synchronization domain 526 also transmits a free XID (e.g., XID=3) message 641 to the dispatch interface 225.

[0268] The AF Continue message 616 may include a TID or XID_WR value as an index into the Suspend table 420 on the destination base tile 210D. The Suspend table accumulates received completion messages and determines when the necessary number is reached and a new thread can be started (step 620). The tile 210B that sends the AF Continue message 616 sends the selected TID or XID_WR value as the PID (Suspend Table Index) and changes the downstream TID value of the sync domain to the selected value (e.g., TID (for the first type) = 11, TID (for the second type) = 1). This new TID value is passed in all AF Completion messages to be used as an index into the Suspend table 420 of the base tile 210D.

[0269] An AF completion message 622 is sent to the base tile 210D of the second synchronization domain 538 with a TID value (e.g., TID (of the first type) = 11) (step 624). The AF completion message 622 decrements the entry of the delta count field in the pause table 420 of the base tile 210D. The AF completion message 622 and the AF continue message 616 may arrive in any order. The last message to arrive will observe that the AF continue message 616 has arrived and the delta count field in the pause table 420 has reached 0. This condition indicates that the pause has been completed and the second synchronization thread 626 can be initiated. The base tile 210D also determines or observes that the pause operation has been completed, determines that the XID identifier value is non-null and assigns an XID (e.g., XID = 5), and the spoke Ram is selecting the base tile as the input of the tile data path (step 628).

[0270] Next, the base tile 210D starts a second synchronization thread 626 through the second synchronization domain 538 (step 630) with the TID and XID_RD (e.g., TID (of the first type) = 11, TID (of the second type) = 1, XID_RD = 7) assigned the values ​​obtained from the AF Continue message 616. In step 628, XID_WR is assigned a value obtained from the XID pool (e.g., XID_WR = 5).

[0271] When the computation of the second synchronization thread 626 has completed, several housekeeping messages are sent by the various tiles 210 of the second sync domain 538. An AF Free TID message 632 is sent to the base tile 210A of the first sync domain 526 (step 634), and the receiving base tile 210A adds the TID value to the TID pool 410 (step 636), making it available for use again. An AF Free XID message 638 is sent to the base tile 210A of the first sync domain 526 (step 640), and the receiving base tile 210 adds the XID value to the XID pool 415 (step 642), also making it available for use again. An AF Complete message 644 indicating that the second synchronization thread 626 has completed is sent to the dispatch interface 225 (step 646). The dispatch interface 225 has a count of expected completion messages. The AF Complete message 644 includes the XID_WR value and the TID value (TID (of the first type) = 11) of the second sync domain 538 to the dispatch interface. Next, the dispatch interface 225 sends an AF Free XID message 648 to the base tile 210D of the second sync domain 538 (step 650). Next, the receiving base tile 210D adds the XID value to the XID pool 415 (step 652), making it available for use again.

[0272] The data transfer operation is used to transfer data from one synchronization domain to the next synchronization domain. Typically, data transfer is used in conjunction with a load operation that obtains data from the memory 125. Once the load data has arrived at the second synchronization domain 538, the data calculated from the first synchronization domain 526 is required in the second synchronization domain 538. In this case, a single pause containing the total completion message count from all load and data transfer operations is sent from the first synchronization domain 526 to the second synchronization domain 538.

[0273] Next, the data transfer operation between the sync domains utilizes a variation of step 624. Instead of sending the AF completion message 622 in step 624, the first sync domain 526 sends an AF data message with the data to the second sync domain 538. The destination tile 210 in the second sync domain 538 writes the data within the AF data message to the selected tile memory 325. Next, the tile 210 receiving the AF data message sends an AF completion message to the base tile 210 of the second sync domain 538. Once the load data has arrived at the second sync domain 538, the base tile 210 of the second sync domain 538 starts a second thread on the second sync domain 538.

[0274] The control of iterative thread loops across synchronization domains utilizes a similar control message passing pattern. The loop message flow allows multiple synchronization domains to be initiated from a single loop message. Each of the initiated synchronization threads is able to access its iteration index. Fig. 20is a diagram of representative hybrid threaded architecture configurable computing circuits (tiles) forming a synchronization domain and representative asynchronous packet network message passing for executing loops in a computation by a cluster of hybrid threaded architecture circuits. Fig.21 is used by the hybrid thread architecture circuit cluster in Fig. 20 Flowchart of representative asynchronous packet network message passing and execution of a computational loop by a hybrid threaded architecture configurable computing circuit (block).

[0275] Fig. 20 Three synchronization domains are shown: a first synchronization domain 526, a second synchronization domain 538, and a third synchronization domain 654. The first synchronization domain 526 is used for pre-loop setup, the second synchronization domain 538 starts with an iteration count (IterCnt) of the number of threads, and finally the third synchronization domain 654 is the post-loop. It should be noted that loops can also be nested using additional layers of indexes as well, discussed in more detail below.

[0276] Reference again Fig.11 , the control registers 340 include a completion table 422 (or pause table 420). For a loop, two types of completion information are maintained in the completion table 422: a first completion count regarding the number of completion messages that should arrive before a thread can start, as discussed above; and a second loop or iteration (completion) count to track how many loop threads have started and completed. A loop is started by sending an AF loop message containing a loop count (and various TIDs, discussed below) to the base tile 210 of the sync domain. The loop count is stored in the completion table 422 (or pause table 420) and is used to determine the number of times a new thread is started on the sync domain. In one embodiment, each thread is started with a new TID obtained from the TID pool 410. For example, each active thread has a unique TID that allows thread-private variables. Threads of nested loops are provided access to data or variables of their own TID plus the TID of the outer loop. In a second embodiment discussed below, TIDs are reused by successive threads of the loop.

[0277] The TID is returned to the TID pool 410 by an AF message sent from a tile within the synchronization domain when the thread is terminating. The AF message may be an AF completion message, or for the second embodiment, an AF reentry message. This may also be achieved by a free TID message to the base tile 210. The AF message that returns the TID to the pool or reuses the TID is also used by the loop base tile 210 to maintain a count of the number of valid loop threads in the loop count of the completion table 422 (or pause table 420). When the number of valid loop threads reaches 0, the loop is completed. When the loop completion is detected by the loop count going to 0, an AF completion message is sent to the post-loop synchronization domain to notify completion. This mechanism provides minimal (if non-zero) idle cycles for nested loops, resulting in better performance.

[0278] refer to Fig. 20 and 21 , the first sync domain 526 (illustrated as tile 210B, although it could be from any other tile in the first sync domain 526) sends an AF Continue message 656 to the base tile 210D of the third post-loop sync domain 654 (step 658) to wait for the loop complete message (which will come from the second sync domain 538). One of the tiles in the first sync domain 526, illustrated as tile 210B, sends an AF Loop message 660 with an iteration (loop) count to the base tile 210C, which is the loop domain of the second sync domain 538 (step 664). The base tile 210C starts a loop (IterCnt) thread (662, e.g., 6620, 6621 to 6622) on the second sync domain 538. N-1 , where "N" is the iteration count (IterCnt). Each thread 662 has the same TID and XID_RD identifier. The XID_WR identifier is assigned by the loop base tile 210C (if enabled). The iteration index (i.e., ordered from 0 to IterCnt-1 (N-1)) can be accessed as a data path multiplexer selection in the base tile 210C of the loop domain.

[0279] Then, each iteration of the loop domain sends an AF completion message 666 back to the base tile 210C of the second synchronization (loop) domain 538 (step 668). It should be noted that Fig. 20 The second sync domain 538 shown in the figure may actually be several sync domains. For the case where multiple sync domains form a loop, the thread of the last sync domain of the loop should transmit the AF completion message 666 so that the post-loop third sync domain 654 properly waits for all loop operations to complete. Once the base tile 210C of the second sync (loop) domain 538 has received all iterative AF completion messages 666, it sends a loop AF completion message (or AF continuation message) 670 to the base tile 210D of the third (post-loop) sync domain 654.

[0280] For loops including nested loops and doubly nested loops, several additional and novel features are utilized, such as to minimize idle time, including, by way of example and without limitation, a reentry queue 445 and additional sub-TIDs, such as TID2 for the outermost loop, TID1 for the middle / intermediate loop, and TID0 for the innermost loop. Each thread executing in the loop also has a unique TID, such as TID2 0-49 for an outer loop having 50 iterations, also by way of example and without limitation, which is also used in the corresponding completion message when each iteration completes execution.

[0281] Reference again Fig.11 , providing several novel mechanisms to support efficient loops and minimize idle time. For example, loops with data-dependent end conditions (e.g., "while" loops) require the end conditions to be calculated when the loop is executed. Also for the control and execution of the loop, if all TIDs are allocated from the TID pool 410, but the thread at the head of the queue for execution is a new thread, it cannot execute due to lack of available TIDs, thereby preventing other loop threads from completing and releasing their assigned TIDs, then potential deadlock problems may occur. Therefore, in a representative embodiment, the control registers 340 include two separate queues for threads ready to run, wherein the first queue is used to start a new loop (continuation queue 430, also for non-loop threads), and the second separate queue (reentry queue 445) is used for loop continuation. The continuation queue 430 allocates TIDs from the TID pool 410 to start threads, as previously discussed. When each iteration of the loop thread executes and transmits an AF reentry message with the previously allocated TID, the reentry queue 445 uses the previously allocated TID. Any thread (TID) in the reentrant queue 445 will be moved to the run queue 440 ahead of threads (TIDs) that may be in other queues (continuation queue 430). Therefore, once the loop starts, loop iterations occur very quickly, with each next thread of the loop starting quickly by using a separate reentrant queue 445, and again, there is no possibility of deadlock issues. Additionally, the reentrant queue 445 allows this fast execution, which is very important for loops with data-dependent end conditions, which can now run efficiently without interrupting the last iteration that generated the data-dependent end condition.

[0282] Reference again Fig. 9 and 10, the control register 340 includes a memory area RAM 405. In various embodiments, the memory area RAM 405 can also maintain the top of the TID stack (with identifiers) through the nested loops, described below. As mentioned above, each nested loop starts a thread with a new (or reused) set of TIDs. The threads of the loop may need to access their TIDs plus the TIDs of the outer loop threads. Accessing the TID of each nested loop thread allows access to private variables of each thread, such as the different layers or types of TIDs described above, TID0, TID1, and TID2. The top of the stack TID identifier indicates the TID of the active thread. The top of the stack TID identifier is used to select which of the three TIDs (TID0, TID1, and TID2) is used for various operations. These three TIDs and the top of the stack TID identifier are included in the synchronous architecture control information (or message) transmitted on the synchronous mesh communication network 275, so they are known to each thread. Because multiple TIDs are included within the sync fabric message and include the top of stack TID identifier, multiple TIDs allow threads in nested loops to access variables from any level within the nested loop threads. The selected TID plus the tile memory region RAM 405 identifier is used to access private thread variables.

[0283] Another novel feature of the present invention is a mechanism to order loop thread execution to handle loop iteration dependencies, which also accommodates any delays in completion messages and data received over the asynchronous packet network 265. Fig.23 2 is a diagram of a block 210 forming a synchronization domain and a diagram of representative asynchronous packet network messaging and synchronization messaging for executing a cycle in a computation by a hybrid thread architecture circuit cluster. Fig.23 , multiple synchronization domains 682, 684, and 686 are involved in the execution of a loop computation: a second synchronization domain 682, a third synchronization domain 684, a fourth synchronization domain 686, in addition to the pre-loop first synchronization domain 526 and the post-loop (fifth) synchronization domain 654. The loop computation may be any kind of loop, including nested loops, and in this case, there are data dependencies within the various loops. For example, these data dependencies may occur within a single iteration, such as when information from the memory 125 is needed, including AF messaging through the asynchronous packet network 265. Therefore, thread execution should proceed in a defined order, and not just when any particular thread has a completion count of 0 (meaning that the thread is not waiting for any data, where all completion messages for that thread have arrived).

[0284] In order to provide ordered loop thread execution, in a representative embodiment, additional messaging and additional fields are utilized in the completion table 422 for each loop iteration. The loop base tile 210B provides four pieces of information (for each loop iteration) that are passed in a synchronization message 688 through the synchronous mesh communication network 275 to each sync domain 682, 684, 686 (i.e., to each consecutive tile 210 in that given sync domain) and an AF continue message 692 to the base tile 210 of the consecutive sync domain via the asynchronous packet network 265 (which is then passed in a synchronization message to each consecutive tile 210 in that given sync domain). Then, those four information fields are stored and indexed in the completion table 422 and used for comparison as loop execution progresses. The four pieces of information are: a first flag indicating the first thread in a set of threads for the loop, a second flag indicating the last thread in a set of threads for the loop, the TID of the current thread, and the TID of the next thread. The TID of the current thread is obtained from a pool of TIDs, and the TID of the next thread is the TID from the pool that will be provided for the next thread. These four pieces of information are used by the base tile of each consecutive synchronization domain to order thread starts. A thread can be started if its dependency count has reached 0 and the thread is the first thread of the loop or the thread TID is equal to the next TID of the previously started thread.

[0285] Stated another way, the thread control circuitry 330 (which typically includes various state machines) checks the completion table 422 of each thread that has received all data completions (so would have been ready to run), whether that thread is the next thread to run (with the next thread ID, e.g., TID=4), and if so, moves the thread (TID=4) into the run queue 440, and if not, does not start that thread (e.g., the thread whose data completion count goes to 0 but has TID=5) but maintains the index of the next TID to start. When the data completions for the thread with the next TID are decremented to 0 (in this case, TID=4), so all completion messages have arrived, that thread is queued for execution, and the thread that was about to be executed (TID=4) also has a next TID, in this case, its next TID is TID=5. Therefore, when the thread with TID=4 has completed, the thread control circuitry 330 checks the completion table 422 and now determines that the thread (TID=5) is the next thread ID, and queues that thread for execution. Next, when the thread ID is the last TID, after its execution, an AF completion message 656 is transmitted to the post-cycle base tile (in this case, 210E). It should be noted that this use of additional fields in completion table 422 can be extended to any situation where a specific ordering of thread execution should be maintained.

[0286] Fig.243 is a block diagram and circuit diagram of a representative embodiment of the conditional branching circuit system 370. A synchronization domain, such as the first, second, and third synchronization domains mentioned above, is a set of interconnected tiles connected in sequence or in series through a synchronization mesh communication network 275. Execution of a thread begins at the first tile 210 of a synchronization domain (referred to as a base tile 210), and proceeds from there to other tiles 210 of the synchronization domain via configured connections of the synchronization mesh communication network 275. Fig.24 , when a tile 210 has been configured as a base tile 210 of a sync domain (because those configurations have been loaded into the HTF circuit 200 prior to run time), the select 374 of the configuration memory multiplexer 372 is set equal to 1, which thereby selects the spoke RAM 320 to provide the instruction index to select an instruction from the instruction RAM 315. For all other tiles 210 of the sync domain, the select 374 of the configuration memory multiplexer 372 is set equal to 0, which thereby selects the instruction index provided by the previous tile 210 in the sequence of tiles 210 of the sync domain. Thus, the base tile 210 provides the instruction index (or instruction) to be executed to the next second tile of the domain via the designated fields (or portions) of the communication lines (or wires) 270B and 270A (which have been labeled as the master sync input, as mentioned above). Thereafter, this next tile 210 and each subsequent tile 210 of the synchronization domain will provide the same instruction to each next tile 210 of the connected tiles 210 for execution by default as a static configuration.

[0287] However, in a representative embodiment, spoke RAM 320, instruction RAM 315, and conditional branch circuitry 370 are used to provide a mechanism for dynamic self-configuration. Fig.24 , for the current tile 210, the ALB Op 310 may be configured to generate an output as a result of a test condition, such as, for example, whether one input is greater than a second input. The test condition input is provided to the conditional branch circuitry 370 on a communication line (or wire) 378. When the conditional branch circuitry 370 is enabled (by one or more bits of the instruction provided on line (or wire) 379), the test condition output is used to select a next instruction index (or instruction) for the next tile 210 provided to the synchronization domain, such as to select between an "X" instruction or a "Y" instruction for the next tile 210, thereby providing a conditional branch of the data path when the first or second instruction is selected. This conditional branch may also be cascaded, such as when the next tile 210 is also enabled to provide a conditional branch. By selecting the next instruction for one or more of the next tiles 210, dynamic self-configuration and re-self-configuration is enabled in each such HTF circuit cluster 205.

[0288] In a representative embodiment, the conditional branch circuit system 370 has been arranged to select or switch between two different instructions depending on the test condition result. The branch enable is provided in one of the fields of the current (current next) instruction and is provided to the AND gate 362 of the conditional branch circuit system 370, where it is ANDed with the test condition output. Depending on whether the test condition output is a logic "0" or "1", the AND gate 362 will produce a logic "0" or "1" as an output, which is provided as an input to the OR gate 364. Another designated bit of the selected field of the current next instruction index, typically the least significant bit ("LSB") of the next instruction index, is also provided to the OR gate 364, where it is ORed with the output of the AND gate 362. If the LSB of the next instruction index is 0 and it is ORed with the logic "1" of the output of the AND gate 362, then the next instruction index as output has been incremented by 1, thereby providing a different next instruction index to the next tile 210. If the LSB of the next instruction index is 0 and is ORed with the logic "0" of the output of AND gate 362, then the next instruction index as output has not been incremented by 1, thereby providing the same next instruction index to the next tile 210. Therefore, the current tile 210 has conditionally specified an alternative instruction of the connected tile 210 to be executed, thereby implementing the execution of one or more selection statements in the HTF circuit cluster 205. The alternative instruction is selected by causing the data path of the current tile to produce a Boolean conditional value and using the Boolean value to select between the instruction of the current tile and the alternative instruction of the next tile 210 provided as the next instruction index to the synchronization domain. Therefore, the current tile 210 has dynamically configured the next tile 210, etc., resulting in dynamic self-configuration and re-self-configuration in each HTF circuit cluster 205.

[0289] Numerous advantages of representative embodiments are apparent. Representative devices, systems, and methods provide a computing architecture capable of providing high performance and energy efficient solutions for computationally intensive cores, such as computation of Fast Fourier Transforms (FFTs) and Finite Impulse Response (FIR) filters used in sensing, communication, and analysis applications (synthetic aperture radar, 5G base stations) and graph analysis applications (e.g., graph clustering using spectroscopy, machine learning, 5G networking algorithms, and large template codes), by way of example and without limitation.

[0290] As used herein, a "processor" 110, 300 may be any type of processor or controller, and may be embodied as one or more processors 110, 300 that are configured, designed, programmed, or otherwise adapted to perform the functionality discussed herein. As the term processor or controller is used herein, the processor 110, 300 may include the use of a single integrated circuit ("IC"), or may include the use of multiple integrated circuits or other components connected, arranged, or grouped together, such as a controller, a microprocessor, a digital signal processor ("DSP"), an array memory, a graphics or image processor, a parallel processor, a multi-core memory, a custom IC, an application specific integrated circuit ("ASIC"), a field programmable gate array ("FPGA"), an adaptive computing IC, associated memory (such as RAM, DRAM, and ROM), and other ICs and components, whether analog or digital. Therefore, as used herein, the term processor or controller should be understood to equivalently mean and include a single IC, or a custom IC, ASIC, processor, microprocessor, controller, FPGA, adaptive computing IC, or with associated memory (e.g., microprocessor memory or additional RAM, DRAM, SDRAM, SRAM, MRAM, ROM, FLASH, EPROM, or E 2 The processor 110, 300 and associated memory may be adapted or configured (via programming, FPGA interconnection, or hard wiring) to perform the methodology of the present invention, as discussed herein. For example, the method may be programmed and stored in the processor 110, 300 and its associated memory (and / or memory 125) and its equivalent components as a set of program instructions or other code (or equivalent configuration or other program) for subsequent execution when the processor 110, 300 is operating (i.e., powered on and running). Equivalently, when the processor 110, 300 may be implemented in whole or in part as an FPGA, a custom IC and / or an ASIC, the FPGA, the custom IC or ASIC may also be designed, configured and / or hard wired to implement the method of the present invention. For example, processors 110, 300 may be implemented as an arrangement of analog and / or digital circuits, controllers, microprocessors, DSPs and / or ASICs (collectively referred to as "processors" or "controllers") that are hardwired, programmed, designed, adapted or configured to implement the methods of the present invention, including possibly in conjunction with memory 125 to implement the methods of the present invention.

[0291] The memory 125, 325, which may include a data repository (or database), may be embodied in any number of forms, including being embodied in any computer or other machine-readable data storage medium, memory device, or other storage device or communication device for storage or communication of information, which is currently known or available in the future, including (but not limited to) a memory integrated circuit ("IC") or a memory portion of an integrated circuit (e.g., a resident memory within a processor 110, 300 or a processor IC), whether volatile or non-volatile, whether removable or non-removable, including (without limitation) RAM, FLASH, DRAM, SDRAM, SRAM, MRAM, FeRAM, ROM, EPROM, or E 2 PROM or any other form of memory device, such as a magnetic hard drive, optical drive, magnetic or tape drive, hard disk drive, other machine-readable storage device or storage medium, such as a floppy disk, CDRAM, CD-RW, digital versatile disk (DVD) or other optical storage or any other type of memory, storage medium or data storage device or circuit, which is or will become known depending on the embodiment selected. The memory 125, 325 may be suitable for storing various lookup tables, parameters, coefficients, other information and data, programs or instructions (of the software of the present invention) or other types of tables (such as database tables).

[0292] As indicated above, the processor 110, 300 is hardwired or programmed with the software and data structures of the present invention, for example, to perform the methods of the present invention. Thus, the systems and related methods of the present invention, including various instructions to configure the memory 160, may be embodied as software that provides such programming or other instructions (e.g., the instruction set and / or metadata embodied in a non-transitory computer-readable medium discussed above). Additionally, metadata may also be used to define various data structures of a lookup table or database. By way of example and without limitation, such software may be in the form of source code or object code. The source code may further be compiled into some form of instructions or object code (including assembly language instructions or configuration information). The software, source code, or metadata of the present invention may be embodied as any type of code, such as C, C++, Matlab, SystemC, LISA, XML, Java, Brew, SQL and variations thereof (e.g., SQL 99 or a proprietary version of SQL), DB2, Oracle, or any other type of programming language that performs the functionality discussed herein, including various hardware definition or hardware modeling languages ​​(e.g., Verilog, VHDL, RTL) and resulting database files (e.g., GDSII). Therefore, "construct", "program construct", "software construct" or "software" used equivalently herein means and refers to any programming language of any kind with any syntax or signature that provides or can be interpreted to provide (when instantiated or loaded into a processor or computer and executed, such as, including processors 110, 300) the specified associated functionality or methodologies.

[0293] The software, metadata or other source code, and any resulting bit files (object code, databases, or lookup tables) of the present invention may be embodied in any tangible, non-transitory storage medium, such as any of a computer or other machine-readable data storage medium, as computer-readable instructions, data structures, program modules, or other data, such as discussed above with respect to memory 125, 325, such as a floppy disk, CDROM, CD-RW, DVD, magnetic hard drive, optical drive, or any other type of data storage device or medium, as mentioned above.

[0294] The communication interface 130 is used to appropriately connect to relevant channels, networks or buses; for example, the communication interface 130 can provide impedance matching, drivers or other functions for cables or wireless interfaces, can provide demodulation and analog-to-digital conversion for wireless interfaces, and can provide physical interfaces for processors 110, 300 and / or memory 125 and other devices respectively. In general, the communication interface 130 is used to receive and transmit data, such as program instructions, parameters, configuration information, control messages, data and other related information depending on the selected embodiment.

[0295] The communication interface 130 may be implemented as known or may become known in the art to provide data communication between the HTF 200 and / or the processors 110, 300 and any type of network or external device, such as wireless, optical, or cable, and using any applicable standard (such as, by way of example and without limitation, various PCI, USB, RJ 45, Ethernet (Fast Ethernet, Gigabit Ethernet, 300ase-TX, 300ase-FX, etc.), IEEE 802.11, Bluetooth, WCDMA, WiFi, GSM, GPRS, EDGE, 3G, and one of the other standards and systems mentioned above), and may include impedance matching capabilities, voltage shifting for low voltage processors to interface with higher voltage control buses, wires or wireless transceivers, and various switching mechanisms (e.g., transistors) to turn various lines or connectors on or off in response to signaling from the processors 110, 300. In addition, the communication interface 130 may also be configured and / or adapted to receive and / or transmit signals external to the system 100, such as by hard wiring or RF or infrared signaling, for example, to receive information in real time for output, such as on a display. The communication interface 130 may provide a connection to any type of bus or network structure or media using any selected architecture. By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, an Enhanced ISA (EISA) bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a SAN bus, or any other communication or signaling media, such as Ethernet, ISDN, T1, satellite, wireless, etc.

[0296] The present invention will be considered as an example of the principles of the present invention and it is not intended to limit the present invention to the specific embodiments described. In this regard, it should be understood that the present invention is not limited in its application to the construction details described in the drawings or examples and the arrangement of components stated above and below. Systems, methods and devices consistent with the present invention can have other embodiments and can be practiced and implemented in various ways.

[0297] Although the present invention has been described with respect to specific embodiments of the present invention, these embodiments are only illustrative and do not limit the present invention. In the description herein, numerous specific details are provided, such as examples of electronic components, electronic and structural connections, material and structural changes, to provide a detailed understanding of embodiments of the present invention. However, those skilled in the relevant art will recognize that embodiments of the present invention may be practiced without using one or more of the specific details or using other equipment, system assemblies, components, materials, parts, etc. In other examples, well-known structures, materials or operations are not clearly shown or described in detail to avoid blurring the aspects of embodiments of the present invention. In addition, each figure is not drawn to scale and should not be considered as restrictive.

[0298] References throughout this specification to "one embodiment," "an embodiment," or a specific "embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention and is not necessary in all embodiments, and further, does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics of any particular embodiment of the invention may be combined in any suitable manner and in any suitable combination with one or more other embodiments, including the use of selected features without the corresponding use of other features. In addition, many modifications may be made to adapt specific applications, situations, or materials to the basic scope and spirit of the invention. It should be understood that various changes and modifications of the embodiments of the invention described and illustrated herein may be made in light of the teachings herein and should be considered part of the spirit and scope of the invention.

[0299] For the statement of numerical ranges herein, each intervening number having the same precision therebetween is expressly contemplated. For example, for the range 6 to 9, the numbers 7 and 8 are contemplated in addition to 6 and 9, and for the range 6.0 to 7.0, the numbers 6.0, 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, 6.7, 6.8, 6.9, and 7.0 are expressly contemplated. In addition, each intervening subrange within the range is contemplated, in any combination, and is within the scope of the invention. For example, for the range 5 to 10, the subranges 5 to 6, 5 to 7, 5 to 8, 5 to 9, 6 to 7, 6 to 8, 6 to 9, 6 to 10, 7 to 8, 7 to 9, 7 to 10, 8 to 9, 8 to 10, and 9 to 10 are contemplated and within the scope of the disclosed ranges.

[0300] It should also be understood that one or more of the elements depicted in the figure may also be implemented in a more separate or integrated manner, or in some cases, even removed or rendered inoperable, which may be useful depending on the specific application. Combinations of components formed as a whole are also within the scope of the present invention, especially for embodiments in which the separation or combination of discrete components is unclear or difficult to distinguish. In addition, the use of the term "coupled" in this article, including in its various forms such as "coupled" or "couplable", means and includes any direct or indirect electrical, structural or magnetic coupling, connection or attachment, or the adaptation or ability for such direct or indirect electrical, structural or magnetic coupling, connection or attachment, including components formed as a whole and components coupled via or through another component.

[0301] With respect to signals, reference is made herein to a parameter that "represents" or is "representative of" a given metric, where a metric is a measured value of the state of at least a portion of a regulator or its input or output. A parameter is considered to represent a metric if the parameter is directly related enough to the metric that adjusting the parameter will satisfactorily adjust the metric. A parameter may be considered to be an acceptable representation of the metric if it represents a multiple or fraction of the metric.

[0302] In addition, any signal arrows in the drawings / Figures shall be considered to be exemplary only and non-limiting, unless otherwise expressly mentioned. It will also be considered that the combination of components of the steps is within the scope of the present invention, especially when the ability to separate or combine is unclear or unforeseeable. As used herein and throughout the following claims, the disjunctive term "or" is generally intended to mean "and / or", with a combination and separation meaning (and not limited to the "mutually exclusive or" meaning), unless otherwise indicated. As used in the description herein and throughout the attached claims, "a / an" and "the" include plural references, unless the context clearly indicates otherwise. Moreover, as used in the description herein and throughout the attached claims, the meaning of "in..." includes "in..." and "on...", unless the context clearly indicates otherwise.

[0303] The foregoing description of the illustrated embodiments of the present invention (including that described in the Summary of the Invention and the Abstract) is not intended to be exhaustive or to limit the present invention to the precise form disclosed herein. It should be observed from the foregoing that numerous variations, modifications, and substitutions are desirable and can be achieved without departing from the spirit and scope of the novel concepts of the present invention. It should be understood that no limitation to the particular methods and apparatus described herein is intended or should be inferred. Of course, it is desired that all such modifications falling within the scope of the claims be covered by the appended claims.

Claims

1. A configurable circuit among a plurality of configurable circuits, each configurable circuit comprising: Configurable computing circuits; a control circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs, comprising a plurality of input registers; a plurality of synchronous network outputs, comprising a plurality of output registers; Features: The plurality of synchronization network outputs are directly coupled to the synchronization network inputs of adjacent configurable circuits of the plurality of configurable circuits through communication lines of the synchronization network; And further includes: a configuration memory coupled to the configurable computing circuit, the control circuit, the synchronous network input, and the synchronous network output, the configuration memory comprising: A first instruction memory storing a first plurality of data path configuration instructions for configuring an internal data path of the configurable computing circuit; and a second instruction and instruction index memory storing a second plurality of instructions and datapath configuration instruction indexes for selecting a current datapath configuration instruction from the first plurality of datapath configuration instructions from the first instruction memory and for selecting a master synchronization input of the plurality of synchronization network inputs to receive the current datapath configuration instruction or instruction index from another different configurable circuit.

2. The configurable circuit of claim 1 , wherein each instruction and data path configuration instruction index of the second plurality of instructions and data path configuration instruction indexes used to select the current data path configuration instruction from the first instruction memory of the configurable computing circuit is selected according to a predetermined cadence or count for execution by the configurable computing circuit.

3. The configurable circuit of claim 1 , wherein the second plurality of instructions and datapath configuration instruction indexes further include instructions for selecting a next datapath configuration instruction or index to output to the master synchronization input of a next configurable computing circuit.

4. The configurable circuit according to claim 1, further comprising: a control memory circuit coupled to the configurable computing circuit; and The control circuit comprises: memory control circuit; Thread control circuit; and Multiple control registers.

5. The configurable circuit according to claim 4, further comprising: an asynchronous network input queue coupled to an asynchronous packet network and the control memory circuit, the asynchronous network input queue receiving asynchronous network messages and packets routed on the asynchronous packet network; Asynchronous network output queue; a stop signal communication line directly coupled to all of the plurality of configurable circuits; and a flow control circuit coupled to the asynchronous network output queue, the flow control circuit being adapted to generate a stop signal on the stop signal communication line when the number of messages in the asynchronous network output queue has reached a predetermined threshold; Wherein in response to receipt of the stop signal, each of the plurality of configurable circuits suspends execution while continuing to receive one or more asynchronous network messages and packets routed over the asynchronous packet network.

6. The configurable circuit according to claim 3, further comprising: a conditional logic circuit coupled to the configurable computation circuit, wherein the conditional logic circuit is adapted to provide conditional branching by modifying a next data path instruction or a next data path instruction index to output a different next data path instruction or next data path instruction index to the primary synchronization input of the next configurable computation circuit, depending on an output from the configurable computation circuit.

7. The configurable circuit according to claim 1, wherein the control circuit comprises: memory control circuit; Thread control circuit; and A plurality of control registers, wherein the plurality of control registers stores a completion table, the completion table having a plurality of thread identifiers and, for each thread identifier of a current thread, further having a thread identifier identifying a next thread for execution after execution of the current thread to provide in-order thread execution.

8. The configurable circuit according to claim 1, wherein the control circuit comprises: memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a first data completion count; and Thread control circuitry is adapted to queue a thread for execution when its completion count for its thread identifier has been decremented to zero.

9. The configurable circuit according to claim 1, wherein the control circuit comprises: memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a first data completion count; and A thread control circuit is adapted to queue a thread for execution when its completion count has been decremented to zero for its thread identifier and it has a thread identifier identifying it as the next thread to be executed.

10. The configurable circuit according to claim 1, wherein the control circuit comprises: memory control circuit; Thread control circuit; and A plurality of control registers storing a completion table having a plurality of types of thread identifiers, wherein each type of thread identifier indicates a loop stage for loop and nested loop execution, and wherein the plurality of control registers further store a top of a thread identifier stack to allow each type of thread identifier to access private variables of a selected loop.

11. The configurable circuit according to claim 1 , wherein the control circuit comprises: memory control circuit; Multiple control registers; and A thread control circuit, comprising: a run queue that stores one or more thread identifiers of one or more computational threads that are ready to execute; a continuation queue that stores one or more thread identifiers of compute threads that have completion counts that are allowed to execute but that do not yet have assigned thread identifiers; and A reentrant queue that stores one or more thread identifiers of computing threads having completion counts allowed to execute and having assigned thread identifiers to provide continued execution of the computing threads in the reentrant queue after a specified count by moving the computing threads in the reentrant queue to the run queue ahead of any computing threads in the continuation queue.

12. The configurable circuit according to claim 1, further comprising: an asynchronous network input queue coupled to the asynchronous packet network; an asynchronous network output queue coupled to the asynchronous packet network; and The control circuit comprises: memory control circuit; a plurality of control registers storing a pool of thread identifiers and a completion table having loop counts for a valid number of loop threads; and Thread control circuitry, wherein in response to receipt of an asynchronous packet network message returning a thread identifier to the thread identifier pool, the control circuitry decrements the cycle count and transmits an asynchronous packet network completion message when the cycle count reaches zero.

13. The configurable circuit according to claim 1, further comprising: an asynchronous packet network coupled to said plurality of said configurable circuits; and Wherein one or more of the plurality of the configurable circuits are coupled in series with the corresponding synchronization network output coupled to the corresponding synchronization network input to form a first synchronization domain having a first basic block, and one or more of the plurality of the configurable circuits are coupled in series with the corresponding synchronization network output coupled to the corresponding synchronization network input to form a second synchronization domain having a second basic block, the plurality of configurable circuits are suitable for performing a plurality of calculations using the first and second synchronization domains, and the plurality of configurable circuits are further suitable for generating and transmitting a plurality of control messages through the asynchronous packet network, the plurality of control messages including one or more completion messages from the second synchronization domain and one or more continuation messages of the second basic block from the first synchronization domain to the second synchronization domain.

14. The configurable circuit according to claim 1, further comprising: Interconnection network; a processor coupled to the interconnection network; a host interface coupled to the interconnect network; and A plurality of configurable circuit clusters coupled to the interconnect network, each configurable circuit cluster of the plurality of configurable circuit clusters comprising: The plurality of configurable circuits are arranged in an array; an asynchronous packet network coupled to each configurable circuit of the plurality of configurable circuits of the array; a memory interface coupled to the asynchronous packet network and the interconnect network; and A dispatch interface is coupled to the asynchronous packet network and the interconnect network.

15. The configurable circuit of claim 1, further comprising: a hierarchical interconnection network comprising a first plurality of crossbar switches having a folded Claus configuration and a plurality of direct mesh connections at interfaces with endpoints; a processor coupled to the interconnection network; a host interface coupled to the interconnect network; and A plurality of configurable circuit clusters coupled to the interconnect network, each configurable circuit cluster of the plurality of configurable circuit clusters comprising: The plurality of configurable circuits are arranged in an array; wherein the synchronization network provides a plurality of direct connections and at least one transitive connection between adjacent configurable circuits of the plurality of configurable circuits arranged in the array; an asynchronous packet network comprising a second plurality of crossbar switches, each crossbar switch coupled to at least one configurable circuit of the plurality of configurable circuits of the array and another crossbar switch of the second plurality of crossbar switches; a memory interface coupled to the asynchronous packet network and the interconnect network; and A dispatch interface is coupled to the asynchronous packet network and the interconnect network.

16. A computing system comprising: Asynchronous packet networking; Synchronous network; and It is characterized by further comprising: a plurality of configurable circuits arranged in an array, each of the plurality of configurable circuits comprising a plurality of asynchronous inputs and asynchronous outputs coupled to the asynchronous packet network, each of the plurality of configurable circuits further comprising a plurality of synchronous inputs directly coupled to a plurality of synchronous outputs of adjacent configurable circuits of the plurality of configurable circuits through communication lines of the synchronous network; wherein one or more of the plurality of the configurable circuits are coupled in series with respective synchronization outputs coupled to respective synchronization inputs of other configurable circuits to form a first synchronization domain having a first basic block, and one or more of the plurality of the configurable circuits are coupled in series with respective synchronization outputs coupled to respective network inputs of other configurable circuits to form a second synchronization domain having a second basic block, the plurality of configurable circuits are adapted to perform a plurality of calculations using the first and second synchronization domains, and the plurality of configurable circuits are further adapted to generate and transmit a plurality of control messages through the asynchronous packet network, the plurality of control messages comprising one or more completion messages from the second synchronization domain and one or more continue messages of the second basic block from the first synchronization domain to the second synchronization domain; and Each of the plurality of configurable circuits further comprises: Configurable computing circuits; and a configuration memory coupled to the configurable computing circuit, the synchronous network input, and the synchronous network output, the configuration memory comprising: A first instruction memory storing a first plurality of data path configuration instructions for configuring an internal data path of the configurable computing circuit; and a second instruction and instruction index memory storing a second plurality of instructions and datapath configuration instruction indexes for selecting a current datapath configuration instruction from the plurality of datapath configuration instructions from the first instruction memory, for selecting a master synchronization input from the plurality of synchronization network inputs to receive the current datapath configuration instruction or instruction index from another different configurable circuit, and for selecting a next datapath configuration instruction or instruction index for output to the master synchronization input of a next configurable computing circuit.

17. The computing system of claim 16, wherein each of the plurality of configurable circuits comprises: a control memory circuit coupled to the configurable computing circuit; Asynchronous network input queue and asynchronous network output queue; and a control circuit coupled to the configurable computing circuit, the control circuit comprising: memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a first data completion count; and A thread control circuit is adapted to queue a thread for execution when its completion count has been decremented to zero for its thread identifier and its thread identifier is the next thread.

18. The computing system of claim 17, further comprising: a conditional logic circuit coupled to the configurable computation circuit, wherein the conditional logic circuit is adapted to provide conditional branching by modifying a next datapath configuration instruction or index to form and output a different next datapath instruction or index to the primary synchronization input of the next configurable computation circuit, depending on an output from the configurable computation circuit.

19. The computing system of claim 17, wherein the thread control circuit further comprises: a run queue that stores one or more thread identifiers of one or more computing threads ready for execution; a continuation queue that stores one or more thread identifiers of computing threads that have completion counts that are allowed to execute but do not yet have assigned thread identifiers; and A reentrant queue that stores one or more thread identifiers of computing threads having completion counts allowed to execute and having assigned thread identifiers to provide continued execution of the computing threads in the reentrant queue after a specified count by moving the computing threads in the reentrant queue to the run queue ahead of any computing threads in the continuation queue.

20. A computing system comprising: Interconnection network; a processor coupled to the interconnection network; Features: a host interface coupled to the interconnect network; and A plurality of configurable circuit clusters coupled to the interconnect network, each configurable circuit cluster of the plurality of configurable circuit clusters comprising: Synchronous network; Asynchronous packet networking; a memory interface coupled to the asynchronous packet network and the interconnect network; a dispatch interface coupled to the asynchronous packet network and the interconnect network; and A plurality of configurable circuits arranged in an array, each configurable circuit comprising: Configurable computing circuits; A control circuit coupled to the configurable computing circuit, the control circuit comprising: a memory control circuit; a thread control circuit; and a plurality of control registers; a first memory circuit coupled to the configurable computing circuit; a plurality of synchronous network inputs, comprising a plurality of input registers; a plurality of synchronization network outputs, comprising a plurality of output registers, the plurality of synchronization network outputs being directly coupled to the synchronization network inputs of adjacent configurable circuits of the plurality of configurable circuits through communication lines of the synchronization network; an asynchronous network input queue and an asynchronous network output queue coupled to the asynchronous packet network; a second memory circuit coupled to the configurable computing circuit, the control circuit, the synchronization network input, and the synchronization network output, the second memory circuit comprising: A first instruction memory storing a first plurality of data path configuration instructions for configuring an internal data path of the configurable computing circuit; and a second instruction and instruction index memory storing a second plurality of instructions and datapath configuration instruction indexes for selecting a current datapath configuration instruction from the plurality of datapath configuration instructions from the first instruction memory, for selecting a master synchronization input from the plurality of synchronization network inputs to receive the current datapath configuration instruction or instruction index from another different configurable circuit, and for selecting a next datapath configuration instruction or instruction index for output to a next configurable computing circuit, wherein each instruction and datapath configuration instruction index of the second plurality of instructions and datapath configuration instruction indexes for selecting the current datapath configuration instruction from the first instruction memory of the configurable computing circuit is selected according to a predetermined rhythm or count for execution by the configurable computing circuit.

Images