Integrated Circuit Devices

Abstract

An integrated circuit (IC) device includes: a fin-type active region extending longitudinally in a first direction; a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region; and a source / drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets includes a first nanosheet that is closest to the fin top surface of the fin-type active region among the plurality of nanosheets and has the shortest length in the first direction. The source / drain region includes a source / drain main region and a first source / drain protruding region protruding from the source / drain main region. The first source / drain protruding region protrudes from the source / drain main region toward the first nanosheet and overlaps with a portion of the plurality of nanosheets in the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0055843 filed on May 13, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept relate to an integrated circuit (IC) device, and more particularly, to an IC device including a horizontal nanosheet field effect transistor (hNSFET). Background Art

[0004] As the size of IC devices decreases, it may be desirable to increase the integration density of FETs on a substrate. Therefore, hNSFETs including a plurality of horizontal nanosheets stacked on the same layout area have been developed. However, when current is concentrated in a specific channel layer among a plurality of channel layers formed in a plurality of horizontal nanosheets, even if the number of stacks of channel layers included in the hNSFET increases, the current flowing in the on-state of the transistor (i.e., the on-current) may not increase in proportion to the number of stacks of channel layers. Summary of the invention

[0005] The inventive concept provides an integrated circuit (IC) device that can reduce or minimize a deviation in the amount of current flowing through a nanosheet in an on-state of a nanosheet field effect transistor (FET) and can improve its on-state performance.

[0006] According to one aspect of the inventive concept, an IC device is provided, comprising: a fin-type active region extending longitudinally in a first direction; a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region; and a source / drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets includes a first nanosheet that is closest to the fin top surface of the fin-type active region among the plurality of nanosheets and has the shortest length in the first direction. The source / drain region includes a source / drain main region and a first source / drain protruding region protruding from the source / drain main region. The first source / drain protruding region protrudes from the source / drain main region toward the first nanosheet and overlaps with portions of the plurality of nanosheets in the second direction.

[0007] According to another aspect of the inventive concept, an IC device is provided, comprising: a fin-type active region extending longitudinally in a first direction; a pair of nanosheet stacks, each of the nanosheet stacks comprising a plurality of nanosheets overlapping each other in a second direction on the fin-type active region; and a source / drain region between the pair of nanosheet stacks on the fin-type active region. The plurality of nanosheets comprises a first nanosheet that is closest to the fin-type active region and has the shortest length in the first direction among the plurality of nanosheets. The source / drain region comprises: a source / drain main region that does not overlap with the pair of nanosheet stacks in the second direction; and a pair of first source / drain protruding regions that protrude in opposite directions from the source / drain main region toward a first nanosheet of each of the pair of nanosheet stacks.

[0008] According to another aspect of the inventive concept, an IC device is provided, comprising: a fin-type active region extending longitudinally in a first direction; a pair of source / drain regions located on the fin-type active region; and a plurality of nanosheets overlapping each other in a second direction between the pair of source / drain regions and on the fin-type active region. The plurality of nanosheets include a first nanosheet and a second nanosheet having different lengths in the first direction. Each of the pair of source / drain regions includes at least one source / drain protruding region protruding toward the plurality of nanosheets. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 shows a planar layout of some components of an integrated circuit (IC) device according to some embodiments of the inventive concept;

[0011] Figure 2A is along Figure 1 A cross-sectional view taken along line XX';

[0012] Figure 2B yes Figure 2A An enlarged cross-sectional view of a local area indicated by "X1" in FIG.

[0013] Figure 3 is a cross-sectional view of an IC device according to some embodiments of the present invention, which is Figure 2A An enlarged cross-sectional view of a region corresponding to the partial region indicated by "X1" in FIG.

[0014] Figure 4 is a cross-sectional view of an IC device according to some embodiments of the present invention, which is Figure 2A An enlarged cross-sectional view of a region corresponding to the partial region indicated by "X1" in FIG. FIG. 5A to FIG. 5Qare cross-sectional views illustrating a process sequence of a method for manufacturing an IC device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0015] The embodiments of the present invention will now be described with reference to the accompanying drawings showing some embodiments. The same reference numerals in the accompanying drawings represent the same elements, and therefore, their description will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be understood that when an element is referred to as "on" another element, "attached" to another element, "connected" to another element, "coupled" to another element, "contacted" to another element, etc., it can be directly on another element, attached to another element, connected to another element, coupled to another element or contacted to another element, or there may also be an intermediate element. On the contrary, when an element is referred to as, for example, "directly on another element", "directly attached" to another element, "directly connected" to another element, "directly coupled" to another element or "directly contacted" to another element, there is no intermediate element. It should be noted that, although not specifically described with respect to this, the various aspects described for an embodiment can be incorporated into different embodiments. That is, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination.

[0016] Some embodiments of the inventive concept arise from the recognition that in a multi-bridge channel field effect transistor (MBCFET), current may be concentrated in the top channel near the contact due to the source / drain resistance at the junction cross section. As a result, increasing the number of layers in the channel stack may not result in an increase in the on-current in proportion to the increase in the number of layers in the stack. Some embodiments of the inventive concept may provide an integrated circuit device including a channel structure that reduces the variation in current flowing through each of a plurality of stacked nanosheets forming the channel structure. According to different embodiments of the inventive concept, various techniques may be used to reduce such variation in current flow, including, for example, designing the band gap of the nanosheet closest to the active area to be lower than other nanosheets in the stack and / or reducing the length of the nanosheet closest to the active area relative to other nanosheets in the stack. In other embodiments, different doping profiles and / or Ge or Ga content profiles may be used in the nanosheets to improve current dispersion throughout the nanosheet stack.

[0017] Figure 1 A planar layout of some components of an integrated circuit (IC) device 100 according to some embodiments of the inventive concept is shown. Figure 2A is along Figure 1 A cross-sectional view taken along line XX', Figure 2B yes Figure 2A An enlarged cross-sectional view of a partial area X1 in FIG.

[0018] Reference Figure 1 , Figure 2A and Figure 2B , the IC device 100 may include: a plurality of fin-type active areas FA, which protrude from the substrate 102 and extend in a first horizontal direction (X direction); and a plurality of nanosheet stacks NSS, which are separated from the plurality of fin-type active areas FA and face the fin top surfaces FT of the plurality of fin-type active areas FA. As used herein, the term "nanosheet" refers to a conductive structure having a cross section substantially perpendicular to the direction of current flow. The nanosheet may be interpreted as including nanowires.

[0019] The substrate 102 may include one or more semiconductors (e.g., silicon (Si) or germanium (Ge)) and / or one or more compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), or indium phosphide (InP)). The trench T1 may be formed in the substrate 102 to define a plurality of fin-type active areas FA and may be at least partially filled by a device isolation film 114. The device isolation film 114 may include an oxide film, a nitride film, or a combination thereof.

[0020] A plurality of gate lines 160 may be located on a plurality of fin-type active areas FA and extend in a second horizontal direction (Y direction) intersecting with a first horizontal direction (X direction). In some embodiments, the first horizontal direction and the second horizontal direction may be perpendicular to each other. A plurality of nanosheet stacks NSS may be located on the fin top surfaces FT of the plurality of fin-type active areas FA, at intersections between the plurality of fin-type active areas FA and the plurality of gate lines 160, respectively. A plurality of nanosheet stacks NSS may be separated from the fin-type active areas FA and face the fin top surfaces FT of the plurality of fin-type active areas FA. Each of the plurality of nanosheet stacks NSS may include a plurality of nanosheets (e.g., first to third nanosheets N1, N2, and N3) overlapping each other in a vertical direction (Z direction) on the fin top surface FT of the fin-type active area FA. The first to third nanosheets N1, N2, and N3 may have different respective distances (i.e., Z direction distances) from the fin top surface FT of the fin-type active area FA. The first nanosheet N1 , the second nanosheet N2 , and the third nanosheet N3 may be sequentially stacked on the fin top surface FT of the fin type active area FA in the order set forth.

[0021] although Figure 1An example is shown in which the planar shape of the nanosheet stack NSS has a substantially quadrilateral shape, but the embodiments of the inventive concept are not limited thereto. The nanosheet stack NSS may have various planar shapes according to the planar shape of the fin-type active area FA and the planar shape of each gate line 160. This example shows a case where a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are formed on one fin-type active area FA and a plurality of nanosheet stacks NSS may be located in a row on one fin-type active area FA in the first horizontal direction (X direction). However, according to some embodiments of the inventive concept, the number of nanosheet stacks NSS located on one fin-type active area FA may not be specifically limited. For example, one nanosheet stack NSS may be formed on one fin-type active area FA. This example shows a case in which each of the plurality of nanosheet stacks NSS includes three nanosheets, but the embodiments of the inventive concept are not limited thereto. For example, the nanosheet stack NSS may include at least two nanosheets, and the number of nanosheets included in the nanosheet stack NSS may not be specifically limited.

[0022] Each of the first to third nanosheets N1, N2, and N3 may have a channel region. In some embodiments, each of the first to third nanosheets N1, N2, and N3 may have a thickness selected in the range of about 4.5 nm to about 5.5 nm, but the embodiments of the present inventive concept are not limited thereto. Here, the thickness of each of the first to third nanosheets N1, N2, and N3 may refer to the size of each of the first to third nanosheets N1, N2, and N3 in the vertical direction (Z direction). In some embodiments, the first to third nanosheets N1, N2, and N3 may have substantially the same thickness. In some other embodiments, at least some of the first to third nanosheets N1, N2, and N3 may have different thicknesses.

[0023] At least some of the first to third nanosheets N1, N2, and N3 may have different sizes in the first horizontal direction (X direction). The first nanosheet N1 closest to the fin top surface FT among the first to third nanosheets N1, N2, and N3 may have a minimum length LN1 in the first horizontal direction (X direction). The length of each of the second nanosheet N2 and the third nanosheet N3 in the first horizontal direction (X direction) may be greater than the length LN1 of the first nanosheet N1. In some embodiments, the second nanosheet N2 and the third nanosheet N3 may have substantially the same length.

[0024] As described above, the first nanosheet N1 closest to the fin-type active area FA among the first to third nanosheets N1, N2, and N3 may have the smallest length LN1, and therefore, the effective channel length of the channel formed in the first nanosheet N1 may be relatively reduced. Therefore, compared with the case where the first nanosheet N1 has the same length as the second nanosheet N2 and the third nanosheet N3, the amount of current flowing through the first nanosheet N1 may be increased at the same operating voltage. Therefore, the thickness and length of the nanosheets N1, N2, and N3 may affect the amount of current flowing therethrough, with a decrease in thickness and an increase in length causing less current to flow, and an increase in thickness and a decrease in length causing more current to flow.

[0025] A plurality of recesses R1 may be formed in an upper portion of the fin-type active region FA, and a plurality of source / drain regions 134 may be formed on the plurality of recesses R1. The plurality of source / drain regions 134 may include an epitaxially grown semiconductor layer. For example, the plurality of source / drain regions 134 may include a Group IV semiconductor, a Group IV compound semiconductor, or a Group III-V compound semiconductor.

[0026] The plurality of source / drain regions 134 may be doped with n-type dopants or p-type dopants. In some embodiments, the plurality of source / drain regions 134 may include a Si layer or a SiGe layer. In this case, the plurality of source / drain regions 134 may be doped with an n-type dopant selected from phosphorus (P), arsenic (As) and / or antimony (Sb) or a p-type dopant selected from boron (B) and / or gallium (Ga). In some other embodiments, the plurality of source / drain regions 134 may include an InGaAs layer or an InGaSb layer. In this case, the plurality of source / drain regions 134 may be doped with an n-type dopant selected from silicon (Si), sulfur (S), selenium (Se) and / or tellurium (Te).

[0027] In some embodiments, each of the plurality of source / drain regions 134 may include a plurality of semiconductor layers having different dopant concentrations. For example, each of the plurality of source / drain regions 134 may have a dopant concentration that decreases in a direction toward the fin-type active area FA and the first to third nanosheets N1, N2, and N3, and may have a dopant concentration that increases in a direction away from the fin-type active area FA and the first to third nanosheets N1, N2, and N3. In some embodiments, the dopant concentration may decrease monotonically in a direction toward the fin-type active area FA, and may increase monotonically in a direction away from the fin-type active area FA.

[0028] Each of the plurality of source / drain regions 134 may include a source / drain main region 134M located on the recess R1 and a source / drain protruding region 134P integrally connected to the source / drain main region 134M and protruding from the source / drain main region 134M toward the first nanosheet N1. The source / drain protruding region 134P may be in contact with the first nanosheet N1. The plurality of source / drain regions 134 may face the first to third nanosheets N1, N2, and N3 in the first horizontal direction (X direction). One source / drain region 134 may include a pair of source / drain protruding regions 134P, which protrude in opposite directions toward the first nanosheet N1 of each of a pair of nanosheet stacks NSS adjacent to each other on both sides of the one source / drain region 134. The source / drain main region 134M may not overlap with a pair of nanosheet stacks NSS adjacent to it on both sides of the source / drain region 134 in the vertical direction (Z direction). The source / drain protrusion region 134P may overlap portions of the first to third nanosheets N1 , N2 , and N3 included in the nanosheet stack NSS in the vertical direction (Z direction).

[0029] The length LN1 of the first nanosheet N1 may be defined in the first horizontal direction (X direction) by two source / drain protruding regions 134P respectively contacting two sidewalls of the first nanosheet N1. The length LN1 of the first nanosheet N1 may be less than the maximum length L1 of the nanosheet stack NSS in the first horizontal direction (X direction). In some embodiments, the length LP of the source / drain protruding region 134P may be less than 1 / 2 of the length LN1 of the first nanosheet N1. In some embodiments, the length LN1 of the first nanosheet N1 may be at least twice the length LP of the source / drain protruding region 134P, but embodiments of the inventive concept are not limited thereto.

[0030] The gate line 160 may be located on the fin-type active area FA to at least partially cover the nanosheet stack NSS and at least partially surround each of the first to third nanosheets N1, N2, and N3. Each of the plurality of gate lines 160 may include: a main gate portion 160M, which at least partially covers the top surface of the nanosheet stack NSS and extends in the second horizontal direction (Y direction); and a plurality of sub-gate portions 160S, which are integrally connected to the main gate portion 160M and are located one by one between the first to third nanosheets N1, N2, and N3 and between the fin-type active area FA and the first nanosheet N1. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M. In some embodiments, the first to third nanosheets N1, N2, and N3 may be completely surrounded by the gate line 160 in the Z direction and have a gate-around (GAA) structure. That is, the first to third nanosheets N1 , N2 , and N3 are located between the main gate portion 160M and the lowest one of the plurality of sub-gate portions 160S with respect to the substrate 102 in the Z direction.

[0031] The gate line 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), cobalt (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and / or palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and / or tantalum nitride (TaN). The metal carbide may be titanium aluminum carbide (TiAlC).

[0032] The gate dielectric film 152 may be between the nanosheet stack NSS and the gate line 160. In some embodiments, the gate dielectric film 152 may include a stacked structure of an interface film and a high-k dielectric film. The interface film may include a low-k dielectric material film having a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some embodiments, the interface film may be omitted. The high-k dielectric film may include a material having a dielectric constant higher than that of the silicon oxide film. For example, the high-k dielectric film may have a dielectric constant of about 10 to about 25. The high-k dielectric film may include hafnium oxide, but embodiments of the inventive concept are not limited thereto.

[0033] A plurality of nanosheet transistors TR1 may be formed at intersections between a plurality of fin-type active areas FA and a plurality of gate lines 160 on a substrate 102. Among the plurality of nanosheet transistors TR1, the first nanosheet N1 closest to the fin-type active area FA among the first to third nanosheets N1, N2, and N3 may have the shortest length LN1, so that the effective channel length of the channel formed in the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 may be less than the effective length of the channel formed in the other nanosheets. Therefore, the resistance of the first nanosheet N1 may be relatively reduced, and the amount of current flowing through the first nanosheet N1 may be increased at the same operating voltage. As a result, the deviation of the amount of current flowing through the first to third nanosheets N1, N2, and N3 in the on-state of the nanosheet transistor TR1 may be reduced or minimized, and therefore, the performance of the IC device 100 in the on-state may be improved or optimized.

[0034] In some embodiments, the first to third nanosheets N1, N2, and N3 may include a semiconductor layer having the same element. In an example, each of the first to third nanosheets N1, N2, and N3 may include a Si layer. In another example, each of the first to third nanosheets N1, N2, and N3 may include a SiGe layer.

[0035] In some other embodiments, the first to third nanosheets N1, N2, and N3 may include semiconductor layers including different elements. For example, the first nanosheet N1 may include a SiGe layer, and the second and third nanosheets N2 and N3 may include a Si layer.

[0036] In some other embodiments, the first to third nanosheets N1 , N2 , and N3 may include semiconductor layers having different dopant concentrations.

[0037] For example, the first to third nanosheets N1, N2, and N3 may include a semiconductor element selected from group IV semiconductor elements such as Si and Ge. In this case, the first nanosheet N1 may include a doped semiconductor layer, and the second and third nanosheets N2 and N3 may include an undoped semiconductor layer. In an example, the first nanosheet N1 may include a silicon layer doped with an n-type dopant or a p-type dopant, and the second and third nanosheets N2 and N3 may include an undoped silicon layer. For example, the first nanosheet N1 may be doped with a dopant of the same conductivity type as the conductivity type of the plurality of source / drain regions 134. In an example, the first nanosheet N1 may include a Si layer doped with an n-type dopant, the second and third nanosheets N2 and N3 may include an undoped Si layer, and the plurality of source / drain regions 134 may include a Si layer doped with an n-type dopant. In another example, the first nanosheet N1 may include a Si layer doped with a p-type dopant, the second nanosheet N2 and the third nanosheet N3 may include an undoped Si layer, and the plurality of source / drain regions 134 may include a SiGe layer doped with a p-type dopant. In the Si layer doped with an n-type dopant, the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof, but embodiments of the present invention are not limited thereto. In the Si layer doped with a p-type dopant and the SiGe layer doped with a p-type dopant, the p-type dopant may include boron (B), gallium (Ga), or a combination thereof, but embodiments of the present invention are not limited thereto. For example, the dopant concentration of the Si layer may be about 1×10 18 cm -3 About 1×10 21 cm -3 , but the embodiments of the inventive concept are not limited thereto.

[0038] In some other embodiments, the first to third nanosheets N1, N2, and N3 may include a compound semiconductor selected from a group IV compound semiconductor and a group III-V compound semiconductor. In this case, the first nanosheet N1 may include a doped compound semiconductor layer, and the second nanosheet N2 and the third nanosheet N3 may include an undoped compound semiconductor layer. The group III-V compound semiconductor may be a binary, ternary, or quaternary group III-V compound semiconductor including two, three, or four elements selected from group III semiconductors and group V semiconductors. For example, the first to third nanosheets N1, N2 and N3 may be selected from group IV compound semiconductors such as silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), germanium tin (GeSn), silicon tin (SiSn) and silicon germanium tin (SiGeSn), and group III-V compound semiconductors such as indium gallium arsenide (InGaAs), indium gallium antimonide (InGaSb), indium arsenide (InAs), indium phosphide (InP), gallium arsenide phosphide (GaAsP) and indium gallium phosphide (GaInP), but the embodiments of the inventive concept are not limited thereto.

[0039] In an example, the first to third nanosheets N1, N2, and N3 may include SiGe layers. In this case, the first nanosheet N1 may include a SiGe layer doped with an n-type or p-type dopant, and the second and third nanosheets N2 and N3 may include undoped SiGe layers. The conductivity type of the doped SiGe layer may be the same as the conductivity type of the plurality of source / drain regions 134.

[0040] In another example, the first to third nanosheets N1, N2, and N3 may include an InGaAs layer. In this case, the first nanosheet N1 may include an InGaAs layer doped with an n-type or p-type dopant, and the second and third nanosheets N2 and N3 may include an undoped InGaAs layer. The conductivity type of the doped InGaAs layer may be the same as the conductivity type of the plurality of source / drain regions 134.

[0041] In another example, the first to third nanosheets N1, N2, and N3 may include an InGaSb layer. In this case, the first nanosheet N1 may include an InGaSb layer doped with an n-type or p-type dopant, and the second and third nanosheets N2 and N3 may include an undoped InGaSb layer. The conductivity type of the doped InGaSb layer may be the same as the conductivity type of the plurality of source / drain regions 134.

[0042] As in the above example, when the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 closest to the fin-type active region FA includes a semiconductor layer doped with a dopant having the same conductivity type as the conductivity type of the plurality of source / drain regions 134 and the second nanosheet N2 and the third nanosheet N3 include undoped semiconductor layers, in the on-state of the nanosheet transistor TR1, the first nanosheet N1 can form a junctionless channel and the second nanosheet N2 and the third nanosheet N3 can form a p-n junction-based channel. As used herein, the term "junctionless" means that there is no doped p-n junction in the channel at the boundary of the nanosheet transistor TR1. The junctionless channel can include a region having a relatively high dopant concentration and a region having a relatively low dopant concentration with the same conductivity type. In the on-state of the nanosheet transistor TR1, only the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 closest to the fin-type active region FA can form a junctionless channel. Therefore, the amount of current flowing through the first nanosheet N1 can increase.

[0043] In some other embodiments, the first to third nanosheets N1, N2, and N3 can include the same group-IV compound semiconductor layer. In this case, at least some of the first to third nanosheets N1, N2, and N3 can include group-IV compound semiconductor layers having different compositions. In an example, the first to third nanosheets N1, N2, and N3 can include Si 1-x Ge x (0 < x < 1). In this case, the Ge content ratio (the value of x) of the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 can be higher than the Ge content ratio (the value of x) of the nanosheets other than the first nanosheet N1. In another example, the first to third nanosheets N1, N2, and N3 can include Si 1-x Ge x (0 < x < 1). In this case, the Ge content ratio (the value of x) can gradually increase in the direction toward the fin-type active region FA. For example, the first nanosheet N1 can include Si 0.55 Ge 0.45 , the second nanosheet N2 can include Si 0.65 Ge 0.35 , and the third nanosheet N3 can include Si 0.75 Ge 0.25, but embodiments of the inventive concept are not limited thereto. As described above, since the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 closest to the fin-type active region FA may have the highest Ge content ratio, the bandgap of the first nanosheet N1 may be lower than the bandgaps of other nanosheets in the on-state of the plurality of nanosheet transistors TR1. Accordingly, in the on-state of the nanosheet transistor TR1, the amount of current flowing through the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 closest to the fin-type active region FA may increase. As a result, the deviation in the amount of current flowing through the first to third nanosheets N1, N2, and N3 in the on-state of the nanosheet transistor TR1 may be reduced or minimized, and thus, the performance of the IC device 100 in the on-state may be improved or optimized.

[0044] In some other embodiments, the first to third nanosheets N1, N2, and N3 may include the same III-V compound semiconductor layer. In this case, at least some of the first to third nanosheets N1, N2, and N3 may include III-V compound semiconductor layers having different compositions. In an example, the first to third nanosheets N1, N2, and N3 may include In 1-y Ga y As (0 < y < 1). In this case, the Ga content ratio (value of y) of the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 may be lower than the Ga content ratio (value of y) of the nanosheets other than the first nanosheet N1. The Ga content ratio (value of y) of the first to third nanosheets N1, N2, and N3 may gradually decrease in a direction toward the fin-type active region FA, while the In content ratio of the first to third nanosheets N1, N2, and N3 may gradually increase in a direction toward the fin-type active region FA. For example, the first nanosheet N1 may include In 0.80 Ga 0.20 As, the second nanosheet N2 may include In 0.65 Ga 0.35 As, and the third nanosheet N3 may include In 0.53 Ga 0.47 As, but embodiments of the inventive concept are not limited thereto.

[0045] In another example, the first to third nanosheets N1, N2, and N3 may include In 1-z Ga zSb (0 < z < 1). In this case, the Ga content ratio (value of z) of the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 may be lower than the Ga content ratio (value of z) of the nanosheets other than the first nanosheet N1. The Ga content ratio (value of z) of the first to third nanosheets N1, N2, and N3 may gradually decrease in the direction toward the fin-type active region FA. For example, the first nanosheet N1 may include In 0.80 Ga 0.20 Sb, the second nanosheet N2 may include In 0.65 Ga 0.35 Sb, and the third nanosheet N3 may include In 0.53 Ga 0.47 Sb, but embodiments of the inventive concept are not limited thereto.

[0046] As in the above example, since the first nanosheet N1 closest to the fin-type active region FA among the first to third nanosheets N1, N2, and N3 has the lowest Ga content ratio, the bandgap of the first nanosheet N1 may become lower than the bandgaps of the other nanosheets in the on state of the plurality of nanosheet transistors TR1. Therefore, in the on state of the nanosheet transistor TR1, the amount of current flowing through the first nanosheet N1 closest to the fin-type active region FA among the first to third nanosheets N1, N2, and N3 may increase. As a result, the deviation of the amount of current flowing through the first to third nanosheets N1, N2, and N3 in the on state of the nanosheet transistor TR1 may be reduced or minimized, and thus, the performance of the IC device 100 in the on state may be improved or optimized.

[0047] A metal silicide film 182 may be formed on the top surface of each of the plurality of source / drain regions 134. The metal silicide film 182 may include titanium silicide, but embodiments of the inventive concept are not limited thereto. The metal silicide film 182 may be omitted.

[0048] Both sidewalls of each of the plurality of gate lines 160 may be at least partially covered by a plurality of outer insulating spacers 118. The plurality of outer insulating spacers 118 may at least partially cover both sidewalls of the main gate portion 160M on the plurality of nanosheet stacks NSS. The plurality of outer insulating spacers 118 and the plurality of source / drain regions 134 may be at least partially covered by a protective insulating film 142. Each of the outer insulating spacers 118 and the protective insulating film 142 may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), silicon dioxide (SiO 2 ) or a combination thereof. In some embodiments, the protective insulating film 142 may be omitted.

[0049] A plurality of inner insulating spacers 120 may be between the first to third nanosheets N1, N2, and N3 and between the fin-type active area FA and the first nanosheet N1. Both sidewalls of each of the plurality of sub-gate portions 160S may be at least partially covered by the inner insulating spacer 120 via the gate dielectric film 152. The plurality of inner insulating spacers 120 may overlap the source / drain protruding region 134P between the plurality of sub-gate portions 160S and the plurality of source / drain main regions 134M and in the vertical direction (Z direction). The source / drain protruding region 134P may contact the first nanosheet N1 and define the length of the first nanosheet N1 in the first horizontal direction (X direction). In the first horizontal direction (X direction), the maximum length L1 of the nanosheet stack NSS may be substantially equal to the distance 120L between the two outermost sidewalls of the inner insulating spacer 120 located on both sides of each of the plurality of sub-gate portions 160S of the gate line 160.

[0050] In some embodiments, the outer insulating spacer 118 may include the same material as the inner insulating spacer 120. In some other embodiments, the outer insulating spacer 118 may include a different material than the inner insulating spacer 120. The inner insulating spacer 120 may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO 2 Or a combination thereof. The inner insulating spacer 120 may further include an air gap.

[0051] The inter-gate dielectric film 144 and the inter-layer insulating film 174 may be sequentially formed on the protective insulating film 142. Each of the inter-gate dielectric film 144 and the inter-layer insulating film 174 may include a silicon oxide film.

[0052] A plurality of contact plugs 184 may be located inside a plurality of contact holes 180 that pass through the interlayer insulating film 174, the inter-gate dielectric film 144, and the protective insulating film 142. The plurality of contact plugs 184 may be connected to the plurality of source / drain regions 134 through the plurality of metal silicide films 182. Each contact plug 184 may include a metal, a conductive metal nitride, or a combination thereof. For example, each contact plug 184 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), an alloy thereof, or a combination thereof.

[0053] In the IC device 100, since the first nanosheet N1 closest to the fin-type active area FA among the first to third nanosheets N1, N2, and N3 has the shortest length, the effective channel length of the channel formed in the first nanosheet N1 can be reduced. Therefore, compared with the case where the first nanosheet N1 has the same length as the second nanosheet N2 and the third nanosheet N3, the amount of current flowing through the first nanosheet N1 under the same operating voltage can be increased. For example, when the first nanosheet N1 includes a semiconductor layer doped with a dopant of the same conductivity type as the plurality of source / drain regions 134, only the first nanosheet N1 among the first to third nanosheets N1, N2, and N3 can be configured to selectively form a junction-free channel in the on-state of the nanosheet transistor TR1, and therefore, the amount of current flowing through the first nanosheet N1 can be increased. In addition, when the first to third nanosheets N1, N2, and N3 include a compound semiconductor layer including Ge or Ga, the first nanosheet N1 may be controlled to have the highest Ge content ratio or the lowest Ga content ratio among the first to third nanosheets N1, N2, and N3. Therefore, the band gap of the first nanosheet N1 may be controlled to be lower than the band gaps of other nanosheets in the on-state of the plurality of nanosheet transistors TR1, and thus, the amount of current flowing through the first nanosheet N1 may be increased. As a result, the deviation of the amount of current flowing through the first to third nanosheets N1, N2, and N3 in the on-state of the nanosheet transistor TR1 may be reduced or minimized, and thus, the performance of the IC device 100 in the on-state may be improved or optimized.

[0054] Figure 3 is a cross-sectional view of an IC device 200 according to some embodiments of the present inventive concept, which is Figure 2A An enlarged cross-sectional view of the area corresponding to the partial area X1 in FIG.

[0055] Reference Figure 3 , the IC device 200 may have a reference Figure 1 , Figure 2A and Figure 2B The IC device 100 described above has substantially the same configuration. However, the IC device 200 may include a plurality of nanosheet stacks NSS2 facing the fin top surfaces FT of the plurality of fin-type active areas FA. The plurality of nanosheet stacks NSS2 may include a first nanosheet N21, a second nanosheet N22, and a third nanosheet N23 sequentially stacked on the fin top surfaces FT of the fin-type active areas FA. The maximum length L2 of each of the plurality of nanosheet stacks NSS2 in the first horizontal direction (X direction) may be less than the distance 120L between the two outermost sidewalls of the inner insulating spacer 120 located on both sides of each of the plurality of sub-gate portions 160S of the gate line 160.

[0056] The first nanosheet N21 closest to the fin top surface FT among the first to third nanosheets N21 , N22 , and N23 may have the shortest length in the first horizontal direction (X direction), and the second and third nanosheets N22 and N23 may have substantially the same length.

[0057] The IC device 200 may include a plurality of source / drain regions 234. Each of the plurality of source / drain regions 234 may include: a source / drain main region 234M, which is located on the recess R1; and first to third source / drain protruding regions 234P1, 234P2, and 234P3, which are integrally connected to the source / drain main region 234M and protrude from the source / drain main region 234M toward the first to third nanosheets N21, N22, and N23. The first to third source / drain protruding regions 234P1, 234P2, and 234P3 may be in physical contact with the first to third nanosheets N21, N22, and N23, respectively. One source / drain region 234 may include a pair of first source / drain protruding regions 234P1, a pair of second source / drain protruding regions 234P2, and a pair of third source / drain protruding regions 234P3. The pair of first source / drain protruding regions 234P1 may protrude in opposite directions toward a first nanosheet N21 of each of a pair of nanosheet stacks NSS2 adjacent to each other on both sides of the source / drain region 234. The pair of second source / drain protruding regions 234P2 may protrude in opposite directions toward a second nanosheet N22 of each of a pair of nanosheet stacks NSS2. The pair of third source / drain protruding regions 234P3 may protrude in opposite directions toward a third nanosheet N23 of each of a pair of nanosheet stacks NSS2. In the first horizontal direction (X direction), the lengths LP22 of the second and third source / drain protrusion regions 234P2 and 234P3 may be substantially equal or similar and smaller than the length LP21 of the first source / drain protrusion region 234P1 .

[0058] The detailed configuration and effects of the plurality of nanosheet stacks NSS2 and the plurality of source / drain regions 234 may be referred to in Figure 1 , Figure 2A and Figure 2B The plurality of nanosheet stacks NSS and the plurality of source / drain regions 134 are described to be the same or similar.

[0059] Figure 4 is a cross-sectional view of an IC device 300 according to some embodiments of the present inventive concept, which is similar to Figure 2A An enlarged cross-sectional view of the area corresponding to the partial area X1 in FIG.

[0060] Reference Figure 4, the IC device 300 may have a reference Figure 1 , Figure 2A and Figure 2B The IC device 100 described above has substantially the same configuration. However, the IC device 300 may include a plurality of nanosheet stacks NSS3 facing the fin top surfaces FT of the plurality of fin-type active areas FA. The plurality of nanosheet stacks NSS3 may include a first nanosheet N31, a second nanosheet N32, and a third nanosheet N33 sequentially stacked on the fin top surfaces FT of the fin-type active areas FA. In the first horizontal direction (X direction), the maximum length L3 of the plurality of nanosheet stacks NSS3 may be less than the distance 120L between the two outermost walls of the inner insulating spacer 120 located on both sides of each of the plurality of sub-gate portions 160S of the gate line 160.

[0061] The first to third nanosheets N31, N32, and N33 may have different lengths in the horizontal direction (X direction). The first nanosheet N31 closest to the fin top surface FT among the first to third nanosheets N31, N32, and N33 may have the shortest length, and the lengths of the second nanosheets N32 and the third nanosheets N33 may increase in a direction away from the fin top surface FT.

[0062] The IC device 300 may include a plurality of source / drain regions 334. Each of the plurality of source / drain regions 334 may include: a source / drain main region 334M, which is located on the recess R1; and first to third source / drain protruding regions 334P1, 334P2, and 334P3, which are integrally connected to the source / drain main region 334M and protrude from the source / drain main region 334M toward the first to third nanosheets N31, N32, and N33. The first to third source / drain protruding regions 334P1, 334P2, and 334P3 may be in physical contact with the first to third nanosheets N21, N22, and N23, respectively. In the first horizontal direction (X direction), among the first to third source / drain protrusion regions 334P1, 334P2, and 334P3, the first source / drain protrusion region 334P1 may have the longest length, and the second and third source / drain protrusion regions 334P2 and 334P3 may have decreasing lengths in a direction away from the fin top surface FT.

[0063] One source / drain region 334 may include a pair of first source / drain protruding regions 334P1, a pair of second source / drain protruding regions 334P2, and a pair of third source / drain protruding regions 334P3. The pair of first source / drain protruding regions 334P1 may protrude in opposite directions toward a first nanosheet N31 of each of a pair of nanosheet stacks NSS3 adjacent to each other on both sides of the source / drain region 334. The pair of second source / drain protruding regions 334P2 may protrude in opposite directions toward a second nanosheet N32 of each of a pair of nanosheet stacks NSS3. The pair of third source / drain protruding regions 334P3 may protrude in opposite directions toward a third nanosheet N33 of each of a pair of nanosheet stacks NSS3. In the first horizontal direction (X direction), lengths LP31, LP32 and LP33 from the first source / drain protrusion region to the third source / drain protrusion region 334P1, 334P2 and 334P3 may decrease in a direction away from the fin top surface FT, and the length LP31 of the first source / drain protrusion region 334P1 may be the longest.

[0064] although Figure 4 An example is shown in which the length of the second nanosheet N32 is less than the length of the third nanosheet N33 in the first horizontal direction (X direction), but the inventive concept is not limited thereto. For example, the length of the third nanosheet N33 may be less than the length of the second nanosheet N32. In this case, the length LP32 of the second source / drain protruding region 334P2 may be less than the length LP33 of the third source / drain protruding region 334P3.

[0065] The detailed configuration and effects of the plurality of nanosheet stacks NSS3 and the plurality of source / drain regions 334 can be referred to in Figure 1 , Figure 2A and Figure 2B The plurality of nanosheet stacks NSS and the plurality of source / drain regions 134 are described to be the same or similar.

[0066] FIG. 5A to FIG. 5Q is a cross-sectional view showing a process sequence of a method for manufacturing an IC device 100 according to some embodiments of the inventive concept. Figure 1 , Figure 2A and Figure 2B The method of manufacturing the IC device 100 will be described with reference to FIG. 5A to FIG. 5Q describe. FIG. 5A to FIG. 5Q The processing sequence is shown along Figure 1 The cross-sectional configuration of the portion corresponding to the cross-sectional view taken along the line XX'. FIG. 5A to FIG. 5Q In the Figure 1 , Figure 2A and Figure 2B , and their detailed description will be omitted.

[0067] Reference Figure 5A , a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS may be alternately stacked on the substrate 102 .

[0068] The plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may include semiconductor materials having different etching selectivities. In some embodiments, the plurality of nanosheet semiconductor layers NS may include silicon (Si), and the plurality of sacrificial semiconductor layers 104 may include silicon germanium (SiGe). In some other embodiments, the plurality of nanosheet semiconductor layers NS may include silicon germanium, and the plurality of sacrificial semiconductor layers 104 may include silicon or germanium. In some other embodiments, the plurality of nanosheet semiconductor layers NS may include indium gallium arsenide (InGaAs) or indium gallium antimonide (InGaSb), and the plurality of sacrificial semiconductor layers 104 may include indium phosphide (InP).

[0069] Reference Figure 5B , a mask pattern MP may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS. The plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and the substrate 102 may be partially etched using the mask pattern MP as an etching mask to form a trench T1. As a result, a fin-type active area FA may be defined by the trench T1, and the stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may remain on the fin top surface FT of the fin-type active area FA.

[0070] The mask pattern MP and the fin type active area FA may include a line pattern extending longitudinally in the X direction. The mask pattern MP may include a pad oxide film pattern 512 and a hard mask pattern 514. The hard mask pattern 514 may include silicon nitride, polysilicon, a spin-on hard mask (SOH) material, or a combination thereof. The SOH material may include a hydrocarbon compound having a relatively high carbon content of approximately 85% to 99% by weight based on the total weight of the SOH material.

[0071] Reference Figure 5C , a device isolation film 114 may be formed inside the trench T1.

[0072] Reference Figure 5D , available from Figure 5C The mask pattern MP is removed from the resultant structure, and the device isolation film 114 may be partially removed so that a top surface of the device isolation film 114 may be at substantially the same level or a similar level as a fin top surface FT of the fin type active region FA.

[0073] Reference Figure 5E , a plurality of dummy gate structures DGS may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS remaining on the fin-type active area FA.

[0074] Each of the plurality of dummy gate structures DGS may extend in a direction intersecting the fin-type active area FA. Each of the plurality of dummy gate structures DGS may have a structure in which an oxide film D112, a dummy gate layer D114, and a capping layer D116 are sequentially stacked. In some embodiments, the dummy gate layer D114 may include polysilicon, and the capping layer D116 may include a silicon nitride film.

[0075] Reference Fig. 5F , a plurality of outer insulating spacers 118 may be formed to cover both sidewalls of the plurality of dummy gate structures DGS, respectively. Thereafter, the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may be partially removed using the plurality of dummy gate structures DGS and the plurality of outer insulating spacers 118 as etching masks, so that the plurality of nanosheet semiconductor layers NS may be divided into a plurality of nanosheet stacks NSS including a plurality of nanosheets (e.g., first to third nanosheets N1, N2, and N3). Thereafter, the fin-type active area FA exposed between the respective nanosheet stacks NSS may be etched to form a recess R1 in an upper portion of the fin-type active area FA. In order to form the plurality of recesses R1, the fin-type active area FA may be etched using a dry etching process, a wet etching process, or a combination thereof.

[0076] Reference Figure 5G , the plurality of sacrificial semiconductor layers 104 exposed on both sides of the plurality of nanosheet stacks NSS through the plurality of recesses R1 may be partially removed to form a plurality of sacrificial recessed regions 104D between the first to third nanosheets N1, N2, and N3 and between the first nanosheet N1 and the fin top surface FT of the fin-type active area FA.

[0077] To form the plurality of sacrificial recessed regions 104D, portions of the plurality of sacrificial semiconductor layers 104 may be selectively etched using an etching selectivity between the plurality of sacrificial semiconductor layers 104 and the first to third nanosheets N1 , N2 , and N3 .

[0078] Reference Figure 5H , a plurality of inner insulating spacers 120 may be formed to at least partially fill the plurality of sacrificial recessed regions 104D (see Figure 5G ). To form the plurality of inner insulating spacers 120, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, an oxidation process, or a combination thereof may be used.

[0079] Reference Fig.5I, among the first to third nanosheets N1, N2, and N3 exposed on both sides of each of the plurality of nanosheet stacks NSS through the plurality of recesses R1, the first nanosheet N1 closest to the fin top surface FT may be partially removed so that the length of the first nanosheet N1 may be reduced, and first nanosheet recessed regions ND1 may be formed on both sides of the first nanosheet N1 and connected to the recesses R1.

[0080] After forming the first nanosheet recessed region ND1 , the length LN1 of the first nanosheet N1 may be less than a maximum length L1 of the nanosheet stack NSS in the first horizontal direction (X direction).

[0081] In some embodiments, the first nanosheet recessed region ND1 may be formed using an isotropic etching process. To form the first nanosheet recessed region ND1, an etching atmosphere having an etching selectivity based on the materials included in the first to third nanosheets N1, N2, and N3 and / or an etching atmosphere having an etching selectivity based on whether the first to third nanosheets N1, N2, and N3 are doped may be used to selectively etch only the doped first nanosheet N1 among the first to third nanosheets N1, N2, and N3.

[0082] In an example, when the first nanosheet N1 includes a doped Si layer and the second and third nanosheets N2 and N3 include undoped Si layers, the first nanosheet recessed region ND1 may be formed by selectively etching only the doped first nanosheet N1 among the first to third nanosheets N1, N2, and N3 through the vacant space on the plurality of recesses R1 in the first etching atmosphere using an etching rate difference based on whether the Si layer is doped. The first etching atmosphere may include a liquid or gaseous etchant. For example, the first etching atmosphere may include HF and HNO 3 mixture of HF, HNO 3 and acetic acid (CH 3 COOH), an aqueous solution including HF and isopropyl alcohol, an aqueous solution including HF and HCl, an aqueous KOH solution, tetramethylammonium hydroxide (TMAH), and / or ethylenediaminepyrrolidone (EDP), but embodiments of the inventive concept are not limited thereto.

[0083] In another example, when the first nanosheet N1 includes a SiGe layer and the second and third nanosheets N2 and N3 include a Si layer, the first nanosheet recessed region ND1 may be formed by selectively etching only the doped first nanosheet N1 among the first to third nanosheets N1, N2, and N3 through the vacant space on the plurality of recesses R1 in the second etching atmosphere using the etching rate difference between SiGe and Si. The second etching atmosphere may include a liquid or gaseous etchant. For example, the second etching atmosphere may include a CH 3COOH etchants such as HNO 3 , HF and CH 3 The present invention may include a mixture of COOH, but the present inventive concept is not limited thereto.

[0084] Reference Figure 5J , a plurality of source / drain regions 134 may be formed on the fin-type active regions FA on both sides of the plurality of nanosheet stacks NSS. Each of the plurality of source / drain regions 134 may include: a source / drain main region 134M located on the recess R1; and a source / drain protruding region 134P integrally connected to the source / drain main region 134M and protruding from the source / drain main region 134M toward the first nanosheet N1 to at least partially fill the first nanosheet recessed region ND1.

[0085] In order to form the plurality of source / drain regions 134 , a semiconductor material may be epitaxially grown from the surface of the recess R1 and both sidewalls of the first nanosheet N1 exposed through the first nanosheet recessed region ND1 .

[0086] In some embodiments, a low pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed using a precursor including a semiconductor element precursor to form the plurality of source / drain regions 134. The semiconductor element precursor may include elements such as silicon (Si), germanium (Ge), indium (In), gallium (Ga), arsenic (As), and antimony (Sb).

[0087] In an example, the plurality of source / drain regions 134 including silicon may be formed by using a compound including Si (e.g., silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ) and dichlorosilane (SiH 2 Cl 2 )) as a silicon source. In another example, the plurality of source / drain regions 134 including SiGe may be formed by using a Ge-containing gas (e.g., germanium (GeH)) in addition to the silicon source. 4 )) and H 2 A dopant ion implantation process may be performed in situ with the epitaxial growth process to form a plurality of source / drain regions 134 .

[0088] In some embodiments, when the first to third nanosheets N1, N2, and N3 include Si, Ge, and / or SiGe, the plurality of source / drain regions 134 may include a Si layer, a SiGe layer, and / or a SiC layer. In some other embodiments, when the first to third nanosheets N1, N2, and N3 include InGaAs, the plurality of source / drain regions 134 may include InGaAs and / or InAs. When the first to third nanosheets N1, N2, and N3 include InGaSb, the plurality of source / drain regions 134 may include InGaSb.

[0089] In some embodiments, each of the plurality of source / drain regions 134 may be formed to include a plurality of semiconductor layers having different dopant concentrations. For example, each of the plurality of source / drain regions 134 may be formed to have a dopant concentration that decreases in a direction toward the fin-type active area FA and the first to third nanosheets N1, N2, and N3, and to have a dopant concentration that increases in a direction away from the fin-type active area FA and the first to third nanosheets N1, N2, and N3. In some embodiments, the dopant concentration may decrease monotonically in a direction toward the fin-type active area FA, and may increase monotonically in a direction away from the fin-type active area FA.

[0090] Reference Figure 5K A protective insulating film 142 may be formed to at least partially cover the resulting structure having the plurality of source / drain regions 134. An inter-gate dielectric film 144 may be formed on the protective insulating film 142, and the protective insulating film 142 and the inter-gate dielectric film 144 may be planarized to expose the top surface of the capping layer D116.

[0091] Reference Figure 5L , available from Figure 5K The capping layer D116 is removed from the resulting structure to expose the dummy gate layer D114. Thereafter, the protective insulating film 142 and the inter-gate dielectric film 144 may be partially removed so that the top surface of the inter-gate dielectric film 144 may be at substantially the same level as the top surface of the dummy gate layer D114.

[0092] Reference Figure 5M , available from Figure 5L The dummy gate layer D114 and the oxide film D112 located thereunder are removed from the resulting structure to prepare a gate space GS, and the plurality of nanosheet stacks NSS may be exposed through the gate space GS. Thereafter, the plurality of sacrificial semiconductor layers 104 remaining on the fin-type active area FA may be removed through the gate space GS, so that the gate space GS may extend to the space between the first to third nanosheets N1, N2, and N3 and the space between the first nanosheet N1 and the fin top surface FT.

[0093] Reference Figure 5N, a gate dielectric film 152 may be formed to at least partially cover the exposed surfaces of the first to third nanosheets N1, N2, and N3 and the fin type active area FA. The gate dielectric film 152 may be formed using an ALD process.

[0094] Reference Fig.5O A gate-forming conductive layer 160L may be formed on the gate dielectric film 152 to at least partially fill the gate space GS (see Figure 5N ) and covers the top surface of the inter-gate dielectric film 144. The gate-forming conductive layer 160L may include a metal, a metal nitride, a metal carbide, or a combination thereof. The gate-forming conductive layer 160L may be formed using an ALD process.

[0095] Reference Figure 5P , available in Fig.5O In the resulting structure, the gate-forming conductive layer 160L and the gate dielectric film 152 are at least partially removed from the top surface of the inter-gate dielectric film 144 to expose the top surface of the inter-gate dielectric film 144. As a result, a plurality of gate lines 160 may be formed to fill the plurality of gate spaces GS. Each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. A planarization process may be performed during the formation of the plurality of gate lines 160; as a result, the height of each of the plurality of outer insulating spacers 118, the protective insulating film 142, and the inter-gate dielectric film 144 may be reduced.

[0096] Reference Figure 5Q , an interlayer insulating film 174 may be formed to at least partially cover the plurality of gate lines 160. Thereafter, the interlayer insulating film 174, the inter-gate dielectric film 144, and the protective insulating film 142 may be partially etched to form a plurality of contact holes 180 exposing the plurality of source / drain regions 134. A metal silicide film 182 may be formed on a top surface of each of the plurality of source / drain regions 134 exposed through the plurality of contact holes 180. A contact plug 184 may be formed on the metal silicide film 182 to at least partially fill the contact hole 180. As a result, a plurality of contact holes 180 may be formed. Figure 1 , Figure 2A and Figure 2B An IC device 100 is shown.

[0097] According to reference FIG. 5A to FIG. 5QThe manufacturing method of the IC device 100 of the embodiment thereof is described, and the IC device 100 including the first nanosheet N1 closest to the fin top surface FT of the fin type active area FA among the first to third nanosheets N1, N2, and N3 in the nanosheet stack NSS has the smallest length in the first horizontal direction (X direction) at a relatively low manufacturing cost using a relatively simple method. Therefore, even if the lower portion of each of the plurality of source / drain regions 134 has a higher resistance than the upper portion thereof due to the higher dopant concentration of each of the plurality of source / drain regions 134 in the upward vertical direction (Z direction) away from the substrate 102, or even if the current flow is likely to be concentrated on the upper nanosheet close to the contact plug 184 among the first to third nanosheets N1, N2, and N3 in the on-state of the nanosheet transistor TR1, the effective channel length of the channel formed in the first nanosheet N1 close to the lower portion of the source / drain region 134 having a relatively high resistance and farthest from the contact plug 184 can be reduced to reduce the resistance of the first nanosheet N1. Therefore, the amount of current flowing through the first nanosheet N1 can be increased at the same operating voltage. As a result, the deviation of the amount of current flowing through the first to third nanosheets N1, N2, and N3 in the on-state of the nanosheet transistor TR1 can be reduced or minimized, and thus, the performance of the IC device 100 in the on-state can be improved or optimized.

[0098] Although the above reference FIG. 5A to FIG. 5Q The present invention describes an exemplary embodiment of the present invention. Figure 1 , Figure 2A and Figure 2B The method of manufacturing the IC device 100 shown in the figure will be understood that various changes and modifications in form and detail may be made thereto without departing from the spirit and scope of the present invention, and may be learned from references to the present invention. FIG. 5A to FIG. 5Q The description presented herein is for manufacturing IC devices with various changes and modifications to the structure. For example, in order to manufacture Figure 3 and Figure 4 The IC devices 200 and 300 shown may be used with reference to FIG. 5A to FIG. 5Q For example, the same method as described in Fig.5I The portion of the sidewall of each of the first to third nanosheets N1, N2, and N3 exposed in the upper portion of the recess R1 is etched in a similar manner to the method of forming the first nanosheet recessed region ND1, and thus, a recessed region including Figure 3 The plurality of recessed regions of the first source / drain protrusion region to the third source / drain protrusion region 234P1, 234P2, and 234P3 shown may include Figure 4The first source / drain protrusion region to the third source / drain protrusion region 334P1, 334P2 and 334P3 are shown as a plurality of recessed regions. To this end, the type and composition of the etchant included in the isotropic etching atmosphere, the temperature of the etching atmosphere, etc. may be adjusted according to the length to be removed from the sidewall of each of the first to third nanosheets N1, N2 and N3 to control the desired etching amount of each of the first to third nanosheets N1, N2 and N3.

[0099] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: a fin-type active region extending longitudinally in a first direction; a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region; and a source / drain region on the fin-type active area and facing the plurality of nanosheets in the first direction, The plurality of nanosheets include a first nanosheet that is closest to the fin top surface of the fin-type active region and has the shortest length in the first direction among the plurality of nanosheets, wherein the source / drain region includes a source / drain main region and a first source / drain protruding region protruding from the source / drain main region, wherein the first source / drain protruding region protrudes from the source / drain main region toward the first nanosheet to overlap with a portion of the plurality of nanosheets in the second direction, The source / drain region includes a first semiconductor layer doped with a first dopant of a first conductivity type, wherein the first nanosheet includes a second semiconductor layer doped with a second dopant of the first conductivity type, and Among the plurality of nanosheets, nanosheets other than the first nanosheet include an undoped third semiconductor layer.

2. The integrated circuit device according to claim 1, wherein: The first nanosheet is configured to form a junction-free channel, and Each of the nanosheets other than the first nanosheet among the plurality of nanosheets is configured to form a channel based on a pn junction.

3. The integrated circuit device according to claim 1, wherein: The first nanosheet includes a first compound semiconductor layer having a first composition, and Nanosheets other than the first nanosheet among the plurality of nanosheets include a second compound semiconductor layer having a second composition different from the first composition.

4. The integrated circuit device according to claim 1, wherein: The first nanosheet is configured to have a lower band gap than nanosheets other than the first nanosheet among the plurality of nanosheets.

5. The integrated circuit device according to claim 1, wherein: The first source / drain protrusion region is in physical contact with the first nanosheet and defines a length of the first nanosheet in the first direction.

6. The integrated circuit device according to claim 1, wherein: The plurality of nanosheets further include a second nanosheet and a third nanosheet sequentially stacked on the first nanosheet, The second nanosheet and the third nanosheet have the same length in the first direction.

7. The integrated circuit device according to claim 1, wherein: The plurality of nanosheets further include a second nanosheet and a third nanosheet sequentially stacked on the first nanosheet, The second nanosheet and the third nanosheet have different lengths in the first direction.

8. The integrated circuit device according to claim 7, wherein: The source / drain region further includes a second source / drain protruding region protruding from the source / drain main region toward any one of the second nanosheet and the third nanosheet, Wherein, in the first direction, the length of the second source / drain protruding region is smaller than the length of the first source / drain protruding region.

9. The integrated circuit device according to claim 1, wherein: A length of each of the plurality of nanosheets in the first direction increases in a direction away from a fin top surface of the fin-type active region.

10. The integrated circuit device according to claim 1, further comprising: a gate structure comprising a main gate portion extending in a third direction that is in plane with the first direction and intersects the first direction on the plurality of nanosheets and a plurality of sub-gate portions connected to the main gate portion, the plurality of sub-gate portions alternating with the plurality of nanosheets on a fin top surface of the fin-type active region; as well as A plurality of inner insulating spacers are between the plurality of sub-gate portions and the source / drain main regions, the plurality of inner insulating spacers overlapping the first source / drain protruding regions in the second direction.

11. An integrated circuit device comprising: a fin-type active region extending longitudinally in a first direction; a pair of nanosheet stacks, each of the pair of nanosheet stacks comprising a plurality of nanosheets overlapping each other in a second direction on the fin-type active region; as well as a source / drain region on the fin-type active area between the pair of nanosheet stacks, The plurality of nanosheets include a first nanosheet that is closest to the fin-type active region and has the shortest length in the first direction among the plurality of nanosheets. wherein the source / drain region comprises a source / drain main region and a pair of first source / drain protruding regions, the source / drain main region does not overlap with the pair of nanosheet stacks in the second direction, and the pair of first source / drain protruding regions protrude from the source / drain main region toward a first nanosheet of each of the pair of nanosheet stacks in opposite directions, wherein each of the plurality of nanosheets comprises a compound semiconductor layer, and The composition of the compound semiconductor layer in a first nanosheet among the plurality of nanosheets is different from the composition of the compound semiconductor layer in nanosheets other than the first nanosheet among the plurality of nanosheets.

12. The integrated circuit device according to claim 11, wherein: The plurality of nanosheets further includes a second nanosheet having a greater length than the first nanosheet in the first direction, The source / drain region further includes a pair of second source / drain protruding regions protruding in opposite directions from the source / drain main region toward a second nanosheet of each of the pair of nanosheet stacks, and A length of each of the pair of second source / drain protruding regions in the first direction is smaller than a length of each of the pair of first source / drain protruding regions.

13. The integrated circuit device according to claim 11, wherein: The source / drain regions and the first nanosheet are doped with dopants of the same conductivity type.

14. The integrated circuit device according to claim 11, wherein: Each of the plurality of nanosheets includes a silicon germanium (SiGe) layer, The Ge content ratio of a first nanosheet among the plurality of nanosheets is higher than the Ge content ratios of each nanosheet other than the first nanosheet among the plurality of nanosheets.

15. The integrated circuit device according to claim 11, wherein: Each of the plurality of nanosheets includes a Group III-V semiconductor layer including gallium (Ga), The Ga content ratio of a first nanosheet among the plurality of nanosheets is lower than the Ga content ratios of each nanosheet other than the first nanosheet among the plurality of nanosheets.

16. An integrated circuit device comprising: a fin-type active region extending longitudinally in a first direction; a pair of source / drain regions on the fin-type active area; as well as a plurality of nanosheets overlapping each other in a second direction between the pair of source / drain regions and on the fin-type active area, The plurality of nanosheets include a first nanosheet, a second nanosheet, and a third nanosheet, the second nanosheet and the third nanosheet have the same length in the first direction, wherein each of the pair of source / drain regions includes at least one source / drain protruding region protruding toward the plurality of nanosheets, wherein each of the plurality of nanosheets comprises a compound semiconductor layer, and The composition of the compound semiconductor layer in the lowest nanosheet closest to the fin-type active region among the plurality of nanosheets is different from the composition of the compound semiconductor layer in the nanosheets other than the lowest nanosheet among the plurality of nanosheets.

17. The integrated circuit device according to claim 16, wherein: The lowermost nanosheet among the plurality of nanosheets closest to the fin-type active region is configured to form a junction-free channel, and Each of the nanosheets other than the lowermost nanosheet among the plurality of nanosheets is configured to form a channel based on a pn junction.

18. The integrated circuit device according to claim 16, wherein: The first nanosheet is closer to the fin-type active region than the second nanosheet. Wherein, the at least one source / drain protrusion region includes a first source / drain protrusion region protruding toward the first nanosheet and a second source / drain protrusion region protruding toward the second nanosheet, and the length of the first source / drain protrusion region in the first direction is greater than the length of the second source / drain protrusion region.

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