Method and apparatus for fast Fourier transform processing

Abstract

An apparatus includes a front-end circuit for receiving a radar wave signal and a fast Fourier transform (FFT) signal processor. The FFT signal processor includes a multiplication logic circuit and other logic circuits. The FFT signal processor derives Doppler information from the radar wave signal by operating a digital stream representing input data of the radar wave signal, including using the multiplication logic circuit to perform a multiplication operation on the first data in the digital stream while the first data is represented in a signed numerical form, and using the other logic circuit to perform other mathematical operations on the second data in the digital stream while the second data is represented in a two's complement form.

Description

Technical Field

[0001] Aspects of various embodiments are directed to apparatus and methods involving fast Fourier transform (FFT) processing of radar wave signals using data in signed numerical form. Background Art

[0002] FFTs can be calculated for various purposes, such as for deriving range Doppler images in frequency modulated continuous wave (FMCW) radar systems. The FFT performs a so-called FFT butterfly operation. Within the butterfly operation, the input data is multiplied by a constant coefficient. A large number of multiplications can be calculated because many butterfly operations are calculated for each FFT and many FFTs are calculated for each range Doppler image. In FMCW radars, the range Doppler images are calculated at a high frame rate. Although each multiplication consumes several joules of energy, many multiplication operations are performed in a period of time, which can lead to power consumption. The power consumption limits the maximum on time of the radar during a time interval.

[0003] These and other issues have challenged the efficiency of FFT processing implementations for various applications. Summary of the invention

[0004] Various example embodiments address problems such as those set forth above and / or other problems that may become apparent from the following disclosure involving Fast Fourier Transform (FFT) processing of radar wave signals using data selectively represented in signed magnitude (SM) form.

[0005] In certain example embodiments, aspects of the present disclosure relate to performing FFT processing on a radar wave signal by operating a digital stream of input data representing the radar wave signal using a multiplication logic circuit to perform a multiplication operation on a first data in the digital stream represented in SM form, and using other logic circuits to perform other mathematical operations on a second data in the digital stream represented in a two's complement form.

[0006] In a more specific example embodiment, a device includes a front-end circuit and an FFT signal processor for receiving a radar signal. In a specific aspect, the front-end circuit includes a transceiver circuit and a signal processor. The transceiver circuit is arranged with an antenna to output a signal and receive a radar wave signal indicating a reflection from the output signal. A signal processor including an analog-to-digital converter (ADC) mixes the output signal with the radar wave signal and generates a digital stream of input data from the mixture. The FFT signal processor includes a multiplication logic circuit and other logic circuits, and is configured to derive Doppler information from the radar wave signal by operating on a digital stream of input data representing the radar wave signal. The FFT signal processor uses a multiplication logic circuit to perform a multiplication operation on the first data in the digital stream while the first data is represented in SM form, and uses other logic circuits to perform other mathematical operations on the second data in the digital stream while the second data is represented in a binary complement form, thereby deriving Doppler information. In a more specific aspect, the FFT signal processor converts the first data between a binary complement form and an SM form. The multiplication logic circuit and the other logic circuit optimize power consumption by at least ten percent relative to other logic circuits that perform multiplication operations on the first data while the first data is represented in two's complement form.

[0007] The multiplication logic circuit may include a multiplier circuit to perform a multiplication operation on the first data while the first data is represented in SM form. In various embodiments, the multiplier circuit includes a multiplication array circuit and / or a multiplier array, which performs a multiplication operation on the first data while the first data is represented in SM form, and adds the outputs from the multiplication operations together. In other embodiments, the multiplier circuit includes two multiplier circuits and an adder circuit, which performs a multiplication operation on the first data while the first data is represented in SM form, and adds the outputs from the multiplication operations together.

[0008] In a number of related and more specific aspects, the multiplication logic circuit includes a two's complement converter circuit to selectively convert first data from the digital stream from a two's complement form to an SM form. For example, the multiplication logic circuit includes an SM converter circuit for converting output data from a multiplication operation from an SM form to a two's complement form. In other embodiments and / or in addition, the multiplication logic circuit includes a two's complement converter circuit to convert the first data from a two's complement form to an SM form.

[0009] In other related aspects, the other logic circuit performs an addition operation on the second data while the second data is represented in two's complement form. In such aspects, the other logic circuit includes an addition logic circuit. In more specific and related aspects, the other logic circuit may alternatively and / or additionally include another multiplication logic circuit to perform a multiplication operation on the first data while the first data is represented in two's complement form, such as when the input data has a magnitude above a threshold as otherwise described herein.

[0010] Thus, the FFT signal processor may include at least two types of computation paths. The multiplication logic circuit is arranged along one of the at least two types of computation paths or otherwise associated with one of the at least two types of computation paths, and the other logic circuit is arranged along another of the at least two types of computation paths or otherwise associated with another of the at least two types of computation paths. In various specific aspects, the power consumption of the FFT signal processor depends on the amplitude of the digital stream of input data, wherein the FFT signal processor consumes lower power when the amplitude of the input data is below a threshold value than when the amplitude is above the threshold value.

[0011] Although some examples have the advantage that logic circuits are not required to select to provide the first data and the second data along different calculation paths, in some specific and related examples, the FFT signal processor can determine the amplitude of the input data, and in response to the amplitude being above or below a threshold, the first data and the second data can be selectively provided along different calculation paths. In such an alternative example, the FFT signal processor determines whether the amplitude of the digital stream of the input data is above the threshold, and in response, selectively provides the second data along the second of at least two types of calculation paths associated with other logic circuits, and provides the first data along the third of at least two types of calculation paths associated with other logic circuits, wherein the multiplication logic circuit is configured along the first of the at least two types of calculation paths. In such an aspect, the other logic circuits include an addition logic circuit and another multiplication logic circuit. Similarly, not all embodiments are so limited, and various aspects are directed to FFT signal processors that may not include selection logic for allocating input values ​​along different calculation paths.

[0012] In another specific example embodiment, an apparatus includes a front-end circuit for receiving a radar wave and an FFT signal processor including a multiplication logic circuit and an addition logic circuit. The FFT signal processor derives Doppler information from a radar wave signal by operating on a digital input stream in input data representing the radar wave, including performing a multiplication operation on first data in the digital stream using the multiplication logic circuit while the first data is represented in SM form, and performing an addition operation on second data in the digital stream using the addition logic circuit while the second data is represented in a two's complement form.

[0013] The multiplication logic circuit may further include an SM converter circuit for converting output data from the multiplication operation from SM form to two's complement form and / or a two's complement converter circuit for converting the first data from two's complement form to SM form.

[0014] The FFT signal processor may additionally include another multiplication logic circuit to perform a multiplication operation on the first data while the first data is represented in binary complement form in response to a digital stream of input data having an amplitude above a threshold. The FFT signal processor may determine the amplitude of the digital stream and, in response, selectively provide the first data to one of the multiplication logic circuit and the other multiplication logic circuit based on the amplitude. In various specific aspects, 24 bits are used to characterize the amplitude. In some examples, 8 bits can be used for a multiplier that multiplies the least significant 8 bits and another multiplier that multiplies the most significant 16 bits. The rotation coefficient is another input and / or output of the multiplier and has 24 bits.

[0015] Other embodiments are directed to methods for using the above-described apparatus. An example method includes receiving a radar wave signal by a front-end circuit of the apparatus, and deriving Doppler information from the radar wave signal by an FFT signal processor. The Doppler information is derived by operating on a digital stream of input data representing the radar wave signal, including performing a multiplication operation on the first data in the digital stream using a multiplication logic circuit of the FFT signal processor while the first data is represented in SM form, and performing other mathematical operations on the second data in the digital stream using other logic circuits of the FFT signal processor while the second data is represented in a binary complement form. The method may further include converting the first data from a binary complement form to an SM form, and converting the output of the performed multiplication operation from the SM form to a binary complement form. Performing the multiplication operation includes performing a multiplication operation on the first data using a Booth multiplier or another type of multiplier while the first data is represented in a signed numerical form, and adding the outputs from the multiplication operation together.

[0016] The above discussion / summary is not intended to describe every embodiment or every implementation of the present disclosure. The following figures and detailed description also illustrate various embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various example embodiments may be more fully understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0018] Figure 1 An example apparatus including a Fast Fourier Transform (FFT) signal processor according to the present disclosure is shown;

[0019] Figure 2 An example FFT signal processor according to the present disclosure is shown;

[0020] Figure 3A-3C An example multiplication logic circuit according to the present disclosure is shown;

[0021] Figure 4 Other example multiplication logic circuits according to the present disclosure are shown;

[0022] Figure 5 Other example multiplication logic circuits according to the present disclosure are shown;

[0023] Figure 6 shows an example circuit of an apparatus according to the present disclosure; and

[0024] Figure 7 An example FFT signal processor according to the present disclosure is shown.

[0025] Although the various embodiments discussed herein are subject to modification and alternative forms, their various aspects have been illustrated in the drawings by way of example and will be described in detail. However, it should be understood that the present disclosure is not limited to the specific embodiments described. On the contrary, the present invention encompasses all modifications, equivalents and alternatives falling within the scope of the present disclosure, including aspects defined in the claims. In addition, the term "example" used throughout this application is only for illustration and not limitation. DETAILED DESCRIPTION

[0026] Aspects of the present disclosure are considered applicable to various different types of devices, systems, and methods involving fast Fourier transform (FFT) processing of radar wave signals using data selectively represented in the form of signed numerical values ​​(SM). In certain implementations, when in the context of FFT processing of radar wave signals, various aspects of the present disclosure are shown to be beneficial by performing multiplication operations on first data in a digital stream represented in the form of SM using multiplication logic circuits, and performing other mathematical operations on second data in a digital stream represented in a binary complement using other logic circuits to operate on a digital stream of input data. Although not necessarily limited to this, various aspects can be understood through the following discussion of non-limiting examples using exemplary contexts.

[0027] Therefore, in the following description, various specific details are set forth to describe the specific embodiments presented herein. However, it will be appreciated by those skilled in the art that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other cases, well-known features are not described in detail to avoid blurring the description of the examples herein. For ease of illustration, the same reference numerals may be used in different figures to represent the same elements or additional examples of the same elements. In addition, although aspects and features may be described in various figures in some cases, it will be understood that the features of one figure or embodiment may be combined with the features of another figure or embodiment, even if the combination is not explicitly shown or explicitly described as a combination.

[0028] FFTs can be calculated for various purposes, such as for deriving a range Doppler image in a frequency modulated continuous wave (FMCW) radar system. FMCW radar systems typically have two or more FFTs, one for range and another for speed estimation of the target. In some embodiments, the FMCW radar system may have a third FFT calculated for each range Doppler bin in the two-dimensional spectrum to obtain the angle of arrival of the signal. The third FFT may have the size of the number of virtual antennas. The FMCW system may be run by a timing engine that generates a periodic start signal. After each start signal, the transmitter (TX) generates a frequency ramp, for example, a sine wave signal with a frequency signal (linear frequency modulation pulse) that increases linearly between, for example, 75 and 76 GHz. The signal is propagated to the antenna and transmitted. After the transmitted signal is mixed down in the RX front-end circuit, it is reflected by the target and picked up by the receiver (RX) antenna. Since radio waves travel at the speed of light and the target distance is constant, there is a time delay between the transmitted signal and the received signal. After mixing the received signal and the transmitted signal, the time delay results in a sine wave signal with a specific frequency. This signal is called a beat signal. After the beat signal is sampled by an analog-to-digital converter (ADC), it is further processed in the digital domain using multiple steps. The first step is to calculate the range FFT for each sample of the linear frequency modulation pulse. If the target exists at different distances (e.g., range), the resulting FFT output contains peaks. The results of multiple (e.g., 256) range FFTs are stored in rows of a memory. After the 256 range FFT results are stored in the memory, the matrix with data in the memory is transposed. After the transposition, the FFT as a velocity FFT is calculated again on each row, and the result is 256. The results of the velocity FFT are stored in the memory again. The resulting data matrix is ​​called a range Doppler map because it contains range and Doppler information about the target. The range Doppler map is processed, and the peak is identified as a target, and a target list is generated as the output of the FMCW radar system. Embodiments according to the present disclosure include FFT processing associated with calculations in a range FFT and / or a velocity FFT, the FFT processing including selectively performing multiplication operations on input data represented in SM form, such that power consumption is reduced and / or maximum on-time is increased compared to performing multiplication operations on input data in two's complement form. In a specific embodiment, the power reduction is in response to one of the input operands being below a threshold size. This may occur during FMCW radar signal processing because most of the output bins in a so-called range FFT tend to contain noise with an amplitude below a threshold. For a so-called velocity FFT that takes the result of a range FFT as input, the FFT input is typically noise with low amplitude.

[0029] FFT performs a butterfly operation, in which the input data is multiplied by a constant coefficient within the butterfly operation. In a butterfly operation, fixed-point multiplication is calculated with a certain absolute precision. If one of the operands a of the multiplier is small, the number of bits used to represent the other operand b can be reduced. The reduction of the number of bits of b is equal to making a plurality of the least significant bits (lsb's) of b equal to zero. Since many input values ​​a are small, the lsb's of b will not change for most clock cycles. If these bits do not change, a large portion of the multiplier hardware gates have constant inputs and do not consume any dynamic power. Multiple embodiments further improve this finding by utilizing SM number representation. In this representation, for small numbers other than the sign bit, the most significant bits (msb's) are equal to zero. This has nothing to do with whether the number is positive or negative. As a result, only a small portion of the multiplier hardware receives the changing input bits, and therefore dissipates dynamic power. For so-called array multipliers, the number of active hardware units in the multiplier scales quadratically with the number of non-constant bits of the two operands. Additionally, for SM number representation, truncation introduces symmetry errors, while for two's complement representation, additional rounding operations are required to achieve this.

[0030] The benefits of this approach are greater when applying a decimation-in-frequency (DIF) FFT rather than a decimation-in-time (DIT) FFT. The reason is that the DIF FFT has already split the input data into different frequency bands during the first FFT stage. As a result, given a sine wave at the input of the FFT, half of the remaining butterflies in the subsequent FFT stages may have received an input signal with zero (or very small) amplitude.

[0031] In a number of embodiments, a device includes a front-end circuit and an FFT signal processor. The front-end circuit receives a radar wave signal (e.g., in response to outputting the radar wave signal). The FFT signal processor includes a multiplication logic circuit and other logic circuits. The FFT signal processor derives Doppler information from the radar wave signal by operating on a digital stream of input data representing the radar wave signal. For example, the FFT signal processor uses the multiplication logic circuit to perform a multiplication operation on first data in the digital stream while the first data is represented in SM form. The FFT signal processor uses other logic circuits to perform other mathematical operations on second data in the digital stream while the second data is represented in binary complement form.

[0032] Many embodiments are directed to the above apparatus, wherein the other logic circuitry includes an addition logic circuitry. In such embodiments, the FFT signal processor operates on the digital stream of input data by performing a multiplication operation on first data in the digital stream using the multiplication logic circuitry while the first data is represented in SM form, and by performing an addition operation on second data in the digital stream using the addition logic circuitry while the second data is represented in two's complement form. The multiplication logic circuitry may optionally include an SM converter circuitry for converting output data from the multiplication operation from SM form to two's complement form and / or a two's complement converter circuitry for converting the first data from two's complement form to SM form.

[0033] In a specific and related embodiment, the FFT signal processor further includes another multiplication logic circuit to, in response to the digital stream having an amplitude above a threshold, perform a multiplication operation on the first data while the first data is represented in a two's complement form. The FFT signal processor can determine the amplitude of the digital stream and, in response, selectively provide the first data to one of the multiplication logic circuit and the another multiplication logic circuit based on the amplitude.

[0034] Various embodiments are directed to methods of using the above-described apparatus to perform mathematical operations on radar wave data and provide a range-Doppler image, such as such example method embodiments otherwise described herein.

[0035] Now turning to the attached figure, Figure 1 An example device including an FFT signal processor according to the present disclosure is shown. Device 100 may include or form part of a FMCW radar system for deriving Doppler information, such as a radar image of a target. As shown, device 100 includes front-end circuitry 102 and an FFT signal processor 104.

[0036] The front-end circuit 102 receives the radar wave signal. The front-end circuit 102 includes a transceiver circuit and a signal processor. The transceiver circuit is arranged with an antenna to output a signal and receive a radar wave signal indicating a reflection from the output signal. The signal processor is configured and arranged with a transceiver circuit to mix the output signal with the radar wave signal and generate a digital stream of input data from the mixture. The signal processor may include an ADC and a timing circuit. In a specific embodiment, the front-end circuit may include TX, RX, one or more antennas, a timing circuit and / or an ADC, as described in addition herein. As shown in the figure, according to various embodiments, the digital stream input to the FFT signal processor 104 is represented in a binary complement form.

[0037] The FFT signal processor 104 derives Doppler information from the radar wave signal by operating on the digital stream of input data. As shown in the figure, the FFT signal processor 104 includes a multiplication logic circuit 106 and other logic circuits 108. The FFT signal processor 104 uses the multiplication logic circuit 106 to perform multiplication operations on the first data in the digital stream while the first data is represented in SM form, and uses the other logic circuit 108 to perform other mathematical operations on the second data in the digital stream while the second data is represented in binary complement form.

[0038] In a specific embodiment, the multiplication logic circuit 106 includes a multiplier logic 112 to perform a multiplication operation on the first data while the first data is represented in SM form. The multiplier logic 112 may include a multiplication array circuit. The multiplication array circuit includes a multiplier array and is configured and arranged to perform a multiplication operation on the first data while the first data is represented in signed numerical form, and to add together the outputs from the multiplication operations. In other embodiments, the multiplier logic 112 includes two Booth multiplier circuits and an adder circuit, as described elsewhere herein.

[0039] In various embodiments, the multiplication logic circuit 106 additionally includes a two's complement converter circuit 110 to selectively convert the first data in the digital stream from two's complement form to SM form. Figure 1 Not shown, but in various embodiments, the multiplication logic circuit 106 and / or the FFT signal processor 104 additionally includes an SM converter circuit that converts the output data from the multiplication operation from SM form to two's complement form.

[0040] The other logic circuit 108 includes logic to perform other mathematical operations on the second data. In a related embodiment, the other logic circuit 108 performs an addition operation on the second data while the second data is represented in two's complement form. For example, the other logic circuit 108 includes an addition logic circuit to perform an addition operation on the second data while the second data is represented in two's complement form. In a more specific and related embodiment, the other logic circuit 108 additionally includes another multiplication logic circuit to perform a multiplication operation on the first data while the first data is represented in two's complement form.

[0041] According to the above-described embodiments, the FFT signal processor 104 includes at least two types of computation paths. One of the computation paths is associated with blocks 110 and 112, and the other computation path is associated with block 108. The multiplication logic circuit 106 is configured along one of the at least two types of computation paths, and the other logic circuits 108 are configured along another of the at least two types of computation paths. In various embodiments, the power consumption of the FFT signal processor 104 depends on the amplitude of the digital stream of the input data. The FFT signal processor 104 converts the first data between the binary complement form and the SM form, and the multiplication logic circuit 106 and the other logic circuits 108 optimize the power consumption by at least ten percent (e.g., less than 20%) relative to the other logic circuits 108 that perform multiplication operations on the first data while the first data is represented in the binary complement form. In various embodiments, the FFT signal processor 104 can determine the amplitude of the input digital stream and selectively provide data along the computation path in response to the amplitude being above or below a threshold, as described further herein. In various embodiments, the multiplication logic circuit 106 is a radix-2 FFT butterfly operation that performs complex multiplication consisting of four real-valued multipliers. Each of the multipliers has an input in SM form, and the results of each of the four real-valued multipliers are added or subtracted after being converted from SM form to two's complement form.

[0042] Figure 2 An example FFT signal processor according to the present disclosure is shown. Figure 2 The FFT signal processor 220 shown may include the Figure 1 The FFT signal processor 104 is shown and has other logic circuits including an addition logic circuit 226 and, optionally, an additional, for example, another multiplication logic circuit 228.

[0043] Similar to Figure 1, the FFT signal processor 220 includes a multiplication logic circuit 224 and other logic circuits. The multiplication logic circuit 224 includes a multiplier logic 232 configured to perform a multiplication operation on the data while the data is represented in SM form. The multiplier logic 232 may include one or more multiplier arrays and / or Booth multipliers, as described elsewhere herein. The multiplication logic circuit 224 may further include a binary complement converter circuit 230 and / or an SM converter circuit 234. Other logic circuits include an addition logic circuit 226, which performs an addition operation on the second data in the digital stream while the second data is represented in binary complement form. Although the multiplication logic circuit 224 shows an input in SM form, the embodiment is not limited thereto, and the multiplication logic circuit 224 may include another input in SM form (e.g., a rotation coefficient) so that the output of the multiplication logic circuit 224 is in SM form.

[0044] In various embodiments, the other logic circuits additionally include another multiplication logic circuit 228. Another multiplication logic circuit 228 includes a multiplier logic 236 configured to perform a multiplication operation on the first data while the first data is represented in two's complement form. The multiplier logic 236 may include one or more multiplier arrays and / or Booth multipliers.

[0045] As described above, in some specific embodiments, the calculation path of the first data can depend on the amplitude of the digital stream of the input data. For example, another multiplication logic circuit 228 can be used to perform a multiplication operation on the first data while the first data is represented in a two's complement form in response to a digital stream having an amplitude above a threshold. Embodiments are not limited to the use of another multiplication logic circuit 228 and can include only the use of multiplication logic circuit 224.

[0046] In a specific embodiment, the FFT signal processor 220 determines the amplitude of the digital stream of input data and selectively provides the first data to one of the multiplication logic circuit 224 and the other multiplication logic circuit 228. In such an embodiment, the FFT signal processor 220 provides the data along one of at least two types of computation paths based on the amplitude based on the amplitude. For example, in response to the FFT signal processor 220 determining that the amplitude of the digital stream of input data is below a threshold value, the FFT signal processor 220 selectively provides the first data along a first of at least two types of computation paths associated with the multiplication logic circuit 224 and provides the second data along a second of at least two types of computation paths associated with the other logic circuit (i.e., the addition logic circuit 226). In response to the FFT signal processor 220 determining that the amplitude of the digital stream of input data is above the threshold, the FFT signal processor 220 selectively provides the second data along a second of at least two types of computation paths associated with other logic circuits (e.g., the addition logic circuit 226), and provides the first data along a third of at least two types of computation paths associated with other logic circuits (e.g., another multiplication logic circuit 228). In such an embodiment, the FFT signal processor 220 may include selection logic for distributing the input data along different computation paths.

[0047] As described above, embodiments are not limited to using selection logic to distribute data along different computation paths. In SM form, small negative numbers have leading zeros in their most significant bits, as do positive numbers. As a result, the inputs to both multipliers are zero, and all internal partial product results within the multipliers are also zero. This applies to commonly used Booth multipliers even though the Booth multiplier generates internal negative numbers from positive input numbers, since the negative version of zero is equal to zero, e.g., negative zero is equal to zero.

[0048] Figure 3A-3C An example multiplication logic circuit according to the present disclosure is shown. In various embodiments, the multiplication logic circuit may include an array multiplier that performs a multiplication operation on data represented in SM form, which array multiplier is referred to herein as an "SM array multiplier". In various embodiments, when both operands a and b have small numerical values, a portion of the units are active in the SM array multiplier. However, this situation does not usually occur in FFT because the rotation coefficients in FFT are usually not small. The result of two n-bit numbers a and b is a number c with a maximum amplitude of 2-n bits. During the calculation of the FFT, the value of c is truncated (or rounded) to a number with only n bits, where only the msb's are retained. This can guarantee the maximum absolute error.

[0049] As previously described, in various embodiments, one of the operands a is smaller in magnitude and a portion of the cells of the SM array multiplier is used. For example, when operand a is smaller, the lsb's of b are set to zero. Various embodiments use the above-described FFT processor circuit and its logic to implement the use of a portion of the cells.

[0050] Figure 3A The internal logic of an example SM array multiplier is shown according to various embodiments. Figure 3A The SM array multiplier 340 shown may be implemented as Figure 1 and / or Figure 2 The logic of the multiplication logic circuits 106, 224. In such an array multiplier 340, shifted versions of operand a are conditionally added together. When operand a is below a threshold (e.g., small) and the lsb bits b0 and b1 are set to zero, Figure 3B As shown previously by Figure 3A The active logic of the array multiplier array is shown.

[0051] Figure 3C Additional logic for adding the inputs of the full adder (FA) of the SM array multiplier 340 is shown. As previously described, because all inputs of the other FAs are zero, one row of the FA is active, so some additional logic 350, 352 is added. In the case where the input operand a is small, the logic 350, 352 is responsible for feeding zero to the input of the FA. In addition, the logic is responsible for providing a shifted version of the operand a to the FA of the multiplier, which is usually the last row or rows. In addition, additional logic 353, 354, 355 detects that a is small and is responsible for setting the lsb's of the operand b to zero. Although the additional logic 350, 352, 353, 354, 355 can cause additional power consumption when the input operand a has a large value, if at least a portion (e.g., most of the time) of the time a is small, the total power consumption of the multiplier is small. In other embodiments, as described in addition herein, when a is not small, an additional array multiplier can be used to perform the multiplication operation.

[0052] Figure 4 Other example multiplication logic circuits according to the present disclosure are shown. As described above, various embodiments include the use of additional multiplication logic circuits. In such embodiments, Figure 4As shown in the multiplication logic circuit 460, one multiplier array is used for small numbers (e.g., data with a magnitude below a threshold) and another multiplier array is used for large numbers (e.g., data with a magnitude above a threshold). In this configuration, the input to one multiplier remains constant while the other multiplier is used for multiplication. This is different from setting the bit to zero when the multiplier is not used, which may result in dynamic power consumption if the previous value was not zero. Such an embodiment includes adding registers in front of the multiplier array and adding some multiplexers at the input and output of the multiplier array.

[0053] Such an embodiment includes using SM as a number representation so that if the numbers are typically small, the msb's of operand a do not change most of the time. Without using SM representation, sign extension logic is added when the result of the small multiplier is negative. This consumes hardware. In addition, rounding logic is added to prevent negative deviations in the result of the multiplication. In such an embodiment, power savings are achieved when a is small and b is large. To save power, the circuit takes advantage of the fact that a fixed-point FFT is used, which is sufficient to keep the absolute truncation error constant. Therefore, the lsb's of b are set to zero, and the multiplication logic uses its msb's during the multiplication process.

[0054] In various experimental embodiments, the functional correctness of the above device was evaluated for different input signals, and no significant degradation of the signal-to-noise ratio was detected. The reduction in power consumption was evaluated by creating a hardware design of the FFT and using a gate-level power simulator. The reduction in power consumption in the combinatorial logic is up to 10 times. This factor depends on the input data and the target clock frequency used. Especially in FMCW radar signal processing, the power consumption of the integrated circuit may depend on the amplitude of the input digital stream. In programmable circuits, the use of SM multipliers can make the input range of the multiplier [-(2n-1), 2n-1]. In addition, the carry of the lsb bit can be ignored.

[0055] Various changes can be made to the above-mentioned apparatus and FFT processor to improve power efficiency and / or the maximum clock frequency at which the multiplier can operate. One such change includes directly performing the conversion of the first data from the binary complement form to the SM form after the operation of generating the input value of the multiplier rather than at the input of the multiplier. By performing the conversion after the operation of generating the input value of the multiplier, the multiplier reads its input directly from the register, which can reduce or eliminate any false signals in the input signal caused by the conversion unit. Compared with solving the false signals, reducing or eliminating false signals can increase the power efficiency of the multiplier. For example, compared with performing the conversion after the operation of generating the input value of the multiplier, performing the conversion at the input of the multiplier can halve the power efficiency of the multiplier.

[0056] Another variation includes using Booth multipliers. The embodiments described and shown above include using an array of multipliers. The array of multipliers can have long delay paths and therefore have a low maximum clock frequency. In various embodiments, Booth multipliers are used instead. Using Booth multipliers, they generate internal negative numbers even for positive input numbers, for example, using an input operand equal to -1×a. As a result, all sign bits can be switched.

[0057] Figure 5 Other example multiplication logic circuits according to the present disclosure are shown. The multiplication logic circuit 580 includes two Booth multipliers 583, 584. In such a multiplication logic circuit 580, the multiplication operation is divided into two sixth multipliers 583, 584, and their outputs or results are added by an adder (logic) circuit 585. As shown, the inputs a and b are represented in SM form, and the output is represented in binary complement form. As further shown, registers 581, 582 are before the Booth multipliers 583, 584, and an SM conversion circuit 586 follows the adder (logic) circuit 585 for converting data from SM form to binary complement form. A rounding block 587 selects bits from the multiplication result, and another register 588 follows the rounding block 587.

[0058] In a specific embodiment, and for small numbers, bits 22 to 8 of the a operand are typically zero. Since -1×0=0, the Booth multiplier 583 also typically does not generate negative internal numbers. Therefore, typically no transitions occur within the Booth multiplier 583 during so-called partial product additions. Experimental embodiments show that during a(23,8)×b(24,0) multiplication, if a is equal to 0, setting the input operand b to zero does not save much power.

[0059] The split Booth multiplier embodiment allows for smaller input operands to be used in filters and / or may allow for coefficients b to be more coarsely quantized for FFT applications. This can be achieved by setting the lsb's of the input operand b to 0. This is equivalent to reducing the size of the second Booth multiplier 584 from 8×24 to 8×16 bits. This is experimentally verified by applying the multiplier in an FFT application. The reduction in the b operand of the second multiplier 584 may not (or minimally) affect the noise floor.

[0060] In various embodiments, the split into two Booth multipliers 583, 584 can be generalized to more than two multipliers. It should also be noted that the range of the input operands of a to the different Booth multipliers 583, 584 can be selected differently. The bits selected for the b operand of the second multiplier 584 remain the same.

[0061] In such an embodiment, the FFT processor does not perform zeroing of bits of the operands, nor does it use multiplexer select bits, in contrast to using a multiplication array.

[0062] Figure 6 An example circuit of an apparatus according to the present disclosure is shown. More specifically, the circuit shown includes an example FMCW radar system 685. The above-described FFT processing and multiplication logic circuit can be implemented in the shown (range) FFT 689 and / or (speed) FFT 691 of the FMCW radar system 685. As previously described, during FMCW radar signal processing, most of the output bins of the so-called range FFT 689 contain noise with low amplitude. As such, the result or output of the range FFT 689 is typically small. For the so-called speed FFT 691 that takes the result of the range FFT 689 as input, the FFT input is typically noise with low amplitude.

[0063] The FMCW radar system 685 can operate as follows. The timing engine 693 generates a periodic start signal. After each start signal, the TX block 694 generates a frequency ramp, for example, a sine wave signal with a frequency signal (linear frequency modulation pulse) that increases linearly between, for example, 75 to 76GHz. The signal is provided to the antenna and transmitted. After the transmitted signal is down-mixed in the receiving front-end circuit 687, it is reflected by the target and picked up by the receiving antenna. Due to the fact that radio waves travel at the speed of light and the target distance is certain, there is a time delay between the transmitted signal and the received signal. After mixing the received signal with the transmitted signal, the time delay results in a sine wave signal with a specific frequency. This signal is called a beat frequency signal.

[0064] After the beat signal is sampled by ADC688, it is further processed in the digital domain. The first step is to calculate (range) FFT689 for each linear frequency modulation pulse sample. If the target exists at different distances (ranges), the resulting FFT output contains peaks. The results of multiple (e.g., 256) range FFTs are stored in rows of the memory. After the 256 range FFT results are stored in the memory, the matrix with data in the memory 690 is transposed. After the transposition, the FFT (speed FFT691) is additionally calculated on each row, and the result is 256. The result of the speed FFT691 is stored again in the memory 690. The resulting data matrix is ​​called a range Doppler map because it contains distance and Doppler information about the target. The range Doppler map is processed, and the peak is identified as a target at 692, and a target list is generated as the output of the FMCW radar system 685. The FFT processing according to various embodiments involves calculations in the range FFT689 and / or the speed FFT691.

[0065] Figure 7 An example FFT signal processor according to the present disclosure is shown. In various embodiments, the FFT signal processor includes a complex multiplier having multiple internal multipliers. As shown, the FFT signal processor may include a radix-2 FFT butterfly operation. Additionally, various embodiments may include a higher radix FFT butterfly operation. More specifically, Figure 7 A butterfly operation of time extraction base-2 is shown. In such an embodiment, all inputs are complex numbers, and the multiplier is a complex multiplier including four real multipliers inside. Each I, Q pair in the complex number is represented in binary complement form, wherein the conversion to SM form occurs before the multiplier (e.g., immediately before the multiplier). The conversion from SM form to binary complement form can occur after each of the four multipliers in the complex multiplier (e.g., immediately thereafter). In various embodiments, in addition to or as a replacement for the complex multiplier in the butterfly operation, other multiplication logic can be used in the FFT signal processor.

[0066] The above-mentioned device and circuit can be used to perform a variety of methods. An example method includes receiving a radar wave signal by a front-end circuit of the device, and deriving Doppler information from the radar wave signal via an FFT signal processor by operating a digital stream of input data representing the radar wave signal. For example, by using a multiplication logic circuit of the FFT signal processor to perform a multiplication operation on the first data in the digital stream while the first data is represented in a signed numerical form, and using other logic circuits of the FFT signal processor to perform other mathematical operations on the second data in the digital stream while the second data is represented in a binary complement form, thereby deriving Doppler information. Performing a multiplication operation includes performing a multiplication operation on the first data using a multiplier array and / or a Booth multiplier while the first data is represented in a signed numerical form, and adding the outputs from the multiplication operation together. In various embodiments, the method further includes converting the first data from a binary complement form to a signed numerical form, and converting the output of the performed multiplication operation to a binary complement form. The conversion can occur at the input of the logic and / or after the input.

[0067] Terms used to illustrate orientation, such as up / down, left / right, top / bottom, and above / below, may be used herein to indicate the relative positions of elements shown in the accompanying drawings. It should be understood that the terms used are merely for the convenience of notation, and in actual use, the orientation of the disclosed structures may differ from the orientation shown in the accompanying drawings. Therefore, these terms should not be interpreted in a limiting manner.

[0068] Those skilled in the art will recognize that, unless otherwise specified, various terms used in the specification (including claims) have ordinary meanings in the art. As an example, the specification describes and / or illustrates aspects of the claimed disclosure through various circuits (circuits / circuitry), which may be shown or use, for example, blocks, modules, devices, systems, units, controllers, converters, and / or other circuit types (e.g., Figure 1 Reference numerals 102 and 110 describe the terminology of blocks / modules as described herein. Such circuits / circuitry are used together with other elements to illustrate how certain embodiments are implemented in form or structure, steps, functions, operations, activities, etc. For example, in certain embodiments described above, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged to implement these operations / activities, which can be in the form of Figures 3A-3C , Figure 4 and Figure 5 In some embodiments, such a programmable circuit is one or more computer circuits, including a memory circuit for storing and accessing a program to be executed as a set (or multiple sets) of instructions (and / or to be used as configuration data to define how the programmable circuit is to be executed), and the programmable circuit uses the algorithm or process described in this article to perform the relevant steps, functions, operations, activities, etc. Depending on the application, the instructions (and / or configuration data) can be configured for implementation in a logic circuit, where the instructions (whether represented in the form of object code, firmware or software) are stored in the memory (circuit) and can be accessed from the memory (circuit).

[0069] Based on the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications shown and described herein. For example, the methods illustrated in the figures may involve steps performed in various orders, wherein one or more aspects of the embodiments herein are retained, or may involve fewer or more steps. For example, Figure 3A-3C , Figure 4 and Figure 5 The logic circuit shown can be implemented as Figure 1 As another example, Figure 2 The additional multiplication logic circuit system shown may be included in Figure 1 Such modifications do not depart from the true spirit and scope of the various aspects of the present disclosure, including those set forth in the claims.

Claims

1. A device for fast Fourier transform processing, characterized in that: include: a front end circuit configured and arranged to receive a radar wave signal; as well as A Fast Fourier Transform (FFT) signal processor, the Fast Fourier Transform (FFT) signal processor including multiplication logic circuits and other logic circuits, and configured and arranged to derive Doppler information from the radar wave signal by operating on a digital stream of input data representing the radar wave signal, comprising: using the multiplication logic circuit to perform a multiplication operation on the first data in the digital stream while the first data is represented in signed numerical form; as well as The other logic circuit is used to perform other mathematical operations on the second data in the digital stream while the second data is represented in two's complement form.

2. The device according to claim 1, characterized in that The FFT signal processor is configured and arranged to convert the first data between the two's complement form and the signed numeric form, and the multiplication logic circuit and the other logic circuits are configured and arranged to optimize power consumption by at least ten percent relative to other logic circuits that perform the multiplication operation on the first data while the first data is represented in the two's complement form.

3. The device according to claim 1, characterized in that The multiplication logic circuit comprises: a twos complement converter circuit configured and arranged to selectively convert the first data in the digital stream from the twos complement form to the signed numeric form; and Multiplier logic is configured to perform the multiplication operation on the first data while the first data is represented in the signed numerical form.

4. The device according to claim 1, characterized in that The multiplication logic circuit includes a multiplication array circuit, which includes a multiplier array, and the multiplier array is configured and arranged to perform the multiplication operation on the first data while the first data is represented in the signed numerical form, and add the outputs from the multiplication operation together.

5. The device according to claim 1, characterized in that The other logic circuit is configured and arranged to perform an addition operation on the second data while the second data is represented in the two's complement form, and the multiplication logic circuit includes two Booth multiplier circuits, which are configured and arranged to perform a multiplication operation on the first data while the first data is represented in the signed numeric form.

6. The device according to claim 1, characterized in that The multiplication logic circuit additionally includes a signed numeric converter circuit configured and arranged to convert output data from the multiplication operation from the signed numeric form to the two's complement form.

7. The device according to claim 1, characterized in that The FFT signal processor includes at least two types of calculation paths, and the multiplication logic circuit is configured along one of the at least two types of calculation paths, while the other logic circuits are configured along another of the at least two types of calculation paths, and the power consumption of the FFT signal processor depends on the amplitude of the digital stream of the input data.

8. The device according to claim 1, characterized in that The FFT signal processor is configured and arranged to determine that the amplitude of the digital stream of input data is below a threshold and, in response, selectively provide the first data along a first of at least two types of computational paths associated with the multiplication logic circuit and provide the second data along a second of the at least two types of computational paths associated with the other logic circuit.

9. A device for fast Fourier transform processing, characterized in that: include: a front end circuit configured and arranged to receive a radar wave signal; as well as A Fast Fourier Transform (FFT) signal processor, the Fast Fourier Transform (FFT) signal processor including a multiplication logic circuit and an addition logic circuit, and configured and arranged to derive Doppler information from the radar wave signal by operating on a digital stream of input data representing the radar wave signal, comprising: using the multiplication logic circuit to perform a multiplication operation on the first data in the digital stream while the first data is represented in signed numerical form; as well as The addition logic circuit is used to perform an addition operation on the second data in the digital stream while the second data is represented in a two's complement form.

10. A method for fast Fourier transform processing, characterized in that: include: The radar wave signal is received by the front-end circuit of the device; and The method comprises: deriving Doppler information from the radar wave signal by operating a digital stream of input data representing the radar wave signal via a fast Fourier transform (FFT) signal processor, including: Using multiplication logic of the FFT signal processor, performing a multiplication operation on the first data in the digital stream while the first data is represented in signed numerical form; and Other mathematical operations are performed on the second data in the digital stream while the second data is represented in two's complement form using other logic circuits of the FFT signal processor.

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