Chip Back-End Design and Layout Design Method, Tool, Chip and Storage Medium

Abstract

An embodiment of the present application discloses a method, tool, chip, and storage medium for chip backend design and layout design. The generation method includes: importing library files and design data; when a routing PnR tool performs routing processing based on the library files and design data, after executing an optimization timing command, execute a first write command to obtain a first report, a first netlist, and a first file; based on the first netlist and the first file, a static timing analysis STA tool executes a first analysis command to generate a second report; based on the first report and the second report, correct the information of the PnR tool to obtain corrected information; based on the library files and design data, the STA tool executes a second analysis command to obtain a timing report; if there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool other than the corrected information; the STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and output the layout.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular, to a method, tool, chip and storage medium for chip backend design and layout design. Background Art

[0002] The time of chip backend design occupies a large proportion in the whole chip design cycle. Therefore, in order to improve the design efficiency of chips, how to shorten the time of chip backend design becomes extremely important.

[0003] In the process of integrated circuit layout design, due to the long process and many links in the integrated circuit backend design, the design process is very complex. As the chip scale becomes larger and the competition becomes more intense, the requirements for chip backend design are also getting higher and higher. At present, when performing the backend design of a chip, it is necessary to continuously iterate through the Engineer Changing Order (ECO) process to fix the problems existing in the design. However, the inconsistency between the routing tool and the static timing tool will lead to an increase in the number of iterations in the backend design process, seriously affecting the on-time tape-out of the chip. Summary of the Invention

[0004] The embodiments of the present application provide a method, tool, chip and storage medium for chip backend design and layout design, which can greatly reduce the number of iterations of the ECO process, thereby shortening the time of chip backend design and effectively improving the chip design efficiency.

[0005] The technical solution of the embodiments of the present application is realized as follows:

[0006] In a first aspect, the embodiments of the present application provide a method for chip backend design, the method includes:

[0007] Import library files and design data; wherein, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip;

[0008] When the routing PnR tool performs routing processing based on the library files and the design data, after executing the optimize timing command, execute a first write command to obtain a first report, a first netlist and a first file;

[0009] Based on the first netlist and the first file, the static timing analysis STA tool executes a first analysis command to generate a second report;

[0010] Based on the first report and the second report, correct the information of the PnR tool to obtain corrected information;

[0011] Based on the library files and the design data, the STA tool executes a second analysis command to obtain a timing report;

[0012] If there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool other than the corrected information;

[0013] The STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and outputs the layout.

[0014] In a second aspect, an embodiment of the present application provides a layout design method, which is applied to an EDA tool. The method includes:

[0015] Receive a fourth start command to start the layout design process and parse the library file and design data carried in the fourth start command; wherein, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip;

[0016] When performing routing processing in the layout design process by calling a routing PnR tool based on the library file and the design data, if the optimize timing command is executed, a second stop command and a second write command are generated;

[0017] In response to the second stop command, abort the routing processing, and at the same time, in response to the second write command, obtain a third report, a second netlist, and a second file;

[0018] Based on the second netlist and the second file, call the STA tool to perform static timing analysis processing to generate a fourth report;

[0019] Receive a fifth start command to start a correction process, and correct the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

[0020] Receive a sixth start command to continue the layout design process based on the corrected information and output the layout.

[0021] In a third aspect, an embodiment of the present application provides a back-end design tool, which includes an import unit, a first acquisition unit, a first generation unit, a first correction unit, a change unit, and a first output unit.

[0022] The import unit is used to import a library file and design data; wherein, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip;

[0023] The first acquisition unit is used to, when a routing PnR tool performs routing processing based on the library file and the design data, after executing the optimize timing command, execute a first write command to obtain a first report, a first netlist, and a first file;

[0024] The first generation unit is configured to execute a first analysis command by a static timing analysis (STA) tool based on the first netlist and the first file, and generate a second report;

[0025] The first correction unit is configured to correct the information of the PnR tool based on the first report and the second report, and obtain corrected information;

[0026] The first acquisition unit is further configured to execute a second analysis command by the STA tool based on the library file and the design data, and obtain a timing report;

[0027] The change unit is configured to execute a change command if there is a timing violation in the timing report, and perform ECO processing on other information of the PnR tool except for the corrected information;

[0028] The first acquisition unit is further configured to continue to execute the next analysis command by the STA tool until there is no timing violation in the obtained timing report;

[0029] The first output unit is configured to output a layout.

[0030] In a fourth aspect, an embodiment of the present application provides a backend design tool, which includes a first processor and a first memory storing instructions executable by the first processor. When the instructions are executed by the first processor, the chip backend design method as described above is implemented.

[0031] In a fifth aspect, an embodiment of the present application provides an EDA tool, which includes: a receiving unit, a parsing unit, a calling unit, a second generation unit, an aborting unit, a second acquisition unit, a second correction unit, and a second output unit.

[0032] The receiving unit is configured to receive a fourth start command and start a layout design process;

[0033] The parsing unit is configured to parse the library file and the design data carried in the fourth start command; wherein, the design data includes a gate-level netlist and timing constraints obtained after front-end design of the chip.

[0034] The calling unit is configured to, when performing routing processing in the layout design process by calling a routing PnR tool based on the library file and the design data;

[0035] The second generation unit is configured to generate a second stop command and a second write command if an optimized timing command is executed;

[0036] The aborting unit is configured to respond to the second stop command and abort the routing processing;

[0037] The second acquisition unit is configured to, in response to the second write command, acquire a third report, a second netlist, and a second file;

[0038] The calling unit is further configured to, based on the second netlist and the second file, call a STA tool to perform static timing analysis processing to generate a fourth report;

[0039] The receiving unit is further configured to receive a fifth start command to start a calibration process;

[0040] The second correction unit is configured to correct the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

[0041] The receiving unit is further configured to receive a sixth start command;

[0042] The second output unit is configured to continue the layout design process based on the corrected information and output a layout.

[0043] In a sixth aspect, an embodiment of the present application provides an EDA tool, which includes a second processor and a second memory storing instructions executable by the second processor. When the instructions are executed by the second processor, the layout design method described above is implemented.

[0044] In a seventh aspect, an embodiment of the present application provides a chip, which includes a programmable logic circuit and / or program instructions. When the chip runs, the chip backend design method and the layout design method described above are implemented.

[0045] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a program is stored and applied to a backend design tool and an EDA tool. When the program is executed by a first processor, the chip backend design method described above is implemented. When the program is executed by the first processor, the layout design method described above is implemented.

[0046] The embodiments of the present application provide a method, a tool, a chip, and a storage medium for chip backend design and layout design. The backend design tool imports library files and design data. Among them, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip. When the routing PnR tool performs routing processing based on the library files and design data, after executing the optimize timing command, it executes the first write command to obtain a first report, a first netlist, and a first file. Based on the first netlist and the first file, the static timing analysis STA tool executes the first analysis command to generate a second report. Based on the first report and the second report, the information of the PnR tool is corrected to obtain the corrected information. Based on the library files and design data, the STA tool executes the second analysis command to obtain a timing report. If there are timing violations in the timing report, the change command is executed to perform ECO processing on other information of the PnR tool except the corrected information. The STA tool continues to execute the next analysis command until there are no timing violations in the obtained timing report, and then outputs the layout. That is to say, in the present application, in the routing stage, a correction process is inserted to perform precise correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem of increased iteration times in the ECO process caused by the inconsistency between the PnR tool and the STA tool, greatly reducing the iteration times of the ECO process, and then shortening the time of chip backend design and effectively improving the chip design efficiency. Description of the Drawings

[0047] Figure 1 It is a schematic diagram of the backend design process;

[0048] Figure 2 It is a schematic diagram of the ECO process;

[0049] Figure 3 It is a schematic diagram of the implementation process of the chip backend design method Figure 1 ;

[0050] Figure 4 It is a schematic diagram of the implementation process of the chip backend design method Figure 2 ;

[0051] Figure 5 It is a schematic diagram of the implementation process of the chip backend design method Figure 3 ;

[0052] Figure 6 It is a schematic diagram of the backend design process of the chip proposed in the present application;

[0053] Figure 7 It is a schematic diagram of the implementation process of the layout design method;

[0054] Figure 8Schematic diagram of the composition structure of the backend design tool Figure 1 ;

[0055] Figure 9 Schematic diagram of the composition structure of the backend design tool Figure 2 ;

[0056] Figure 10 Schematic diagram of the composition structure of the EDA tool Figure 1 ;

[0057] Figure 11 Schematic diagram of the composition structure of the EDA tool Figure 2 。 Specific implementation manners

[0058] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. In addition, it should be noted that for the convenience of description, only the parts related to the related application are shown in the drawings.

[0059] Before further elaborating on the embodiments of the present invention, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are applicable to the following explanations.

[0060] Performance, power consumption, area (Performence, Power, Area, PPA).

[0061] Place and Route (PnR). Among them, Place is for placement and Route is for routing.

[0062] Electronics Design Automation (EDA) refers to a design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, design rule checking, etc.) of very large scale integration (VLSI) chips.

[0063] Geometry Data Standard (GDS), which records the layout information before chip manufacturing.

[0064] Engineering Change Order (ECO) is usually used for engineering changes after the completion of new product development. After the engineering department confirms the necessary changes, it issues documents for relevant units to countersign to ensure that inventory and work-in-progress are properly handled, whether it is an immediate change or a change after use. The sales unit, manufacturing unit, and material unit all need to agree and take necessary actions. Usually, the scope involved in ECO is large and the implementation schedule is long, so it requires rigorous system management.

[0065] Clock tree synthesis (CTS) is to synthesize the clock tree of the design. The main purpose is to enable each clock to reach all D-type flip-flops (DFFs) it drives in the shortest possible time.

[0066] Static timing analysis (STA) applies a specific timing model (TimingModel) to analyze whether a specific circuit violates the timing constraints given by the designer. That is to say, STA judges whether an integrated circuit (IC) can work properly in the user's timing environment through a complete analysis method, providing a good solution to the issue of ensuring IC quality. Classified by the analysis method, STA can be divided into Path-Based and Block-Based.

[0067] The GDSII stream format, commonly abbreviated as GDSII, is a database file format. It is used for data conversion of integrated circuit layouts and has become the de facto industry standard. GDSII is a binary file that contains planar geometries, texts or labels in the integrated circuit layout, as well as other relevant information and can be composed of a hierarchical structure. GDSII data can be used to reconstruct all or part of the layout information. It can be used to make photolithography masks.

[0068] EDA tool software (EDA tools).

[0069] Flip chip is a pinless structure that generally contains circuit units. It is designed to be electrically and mechanically connected to a circuit through an appropriate number of solder balls (covered with conductive adhesives) located on its surface.

[0070] Gate-Level netlist. In circuit design, a netlist is used to describe the interconnections between circuit elements and is generally a text file following a relatively simple markup syntax. Gate-level refers to the level of circuit synthesis described by the netlist. As the name implies, in a gate-level netlist, the circuit elements described are basically gates or elements of the same level.

[0071] Deep sub-micron. Generally, 0.35 - 0.8μm and below is called the sub-micron level, 0.25μm and below is called the deep sub-micron level, and 0.05μm and below is called the nano level. The key technologies for deep sub-micron manufacturing mainly include ultraviolet lithography technology, plasma etching technology, ion implantation technology, copper interconnect technology (not the same as interconnect), etc. The mainstream production process technology for integrated circuits in the world is 0.010μm - 0.028μm.

[0072] Design For Test (DFT). There is often a built-in test circuit inside the chip. The purpose of DFT is to consider future testing during the design process. A common method of DFT is to insert a scan chain in the design to convert non-scan units (such as registers) into scan units.

[0073] Furthermore, the embodiments of the present application may also involve the following terms: group, region, timing constrain, power ring, timing analysis, wire, net, Congestion, pin, timing engine, row channel, cell, PAD, clock tree, Buffer, buffer tree, fill cell, clock insertion delay, megacell, clock skew, transition time, tap out, standard cell, setup / hold time violation, metal (wiring) layer, script, Built-in self-test (BIST).

[0074] Chip design is undoubtedly an important step in the chip manufacturing process, and chip design can be divided into front-end design and back-end design. The front-end is mainly responsible for logical implementation, usually using languages such as Verilog and VHDL to describe at the behavioral level. The back-end, on the other hand, is mainly responsible for turning the front-end design into real schematics and layouts (schematic & layout), tape-out, and mass production. To put it metaphorically, the front-end is like the one making the blueprint, which can be for functional and structural things. The back-end is then turning the blueprint into a real high-rise building.

[0075] Among them, chip back-end design mainly includes the following parts:

[0076] 1. Design For Test (DFT)

[0077] There are often built-in test circuits inside the chip. The purpose of DFT is to consider future testing during the design. The common method of DFT is to insert scan chains in the design to turn non-scan units (such as registers) into scan units.

[0078] 2. Floor Plan

[0079] 3. CTS

[0080] Simply put, it is the routing of the clock. Due to the global commanding role of the clock signal in digital chips, its distribution should be symmetrically connected to each register unit, so that when the clock reaches each register from the same clock source, the clock delay difference is minimized. This is also the reason why the clock signal needs to be routed separately.

[0081] 4. Place and Route (PnR)

[0082] The routing here is the routing of ordinary signals, including the traces between various standard cells (basic logic gate circuits). For example, the 0.13um process or the 90nm process that we usually hear about is actually the minimum width that the metal routing here can reach. Microscopically, it is the channel length of the MOS transistor.

[0083] 5. Parasitic Parameter Extraction

[0084] Due to the resistance of the wire itself, the mutual inductance between adjacent wires, and the coupling capacitance, signal noise, crosstalk, and reflection will be generated inside the chip. These effects will cause signal integrity problems, resulting in signal voltage fluctuations and changes. If serious, it will lead to signal distortion errors. It is very important to extract parasitic parameters for re-analysis and verification to analyze signal integrity problems.

[0085] 6. Layout Physical Verification

[0086] Function and timing verification are performed on the completed physical layout. There are many verification items, such as Layout Vs Schematic (LVS) verification. Briefly speaking, it is the comparison and verification between the layout and the gate-level circuit diagram after logic synthesis; Design Rule Checking (DRC) to check whether the wire spacing, wire width, etc. meet the process requirements, and Electrical Rule Checking (ERC) to check electrical rule violations such as short circuits and open circuits, etc.

[0087] The actual backend process also includes circuit power consumption analysis and Design for Manufacturability (DFM) issues arising from the continuous progress of manufacturing processes.

[0088] The completion of physical layout verification means the completion of the entire chip design stage. Next is chip manufacturing. The physical layout is given to the chip foundry in the GDSII file format to make the actual circuit on the silicon wafer, and then packaged and tested to obtain the actual chip.

[0089] Figure 1 For the schematic diagram of the backend design process, as Figure 1 shown, currently, the processes involved in chip backend design mainly include the following steps:

[0090] Step 101, data preparation.

[0091] For Silicon Ensemble of CDN, the data required for backend design mainly includes the library files of standard cells, macro cells, and I / O Pads provided by the Foundry factory. It includes the physical library, timing library, and netlist library, given in the forms of.lef,.tlf, and.v respectively. The gate-level netlist generated after the front-end chip design is synthesized, the script file with timing constraints and clock definitions, the resulting.gcf constraint file, and the DEF (Design Exchange Format) file defining the power Pads. (For Astro of Synopsys, the gate-level netlist generated after synthesis, the timing constraint file SDC is the same, the Pad definition file - tdf,.tf file - technology file, and the library files of standard cells, macro cells, and I / O Pads provided by the Foundry factory are given in the forms of FRAM, CELL view, LM view (Milkway reference library and DB, LIB file).

[0092] Step 102, layout planning.

[0093] It mainly involves the layout of standard cells, I / O Pads, and macro cells. The positions of I / O Pads are given in advance, macro cells are placed according to timing requirements, and standard cells are placed automatically by tools within a given area. After layout planning, the size of the chip, the area of the Core, the form of the Row, and the Rings and Strips of power and ground wires are determined. If necessary, after automatically placing standard cells and macro cells, a PNA (power network analysis) - IR drop and EM can be performed first.

[0094] Step 103: Layout.

[0095] After layout planning, the positions of macro cells and I / O Pads and the area for placing standard cells are determined. SE (Silicon Ensemble) will pass this information to PC (Physical Compiler) through a DEF file. PC automatically places standard cells based on the netlist and timing constraint information obtained from the.DB file given by synthesis, while performing timing checks and optimizing cell placement. If PC + Astro is used, data can be transferred using write_milkway and read_milkway.

[0096] Step 104: Clock tree synthesis (CTS).

[0097] The clock network in the chip needs to drive all the timing units in the circuit. Therefore, the gate cell at the clock source end has a large load, with a large and unbalanced load delay. Buffers need to be inserted to reduce the load and balance the delay. The clock network and the buffers on it form the clock tree. Generally, it takes several iterations to create a relatively ideal clock tree. --- Clock skew.

[0098] Step 105: Routing. Global route - Track assign - Detail routing - Routing optimization Routing means connecting each unit and I / O Pad with interconnecting wires according to the circuit connection relationship under the conditions of meeting process rules, routing layer limitations, line width, line spacing limitations, and electrical performance constraints of reliable insulation for each net. These are carried out under timing-driven conditions to ensure that the wire lengths on critical timing paths are minimized. -- Timing report clear.

[0099] Step 106: Adding Dummy Metal and inserting Fillers (pad filler, cell filler).

[0100] Filler refers to the logic - independent fillers defined in the standard cell library and I / O Pad library, which are used to fill the gaps between standard cells and between I / O Pads. It mainly connects the diffusion layers to meet the DRC rules and design requirements.

[0101] Foundry factories have regulations on metal density to ensure that the metal density is not lower than a certain value, preventing over - etching of the metal layer of the wiring during the etching stage in the chip manufacturing process, which may reduce the circuit performance. Adding Dummy Metal is to increase the metal density.

[0102] Step 107, STA (Static Timing Analysis) and post - simulation.

[0103] After clock tree insertion, the positions of each cell are determined. The tool can extract the parasitic parameters of the wiring in the form of Global Route. At this time, the extraction of delay parameters is relatively accurate. SE passes the.V and.SDF files to PrimeTime for static timing analysis. After confirming that there are no timing violations, these two files are passed to the front - end personnel for post - simulation. For Astro, after detail routing, parameter extraction is performed using starRC XT, and the generated E.V and.SDF files are passed to PrimeTime for static timing analysis, which will be more accurate.

[0104] Step 108, ECO (Engineering Change Order).

[0105] For the problems found in static timing analysis and post - simulation, small - scale modifications are made to the circuit and cell layout.

[0106] Step 109, DRC and LVS. DRC is to check the physical patterns of each layer in the chip layout against the design rules (spacing, width), and it also includes the check of antenna effects to ensure the normal chip fabrication. LVS mainly compares the layout and the circuit netlist to ensure that the layout circuit fabricated is consistent with the actual required circuit. The DRC and LVS checks are performed by EDA tools Synopsy hercules / mentor calibre / CDN Dracula. Astro also includes LVS / DRC check commands.

[0107] Step 1010, chip fabrication. When all checks and verifications are correct, the final layout GDSⅡ file is passed to the Foundry factory for mask manufacturing.

[0108] In the back - end design process of a chip, ECO is a critical path that cannot be ignored. A good ECO process and strategy can accelerate the tape - out time.

[0109] Figure 2 For the schematic diagram of the ECO process, as Figure 2 shown, currently, the conventional ECO process mainly includes the following steps:

[0110] Step 108a: Determine whether there is a timing violation. If there is, execute step 108b; otherwise, execute step 109.

[0111] Step 108b: Perform ECO correction processing, then return to step 106 and continue the next static timing analysis.

[0112] Due to the poor correlation between the PnR tool and the STA tool, especially when the PnR and STA tools are from different suppliers. For example, if the PnR uses the innovus tool of cadence and the STA uses the primetime of synopsis, the consistency between them is poor. And this inconsistency will cause the back - end design to require multiple iterations to meet the timing during timing ECO, and there is even a risk of not being able to fix, resulting in the chip not being able to tape out on time.

[0113] To solve the existing problems, in this application, in the routing stage, a correction process is inserted. Precise correction processing is performed according to the first report obtained by the PnR tool and the second report obtained by the STA tool to correct the correlation between the PnR tool and the STA tool. Thus, the problem of increased iteration times in the ECO process caused by the inconsistency between the PnR tool and the STA tool can be solved, the iteration times of the ECO process can be greatly reduced, and then the time of the chip back - end design can be shortened, effectively improving the chip design efficiency.

[0114] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application.

[0115] An embodiment of this application provides a method for chip back - end design. Figure 3 For the implementation process schematic of the chip back - end design method Figure 1 as Figure 3 shown, in the embodiment of this application, the chip back - end design method may include the following steps:

[0116] Step 201: Import library files and design data; among them, the design data includes the gate - level netlist and timing constraints obtained after the front - end design of the chip.

[0117] In an embodiment of the present application, after the front-end design is completed, when the back-end design tool performs the back-end design of the chip, it can first import the library files and design data. Among them, importing the library files and design data can also be understood as the start of the back-end design process of the chip.

[0118] It should be noted that, in an embodiment of the present application, the back-end design tool can first import the required data when performing the back-end design. Specifically, these data can specifically include library files and design data. Among them, the library files can be library files of standard cells, macro cells, and I / O Pads provided by a chip foundry (Foundry). It includes a physical library, a timing library, and a netlist library, which are given in the forms of.lef,.tlf, and.v respectively. The design data can be the gate-level netlist generated after the synthesis of the chip front-end design, a script file with timing constraints and clock definitions, and the resulting.gcf constraint file.

[0119] Furthermore, in an embodiment of the present application, the back-end design tool is an EDA tool and can include various tools provided by different suppliers. Specifically, different back-end design tools can be used when executing different commands and performing different types of processing. For example, common layout PnR tools include IC Compiler from Synopsys, Astro, and SOC-Enconter from Candance. Among them, IC Compiler is another PnR tool launched by Synopsys after Astro, and Astro is commonly used for layout and wiring of ultra-deep submicron levels below the 10nm process.

[0120] Exemplarily, in the present application, when performing design for testability DFT, the selected DFT tool can be DFT Compiler from Synopsys; when performing layout planning, the tool used can be Astro from Synopsys; when performing clock tree synthesis CTS, the CTS tool used can be Physical Compiler from Synopsys; when performing wiring, the PnR tool used can be Astro from Synopsys; when performing extraction of parasitic parameters, the tool used can be Star-RCXT from Synopsys; when performing physical verification of the layout, the tool used can be Hercules from Synopsys; when performing static timing analysis STA, the STA tool used can be Prime Time from Synopsys.

[0121] It can be understood that in this application, after the chip front-end design meets the requirements, corresponding files can be output, such as gate-level netlists, sdc files, etc., for subsequent timing analysis and verification. Static timing analysis and formal verification are used to verify the correctness of synthesis. Among them, static timing analysis can more accurately analyze timing to check whether the timing of synthesis is correct; while formal verification uses mathematical methods to verify whether the function of the synthesized circuit is consistent with the original circuit. Only after the verification passes can the next step of placement and routing be carried out, otherwise synthesis has to be redone.

[0122] Next, the physical design stage, that is, the chip back-end design, can be entered. In the chip back-end design, in fact, the gate-level netlist generated by the front-end design is converted into layout information that can be used by the Foundry for masking.

[0123] It should be noted that in this application, in the chip back-end design process, the design data output by the front-end design required by the back-end design tool at least includes a gate-level netlist, timing constraints, and a timing analysis report.

[0124] It can be understood that before importing the design data (netlist file), the back-end design tool can first detect the quality of the design data to confirm that the existing errors and defects have been eliminated. For example, the following situations can be checked: grammar errors, connection short circuits, nets with no connections, undriven input pins, assign statements, nets other than wire types, the use of special characters starting with "\", the writing of data buses, the length of names, etc. Different manufacturers and software will have some restrictions on this, so it is recommended to define a relatively strict netlist writing rule.

[0125] Exemplarily, in this application, the netlist writing rule can include no "nets with no connections" and "undriven input pins", no assign statements, only wire-type nets are allowed, all names are only allowed to use uppercase and lowercase English letters, numbers, and underscores, the first character is an English letter, the length is less than 1024, and the calls between modules are all in explicit format.

[0126] Furthermore, in the embodiments of this application, if DFT for testability and automatic test format generation are required, the back-end design tool also needs to check whether it meets the design requirements of scan chains and Memory BIST.

[0127] Next, it is also necessary to check whether the timing settings in the timing constraint file are complete and reasonable. Finally, it is necessary to review the timing analysis report. If there is a setup violation, generally it is not allowed to be greater than 10% of the clock period, while the hold violation can be temporarily left unresolved and removed after routing.

[0128] Step 202, when the PnR tool performs routing based on the library file and design data, after executing the optimize timing command, execute the first write command to obtain the first report, the first netlist, and the first file.

[0129] In the embodiment of the present application, after importing the library file and design data, the PnR tool can perform routing based on the library file and design data. During the routing process, after executing the optimize timing command, the PnR tool can execute the first write command to obtain the first report, the first netlist, and the first file.

[0130] Furthermore, in the embodiment of the present application, the routing process performed by the PnR tool is ordinary signal routing, which specifically may include the routing between various standard cells (basic logic gate circuits). Among them, the common 0.13um process, or 90nm process, is actually the minimum width that the metal routing can reach during the routing process. Microscopically, it is the channel length of the MOS transistor.

[0131] Exemplarily, in the present application, the PnR tool can be Astro of Synopsys.

[0132] It can be understood that in the embodiment of the present application, during the routing process, the routing for analog signals and isolation space can be reserved first. Then consider the routing of the clock tree. At this time, since there are no digital signal routes yet, there is a great deal of freedom to choose a metal layer with a faster transmission speed for the clock tree routing. Finally, it is the digital signal routing. If the routing software can consider the timing requirements, it is recommended to use this function. If there is no such function and there are some critical paths, then weights can be assigned to these nets to make them be routed first. In the result of the routed layout, if there are no large-area or concentrated routing problems, the small problems generated by the automatic routing can be temporarily left uncorrected, and STA can be performed first because there is likely to be a routing engineering change (routing ECO) after STA.

[0133] It should be noted that, in the embodiments of the present application, routing-related route commands may mainly include: route_auto, route_opt, route_eco, route_group, route_global, route_track, and route_detail.

[0134] Specifically, route_auto is for routing, mainly for signal lines. Generally, the clock tree net has been routed in the CTS phase. Of course, if the clock tree is not routed, route_auto can route the clock tree and signal net together. route_auto is only used once in the PnR process.

[0135] route_auto is composed of three subcommands, and is automatically completed. Among them, route_auto = route_global + route_track + route_detail. On the contrary, if you do not want to automatically execute the three subcommands, you can also run route_global + route_track + route_detail manually, and the effect is the same.

[0136] Specifically, route_global is a fast connection, but does not create real metal (only VIA is created); route_track adds real metal based on the result of route_global, but does not consider DRC; route_detail is used to modify DRC.

[0137] route_global, quick connection. After executing route_global, all nets are connected. However, there is no real metal, just thin wires without width. These thin wires have layer information and real holes. For example, for a net, it is output from the Z pin of a buffer_X to the I pin of the next buffer_Y. From the Z pin of buffer_X, there is a VIA12, and then a thin wire of M2 is connected, and then goes to M3 through VIA23, and then M3 is connected to the A pin of buffer_Y through VIA23, M2 and VIA12. In this way, it is a complete global route. It has four VIAs and three connecting wires.

[0138] In addition to thin lines and vias, global route contains a lot of useful information, such as NDR. For some nets with double space requirements, global route will comply, and for some nets that can only be placed on a certain layer, global route can also comply.

[0139] It can be said that the constraints on nets are basically all completed by global route. At the same time, the result of global route largely determines the final routing quality.

[0140] route_global is very useful and can be said to be everywhere in PnR. For example, initial drc calls global route to grow the buffer tree better; placer calls route_global to evaluate congestion; optimizer calls route_global for pre-route RC evaluation; CTS calls global route to grow the clock tree, and even route_eco will call global route to connect the broken wires.

[0141] route_track creates metals (shapes) based on the results of global route without considering DRC. After route_track is completed, the thin lines disappear and become metals with width. Since other costs are not considered, the route_track process is very fast. However, there are also timing_driven and crosstalk_driven versions.

[0142] route_detail(-incr) repairs DRC. The shapes after route_track definitely have a large number of DRCs, and the more complex the process, the more DRCs there are. Repairing DRCs depends entirely on the route_detail engine. Generally, the default is 40 rounds, but it doesn't necessarily have to wait until 40 rounds to end. For example, if it is found that the number of DRCs cannot be repaired, route_detail will exit early.

[0143] route_group routes the specified nets. route_group can be understood as a fast version of route_auto. It routes the specified nets and also includes the three steps of route_global, route_track, and route_detail. Since it only routes the specified nets, it is very fast.

[0144] A common scenario is to route some timing-critical nets in advance to make them run in a straight line, or to route the clock tree.

[0145] route_eco, reroutes the nets (or newly added nets) that are disconnected after eco (timing or function) and repairs DRC. This command is often used in the timing stage, because after ECO, the rerouting must be disconnected, or there is DRC, or there are newly added nets that need to be rerouted. No matter what the situation is, route_eco is used to handle it.

[0146] route_eco actually performs two actions, namely: connecting the new / disconnected net (calling route_global+route_track), and repairing DRC (calling route_detail-incr). When repairing DRC, you can only repair the DRC of ECOnet, or you can repair the DRC of all nets.

[0147] In general, although route_eco can be used to fix DRC, that is, route_eco's connection to a new / disconnected net does not work, only fixing DRC works, but it is recommended to use route_detail-incr to fix DRC.

[0148] route_opt, optimizes timing (also optimizes area, power consumption, transition, hold, etc.), and does ecorouting. Specifically, route_opt can be understood as three steps:

[0149] 1. Post route optimization, optimize setup, area, power consumption, transition, hold, etc. (mainly size_cell and insert_buffer)

[0150] 2. Legalize_placement. After the first step, there are many cells that overlap or are not on the site row. Legalizer is needed to place them on the legal location.

[0151] 3. route_eco, after post route optimization and legalize_placement, the routing loss is large, so route_eco needs to be called. The tool defaults to 5 rounds, which can be set to 10 or more. route_opt can also run multiple rounds to get a better PPA.

[0152] Furthermore, in the embodiments of the present application, when the PnR tool performs routing processing based on the library file and design data, after executing the optimize timing command, that is, after completing route_opt, the first write command can be executed, and then the current hold report, netlist, and def in the PnR tool are written out, that is, the first report, the first netlist, and the first file are obtained.

[0153] It can be understood that in the embodiments of the present application, before the backend design tool enters timing ECO, a correction process can be added in the Routing stage. This correction process is used to correct the inconsistency between the PnR tool and the STA tool, so as to save the correction time and iteration times in the ECO process.

[0154] Specifically, in the embodiments of the present application, when the backend design tool adds a correction process in the Routing stage, after completing route_opt, the current hold report, netlist, and def can be written out first, and then the subsequent correction process is performed using the current hold report, netlist, and def. At this time, the original backend design process is temporarily suspended but not exited.

[0155] It can be understood that in the present application, the def file is a description of the design. Therefore, the def can be written out from the backend tool according to the design requirements. The information in the def file describes the design, and specifically can include PIN foot information, length, height, coordinate positioning, the area size of digital PR, etc.

[0156] It should be noted that in the embodiments of the present application, the first report written by the PnR tool includes holdslack. Specifically, slack can be used to indicate whether the design meets the timing requirements, and can be divided into setup slack and holdslack. If the value of slack is positive, it indicates that the design can meet the setup time or hold time requirements, otherwise it indicates that the design does not meet the setup time or hold time requirements.

[0157] Further, in the embodiments of the present application, if the setup slack is positive, indicating that the Data Required Time is after the Data Arrival Time, the setup time must be satisfied. Conversely, the setup time is not satisfied; if the hold slack is positive, indicating that the Data Arrival Time is after the Data required Time, the hold time must be satisfied. Conversely, the hold time is not satisfied.

[0158] It should be noted that in the embodiments of the present application, the hold slack written by the PnR tool during the execution of the calibration process only represents the timing information of the PnR tool at the current moment, and is not completely accurate and real. Therefore, in the subsequent processing flow, the hold slack in the first report needs to be corrected.

[0159] Step 203: Based on the first netlist and the first file, the STA tool executes the first analysis command to generate a second report.

[0160] In the embodiments of the present application, after the PnR tool executes the first write command to obtain the first report, the first netlist, and the first file, based on the first netlist and the first file, the STA tool can execute the first analysis command to generate a second report.

[0161] Further, in the embodiments of the present application, after the PnR tool executes the write instruction to write out the first report, the first netlist, and the first file, based on the first netlist and the first file, the STA tool can execute the first analysis command and then generate a second report.

[0162] It should be noted that in the embodiments of the present application, during the process of the STA tool executing the first analysis command based on the first netlist and the first file to generate a second report, the backend design tool can first execute the first insertion command based on the first netlist and the first file to perform insertion processing on the gaps; then, the backend design tool can execute the first extraction command to extract the first parasitic parameters; finally, the STA tool can execute the first analysis command to perform static analysis processing on the first parasitic parameters, and then generate a second report.

[0163] That is to say, in the present application, based on the layout result obtained from the first netlist and the first file, the STA tool can extract delay data according to the estimated wire length for static timing analysis.

[0164] It can be understood that in the present application, when the backend design tool executes the first insertion command based on the first netlist and the first file, it mainly performs the insertion processing of fillers and dummies.

[0165] Specifically, in the present application, "filler" refers to the std cell filler, which is the fill silicon layer, poly, and the underlying power rails. Its main purpose is to connect the power supply and the well region. Further, "filler" refers to the logic-independent fillers defined in the standard cell library and the I / O Pad library, which are used to fill the gaps between standard cells and between I / O Pads. The insertion of fillers (pad filler, cell filler) is mainly to connect the diffusion layers to meet the DRC rules and design requirements.

[0166] Specifically, in the present application, "dummy" refers to dummy metal, which is for filling the upper metal layer. Its main purpose is to ensure the effect of CMP. Further, foundries have regulations on the metal density to ensure that the metal density is not lower than a certain value to prevent over-etching of the metal layer of the connection wires during the etching stage in the chip manufacturing process, thereby reducing the circuit performance. Adding dummy metal is to increase the metal density.

[0167] It can be understood that in the present application, when the backend design tool executes the first extraction command based on the first netlist and the first file, it is mainly for extracting parasitic parameters. Among them, the tool for extracting parasitic parameters can be Star-RCXT of Synopsys.

[0168] Specifically, in the present application, due to the resistance of the wire itself, the mutual inductance between adjacent wires, and the coupling capacitance, signal noise, crosstalk, and reflection will be generated inside the chip. These effects will cause signal integrity problems, resulting in signal voltage fluctuations and changes. If it is serious, it will lead to signal distortion errors. To solve this problem, the backend design tool can extract parasitic parameters for re-analysis and verification.

[0169] Further, in the embodiments of the present application, in the second report generated by the STA tool executing the first analysis command and analyzing the extracted first parasitic parameters, there is also hold slack. Compared with the hold slack of the PnR tool in the first report, the hold slack corresponding to the STA tool is accurate and real. Therefore, the hold slack in the second report obtained by referring to the STA tool should be used.

[0170] Step 204: Based on the first report and the second report, correct the information of the PnR tool to obtain the corrected information.

[0171] In the embodiments of the present application, after the STA tool executes the first analysis command and generates the second report, it can correct the information of the PnR tool according to the first report and the second report to obtain the corrected information.

[0172] It should be noted that in the embodiments of the present application, when the backend design tool corrects the information of the PnR tool based on the first report and the second report to obtain the corrected information, it can first determine the margin difference according to the hold slack in the first report and the hold slack in the second report; then, correct the information of the PnR tool according to the margin difference.

[0173] Furthermore, in the embodiments of the present application, the hold slack in the first report written by the PnR tool is not entirely accurate and true. In contrast, the hold slack obtained by the STA tool in the second report can be considered accurate and true. Therefore, the margin difference can be determined first by using the hold slack in the first report and the hold slack in the second report, that is, perform a difference operation on the two hold slacks to obtain the difference result.

[0174] It can be understood that in the embodiments of the present application, after determining the margin difference according to the hold slack in the first report and the hold slack in the second report, the backend design tool can correct the information of the PnR tool according to the margin difference.

[0175] Specifically, in the embodiments of the present application, when the backend design tool corrects the information of the PnR tool according to the margin difference, it can back-annotate the calculated margin difference to the PnR tool, thereby completing the correction of the information of the PnR tool.

[0176] It should be noted that in the embodiments of the present application, during the execution of the correction process, the PnR tool writes to obtain the first report, and the STA tool obtains the second report. Although the hold slack in the second report can be considered correct and true, since the PnR tool cannot directly obtain the hold slack in the second report, the PnR tool cannot directly use the hold slack in the second report to correct its own timing information.

[0177] Furthermore, in the embodiments of the present application, after completing the correction of the information of the PnR tool, the correction process proposed in steps 202 to 204 as above ends. In this correction process, the backend design tool directly completes the correction of the information of the PnR tool by using the first report and the second report, so that in the subsequent ECO process, there is no need to continuously iterate to correct the information of the PnR tool, thereby saving the time and power consumption of the ECO process.

[0178] Step 205: Based on the library file and design data, the STA tool executes a second analysis command to obtain a timing report.

[0179] In the embodiments of the present application, after correcting the information of the PnR tool according to the first report and the second report to obtain the corrected information, the STA tool can continue to execute the second analysis command based on the library file and design data to obtain a timing report.

[0180] It can be understood that in the embodiments of the present application, after the correction process is completed, the back-end design tool can continue to execute the interrupted back-end design process. Specifically, the STA tool can continue to execute the second analysis command to further obtain a timing analysis result, that is, a timing report.

[0181] It should be noted that in the embodiments of the present application, since the wiring has been completed, the authenticity of the delay data extracted at this time is relatively high. Therefore, further optimization based on this should be able to effectively remove any setup and hold violations.

[0182] Furthermore, in the embodiments of the present application, if a complete layout result is obtained based on the library file and design data and there is no congestion problem, the STA tool can extract delay data according to the estimated wire length for static timing analysis to complete the analysis and processing of the timing path of the circuit designed based on the library file and design data, and output a timing report.

[0183] It can be understood that in the embodiments of the present application, the specific process for the STA tool to execute the second analysis command based on the library file and design data may include: the back-end design tool first executes a second insertion command based on the library file and design data to perform an insertion process on the gap; then, the back-end design tool can execute a second extraction command to extract the second parasitic parameters; finally, the STA tool executes the second analysis command to perform static analysis on the second parasitic parameters, and a timing report can be generated.

[0184] Step 206: If there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool other than the corrected information.

[0185] In the embodiments of the present application, based on the library file and design data, after the STA tool executes the second analysis command to obtain a timing report, if there is a timing violation in the timing report, then a change command needs to be executed to perform an engineering change on other information of the PnR tool other than the corrected information.

[0186] Further, in the embodiments of the present application, after the STA tool completes the timing analysis and obtains the timing report, it is possible to determine whether there are timing violations in the current design result according to the timing report. If there are timing violations, then the backend design tool needs to perform ECO processing.

[0187] Different from common solutions, the ECO method proposed in the present application no longer requires correcting the information of the PnR tool to obtain the corrected information, but only needs to correct other information outside of it, so as to be able to accurately fix hold, and the process is simple and easy to implement, which is very helpful for reducing project timing convergence and achieving tapeout on time.

[0188] It can be understood that in the present application, precisely because in the chip routing stage, the backend design tool suspends the routing process in the backend design process without exiting, and simultaneously inserts a correction process, and completes the correction process of the information of the PnR tool, so that in the subsequent ECO process, it is no longer necessary to perform ECO processing on the information of the PnR tool, greatly reducing the number of iterations.

[0189] Generally, the backend design tool can start to repair hold after CTS. According to the execution process of the chip backend design process, the correction of Hold violations that may occur in each stage can use Synopsys's PnR tool ICC.

[0190] Exemplarily, in the present application, for the Hold violations that occur after CTS and before routing, >psynopt-only_hold_time can be used for repair. Among them, the psynopt command has two functions, one is to perform incremental timing-driven logic optimization; the other is to Legalizes placement.

[0191] Exemplarily, in the present application, for the Hold violations that occur in the routing stage, CCD can be used for repair:

[0192] >set_concurrent_clock_and_data_strategy;

[0193] >route_opt-concurrent_clock_and_data;

[0194] It can also be repaired by specifying the routing optimization option:

[0195] >route_opt-incr-only_hold_time.

[0196] Exemplarily, in the present application, for Hold violations occurring in the chipfinish stage, CCD can be used for repair:

[0197] >focal_opt-concurrent_clock_and_data

[0198] -hold_endpoints all

[0199] The software can also be made to automatically repair all hold endpoints:

[0200] >focal_opt-hold_endpoints all

[0201] -effort high

[0202] It is also possible to specify the REG2REG path for repair. If the violations are all concentrated on the REG2REG path, then use:

[0203] >focal_opt-hold_endpoints all

[0204] -register_to_register

[0205] If, in a specific stage, the method of automatic repair using commands cannot repair the violation and the violated value is very large, then it is necessary to manually insert a buffer or a delay cell to solve it, that is, use the ECO method to manually solve it. Before insertion, make sure that no Core filler is inserted, or if there is a filler, remove it.

[0206] Among them, the inserted buffer is placed randomly, and it may overlap with other Cells, or it is not placed on the Row. Therefore, it needs to be placed in a reasonable position. The inserted buffer has no connections, and ECO is required to connect it.

[0207] If the manual ECO method is not used, it is also possible to import the netlist and spef of the entire design into PT, let PT repair it by itself, then export the ECO script, and then import the script into ICC for repair.

[0208] It should be noted that the repair of hold does not need to be clean at every stage. For example, for the relatively old 0.18um process, a WNS violation of about 0.1ns after CTS is still allowed. After all, there are still routing operations later, and wire delay is also beneficial to hold. A very small number of violations with a magnitude of about 0.01 are also allowed after routing and can be solved by focal_opt.

[0209] Specifically, in this application, ECO refers to the situation where the total number of changed (including added and deleted) cells is less than 10%. For too large a change, it is recommended to start over. If you don't want to change the clock tree, it is required that ECO does not involve the addition or deletion of flip-flops or the movement of their positions, but changing the size (size up / down) of existing flip-flops is allowed if the clock tree has not been routed yet. And general logic combination cells (cells) can be modified in any way. The placement change (Placement ECO) and static timing analysis and re-optimization (STA&OPT) can be looped multiple times until there are no major violations.

[0210] In contrast, the routing ECO is more restricted than the placement ECO. Any modification of flip-flops is not allowed, and only logic combination cells (cells) can be changed. Any change to a cell connected to the clock tree will cause a change in the clock tree wiring. To minimize the impact on timing as much as possible, it is recommended to manually modify the clock tree. The routing ECO can be looped multiple times until all setup and hold violations are removed.

[0211] Step 207: The STA tool continues to execute the next analysis command until the obtained timing report has no timing violations, and then outputs the layout.

[0212] In the embodiments of this application, after completing the engineering change for information other than the corrected information of the PnR tool, the STA tool can continue to execute the next analysis command until the obtained timing report has no timing violations, thereby ending the back-end design process of the chip and outputting the layout.

[0213] That is to say, in the embodiments of this application, after completing one ECO repair, the back-end design tool can iterate to the next round to continue the timing analysis. Specifically, the STA tool continues to execute the next analysis command and obtains the next timing report. If the next timing report still has timing violations, then continue with the ECO process until the obtained timing report has no timing violations, at which point the layout can be output.

[0214] It should be noted that in the embodiments of the present application, the backend design tool outputs the layout in the GDSII format. That is to say, the layout is delivered to the Foundry factory in the GDSII file format (the actual circuit is made on the silicon wafer of the wafer, and then packaged and tested to obtain the actual chip).

[0215] It can be seen that for the chip backend design process, the input data includes the gate-level netlist, library files, and timing constraints. After the design and ECO repair by the backend design tool, the finally output is the layout in the GDSII format.

[0216] In summary, through the chip backend design method proposed in the above steps 201 to 207, the backend design tool can basically achieve hold violation clean in the PnR stage by correcting the correlation between the PnR tool and the STA tool in the routing stage, greatly reducing the iteration times of timing fix and reducing the risk of timing fix. In addition, due to the correction of the correlation between the PnR tool and the STA tool, it is avoided to misinsert a large number of delay cells for fixing hold, thereby effectively reducing the dynamic power consumption. That is to say, in the present application, the backend design tool does not exit the wiring process in the chip routing stage but inserts a correction process to correct the correlation between the PnR tool and the STA tool, which can accurately fix hold, and the process is simple and easy to implement, which is very helpful for reducing the timing convergence of the project and achieving tapeout on time.

[0217] An embodiment of the present application provides a chip backend design method. The backend design tool imports a library file and design data. Among them, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip. When the routing PnR tool performs routing processing based on the library file and design data, after executing the optimize timing command, a first write command is executed to obtain a first report, a first netlist, and a first file. Based on the first netlist and the first file, the static timing analysis STA tool executes a first analysis command to generate a second report. Based on the first report and the second report, the information of the PnR tool is corrected to obtain corrected information. Based on the library file and design data, the STA tool executes a second analysis command to obtain a timing report. If there is a timing violation in the timing report, a change command is executed to perform ECO processing on other information of the PnR tool except the corrected information. The STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and then outputs the layout. That is to say, in the present application, in the routing stage, a correction process is inserted to perform precise correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem of increased iteration times in the ECO process caused by the inconsistency between the PnR tool and the STA tool, greatly reducing the iteration times of the ECO process, shortening the time of chip backend design, and effectively improving the chip design efficiency.

[0218] Based on the above embodiment, in another embodiment of the present application, Figure 4 Schematic diagram of the implementation process of the chip backend design method Figure 2 , such as Figure 4 shown, in the embodiment of the present application, after the STA tool executes the second analysis command based on the library file and design data to obtain a timing report, that is, after step 205, the chip backend design method may further include the following steps:

[0219] Step 208, if there is no timing violation in the timing report, then output the layout.

[0220] In the embodiment of the present application, based on the library file and design data, after the STA tool executes the second analysis command to obtain a timing report, if there is no timing violation in the timing report, then there is no need to execute the change command, and the layout can be directly output.

[0221] Further, in the embodiment of the present application, Figure 5 Schematic diagram of the implementation process of the chip backend design method Figure 3 , such as Figure 5As shown, in the embodiments of the present application, when the PnR tool performs routing processing based on the library file and design data, before executing the first write command and obtaining the first report, the first netlist, and the first file after executing the optimized timing command, that is, before step 202, the chip backend design method may further include the following steps:

[0222] Step 209: Based on the library file and design data, the PnR tool executes a placement command to perform placement processing.

[0223] Step 2010: Based on the library file and design data, the PnR tool executes a generation command to generate a clock tree.

[0224] In the embodiments of the present application, after importing the library file and design data, the placement command can be executed first to perform placement processing based on the library file and design data, and then the generation command can be executed to generate a clock tree based on the library file and design data.

[0225] It should be noted that in the embodiments of the present application, placement mainly refers to how to reasonably place standard cells. Generally, it is not desirable for the software to move the placed mega cells too much. Placement can be simply performed according to the connections of the cells, or according to timing requirements, or mainly based on congestion.

[0226] Exemplarily, in the present application, the placement tool can select Astro from Synopsys.

[0227] As the chip speed increases, more and more solutions first choose to place components according to timing requirements. In this case, timing constraints are required. Before the placement starts, some grouping or partitioning can be done first. The advantage is that it can tell the placement software a general placement range. However, this approach may conflict with the given timing requirements, especially for the connecting cells at the boundaries. Therefore, it is recommended to be as loose as possible when defining the grouping or partitioning and allow a certain percentage of cells to be placed outside the grouping or partitioning. The result of doing this has the same effect as the so-called amoeba placement.

[0228] If a timing-required placement is used and the timing engine used for placement is different from the engine used for routing or calculating delays, attention should be paid to the calculation errors between the engines, and sometimes they can differ by a factor of 10.

[0229] It should be noted that in the embodiments of the present application, clock tree synthesis (CTS) is the routing of the clock. Due to the global command function of the clock signal in the digital chip, its distribution should be symmetrically connected to each register unit, so that when the clock reaches each register from the same clock source, the clock delay difference is minimized. Therefore, the clock signal needs to be routed separately.

[0230] Exemplarily, in the present application, the CTS tool can select Synopsys Physical Compiler.

[0231] Furthermore, in the embodiments of the present application, in large-scale integrated circuits, the data transmission of most timing elements is controlled by clock synchronization. The clock frequency determines the speed of data processing and transmission, and the clock frequency is the most important indicator of circuit performance. In the deep sub-micron stage of integrated circuits, there are two main factors determining the clock frequency. One is the longest circuit delay in the combinational logic part, and the other is the clock skew within the synchronous elements. As the transistor size decreases, the switching speed of the combinational logic circuit continuously increases, and the clock skew becomes a limiting factor affecting circuit performance. The main purpose of clock tree synthesis is to reduce the clock skew.

[0232] Taking a clock domain as an example, a clock source point (source) ultimately needs to fan out to the clock terminals (sinks) of many registers. The fan-out from the clock source is very large and the load is very heavy, and the clock source cannot drive so many subsequent loads. Thus, a clock tree structure is required, and through buffers level by level to drive the final leaf nodes (registers).

[0233] Specifically, compared with a buffer tree, the difference between a clock tree and a buffer tree is that a buffer tree generally only considers the driving ability and does not care about issues such as the delay and skew of the tree. It is mainly used for connections without timing requirements such as reset and scan enable.

[0234] It should be noted that in the present application, several items such as the root node of the tree, the clock period, the maximum delay of the tree, the minimum delay of the tree, skew, transition time, and the type of buffer are common necessary indicators when making a clock tree. There are also some optional items: especially the leaf pins, the excluded pins, and the preserved cells such as the cells that need to be specifically retained in the clock tree.

[0235] In an embodiment of the present application, further, after importing the library files and design data, I / O unit placement (I / O Place), megacell placement (Megacell Place), row generation, and power routing can also be performed.

[0236] Specifically, in the present application, when the backend design tool performs I / O unit placement, it needs to consider the positions of internal modules, the number and types of power PADs. Different types of signal PADs require different types of power supplies, and some power supplies with the same voltage cannot be shared either. In particular, analog signals and their power supplies themselves need to be isolated from other signals. The calculation of the number of power PADs should take into account the minimum requirements of chip packaging and the power consumption inside the chip.

[0237] Specifically, in the present application, components such as ADC, DAC, PLL, and memory belong to megacells. All backend EDA layout software has the function of automatically placing megacells. Generally, in designs with more than five megacells, manual placement of megacells is selected. Before placement, it is necessary to understand the flow direction of operation data, the relationships and positions between major modules, and based on this, determine the general positions of the megacells.

[0238] Further, in the present application, when placing each megacell one by one, it is necessary to consider the positions, directions, quantities, and corresponding relationships between their pins. Since megacells often prohibit the use of several metal wiring layers, it is necessary to pay attention to leaving enough space for the signal lines passing through it, especially the distance between megacells.

[0239] If the megacell itself does not have a power ring, then a larger space should be left around it for adding a ring. The width of the ring is obtained according to the formula provided by the manufacturer based on speed and data change rate. Some software can combine several adjacent megacells together to form a ring to save space. At this time, the width of the common ring should be the largest among the widths of each individual ring. A common floor plan method is to place megacells around the perimeter and standard cells in the middle. The best shape for the space left for standard cells is square.

[0240] Specifically, in the present application, the row channel (Row) is used to place standard cells, and its overall shape is generally determined by the positions of megacells. A certain space should be left between the row channel (row) and the megacells to facilitate the signal connection of the megacells. A small amount of row channels can be made between the megacells in case the connection lines are too long, for buffer relay or for use when generating a clock tree.

[0241] Specifically, in the present application, when performing power supply wiring, the wiring density is different according to the different power consumptions of each module. After the power supply wiring is completed, the overall power supply situation can be inspected. In a traditional design where power is supplied through pins around the perimeter and standard cells are placed in the center, a power ring can be added around the rows where standard cells are concentrated.

[0242] The embodiment of the present application provides a method for chip backend design. The backend design tool imports library files and design data. Among them, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip. When the routing PnR tool performs wiring processing based on the library files and design data, after executing the optimize timing command, a first write command is executed to obtain a first report, a first netlist, and a first file. Based on the first netlist and the first file, the static timing analysis STA tool executes a first analysis command to generate a second report. Based on the first report and the second report, the information of the PnR tool is corrected to obtain the corrected information. Based on the library files and design data, the STA tool executes a second analysis command to obtain a timing report. If there is a timing violation in the timing report, a change command is executed to perform ECO processing on the information of the PnR tool other than the corrected information. The STA tool continues to execute the next analysis command until there is no timing violation in the obtained timing report, and then outputs the layout. That is to say, in the present application, in the routing stage, a correction process is inserted to perform precise correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem of increased number of iterations in the ECO process caused by the inconsistency between the PnR tool and the STA tool, greatly reducing the number of iterations in the ECO process, and thus shortening the time for chip backend design and effectively improving the chip design efficiency.

[0243] Based on the above embodiment, in another embodiment of the present application, before importing the library files and design data, that is, before step 201, the method for chip backend design may further include the following steps:

[0244] Step 2011: Execute the first startup command to start the backend design process.

[0245] In an embodiment of the present application, before starting the chip backend design, the backend design tool can execute the first startup command to start the backend design process. After the chip backend design starts, the backend design tool first loads the library file and design data into the local storage space.

[0246] It should be noted that, in an embodiment of the present application, step 202 may include:

[0247] Step 202a: When the PnR tool performs routing processing based on the library file and design data, execute the optimization timing command.

[0248] And after step 202a, that is, after executing the optimization timing command,

[0249] Step 202b: The PnR tool executes the first write command to obtain the first report, the first netlist, and the first file.

[0250] Furthermore, in an embodiment of the present application, when the PnR tool performs routing processing based on the library file and design data, after executing the optimization timing command, that is, after step 202a, the chip backend design method may further include the following steps:

[0251] Step 2012: Execute the first stop command to abort the routing processing in the backend design process.

[0252] Step 2013: Execute the second startup command to start the correction process to correct the information of the PnR tool through the correction process and obtain the corrected information.

[0253] In an embodiment of the present application, in the routing stage, that is, in the routing processing in the backend design process, the backend design tool can execute the first stop command to temporarily abort the routing processing in the backend design process, that is, pause routing. At this time, it does not exit the chip backend design process.

[0254] Furthermore, in an embodiment of the present application, the backend design tool can also execute the second startup command to start the correction process, so that the information of the PnR tool can be corrected through the correction process and the corrected information can be obtained.

[0255] It should be noted that, in the present application, the correction process can be used to correct the correlation between the PnR tool and the STA tool to improve the consistency between the two.

[0256] It can be understood that in the embodiments of the present application, the backend design tool can either sequentially execute the methods of step 2012 and step 2013, or notify the execution of the methods of step 2012 and step 2013.

[0257] Further, in the embodiments of the present application, after correcting the information of the PnR tool based on the first report and the second report and obtaining the corrected information, that is, after step 204, the chip backend design method may further include the following steps:

[0258] Step 2014, execute the third start command to continue the backend design process to complete the backend design of the chip and output the layout.

[0259] In the embodiments of the present application, after the backend design tool completes the correction of the information of the PnR tool according to the first report and the second report, it can execute the third start command to continue the backend design process, and after multiple iterations, complete the backend design of the chip and output the layout.

[0260] It should be noted that in the embodiments of the present application, after the execution of the calibration process is completed, the information of the PnR tool has been corrected. Therefore, when the backend design tool continues the backend design process, it only needs to repair other information other than the corrected information of the PnR tool, and does not need to perform iterative repair on the information of the PnR tool, thereby greatly reducing the number of iterations, accelerating tapeout, and saving power consumption.

[0261] Further, in the embodiments of the present application, Figure 6 is a schematic diagram of the backend design process of the chip proposed by the present application. As Figure 6 shown, compared with the current ECO process in the above Figure 2 , before the project enters the timing ECO, the backend design tool of the present application adds a calibration process in the Routing stage. The specific method is as follows: after route_opt, execute the write instruction to write out the current hold report, netlist, and def (step 108c). At this time, the ECO process stops but does not exit, and insert dummy filler (step 108d), starRC (step 108e), and STA process (step 108f) are called in the background, and then the corresponding STA hold report is generated and compared with the hold report generated by the PnR tool to determine the difference in hold slack. Then, the backend design tool can backannotate the difference in hold slack to the current PnR to achieve fix hold (step 108g). After completing the calibration process, continue to execute step 106.

[0262] It can be seen that in this application, during the routing stage, the backend design tool corrects the correlation between the PnR tool and the STA tool, and basically can achieve a clean hold violation during the PnR stage, greatly reducing the number of iterations of timing fixes and reducing the risk of timing fixes. In addition, due to the correction of the correlation between the PnR tool and the STA tool, a large number of delay cells are avoided from being erroneously inserted for fixing hold, thus effectively reducing the dynamic power consumption. That is to say, in this application, during the routing stage of the chip, the backend design tool does not exit the wiring process in the backend design flow but inserts a correction process to correct the correlation between the PnR tool and the STA tool, which can accurately fix hold, and the process is simple and easy to implement, which is very helpful for reducing the timing convergence of the project and achieving tapeout on time.

[0263] The embodiment of this application provides a chip backend design method. The backend design tool imports library files and design data. Among them, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip. When the wiring PnR tool performs wiring processing based on the library files and design data, after executing the optimize timing command, it executes the first write command to obtain the first report, the first netlist, and the first file. Based on the first netlist and the first file, the static timing analysis STA tool executes the first analysis command to generate the second report. Based on the first report and the second report, the information of the PnR tool is corrected to obtain the corrected information. Based on the library files and design data, the STA tool executes the second analysis command to obtain the timing report. If there is a timing violation in the timing report, the change command is executed to perform ECO processing on the information other than the corrected information of the PnR tool. The STA tool continues to execute the next analysis command until there is no timing violation in the obtained timing report, and then outputs the layout. That is to say, in this application, during the routing stage, a correction process is inserted to perform precise correction processing based on the first report obtained by the PnR tool and the second report obtained by the STA tool to correct the correlation between the PnR tool and the STA tool, so as to solve the problem of increased number of iterations in the ECO process caused by the inconsistency between the PnR tool and the STA tool, which can greatly reduce the number of iterations in the ECO process, thereby shortening the time of chip backend design and effectively improving the chip design efficiency.

[0264] An embodiment of this application provides a layout design method. Figure 7 It is a schematic diagram of the implementation process of the layout design method. As Figure 7 shown, in the embodiment of this application, the layout design method may include the following steps:

[0265] Step 301: Receive a fourth start command, start the layout design process, and parse the library file and design data carried in the fourth start command; wherein, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip.

[0266] Step 302: When calling the routing PnR tool to perform routing processing in the layout design process based on the library file and design data, if the timing optimization command is executed, generate a second stop command and a second write command.

[0267] Step 303: Respond to the second stop command to abort the routing processing, and at the same time respond to the second write command to obtain a third report, a second netlist, and a second file.

[0268] Step 304: Based on the second netlist and the second file, call the STA tool to perform static timing analysis processing and generate a fourth report.

[0269] Step 305: Receive a fifth start command, start the correction process, and correct the information of the PnR tool based on the third report and the fourth report to obtain the corrected information.

[0270] Step 306: Receive a sixth start command, continue the layout design process based on the corrected information, and output the layout.

[0271] In the embodiments of the present application, after the front-end design is completed, when the EDA tool performs layout design, it can first receive a fourth start command, start the layout design process, and parse the library file and design data carried in the fourth start command. Among them, importing the library file and design data can also be understood as the start of the layout design process.

[0272] It should be noted that, in the embodiments of the present application, the EDA tool can first import the required data when performing layout design. Specifically, these data can specifically include a library file and design data. Among them, the library file can be a library file of standard cells, macro cells, and I / O Pads provided by a chip foundry (Foundry factory), which includes a physical library, a timing library, and a netlist library, and are given in the forms of.lef,.tlf, and.v respectively. And the design data can be a gate-level netlist generated after synthesis of the chip front-end design, a script file with timing constraints and clock definitions, and a resulting.gcf constraint file.

[0273] Furthermore, in the embodiments of the present application, the EDA tool is the EDA tool, which may include a variety of tools provided by different suppliers. Specifically, different EDA tools can be used when executing different commands and performing different types of processing. For example, common layout PnR tools include IC Compiler from Synopsys, Astro, and SOC-Enconter from Candance. Among them, IC Compiler is another PnR tool launched by Synopsys after Astro, and Astro is commonly used for layout and wiring of ultra-deep submicron levels below the 10nm process.

[0274] In the embodiments of the present application, after importing the library file and design data, the EDA tool calls the PnR tool to perform wiring processing based on the library file and design data. During the wiring processing, after executing the optimize timing command, the EDA tool can generate a second stop command and a second write command. Then, in response to the second stop command, the wiring processing can be aborted, and at the same time, in response to the second write command, a third report, a second netlist, and a second file can be obtained.

[0275] Exemplarily, in the present application, the PnR tool can be Astro from Synopsys.

[0276] It should be noted that in the embodiments of the present application, the route commands related to wiring mainly include: route_auto, route_opt, route_eco, route_group, route_global, route_track, route_detail.

[0277] Furthermore, in the embodiments of the present application, when the PnR tool performs wiring processing based on the library file and design data, after executing the optimize timing command, that is, after completing route_opt, a second write command can be executed, and then the current hold report, netlist, and def in the PnR tool are written out, that is, the third report, the second netlist, and the second file are obtained.

[0278] Specifically, in the embodiments of the present application, when the EDA tool adds a correction process in the Routing stage, after completing route_opt, the current hold report, netlist, and def can be written out first, and then the subsequent correction process is performed using the current hold report, netlist, and def. At this time, the original layout design process is temporarily aborted but not exited.

[0279] Further, in the embodiments of the present application, after the EDA tool writes out the third report, the second netlist, and the second document, it can call the STA tool to perform static timing analysis processing based on the second netlist and the second document to generate a fourth report.

[0280] It should be noted that, in the embodiments of the present application, the EDA tool can receive a fifth start command to start the correction process, and then can correct the information of the PnR tool based on the third report and the fourth report to obtain the corrected information. Specifically, the EDA tool can first determine the margin difference according to the hold slack in the third report and the hold slack in the fourth report; then, correct the information of the PnR tool according to the margin difference.

[0281] It can be understood that, in the embodiments of the present application, after determining the margin difference according to the hold slack in the third report and the hold slack in the fourth report, the EDA tool can correct the information of the PnR tool according to the margin difference.

[0282] Specifically, in the embodiments of the present application, when the EDA tool corrects the information of the PnR tool according to the margin difference, it can backannotate the calculated margin difference to the PnR tool, thereby completing the correction of the information of the PnR tool.

[0283] Further, in the embodiments of the present application, after completing the correction of the information of the PnR tool, the correction process ends. In this correction process, the EDA tool completes the correction of the information of the PnR tool, so that in the subsequent ECO process, there is no need to continuously iterate to correct the information of the PnR tool, thereby saving the time and power consumption of the ECO process.

[0284] It can be understood that, in the embodiments of the present application, after the correction process ends, the EDA tool can receive a sixth start command and continue the layout design process based on the corrected information to output the layout.

[0285] It should be noted that, in the embodiments of the present application, the EDA tool outputs the layout in the GDSII format. That is to say, the layout is handed over to the Foundry factory in the GDSII file format (an actual circuit is made on the silicon wafer of the wafer, and then packaged and tested to obtain the actual chip).

[0286] Thus, for the chip layout design process, the input data includes the gate-level netlist, library files, and timing constraints. After the design and ECO repair by the EDA tool, the finally output is the layout in the GDSII format.

[0287] Specifically, in the present application, when continuing the layout design process based on the corrected information and outputting the layout, the EDA tool can first call the STA tool for static timing analysis processing based on the library file and design data to obtain a timing report. If there are timing violations in the timing report, a change command is executed to perform ECO processing on other information of the PnR tool except for the corrected information. Then, the EDA tool can continue to call the STA tool for static timing analysis processing until there are no timing violations in the obtained timing report, and then output the layout.

[0288] In summary, through the layout design method proposed in the above steps 301 to 306, the EDA tool can basically achieve hold violation clean in the PnR stage by correcting the correlation between the PnR tool and the STA tool in the routing stage, greatly reducing the iteration times of timing fix and reducing the risk of timing fix. In addition, due to the correction of the correlation between the PnR tool and the STA tool, it is avoided that a large number of delay cells are mis-inserted for fix hold, thereby effectively reducing the dynamic power consumption. That is to say, in the present application, the EDA tool does not exit the routing process in the chip routing stage of the layout design process, and at the same time inserts a correction process to correct the correlation between the PnR tool and the STA tool, which can accurately fix hold, and the process is simple and easy to implement, which is very helpful for reducing the timing convergence of the project and achieving tapeout on time.

[0289] An embodiment of the present application provides a layout design method. The EDA tool receives a fourth start command to start the layout design process and parses the library file and design data carried in the fourth start command. The design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip. When calling the routing PnR tool to perform routing processing in the layout design process based on the library file and design data, if the optimize timing command is executed, a second stop command and a second write command are generated. In response to the second stop command, the routing processing is aborted. At the same time, in response to the second write command, a third report, a second netlist, and a second file are obtained. Based on the second netlist and the second file, the STA tool is called to perform static timing analysis processing to generate a fourth report. A fifth start command is received to start the correction process, and the information of the PnR tool is corrected based on the third report and the fourth report to obtain the corrected information. A sixth start command is received to continue the layout design process based on the corrected information and output the layout. That is to say, in the present application, in the routing stage, a correction process is inserted to perform precise correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem of increased iteration times in the ECO process caused by the inconsistency between the PnR tool and the STA tool, greatly reducing the iteration times of the ECO process, shortening the layout design time, and effectively improving the layout design efficiency.

[0290] Based on the above embodiment, in another embodiment of the present application, Figure 8 Schematic diagram of the composition structure of the back-end design tool Figure 1 , as Figure 8 shown, the back-end design tool 10 proposed by the embodiment of the present application may include: an import unit 11, a first acquisition unit 12, a first generation unit 13, a first correction unit 14, a change unit 15, and a first output unit 16.

[0291] The import unit 11 is used to import a library file and design data. The design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip.

[0292] The first acquisition unit 12 is used to, when the routing PnR tool performs routing processing based on the library file and the design data, after the optimize timing command is executed, execute a first write command to obtain a first report, a first netlist, and a first file.

[0293] The first generation unit 13 is used to, based on the first netlist and the first file, the static timing analysis STA tool executes a first analysis command to generate a second report.

[0294] The first correction unit 14 is configured to correct the information of the PnR tool based on the first report and the second report, so as to obtain corrected information;

[0295] The first acquisition unit 12 is further configured to cause the STA tool to execute a second analysis command based on the library file and the design data, so as to obtain a timing report;

[0296] The change unit 15 is configured to, if there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool other than the corrected information;

[0297] The first acquisition unit 12 is further configured to cause the STA tool to continue to execute the next analysis command until there is no timing violation in the obtained timing report;

[0298] The first output unit 16 is configured to output a layout.

[0299] In an embodiment of the present application, further, Figure 9 It is a schematic structural diagram of a backend design tool Figure 2 As Figure 9 shown, the backend design tool 10 proposed in the embodiment of the present application may further include a first processor 17, a first memory 18 storing executable instructions of the first processor 17. Further, the backend design tool 10 may further include a first communication interface 19, and a first bus 110 for connecting the first processor 17, the first memory 18, and the first communication interface 19.

[0300] In an embodiment of the present application, the above-mentioned first processor 17 may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It can be understood that for different devices, the electronic devices used to implement the above-mentioned processor functions may be others, and the embodiments of the present application do not make specific limitations. The backend design tool 10 may further include a first memory 18, and the first memory 18 may be connected to the first processor 17. Among them, the first memory 18 is used to store executable program codes, and the program codes include computer operation instructions. The first memory 18 may include a high-speed RAM memory and may also include a non-volatile memory, for example, at least two disk memories.

[0301] In an embodiment of the present application, the first bus 110 is used to connect the first communication interface 19, the first processor 17, and the first memory 18 and for mutual communication between these devices.

[0302] In an embodiment of the present application, the first memory 18 is used to store instructions and data.

[0303] Further, in an embodiment of the present application, the above-mentioned first processor 17 is used to import library files and design data; among them, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip; when the routing PnR tool performs routing processing based on the library files and the design data, after executing the optimize timing command, it executes the first write command to obtain a first report, a first netlist, and a first file; based on the first netlist and the first file, the static timing analysis STA tool executes the first analysis command to generate a second report; based on the first report and the second report, the information of the PnR tool is corrected to obtain corrected information; based on the library files and the design data, the STA tool executes the second analysis command to obtain a timing report; if there are timing violations in the timing report, the change command is executed to perform ECO processing on other information of the PnR tool other than the corrected information; the STA tool continues to execute the next analysis command until there are no timing violations in the obtained timing report, and the layout is output.

[0304] In practical applications, the first memory 18 described above may be a volatile memory, such as a Random-Access Memory (RAM); or a non-volatile memory, such as a Read-Only Memory (ROM), a flash memory, a Hard Disk Drive (HDD), or a Solid-State Drive (SSD); or a combination of the above types of memories, and provides instructions and data to the first processor 17.

[0305] In addition, in each functional module of this embodiment, it may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software functional module.

[0306] If the integrated unit is implemented in the form of a software functional module and is not sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method of this embodiment. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0307] The embodiment of the present application provides a backend design tool. In the routing stage, the backend design tool inserts a correction process to perform precise correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem of increased number of iterations in the ECO process caused by the inconsistency between the PnR tool and the STA tool, greatly reducing the number of iterations in the ECO process, and then shortening the time of the chip backend design and effectively improving the chip design efficiency.

[0308] Based on the above embodiment, in another embodiment of the present application, Figure 10Schematic diagram of the composition structure of the EDA tool Figure 1 , as Figure 10 shown, the EDA tool 20 proposed in the embodiment of the present application may include: a receiving unit 21, a parsing unit 22, a calling unit 23, a second generating unit 24, an aborting unit 25, a second obtaining unit 26, a second correcting unit 27, and a second output unit 28,

[0309] The receiving unit 21 is configured to receive a fourth start command and start a layout design process;

[0310] The parsing unit 22 is configured to parse the library file and design data carried in the fourth start command; wherein, the design data includes a gate-level netlist and timing constraints obtained after front-end chip design;

[0311] The calling unit 23 is configured to, when performing routing processing in the layout design process by calling a routing PnR tool based on the library file and the design data;

[0312] The second generating unit 24 is configured to generate a second stop command and a second write command if an optimized timing command is executed;

[0313] The aborting unit 25 is configured to respond to the second stop command and abort the routing processing;

[0314] The second obtaining unit 26 is configured to obtain a third report, a second netlist, and a second file in response to the second write command;

[0315] The calling unit 23 is further configured to perform static timing analysis processing by calling a STA tool based on the second netlist and the second file, and generate a fourth report;

[0316] The receiving unit 21 is further configured to receive a fifth start command and start a correction process;

[0317] The second correcting unit 27 is configured to correct the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

[0318] The receiving unit 21 is further configured to receive a sixth start command;

[0319] The second output unit 28 is configured to continue the layout design process based on the corrected information and output a layout.

[0320] Further, in the embodiments of the present application, the second output unit 28 is specifically configured to perform static timing analysis processing by invoking the STA tool based on the library file and the design data to obtain a timing report; if there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool except for the corrected information; continue to invoke the STA tool to perform static timing analysis processing until there is no timing violation in the obtained timing report, and then output the layout.

[0321] Further, in the embodiments of the present application, the second correction unit 27 is specifically configured to determine the margin difference according to the hold slack in the third report and the hold slack in the fourth report; and correct the information of the PnR tool according to the margin difference.

[0322] In the embodiments of the present application, further Figure 11 Schematic diagram of the composition structure of the EDA tool Figure 2 , as Figure 11 shown, the layout design tool 20 proposed in the embodiments of the present application may further include a second processor 29, a second memory 210 storing executable instructions of the second processor 29. Further, the EDA tool 20 may further include a second communication interface 211 and a second bus 212 for connecting the second processor 29, the second memory 210, and the second communication interface 211.

[0323] The embodiments of the present application provide a backend design tool. In the routing stage, the EDA tool inserts a correction process to perform precise correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem of increased iteration times in the ECO process caused by the inconsistency between the PnR tool and the STA tool, greatly reducing the iteration times of the ECO process, shortening the layout design time, and effectively improving the layout design efficiency.

[0324] The embodiments of the present application provide a computer-readable storage medium, on which a program is stored. When the program is executed by a processor, the chip backend design method described above is implemented.

[0325] Specifically, the program instructions corresponding to a chip backend design method in this embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the program instructions corresponding to a chip backend design method in the storage media are read or executed by an electronic device, the following steps are included:

[0326] Import library files and design data; wherein, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip.

[0327] When the routing PnR tool performs routing processing based on the library file and the design data, after executing the optimize timing command, a first write command is executed to obtain a first report, a first netlist, and a first file;

[0328] Based on the first netlist and the first file, the static timing analysis (STA) tool executes a first analysis command to generate a second report;

[0329] Based on the first report and the second report, the information of the PnR tool is corrected to obtain corrected information;

[0330] Based on the library file and the design data, the STA tool executes a second analysis command to obtain a timing report;

[0331] If there is a timing violation in the timing report, a change command is executed to perform ECO processing on other information of the PnR tool except the corrected information;

[0332] The STA tool continues to execute the next analysis command until there is no timing violation in the obtained timing report, and then outputs the layout.

[0333] Specifically, the program instructions corresponding to a layout design method in this embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the program instructions corresponding to a layout design method in the storage media are read or executed by an electronic device, the following steps are included:

[0334] Receive a fourth start command to start the layout design process and parse the library file and design data carried in the fourth start command; wherein, the design data includes the gate-level netlist and timing constraints obtained after the front-end design of the chip;

[0335] When performing routing processing in the layout design process by calling the routing PnR tool based on the library file and the design data, if the optimize timing command is executed, a second stop command and a second write command are generated;

[0336] In response to the second stop command, the routing processing is aborted, and at the same time, in response to the second write command, a third report, a second netlist, and a second file are obtained;

[0337] Based on the second netlist and the second file, the STA tool is called to perform static timing analysis processing to generate a fourth report;

[0338] Receive a fifth start command to start the correction process and correct the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

[0339] Receive the sixth start command, continue the layout design process based on the corrected information, and output the layout.

[0340] An embodiment of the present application provides a chip, which includes a programmable logic circuit and / or program instructions. When the chip runs, it implements the chip backend design method described above, specifically including the following steps:

[0341] Import library files and design data; wherein, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip;

[0342] When the routing PnR tool performs routing processing based on the library files and the design data, after executing the optimize timing command, execute the first write command to obtain a first report, a first netlist, and a first file;

[0343] Based on the first netlist and the first file, the static timing analysis STA tool executes the first analysis command to generate a second report;

[0344] Based on the first report and the second report, correct the information of the PnR tool to obtain corrected information;

[0345] Based on the library files and the design data, the STA tool executes a second analysis command to obtain a timing report;

[0346] If there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool other than the corrected information;

[0347] The STA tool continues to execute the next analysis command until there is no timing violation in the obtained timing report, and output the layout.

[0348] An embodiment of the present application provides a chip, which includes a programmable logic circuit and / or program instructions. When the chip runs, it implements the layout design method described above, specifically including the following steps:

[0349] Receive the fourth start command, start the layout design process, and parse the library files and design data carried in the fourth start command; wherein, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip;

[0350] When performing routing processing in the layout design process by calling the routing PnR tool based on the library files and the design data, if the optimize timing command is executed, generate a second stop command and a second write command;

[0351] In response to the second stop command, abort the routing process, and at the same time, in response to the second write command, obtain a third report, a second netlist, and a second file;

[0352] Based on the second netlist and the second file, call the STA tool to perform static timing analysis processing to generate a fourth report;

[0353] Receive a fifth start command, start the calibration process, and correct the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

[0354] Receive a sixth start command, continue the layout design process based on the corrected information, and output the layout.

[0355] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can be in the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories and optical memories, etc.) containing computer-usable program code.

[0356] The present application is described with reference to the schematic flow diagrams and / or block diagrams of the implementation processes of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the schematic flow diagrams and / or block diagrams can be implemented by computer program instructions, and the combination of the processes and / or blocks in the schematic flow diagrams and / or block diagrams can also be implemented. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one or more of the following processes or a combination of multiple processes and / or blocks Figure 1 one or more processes and / or blocks Figure 1 one or more blocks.

[0357] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including instruction means, and the instruction means implements the functions specified in one or more of the following processes or a combination of multiple processes and / or blocks Figure 1 one or more processes and / or blocks Figure 1 one or more blocks.

[0358] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes and / or blocks Figure 1 in one or more processes and / or blocks Figure 1 of the functions specified in one or more blocks or multiple blocks.

[0359] As mentioned above, the foregoing are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application.

Claims

1. A method for chip backend design, characterized in that, The backend design method of the chip is applied to a backend design tool, and the method includes: Importing library files and design data; wherein, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip; Aborting the backend design process without exiting the backend design process; when the PnR tool performs routing processing based on the library files and the design data, after executing the optimize timing command, execute a first write command to obtain a first report, a first netlist, and a first file; the first report includes the hold slack; the first file includes PIN foot information, length, height, coordinate positioning, and the area size of digital PR; Executing a first insertion command based on the first netlist and the first file to perform insertion processing on the gaps; executing a first extraction command to extract first parasitic parameters; the STA tool executes a first analysis command to perform static analysis processing on the first parasitic parameters to generate a second report; Determining a margin difference according to the hold slack in the first report and the hold slack in the second report; Performing correction processing on the information of the PnR tool according to the margin difference; Resuming the backend design process; based on the library files and the design data, the STA tool executes a second analysis command to obtain a timing report; If there is a timing violation in the timing report, execute a change command to perform engineering change ECO processing on other information of the PnR tool except the corrected information; The STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and outputs the layout.

2. The method according to claim 1, wherein Performing correction processing on the information of the PnR tool according to the margin difference, including: Backannotating the margin difference to the PnR tool to complete the correction processing.

3. The method according to claim 1, wherein Before importing the library files and design data, the method further includes: Executing a first start command to start the backend design process.

4. The method according to claim 3, characterized in that When the PnR tool performs routing processing based on the library files and the design data, after executing the optimize timing command, the method further includes: Executing a first stop command to abort the routing processing in the backend design process; Executing a second start command to start a correction process to correct the information of the PnR tool through the correction process to obtain corrected information.

5. The method according to claim 4, wherein After correcting the information of the PnR tool based on the first report and the second report to obtain corrected information, the method further includes: Executing a third start command to continue the backend design process to complete the backend design of the chip and output the layout.

6. A layout design method, characterized in that, The layout design method is applied to an EDA tool, and the method includes: Receiving a fourth start command to start the layout design process and parsing the library files and design data carried in the fourth start command; wherein, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip; Suspend the backend design process without exiting the backend design process; when calling a routing PnR tool to perform routing processing in the layout design process based on the library file and the design data, if the optimize timing command is executed, generate a second stop command and a second write command; In response to the second stop command, suspend the routing processing, and at the same time, in response to the second write command, obtain a third report, a second netlist, and a second file; the third report includes the hold slack of the hold time margin; the second file includes PIN foot information, length, height, coordinate positioning, and the area size of digital PR; Based on the second netlist and the second file, call the STA tool to perform static timing analysis processing and generate a fourth report; Receive a fifth start command, start the correction process, and determine the margin difference according to the hold slack in the third report and the hold slack in the fourth report; correct the information of the PnR tool according to the margin difference; Resume the backend design process; receive a sixth start command, based on the library file and the design data, call the STA tool to perform static timing analysis processing to obtain a timing report; if there is a timing violation in the timing report, execute a change command to perform ECO processing on other information of the PnR tool except the corrected information; continue to call the STA tool to perform static timing analysis processing until the obtained timing report has no timing violation, and output the layout.

7. A backend design tool, characterized in that, The backend design tool includes: an import unit, a first acquisition unit, a first generation unit, a first correction unit, a change unit, and a first output unit; The import unit is used to import a library file and design data; wherein, the design data includes a gate-level netlist and timing constraints obtained after the front-end design of the chip; The first acquisition unit is used to suspend the backend design process without exiting the backend design process. When the routing PnR tool performs routing processing based on the library file and the design data, after the optimize timing command is executed, execute a first write command to obtain a first report, a first netlist, and a first file; the first report includes the hold slack of the hold time margin; the first file includes PIN foot information, length, height, coordinate positioning, and the area size of digital PR; The first generation unit performs an insertion process on the gap based on the first netlist and the first file by executing a first insertion command; executes a first extraction command to extract first parasitic parameters; the STA tool executes a first analysis command to perform static analysis processing on the first parasitic parameters and generate a second report; The first correction unit is used to determine the margin difference according to the hold slack in the first report and the hold slack in the second report; correct the information of the PnR tool according to the margin difference; The first acquisition unit is further configured to resume the backend design process. Based on the library file and the design data, the STA tool executes a second analysis command to obtain a timing report; The change unit is configured to execute a change command to perform ECO processing on information other than the corrected information of the PnR tool if there are timing violations in the timing report; The first acquisition unit is further configured to cause the STA tool to continue executing the next analysis command until there are no timing violations in the obtained timing report; The first output unit is configured to output a layout.

8. A backend design tool, characterized in that, The backend design tool includes a first processor and a first memory storing instructions executable by the first processor. When the instructions are executed by the first processor, the method according to any one of claims 1-5 is implemented.

9. An EDA tool, characterized in that, The EDA tool includes: a receiving unit, a parsing unit, a calling unit, a second generating unit, an aborting unit, a second acquiring unit, a second correcting unit, a second output unit, The receiving unit is configured to receive a fourth start command to start a layout design process; The parsing unit is configured to parse the library file and design data carried in the fourth start command; wherein the design data includes a gate-level netlist and timing constraints obtained after front-end design of the chip; The calling unit is configured to abort the backend design process without exiting the backend design process, and based on the library file and the design data, call a routing PnR tool to perform routing processing in the layout design process; The second generating unit is configured to generate a second stop command and a second write command if the optimized timing command is executed; The aborting unit is configured to respond to the second stop command and abort the routing processing; The second acquiring unit is configured to respond to the second write command and acquire a third report, a second netlist, and a second file; the third report includes a hold slack; the second file includes PIN foot information, length, height, coordinate positioning, and the area size of digital PR; The calling unit is further configured to, based on the second netlist and the second file, call the STA tool to perform static timing analysis processing to generate a fourth report; The receiving unit is further configured to receive a fifth start command to start a correction process; The second correcting unit is configured to determine a margin difference according to the hold slack in the third report and the hold slack in the fourth report; and correct the information of the PnR tool according to the margin difference; The receiving unit is further configured to resume the backend design process and receive a sixth start command; The second output unit, based on the library file and the design data, calls the STA tool to perform static timing analysis processing to obtain a timing report; if there are timing violations in the timing report, execute a change command to perform ECO processing on information other than the corrected information of the PnR tool; continue to call the STA tool to perform static timing analysis processing until there are no timing violations in the obtained timing report, and output a layout.

10. An EDA tool, characterized in that, The EDA tool includes a second processor and a second memory storing instructions executable by the second processor. When the instructions are executed by the second processor, the method described in claim 6 is implemented.

11. A chip, characterized in that, The chip includes programmable logic circuits and / or program instructions. When the chip runs, the method described in any one of claims 1-6 is implemented.

12. A computer-readable storage medium, on which a program is stored and which is applied to a backend design tool and an EDA tool, characterized in that, When the program is executed by the first processor, the method described in any one of claims 1-5 is implemented. When the program is executed by the second processor, the method described in claim 6 is implemented.

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