Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first all-around gate transistor located above a first region of a substrate and a second all-around gate transistor located above a second region of the substrate. The first all-around gate transistor includes a plurality of first channel elements stacked along a first direction perpendicular to a top surface of the substrate and a first gate structure located above the plurality of first channel elements. The second all-around gate transistor includes a plurality of second channel elements stacked along a second direction parallel to the top surface of the substrate and a second gate structure located above the plurality of second channel elements. The plurality of first channel elements and the plurality of second channel elements include a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to semiconductor devices and methods of forming the same. Background Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the history of IC development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component (or circuit) produced during the manufacturing process) has shrunk. This process of device miniaturization provides the benefits of increased production efficiency and reduced associated costs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). Multi-gate devices generally represent devices having a gate structure or a portion of a gate structure disposed on more than one side of a channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular and are potential candidates for high-performance and low-leakage applications. FinFETs have an elevated channel surrounded by a gate on more than one side, for example, the gate surrounds the top and sidewalls of a "fin" of semiconductor material extending from a substrate. Compared to planar transistors, this configuration provides better control of the channel and significantly reduces short-channel effects (particularly, by reducing subthreshold leakage current (i.e., coupling between the source and drain of the FinFET in the off state)). A full-surround gate transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of the gate-surround transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. In some embodiments, the channel region includes a plurality of nanowires or nanosheets stacked vertically or arranged horizontally. When stacked vertically, the gate-surround transistor can be referred to as a vertical gate-surround (vertical GAA, VGAA) transistor. When arranged horizontally, the gate-surround transistor can be referred to as a horizontal gate-surround (horizontal GAA, HGAA) transistor. Summary of the invention

[0004] In some embodiments, a semiconductor device is provided, the semiconductor device comprising a first all-around gate transistor located above a first region of a substrate, the first all-around gate transistor comprising a plurality of first channel elements stacked along a first direction perpendicular to a top surface of the substrate; a first gate structure located above the plurality of first channel elements; and two first source / drain components sandwiching the plurality of first channel elements in between; and a second all-around gate transistor located above a second region of the substrate, the second all-around gate transistor comprising a plurality of second channel elements stacked along a second direction parallel to the top surface of the substrate; a second gate structure located above the plurality of second channel elements; and two second source / drain components sandwiching the plurality of second channel elements in between, wherein the plurality of first channel elements and the plurality of second channel elements comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane, and wherein the first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane.

[0005] In some other embodiments, a semiconductor device is provided, the semiconductor device comprising a first all-around gate transistor located above a first region of a substrate, the first all-around gate transistor comprising a plurality of first channel elements stacked along a first direction perpendicular to a top surface of the substrate; and an N-type source / drain component; and a second all-around gate transistor located above a second region of the substrate, the second all-around gate transistor comprising a plurality of second channel elements stacked along a second direction parallel to the top surface of the substrate; and a P-type source / drain component, wherein the plurality of first channel elements and the plurality of second channel elements comprise silicon having a first crystal plane and a second crystal plane different from the first crystal plane, wherein the first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane.

[0006] In some other embodiments, a method for forming a semiconductor device is provided, the method comprising providing a workpiece, the workpiece comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged alternately above a first region and a second region of a substrate; removing a portion of the first semiconductor layers and the second semiconductor layers arranged alternately above the second region of the workpiece; forming an epitaxial semiconductor layer in the second region; recessing the workpiece to form a first fin in the first region and a plurality of second fins in the second region; forming a first dummy gate stack above a first channel region of the first fin and a second dummy gate stack above a second channel region of the second fin; forming gate spacers on sidewalls of the first dummy gate stack and the second dummy gate stack; recessing the first fin and the second fin to leave a portion of the first fin below the first dummy gate stack and a portion of the second fin below the second dummy gate stack; forming a first source / drain component to sandwich this portion of the first fin in the middle and forming a second source / drain component to sandwich this portion of the second fin in the middle; removing the first dummy gate stack and the second dummy gate stack; and removing the first semiconductor layer in the first channel region of the first fin and the epitaxial semiconductor layer in the second channel region of the second fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the present disclosure may be better understood with reference to the following detailed description and accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the drawings are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0008] Figure 1 The figure is a flow chart of a method for manufacturing a gate-all-around transistor according to various aspects of the embodiments of the present disclosure.

[0009] Figure 2-Figure 11 , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A and Fig. 16B According to various aspects of the embodiments of the present disclosure, for example, Figure 1 Schematic diagrams of perspective and cross-sectional views of a full-wrap-around gate transistor on a workpiece during various manufacturing stages associated with the method.

[0010] Fig.17 FIG. 1 is a schematic cross-sectional diagram of a channel region of a first type of all-around gate transistor according to various aspects of the embodiments of the present disclosure.

[0011] Fig.18FIG. 1 is a schematic cross-sectional diagram of a channel region of a second type of all-around gate transistor according to various aspects of the embodiments of the present disclosure.

[0012] Fig.19 Schematic lateral side view of a third type of all-around gate transistor.

[0013] Fig. 20 FIG. 4 is a schematic cross-sectional diagram of a third type of all-around gate transistor. FIG.

[0014] The reference numerals are described as follows:

[0015] 10: Methods

[0016] 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34: Blocks

[0017] 100: Artifacts

[0018] 102: Base

[0019] 104: First semiconductor layer

[0020] 104B: Bottom first semiconductor layer

[0021] 106: Second semiconductor layer

[0022] 108: First hard mask layer

[0023] 110: Second hard mask layer

[0024] 112: Epitaxial semiconductor layer

[0025] 114: Third hard mask layer

[0026] 116: Fourth hard mask layer

[0027] 118: Isolation components

[0028] 120A: First dummy gate stack

[0029] 120B: Second dummy gate stack

[0030] 122A, 122B: dummy gate dielectric layer

[0031] 124A, 124B: dummy gate electrode layer

[0032] 126: Fifth hard mask layer

[0033] 127: Sixth hard mask layer

[0034] 128: Gate spacer

[0035] 130A: First inner spacer

[0036] 130B: Second inner spacer

[0037] 132: Contact Etch Stop Layer

[0038] 134: Dielectric layer

[0039] 136: Interface layer

[0040] 138: High dielectric constant dielectric

[0041] 140A: First source / drain component

[0042] 140B: Second source / drain component

[0043] 140C: Third source / drain component

[0044] 150A: First gate stack

[0045] 150B: Second gate stack

[0046] 150C: Third gate stack

[0047] 160: Source / drain contacts

[0048] 170A: First channel element

[0049] 170B: Second channel element

[0050] 170C: Third channel element

[0051] 1000: District 1

[0052] 1002A: First channel area

[0053] 1002B: Second channel area

[0054] 1004A: First source / drain region

[0055] 1004B: Second source / drain region

[0056] 1100: First Fin

[0057] 1110: N-type all-around gate transistor

[0058] 1200: Second fin

[0059] 2000: District 2

[0060] 2220: P-type all-around gate transistor

[0061] 3000: District 3

[0062] 3330: Long-channel all-around gate transistor

[0063] (100), (110): crystal planes

[0064] H1, H2, H3: Height

[0065] L: Channel length

[0066] N1, N2, N3: quantity

[0067] P1, P2, P3: Spacing

[0068] S1, S2, S3: Interval

[0069] W1, W2, W3: Width DETAILED DESCRIPTION

[0070] Embodiments of the present disclosure relate to integrated circuit devices, and more particularly to gate-all-around (GAA) transistors.

[0071] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the subject provided. Specific examples of various components and their arrangement are described below to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first component on or above a second component, which means that it includes an embodiment in which the formed first component and the second component are in direct contact, and also includes an embodiment in which an additional component can be formed between the first component and the second component, so that the first component and the second component may not be in direct contact.

[0072] In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between each embodiment and / or the appearance structure. Furthermore, in the following disclosure, a component is formed on another component, connected to another component and / or coupled to another component, which may include embodiments in which these components are directly in contact, and may also include embodiments in which other components are formed between these components, so that these components are not in direct contact. In addition, in order to facilitate the description of the relationship between a component and another component, space-related terms can be used, such as "lower", "upper", "upper", "horizontal", "vertical", "above", "above", "below", "below", "up", "down", "top", "bottom", etc. and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.). Space-related terms also cover different directions of the device including components.

[0073] Disclosed herein are methods of forming a full-surround gate transistor and related full-surround gate transistors. In some embodiments, the full-surround gate transistor disclosed herein may include an N-type full-surround gate transistor adjacent to a P-type full-surround gate transistor. These configurations may be implemented in various devices, such as inverters, inverted AND logic gates, inverted OR logic gates, and oscillators. The disclosed embodiments contemplate other integrated circuit devices in the art that can benefit from the full-surround gate transistor formation method and / or full-surround gate transistor described herein that can be understood by a person of ordinary skill in the art.

[0074] Figure 1 Flow chart of method 10 for manufacturing a full-surround gate transistor. Method 10 is related to Figure 2-Figure 11 , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A and Fig. 16B The schematic perspective view and cross-sectional schematic view shown together describe. Additional steps may be provided before, during, and after the method 10, and some of the steps described may be moved, replaced, or eliminated for other embodiments of the method 10.

[0075] Please refer to Figure 1 and Figure 2. The method 10 of the disclosed embodiment begins at block 12, wherein a workpiece 100 is provided. The workpiece 100 includes a first semiconductor layer 104 and a second semiconductor layer 106 arranged alternately above a first region 1000 and a second region 2000 of a substrate 102. In some embodiments, the substrate 102 may be a semiconductor substrate including, for example, silicon. Alternatively or additionally, the substrate 102 includes other elemental semiconductors (e.g., germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Alternatively, the substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate on the insulating layer may be manufactured by using separation by implantation of oxygen (SIMOX), wafer bonding and / or other suitable methods. In one embodiment, the substrate 102 is composed of silicon or a silicon top surface, and the silicon substrate or the silicon top surface has a (100) crystal plane, and the normal direction of the (100) crystal plane is parallel to the Z direction. As will be described below, when the channel is formed in the first region 1000 and the second region 2000, the channel has a channel length along the crystal direction

[110] parallel to the Y direction.

[0076] In some embodiments, each first semiconductor layer 104 includes silicon and germanium. In some examples, each first semiconductor layer 104 consists of approximately silicon and germanium. In these embodiments, each second semiconductor layer 106 includes silicon. In some examples, each second semiconductor layer 106 consists of approximately silicon. In some embodiments, the first semiconductor layer 104 and the second semiconductor layer 106 can be formed or deposited using an epitaxial process. The epitaxial process can include vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), other suitable epitaxial processes, or combinations thereof. In some embodiments, 2-20 first semiconductor layers 104 and 2-20 second semiconductor layers 106 can be formed in block 12. In one embodiment, the staggered arrangement of the first semiconductor layers 104 and the second semiconductor layers 106 begins with one of the first semiconductor layers 104 being disposed on the substrate 102. In some examples, since the first semiconductor layer 104 and the second semiconductor layer 106 are alternately arranged on the substrate 102 , the first semiconductor layer 104 and the second semiconductor layer 106 share the same crystal plane ( 100 ) parallel to the Z direction.

[0077] In some embodiments, the workpiece 100 may include one or more hard mask layers deposited on the staggered first semiconductor layer 104 and the second semiconductor layer 106, and these hard mask layers are used for the operation of block 14. In some embodiments, as Figure 2 As shown, the workpiece 100 includes a first hard mask layer 108 and a second hard mask layer 110. In some embodiments, the first hard mask layer 108 includes silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride, and the second hard mask layer 110 may include silicon oxide.

[0078] Please refer to Figure 1 and Figure 3 . The method 10 proceeds to block 14, wherein a portion of the staggered first semiconductor layer 104 and the second semiconductor layer 106 in the second region 2000 of the workpiece 100 is removed. In some embodiments, this removal can be performed using a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination of the foregoing. For example, a photoresist layer can be deposited over the second hard mask layer 110 to pattern the underlying first hard mask layer 108 and the second hard mask layer 110, and the patterned first hard mask layer 108 and the second hard mask layer 110 are used as a mask for selectively removing the staggered first semiconductor layer 104 and the second semiconductor layer 106 in the second region 2000. In some embodiments, this removal is performed using a dry etching process, which is anisotropic (directional) and easily controlled by etching time. In Figure 3 In one embodiment, the removal is timed so that the bottom first semiconductor layer 104B remains on the substrate 102 in the second region 2000. In another embodiment, all of the staggered first semiconductor layers 104 and second semiconductor layers 106 in the second region 2000 are removed, and the bottom first semiconductor layer 104B is redeposited on the substrate 102 in the second region 2000. Therefore, for the purpose of the embodiments of the present disclosure, the bottom first semiconductor layer 104B may be the bottom first semiconductor layer 104B that remains on the substrate 102, or the bottom first semiconductor layer 104B that is redeposited after the staggered first semiconductor layers 104 and second semiconductor layers 106 in the second region 2000 are removed.

[0079] Please refer to Figure 1 and Figure 4 The method 10 proceeds to block 16, where an epitaxial semiconductor layer 112 is formed in the second region 2000. In some embodiments, the epitaxial semiconductor layer 112 may be deposited by vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), other suitable epitaxial processes, or combinations thereof. In some embodiments, after depositing the epitaxial semiconductor layer 112, a planarization process (e.g., grinding or chemical mechanical polishing (CMP)) may be performed to provide a planar top surface of the workpiece 100. In some embodiments, the epitaxial semiconductor layer 112 may include silicon. In some examples, the epitaxial semiconductor layer 112 may consist essentially of silicon.

[0080] Please refer to Figure 1 , Figure 5 and Figure 6 . The method 10 proceeds to block 18, where the workpiece 100 is recessed to form a first fin 1100 in the first region 1000 and a plurality of second fins 1200 in the second region 2000, and trenches are formed between the fins. The plurality of second fins 1200 may include 2-50 second fins. In some embodiments, at block 18, a third hard mask layer 114 and a fourth hard mask layer 116 are formed on the planarized top surface of the workpiece 100, the workpiece including the staggered first semiconductor layers 104 and second semiconductor layers 106 in the first region 1000 and the epitaxial semiconductor layer 112 in the second region 2000. In some embodiments, the third hard mask layer 114 includes silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride, and the fourth hard mask layer 116 may include silicon oxide. Next, a photoresist is deposited over the fourth hard mask layer 116. Next, the photoresist layer, the third hard mask layer 114, and the fourth hard mask layer 116 are patterned to serve as patterned masks for recessing the workpiece 100. In some embodiments, the workpiece 100 is recessed to form a first fin 1100 in the first region 1000 and two second fins 1200 in the second region 2000. Figure 6 In some representative embodiments, at block 18 , not only the staggered first semiconductor layer 104 and second semiconductor layer 106 and the epitaxial semiconductor layer 112 are recessed, but also the substrate 102 under the staggered semiconductor layers in the first zone 1000 and the substrate 102 under the bottom first semiconductor layer 104B in the second zone 2000 are recessed.

[0081] Please refer to Figure 1 and Figure 7 The method 10 proceeds to block 20 where an isolation feature 118 is formed. In some embodiments, at block 18, the trench is filled with an insulating material to form the isolation feature. The isolation feature 118 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or a combination thereof. Figure 7 The isolation features 118 shown may be referred to as shallow trench isolation (STI) features. In some embodiments, the isolation features 118 are formed by filling the trenches with an insulating material (e.g., using a chemical vapor deposition process or a spin-on-glass process) (formed at block 18). In some embodiments, the isolation material filled in the trenches may be etched back using a suitable etchant and etching process.

[0082] Please refer to Figure 1 and Figure 8 The method 10 proceeds to block 22 where a first dummy gate stack 120A is deposited over the first channel region 1002A of the first fin 1100 and a second dummy gate stack 120B is deposited over the second channel region 1002B of the plurality of second fins 1200. The first dummy gate stack 120A and the second dummy gate stack 120B may include a multi-layer structure. Figure 8In the illustrated embodiment, the first dummy gate stack 120A includes a dummy gate dielectric layer 122A and a dummy gate electrode layer 124A, and the second dummy gate stack 120B includes a dummy gate dielectric layer 122B and a dummy gate electrode layer 124B. A fifth hard mask layer 126 and a sixth hard mask layer 127 may be deposited over the first dummy gate stack 120A and the second dummy gate stack 120B for protection and subsequent patterning. In some embodiments, the dummy gate dielectric layers 122A and 122B may include silicon oxide or other suitable dielectric materials. The dummy gate electrode layers 124A and 124B may include polysilicon. In some embodiments, the fifth hard mask layer 126 includes silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride, and the sixth hard mask layer 127 may include silicon oxide. The first dummy gate stack 120A and the second dummy gate stack 120B may be formed by a deposition process, a lithography process, an etching process, other suitable processes or a combination thereof. For example, one or more deposition processes may be performed to form a dummy gate dielectric layer over the first channel region 1002A and the second channel region 1002B corresponding to the first fin 1100 and the plurality of second fins 1200. Next, a deposition process is performed to form first and second dummy gate electrode layers over the first and second dummy gate dielectric layers. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods or combinations thereof. Then, a lithography patterning and etching process is performed to pattern the dummy gate dielectric layer and the dummy gate electrode layer to form the first dummy gate stack 120A and the second dummy gate stack 120B. The lithography patterning process includes photoresist coating (eg, spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (eg, hard baking), other suitable processes, or a combination of the foregoing.Alternatively, the lithography exposure process may be supplemented, performed or replaced by other methods, such as maskless lithography, electron beam writing or ion beam writing. Alternatively, the lithography patterning process uses nanoimprint technology. The etching process includes a dry etching process, a wet etching process, other etching methods or a combination of the foregoing.

[0083] Please refer to Figure 1 and Fig. 9 . The method 10 proceeds to block 24, where a gate spacer 128 is formed on the sidewalls of the first dummy gate stack 120A and the second dummy gate stack 120B. The gate spacer 128 is formed by a suitable process, and the gate spacer 128 includes a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or a combination of the foregoing (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer including silicon or nitrogen (e.g., a silicon nitride layer) may be deposited over the workpiece 100, and the dielectric layer is subsequently anisotropically etched to form the gate spacer 128. In some embodiments, the gate spacer 128 includes a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers (e.g., sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers) are formed adjacent to the first dummy gate stack 120A and the second dummy gate stack 120B. In these embodiments, each set of spacers may include materials with different etching rates. For example, a first dielectric layer (e.g., silicon oxide) including silicon and oxygen may be deposited on the workpiece 100, and the first dielectric layer may be subsequently anisotropically etched to form a first set of spacers adjacent to the gate stack, and a second dielectric layer (e.g., silicon nitride) including silicon and nitrogen may be deposited on the workpiece 100, and the second dielectric layer may be subsequently anisotropically etched to form a second set of spacers adjacent to the first set of spacers.

[0084] Please refer to Figure 1 and Fig. 9. Method 10 proceeds to block 26, where the gate spacer 128 is used as an etching mask to remove the portions of the first fin and the second fin in the corresponding source / drain regions. In some embodiments, since the type of the transistor is not determined by the doping type of the first channel region 1002A and the second channel region 1002B, but by the doping type of the source / drain region, the first fin 1100 and the plurality of second fins 1200 are largely or completely removed outside the first channel region 1002A and the second channel region 1002B, so that the source / drain components with dopants can be re-epitaxially grown in subsequent steps. The selective removal of the first fin 1100 and the plurality of second fins 1200 can be achieved by using the gate spacer 128 as an etching mask. The etching process that can be used for block 26 includes a dry etching process, a wet etching process, other etching methods, or a combination of the foregoing.

[0085] Please refer to Figure 1 and Fig.10 The method 10 proceeds to block 28 , where a first inner spacer 130A is formed at both ends of each first semiconductor layer 104 in the first region 1000 , and a second inner spacer 130B is formed at both ends of the bottom first semiconductor layer 104B in the second region 2000 . Fig.10 In the illustrated embodiment, since the second inner spacer 130B is formed only at both ends of the bottom first semiconductor layer 104B, the top of the second inner spacer 130B in the second region 2000 is lower than the top of the first inner spacer 130A in the first region 1000. In some embodiments, the first inner spacer 130A and the second inner spacer 130B can be formed in a self-aligned manner. For example, when the first semiconductor layer 104 is formed of silicon germanium (SiGe), the first semiconductor layer 104 (or the bottom first semiconductor layer 104B of the second region 2000) can be exposed to water and a low oxidation temperature (lower than the temperature required to oxidize silicon) to form SiGe oxide. The inner spacer can prevent the source / drain components from being etched in the gate replacement process of block 32. Alternatively, the inner spacer can be formed of a low dielectric constant dielectric to reduce parasitic capacitance.

[0086] Please refer to Figure 1 and Fig.11The method 10 proceeds to block 30, where a first source / drain feature 140A is formed in the first region 1000, and a second source / drain feature 140B is formed in the second region 2000. In some embodiments, after substantially removing a portion of the first fin 1100 in the first source / drain region 1004A, an N-type doped semiconductor material is epitaxially grown in the first source / drain region 1004A of the first region 1000 to form the first source / drain feature 140A. Similarly, after substantially removing a portion of the plurality of second fins 1200 in the second source / drain region 1004B, a P-type doped semiconductor material is epitaxially grown in the second source / drain region 1004B of the second region 2000 to form the second source / drain feature 140B. In other embodiments, the fin structure in the first source / drain region 1004A and the second source / drain region 1004B is not completely removed, and N-type doped and P-type doped semiconductor materials are epitaxially grown above the fin structure to surround the fin structure. The epitaxial process may use chemical vapor deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (ultra-high vacuum CVD, UHV-CVD), low pressure chemical vapor deposition and / or plasma assisted chemical vapor deposition), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or a combination of the foregoing. The epitaxial process may use gaseous and / or liquid precursors that react with the composition of the fin structure (e.g., the first fin 1100 and the plurality of second fins 1200). In some embodiments, the N-type doped semiconductor material may be epitaxially grown silicon in-situ doped or implanted with one or more N-type dopants (e.g., phosphorus, arsenic, other N-type dopants, or a combination thereof), and the P-type doped semiconductor material may be epitaxially grown silicon germanium in-situ doped or implanted with one or more P-type dopants (e.g., boron, gallium, other P-type dopants, or a combination thereof). In one embodiment, the N-type doped semiconductor material is silicon in-situ doped with phosphorus, and the P-type doped semiconductor material is silicon germanium in-situ doped with boron.

[0087] The following description of the embodiments of the present disclosure will refer to Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A and Fig. 16B . Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16BEach of the drawings shows a cross section AA' and BB' along the X direction. In some of these drawings, the cross sections AA' and BB' may not be clearly shown for the sake of brevity.

[0088] Please refer to Fig. 12A and Fig. 12B Although not shown in Figure 1 In the individual blocks of method 10 of the present invention, a dielectric layer 134 is formed over the first source / drain feature 140A and the second source / drain feature 140B. In some embodiments, the dielectric layer 134 may be referred to as an interlevel dielectric / interlayer dielectric (ILD) layer. In some embodiments, the dielectric layer 134 is part of a multilayer interconnect (MLI) feature that electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components of devices to be formed on the workpiece 100 (e.g., gate structures and / or source / drain features) so that the various devices and / or components can operate in a manner specified by the design requirements of the devices on the workpiece 100. The dielectric layer 134 includes a dielectric material, and the dielectric material includes, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed by tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant dielectric material, other suitable dielectric materials, or a combination thereof. Exemplary low dielectric constant dielectric materials include fluorinated silica glass (FSG), carbon-doped silicon oxide, (Applied Materials, Inc., Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the dielectric layer 134 may have a multi-layer structure having multiple layers of dielectric materials. In some embodiments, a contact etch stop layer (CESL) 132 is disposed between the dielectric layer 134 and the fin structure (the first fin 1100 and the plurality of second fins 1200) and / or the first source / drain component 140A and the second source / drain component 140B. The contact etch stop layer 132 includes a material different from the dielectric layer 134, for example, the contact etch stop layer 132 is a dielectric material different from the dielectric layer 134. In the illustrated embodiment, the dielectric layer 134 includes a low-k dielectric material and the contact etch stop layer 132 includes silicon and nitrogen (e.g., silicon nitride or silicon oxynitride). The dielectric layer 134 and the contact etch stop layer 132 may be formed on the workpiece 100, for example, by a deposition process (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition), plating, other suitable methods, or a combination of the foregoing. In some embodiments, the dielectric layer 134 and the contact etch stop layer 132 may be formed by a flowable chemical vapor deposition (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) on the workpiece 100 and converting the flowable material into a solid material by a suitable technique (e.g., thermal annealing and / or ultraviolet radiation treatment). After the dielectric layer 134 and / or the contact etch stop layer 132 are deposited, a chemical mechanical polishing process and / or other planarization process is performed to reach (expose) the top of the dummy gate electrode layers 124A and 124B. In the illustrated embodiment, the top surfaces of the dummy gate electrode layers 124A and 124B are substantially flush with the top surface of the dielectric layer 134.

[0089] Please refer to Figure 1 , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A and Fig. 15B, the method 10 proceeds to block 32, wherein a gate replacement process is performed to replace the first dummy gate stack 120A and the second dummy gate stack 120B with the first gate stack 150A and the second gate stack 150B, respectively. In some embodiments, as Fig.13A and Fig. 13B As shown, the first dummy gate stack 120A and the second dummy gate stack 120B are first removed by selective etching to expose the first channel region 1002A and the second channel region 1002B. Fig.14A and Fig. 14B As shown, the first semiconductor layer 104 and the bottom first semiconductor layer 104B are removed by a dry etching process, a wet etching process, other suitable etching processes or a combination of the foregoing. After removing the first semiconductor layer 104 and the bottom first semiconductor layer 104B, the remaining second semiconductor layer 106 and the epitaxial semiconductor layer 112 in the plurality of second fins 1200 remain in place in a substantially unetched state to serve as a channel (or channel element) of the all-around gate transistor in the first region 1000 and the second region 2000. Next, an interface layer 136 is formed over the first channel region 1002A and the second channel region 1002B. A high dielectric constant dielectric 138 is formed over the interface layer 136. The interface layer 136 can enhance the bonding of the high dielectric constant dielectric 138 to the second semiconductor layer 106 and the epitaxial semiconductor layer 112. In some embodiments, the interfacial layer 136 may include silicon oxide, and the high-k dielectric 138 may include a high-k dielectric material (and therefore may be referred to as a high-k dielectric layer), such as hafnium dioxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials are generally referred to as dielectric materials having a high dielectric constant, such as a dielectric constant greater than that of silicon oxide (k≈3.9). The high-k dielectric 138 may be formed, for example, by using an atomic layer deposition process to conformally deposit a gate dielectric material over the first channel region 1002A and the second channel region 1002B such that the high-k dielectric 138 has a substantially uniform thickness. Alternatively, the high-k dielectric 138 is formed by using other suitable deposition processes, such as chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or a combination of the foregoing. In some examples, the interface layer 136 and the high-k dielectric 138 may be collectively referred to as a gate dielectric layer.

[0090] After forming the gate dielectric layer, a first gate stack 150A is formed in the first region 1000, and a second gate stack 150B is formed in the second region 2000. The first gate stack 150A and the second gate stack 150B may be deposited in the first channel region 1002A and the second channel region 1002B to surround the gate dielectric layer and the channel (or channel element) therein, respectively. The first gate stack 150A and the second gate stack 150B may include multiple layers, such as a capping layer, one or more work function layers, and a metal filling layer. The capping layer may be deposited using, for example, an atomic layer deposition process. In some embodiments, the capping layer may have a total thickness of about 1000 Å. to about And may include materials to prevent or eliminate diffusion and / or reaction between the gate dielectric layer and components of other layers of the first gate stack 150A and the second gate stack 150B (particularly gate layers including metals). In some embodiments, the capping layer includes metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or a combination of the foregoing. For example, in the embodiment shown, the capping layer includes titanium and nitrogen (e.g., TiN). Alternatively, the capping layer can be formed by using other suitable deposition processes, such as chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or a combination of the foregoing. In some embodiments, one or more N-type work function layers may be formed over the capping layer in the first region 1000, and one or more P-type work function layers may be formed over the capping layer in the second region 2000. In some embodiments, the thickness of the work function layer may be increased or decreased to adjust different threshold voltages of the design.

[0091] One or more P-type work function layers may include any suitable p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or combinations thereof. In the illustrated embodiment, one or more P-type work function layers include titanium and nitrogen, such as TiN. The one or more P-type work function layers may be formed using a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or combinations thereof. In one embodiment, the one or more P-type work function layers may be formed using atomic layer deposition so that the formed one or more P-type work function layers are compliant.

[0092] In some embodiments, one or more N-type work function layers may include any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. In the illustrated embodiment, one or more N-type work function layers include titanium and aluminum, such as TaAlC, TaAl, TiAlC, TiAl, TaSiAl, TiSiAl, TaAlN, or TiAlN. In some embodiments, the one or more N-type work function layers may be formed using a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or combinations thereof. In one embodiment, the one or more N-type work function layers may be formed using atomic layer deposition, such that the formed one or more N-type work function layers are compliant.

[0093] A metal filling (or bulk) layer may be formed above the N-type / P-type work function layer. The metal filling layer may include a suitable conductive material, such as Al, W and / or Cu. In one embodiment, the metal filling layer includes W. In some other embodiments, the metal filling layer may additionally or jointly include other metals, metal oxides, metal nitrides, other suitable materials, or a combination of the foregoing. The metal filling layer may be formed by using a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or a combination of the foregoing. In one embodiment, the metal filling layer may be formed by using atomic layer deposition so that the formed metal filling layer is compliant.

[0094] In some embodiments, an adhesion layer may be formed between the P-type / N-type work function layer and the metal fill layer. In these embodiments, the adhesion layer includes a material that promotes adhesion between adjacent layers (e.g., the N-type / P-type work function layer and subsequently formed layers of the first gate stack 150A and the second gate stack 150B). In some examples, the adhesion layer may include a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), a metal oxide, a metal nitride, or combinations thereof. In one embodiment, the adhesion layer includes titanium and nitrogen, such as TiN. The adhesion layer may be formed using a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, plating, other deposition processes, or combinations thereof. In one embodiment, atomic layer deposition may be used to conformally deposit an adhesion layer on the N-type / P-type work function layer.

[0095] In some other embodiments, before forming the metal filling layer, a barrier layer may be selectively formed so that the metal filling layer is disposed on the barrier layer. The barrier layer includes a material that blocks and / or reduces diffusion between gate stack layers (eg, the metal filling layer and the N-type / P-type work function layer).

[0096] After depositing the first gate stack 150A and the second gate stack 150B, a planarization process may be performed to remove excess gate stack material from the top surface of the workpiece 100. For example, a chemical mechanical polishing process may be performed until the top surface of the dielectric layer 134 is reached (exposed). Fig.16A and Fig. 16BIn a representative embodiment, after the CMP process, the top surfaces of the first gate stack 150A and the second gate stack 150B are substantially coplanar with the top surface of the dielectric layer 134 .

[0097] Please refer to Figure 1 , Fig.16A and Fig. 16B , method 10 proceeds to block 34, where further processing is performed in the first region 1000 and the second region 2000 to complete the fabrication of the N-type all-around gate transistor 1110 and the P-type all-around gate transistor 2220. For example, various contacts (e.g., source / drain contacts and gate contacts) may be formed to facilitate operation of the all-around gate transistors. In some embodiments, one or more interlayer dielectric layers (similar to dielectric layer 134) may be formed above the workpiece 100 (in particular, formed above dielectric layer 134 and the first gate stack 150A and the second gate stack 150B). Next, contacts may be formed in the dielectric layer 134 and / or disposed in an interlayer dielectric layer above the dielectric layer 134. Fig.16A and Fig. 16B In the embodiment shown in the figure, the source / drain contact 160 is electrically coupled to the source / drain components 140A and 140B, respectively. The contacts (e.g., the source / drain contact 160 and the gate contact) include a conductive material, such as a metal. The metal includes aluminum, an aluminum alloy (e.g., an aluminum / silver / copper alloy), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or a combination of the foregoing. In some embodiments, a metal silicide layer may be formed above the source / drain components 140A and 140B to reduce the contact resistance between the source / drain components 140A and 140B and the source / drain contact 160. The metal silicide layer may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or a combination of the foregoing. In some embodiments, the interlayer dielectric layer and the contacts (summing point) disposed above the dielectric layer 134 are part of the above-mentioned multi-layer interconnection components disposed above the substrate 102. The multi-layer interconnection components may include a combination of metal layers and interlayer dielectric layers, which are configured to form vertical interconnection components (such as contacts and / or vias) and / or horizontal interconnection components (such as wires). The various conductive components include materials similar to the contacts. In some embodiments, a damascene process and / or a dual damascene process is used to form the multi-layer interconnection components. In addition, as Fig. 16B As shown, the channel elements in the first gate stack 150A are at least partially staggered with the first inner spacers 130A, while the channel elements in the second gate stack 150B are spaced apart from the substrate 102 by the second inner spacers 130B.

[0098] At this time, the N-type all-around gate transistor 1110 including the first gate stack 150A is disposed in the first region 1000 , and the P-type all-around gate transistor 2220 including the second gate stack 150B is disposed in the second region 2000 . Fig.17 and Fig.18 Display the edges Fig.16A A schematic cross-sectional view of the first channel region 1002A and the second channel region 1002B in the X direction. Fig.17 In some embodiments, the N-type all-around gate transistor 1110 includes a number N1 of first channel elements 170A in the first channel region 1002A. The number N1 of the first channel elements 170A corresponds to the number of second semiconductor layers 106 in the staggered arrangement of the first semiconductor layers 104 and the second semiconductor layers 106. In some embodiments, the number N1 is between 2 and 20. Each first channel element 170A includes a height H1 and a width W1. In some embodiments, because the width W1 is greater than the height H1, the first channel element 170A is in a sheet-like shape, and the N-type all-around gate transistor 1110 can be referred to as a nanosheet transistor. Furthermore, because the first channel elements 170A are stacked vertically (along the Z direction), the N-type all-around gate transistor 1110 can also be referred to as a vertical nanosheet transistor or a vertically stacked nanosheet transistor. In some embodiments, the height H1 is between about 2 nm and about 15 nm, and the width W1 is between about 5 nm and about 50 nm. The first channel elements 170A are arranged at a first pitch P1, and the first pitch P1 is between about 8 nm and about 25 nm. The first channel element 170A adjacent to the top surface of the fin base or isolation member 118 is separated from the top surface of the fin base or isolation member 118 by a first spacing S1. In some examples, the first spacing S1 is between about 3 nm and about 20 nm. In some embodiments, the surface plane defined by the width W1 and the channel length is a (100) crystal plane and represents the main channel surface of the first channel element 170A.

[0099] Please refer to Fig.18In some embodiments, the P-type all-around gate transistor 2220 includes a number N2 of second channel elements 170B in the second channel region 1002B. The number N2 of the second channel elements 170B corresponds to the number of second fins of the plurality of second fins 1200. In some embodiments, the number N2 is between 2 and 50. Each second channel element 170B includes a height H2 and a width W2. In some embodiments, because the height H2 is greater than the width W2, the second channel element 170B is in a sheet-like shape, and the P-type all-around gate transistor 2220 can be referred to as a nanosheet transistor. Furthermore, because the second channel elements 170B are arranged or disposed horizontally (along the Y direction), the P-type all-around gate transistor 2220 can also be referred to as a horizontal nanosheet transistor. In some embodiments, the height H2 is between about 20 nm and about 100 nm, and the width W2 is between about 2 nm and about 15 nm. The second channel elements 170B are disposed at a second pitch P2, and the second pitch P2 is between about 8 nm and about 50 nm. The second channel element 170B adjacent to the top surface of the fin base or isolation member 118 is spaced apart from the top surface of the fin base or isolation member 118 by a second spacing S2. In some examples, the second spacing S2 is between about 3 nm and about 20 nm. In some embodiments, the plane defined by the height H2 and the channel length is a (110) crystal plane and represents a major channel surface of the second channel element 170B.

[0100] In some embodiments, the total channel width of the N-type all-around gate transistor 1110 can be roughly and mathematically represented by twice the product of the number N1 and the width W1 ((N1xW1)x2)), and the total channel width of the P-type all-around gate transistor 2220 can be roughly and mathematically represented by twice the product of the number N2 and the height H2 ((N2xH2)x2)). These mathematical formulas include two factors because each channel element has two long (or major) sides. In some examples, twice the product of the number N1 and the width W1 ((N1xW1)x2)) is roughly equal to twice the product of the number N2 and the height H2 ((N2xH2)x2)). In some embodiments, because the N-type all-around gate transistor 1110 and the P-type all-around gate transistor 2220 have the same channel length, the first occupied area of ​​the first channel element 170A on the substrate 102 is represented by the product of the width W1 and the channel length, and the second occupied area of ​​the second channel element 170B on the substrate 102 is represented by the product of (W2+(N2-1)x P2) and the channel length. With respect to the respective channel elements, each first channel element 170A shares the same channel length (i.e., the dimension in the channel length direction) with each second channel element 170B. In some examples, the first occupied area is equal to the second occupied area. In some embodiments, because the height H2 is greater than the width W1, the number N1 is greater than the number N2.

[0101] Please refer to Fig.19 and Fig. 20 In some embodiments, in addition to the first region 1000 and the second region 2000, the workpiece 100 may include a third region 3000, as shown in FIG. Fig.19 In some embodiments, the third region 3000 is an area where long channel all-around gate (GAA) transistors 3330 are used for analog or input / output (I / O) applications. The channel length L of these long channel all-around gate transistors 3330 is about 3 to about 10 times the channel length of the N-type all-around gate transistor 1110 or the P-type all-around gate transistor 2220, and the N-type all-around gate transistor 1110 and the P-type all-around gate transistor 2220 may have approximately the same channel length. Therefore, Fig.19 Schematic diagram of the cross-section of the long channel all-around gate transistor 3330 along the channel length L. Fig. 20 FIG. 4 is a cross-sectional view of the third gate stack 150C above the third channel region 1002C of the long channel all-around gate transistor 3330. Fig. 20 As shown, because the horizontal nanosheet all-around gate transistor (e.g. Fig.18 The channel element height H3 of the horizontal nanosheet (e.g., the long channel all-around gate transistor 3330) is greater than the channel element width W3, so the horizontal nanosheet all-around gate transistor is subject to less vertical (along the Z direction) deflection than the vertical nanosheet all-around gate transistor, where the deflection of the channel element can cause transistor failure. Therefore, the horizontal nanosheet all-around gate transistor is suitable for forming a long channel all-around gate transistor, such as the long channel all-around gate transistor 3330. Therefore, in some embodiments, the third region 3000 may undergo blocks 14 and 16 of method 10 and may include an alternating arrangement of epitaxial semiconductor layers (similar to epitaxial semiconductor layer 112) rather than first semiconductor layers 104 and second semiconductor layers 106. In Fig.19 In the illustrated embodiment, the third pass element 170C of the long channel all-around gate transistor 3330 has Fig. 20 Schematic cross-section diagram is shown. In some embodiments, the long channel all-around gate transistor 3330 is an N-type all-around gate transistor and includes a third source / drain component 140C, which is also N-type. In some examples, the third source / drain component 140C can be epitaxially formed silicon in-situ doped or implanted with N-type dopants, such as phosphorus or arsenic. In some embodiments, Fig. 20The third channel element 170C in the embodiment has a main channel face on the crystal plane (110). Although the electron mobility on the crystal plane (110) is less than the electron mobility on the crystal plane (100), it is sufficient for analog or input / output applications. The third channel element 170C has a width W3, a height H3, and a spacing P3. In some examples, the width W3, the height H3, and the spacing P3 are substantially equal to the width W2, the height H2, and the spacing P2. In some embodiments, the number N3 of the third channel elements 170C can be substantially similar to the number N2.

[0102] The disclosed embodiments provide many advantages. The electron mobility on the crystal plane (100) is greater than the electron mobility on the crystal plane (110), and the hole mobility on the crystal plane (110) is greater than the hole mobility on the crystal plane (100). By having a primary channel face on the crystal plane (100), the first channel unit 170A has an increased carrier (electron of the N-type transistor) mobility of the N-type all-around gate transistor 1110 in the first region 1000. Similarly, by having a primary channel face on the crystal plane (110), the second channel unit 170B has an increased carrier (proton of the P-type transistor) mobility of the P-type all-around gate transistor 2220 in the second region 2000. In addition, the N-type all-around gate transistor 1110 and the P-type all-around gate transistor 2220 can include approximately the same footprint, and the total channel surface area of ​​the N-type all-around gate transistor 1110 is approximately equal to the total channel surface area of ​​the P-type all-around gate transistor 2220. Substantially similar footprints and channel surface areas facilitate the scaling and design of devices including N-type all-around gate transistors and P-type all-around gate transistors.

[0103] The present disclosure provides many different embodiments. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first all-around gate (GAA) transistor located above a first region of a substrate and a second all-around gate transistor located above a second region of the substrate. The first all-around gate transistor includes a plurality of first channel elements stacked along a first direction perpendicular to a top surface of the substrate, a first gate structure located above the plurality of first channel elements, and two first source / drain (S / D) components sandwiching the plurality of first channel elements. The second all-around gate transistor includes a plurality of second channel elements stacked along a second direction parallel to the top surface of the substrate, a second gate structure located above the plurality of second channel elements, and two second source / drain components sandwiching the plurality of second channel elements. The plurality of first channel elements and the plurality of second channel elements include a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane.

[0104] In some embodiments, the first all-around gate transistor is N-type and the second all-around gate transistor is P-type. In some embodiments, the first crystal plane is a (100) plane and the second crystal plane is a (110) plane. In some examples, each of the plurality of first channel elements has a first width parallel to the top surface of the substrate and a first height perpendicular to the top surface of the substrate, and each of the plurality of second channel elements has a second width parallel to the top surface of the substrate and a second height perpendicular to the top surface of the substrate. In these examples, the first width is greater than the first height, wherein, and the second width is less than the second height. In some embodiments, in some embodiments, the two first source / drain components include silicon and N-type dopants, and the two second source / drain components include silicon germanium and P-type dopants. In some embodiments, the semiconductor material includes silicon. In some embodiments, the plurality of first channel elements are staggered with the plurality of first internal spacer components, and the plurality of second channel elements are separated from the substrate by the plurality of second internal spacer components. The topmost first spacer component of the plurality of first internal spacer components is farther away from the substrate than the topmost second spacer component of the plurality of second internal spacer components. In some embodiments, a channel length of the plurality of first channel elements is substantially the same as a channel length of the plurality of second channel elements.

[0105] In another embodiment, a semiconductor device is provided. The semiconductor device includes a first all-around gate (GAA) transistor located above a first region of a substrate and a second all-around gate transistor located above a second region of the substrate. The first all-around gate transistor includes a plurality of first channel elements stacked along a first direction perpendicular to a top surface of the substrate, and an N-type source / drain (S / D) component. The second all-around gate transistor includes a plurality of second channel elements stacked along a second direction parallel to the top surface of the substrate, and a P-type source / drain component. The plurality of first channel elements and the plurality of second channel elements include silicon having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane.

[0106] In some embodiments, the first crystal plane is a (100) plane, and the second crystal plane is a (110) plane. In some embodiments, the first all-around gate transistor has a first footprint on the substrate, the second all-around gate transistor has a second footprint on the substrate, and the first footprint is substantially equal to the second footprint. In some examples, a first total channel width of the first all-around gate transistor is substantially equal to a second total channel width of the second all-around gate transistor. In some embodiments, the plurality of first channel elements includes a first number (N1) of first channel elements, and the plurality of second channel elements includes a second number (N2) of second channel elements. In some examples, the first number (N1) is greater than the second number (N2). In some embodiments, each of the plurality of first channel elements has a first width (W1) parallel to a top surface of the substrate and a first height (H1) perpendicular to the top surface of the substrate, and each of the plurality of second channel elements has a second width (W2) parallel to the top surface of the substrate and a second height (H2) perpendicular to the top surface of the substrate. In these embodiments, the first width (W1) is greater than the first height (H1), and the second width (W2) is less than the second height (H2). In some embodiments, the first total channel width of the first all-around gate transistor includes twice the product of the first number and the first width ((N1 x W1) x 2)), and the second total channel width of the second all-around gate transistor includes twice the product of the second number and the second height ((N2 x H2) x 2)). The first total channel width is approximately equal to the second total channel width. In some embodiments, the semiconductor device further includes a third all-around gate transistor located above the third region of the substrate. The third all-around gate transistor includes a plurality of third channel elements stacked along a second direction parallel to the top surface of the substrate, and a source / drain component. In these embodiments, the source / drain component is N-type, the first all-around gate transistor has a first channel length, the second all-around gate transistor has a second channel length, and the third all-around gate transistor has a third channel length. In these embodiments, the first channel length is approximately the same as the second channel length, and the third channel length is greater than the first channel length. In some examples, the first all-around-gate transistor is an input / output (I / O) all-around-gate transistor.

[0107] In another embodiment, a method is provided. The method includes providing a workpiece, the workpiece including a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged alternately above a first region and a second region of a substrate; removing a portion of the first semiconductor layers and the second semiconductor layers arranged alternately above the second region of the workpiece; forming an epitaxial semiconductor layer in the second region; recessing the workpiece to form a first fin in the first region and a plurality of second fins in the second region; forming a first dummy gate stack above a first channel region of the first fin and a second dummy gate stack above a second channel region of the second fin; forming gate spacers on sidewalls of the first dummy gate stack and the second dummy gate stack; recessing the first fin and the second fin to leave a portion of the first fin below the first dummy gate stack and a portion of the second fin below the second dummy gate stack; forming a first source / drain component sandwiching the portion of the first fin and forming a second source / drain component sandwiching the portion of the second fin; removing the first dummy gate stack and the second dummy gate stack; and removing the first semiconductor layer of the first channel region of the first fin and the epitaxial semiconductor layer of the second channel region of the second fin.

[0108] In some embodiments, the first semiconductor layer consists essentially of silicon germanium and the second semiconductor layer consists essentially of silicon. In some embodiments, the epitaxial semiconductor layer consists essentially of silicon. In some embodiments, the method further comprises forming an internal spacer between the second semiconductor layer before forming the first source / drain component and the second source / drain component. In some embodiments, the first source / drain component is N-type and the second source / drain component is P-type.

[0109] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present disclosure, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A semiconductor device comprising: A first all-around gate transistor is located above a first region of a substrate, the first all-around gate transistor comprising: A plurality of first channel elements are stacked along a first direction perpendicular to the top surface of the substrate; a first gate structure located above the plurality of first channel elements; and two first source / drain components sandwiching the plurality of first channel elements; and a second all-around gate transistor located above a second region of the substrate, the second all-around gate transistor comprising: A plurality of second channel elements are stacked along a second direction parallel to the top surface of the substrate; a second gate structure located above the plurality of second channel elements; and Two second source / drain components sandwich the plurality of second channel elements, wherein the plurality of first channel elements and the plurality of second channel elements comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane, wherein the first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane, wherein the channel length of the plurality of first channel elements is substantially the same as the channel length of the plurality of second channel elements.

2. The semiconductor device according to claim 1, wherein: The first all-around-gate transistor is N-type, and the second all-around-gate transistor is P-type.

3. The semiconductor device according to claim 1, wherein: The first crystal plane is a (100) plane, and the second crystal plane is a (110) plane.

4. The semiconductor device according to claim 1, wherein: Each of the plurality of first channel elements has a first width parallel to the top surface of the substrate and a first height perpendicular to the top surface of the substrate, wherein the first width is greater than the first height, and each of the plurality of second channel elements has a second width parallel to the top surface of the substrate and a second height perpendicular to the top surface of the substrate, wherein the second width is less than the second height.

5. The semiconductor device according to claim 1, wherein: The plurality of first channel elements are staggered with a plurality of first internal spacing members, wherein the plurality of second channel elements are separated from the substrate by a plurality of second internal spacing members, wherein a topmost first spacing member of the plurality of first internal spacing members is further away from the substrate than a topmost second spacing member of the plurality of second internal spacing members.

6. A semiconductor device comprising: A first all-around gate transistor is located above a first region of a substrate, the first all-around gate transistor comprising: A plurality of first channel elements are stacked along a first direction perpendicular to the top surface of the substrate; and an N-type source / drain component; and a second all-around gate transistor located above a second region of the substrate, the second all-around gate transistor comprising: A plurality of second channel elements are stacked along a second direction parallel to the top surface of the substrate; and A P-type source / drain component, Wherein, the plurality of first channel elements and the plurality of second channel elements include silicon having a first crystal plane and a second crystal plane different from the first crystal plane, wherein the first direction is perpendicular to the first crystal plane, and the second direction is perpendicular to the second crystal plane, wherein a first total channel width of the first all-around gate transistor is substantially equal to a second total channel width of the second all-around gate transistor.

7. The semiconductor device according to claim 6, wherein: The first crystal plane is a (100) plane, and the second crystal plane is a (110) plane.

8. The semiconductor device according to claim 6, wherein: The first all-around gate transistor has a first occupied area on the substrate, the second all-around gate transistor has a second occupied area on the substrate, and the first occupied area is substantially equal to the second occupied area.

9. The semiconductor device according to claim 6, wherein: The plurality of first channel elements include a first number of first channel elements, and the plurality of second channel elements include a second number of second channel elements, and the first number is greater than the second number.

10. The semiconductor device according to claim 9, wherein: Each of the plurality of first channel elements has a first width parallel to the top surface of the substrate and a first height perpendicular to the top surface of the substrate, wherein the first width is greater than the first height, and each of the plurality of second channel elements has a second width parallel to the top surface of the substrate and a second height perpendicular to the top surface of the substrate, wherein the second width is less than the second height.

11. The semiconductor device according to claim 10, wherein: The first total channel width of the first all-around gate transistor comprises twice the product of the first number and the first width, wherein the second total channel width of the second all-around gate transistor comprises twice the product of the second number and the second height.

12. The semiconductor device according to claim 6, further comprising: a third all-around gate transistor located above a third region of the substrate, the third all-around gate transistor comprising: a plurality of third channel elements stacked along the second direction parallel to the top surface of the substrate; and a source / drain component, wherein the source / drain component is of N type, The first all-around gate transistor has a first channel length, the second all-around gate transistor has a second channel length, and the third all-around gate transistor has a third channel length, wherein the first channel length is substantially the same as the second channel length, and the third channel length is greater than the first channel length.

13. The semiconductor device according to claim 12, wherein: The first all-around-gate transistor is an input / output all-around-gate transistor.

14. A method for forming a semiconductor device, comprising: Providing a workpiece, the workpiece comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately arranged above a first region and a second region of a substrate; removing a portion of the plurality of first semiconductor layers and the plurality of second semiconductor layers that are alternately arranged above the second region of the workpiece; forming an epitaxial semiconductor layer in the second region; recessing the workpiece to form a first fin in the first region and a plurality of second fins in the second region; forming a first dummy gate stack above a first channel region of the first fin and forming a second dummy gate stack above a second channel region of the plurality of second fins; forming a gate spacer on the sidewalls of the first dummy gate stack and the second dummy gate stack; recessing the first fin and the plurality of second fins to leave a portion of the first fin under the first dummy gate stack and a portion of the plurality of second fins under the second dummy gate stack; forming a first source / drain component to sandwich the portion of the first fin and forming a second source / drain component to sandwich the portion of the plurality of second fins; removing the first dummy gate stack and the second dummy gate stack; as well as The plurality of first semiconductor layers in the first channel region of the first fin and the epitaxial semiconductor layer in the second channel region of the plurality of second fins are removed.

15. The method for forming a semiconductor device according to claim 14, wherein: The plurality of first semiconductor layers are mainly composed of silicon germanium, and the plurality of second semiconductor layers are mainly composed of silicon.

16. The method for forming a semiconductor device according to claim 14, wherein: The epitaxial semiconductor layer is mainly composed of silicon.

17. The method for forming a semiconductor device according to claim 14, further comprising: Before forming the first source / drain feature and the second source / drain feature, a plurality of inner spacers are formed between the plurality of second semiconductor layers.

18. The method for forming a semiconductor device according to claim 14, wherein: The first source / drain component is of N type, and the second source / drain component is of P type.

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