Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device, which may include a first unit structure, a second unit structure, a pad structure, a circuit, and one or more openings. The pad structure may be arranged between the first unit structure and the second unit structure, and may be electrically connected to the first unit structure and the second unit structure. The pad structure may have a plurality of step structures. The circuit may be arranged below the pad structure. One or more openings may pass through the pad structure and may expose the circuit. One or more openings may be arranged between the plurality of step structures.

Description

[0001] This application is a divisional application of a patent application with an application date of December 9, 2016, application number 201611129796.6, and invention name “Semiconductor device and manufacturing method thereof”. Technical Field

[0002] Various embodiments of the present disclosure generally relate to an electronic device and a method for manufacturing the same, and more particularly, to a three-dimensional semiconductor device and a method for manufacturing the same. Background Art

[0003] A nonvolatile memory device retains stored data regardless of whether the nonvolatile memory device is connected to a power source. As two-dimensional nonvolatile memory device technology reaches its physical scaling limit, some semiconductor manufacturers are producing three-dimensional (3D) nonvolatile memory devices by stacking memory cells on top of each other on a substrate.

[0004] A three-dimensional memory device may include a gate electrode alternately stacked with an interlayer insulating layer, and may also include a channel layer passing through the gate electrode and the interlayer insulating layer. In this way, the memory cells may be arranged vertically along the channel layer. In order to improve the reliability of such a non-volatile memory device having a three-dimensional structure, various structures and manufacturing methods are being developed. Summary of the invention

[0005] In an embodiment of the present disclosure, a semiconductor device may include a circuit, a pad structure, a first opening, a second opening, a first interconnect structure, and a second interconnect structure. The pad structure may be arranged above the circuit, and may include a first stepped structure including a first pad stacked on each other, a second stepped structure including a second pad stacked on each other, and a third stepped structure including a third pad stacked on each other. The first opening may be arranged between the first stepped structure and the second stepped structure, and may pass through the pad structure and expose the circuit. The second opening may be arranged between the second stepped structure and the third stepped structure, and may pass through the pad structure and expose the circuit. The first interconnect structure may electrically couple the first pad and the third pad to each other, and couple the first pad and the third pad to the circuit together through the first opening or the second opening. The second interconnect structure may electrically couple the second pads to each other, and couple the second pad to the circuit through the first opening or the second opening.

[0006] In an embodiment of the present disclosure, a semiconductor device may include a first unit structure, a second unit structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first unit structure and the second unit structure, and may be electrically coupled to the first unit structure and the second unit structure. The pad structure may have a plurality of step structures. The circuit may be disposed below the pad structure. One or more openings may pass through the pad structure and expose the circuit. One or more openings may be disposed between the plurality of step structures.

[0007] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include forming a circuit on a pad region of a substrate, wherein the substrate includes a first unit region, a pad region, and a second unit region sequentially arranged in a first direction. The method may include forming a stacked structure above a substrate on which a circuit is formed, the stacked structure including a first group to an nth group (n is a natural number greater than or equal to 3) stacked on each other. The method may include partially patterning the pad region of the stacked structure, and forming a first unit structure disposed in a first unit region, a second unit structure disposed in a second unit region, and a pad structure disposed in the pad region. The pad structure may include a plurality of step structures, and may be electrically connected to the first unit structure and the second unit structure. The method may include forming one or more openings that pass through the pad structure and expose the circuit. One or more openings may be disposed between a plurality of step structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1D is a diagram showing an example structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A and Figure 2B 1 are a layout diagram and a cross-sectional diagram respectively illustrating an example structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] FIG. 3A to FIG. 3C is a layout diagram showing an example structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] FIG. 4A to FIG. 8A , FIG. 4B to FIG. 8B and Fig. 9 1 are a layout diagram and a cross-sectional diagram respectively illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Fig.10 and Fig.11 is a diagram showing an example configuration of a memory system according to an embodiment of the present disclosure.

[0013] Fig.12 and Fig.13 is a diagram illustrating an example of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0015] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always represent the same elements.

[0016] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. Embodiments are described herein with reference to cross-sectional views, which are schematic views of embodiments (and intermediate structures). Thus, variations in the illustrated shapes will be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but may include shape deviations, for example, caused by manufacturing. In the accompanying drawings, the lengths and sizes of layers and regions may be exaggerated for clarity. The same reference numerals in the drawings represent the same elements.

[0017] Terms such as "first" and "second" may be used to describe various components, but they should not limit the various components. These terms are only used for the purpose of distinguishing one component from other components. For example, a first component may be referred to as a second component, a second component may be referred to as a first component, and so on, without departing from the spirit and scope of the present disclosure. In addition, "and / or" may include any one or combination of the mentioned components.

[0018] In addition, as long as there is no special mention in the sentence, the singular form may include the plural form. In addition, "include / comprise" or "including / comprising" used in this specification means that one or more parts, steps, operations and elements exist or are added.

[0019] In addition, unless otherwise defined, all terms including technical and scientific terms used in this specification have the same meanings as those generally understood by technicians in the relevant fields. Terms defined in commonly used dictionaries should be interpreted as having the same meanings as those explained in the context of the relevant field, and should not be interpreted as having idealized or overly formal meanings unless otherwise clearly defined in this specification.

[0020] It should also be noted that in this specification, "connection / coupling" refers not only to one component being directly coupled to another component, but also to being indirectly coupled to another component through an intermediate component. On the other hand, "direct connection / direct coupling" refers to one component being directly coupled to another component without an intermediate component.

[0021] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the thickness and length of the components may be exaggerated for ease of explanation. In the following description, for simplicity and clarity, the detailed description of the relevant functions and configurations may be omitted. Throughout the specification and the accompanying drawings, the same reference numerals refer to the same elements.

[0022] Figures 1A to 1D is a diagram showing an example structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A and Figure 1B It is a layout diagram. Figure 1C is along Figure 1B A cross-sectional view taken along line A-A', Figure 1D is along Figure 1B A cross-sectional view taken along line BB'.

[0023] Reference Figure 1A and Figure 1B , a semiconductor device according to an embodiment may include a substrate, cell structures CS1 and CS2, a pad structure PS, and a circuit. The substrate may include cell regions CR1 and CR2 and a pad region PR. For example, the cell regions CR1 and CR2 may include a first cell region CR1 and a second cell region CR2, and the pad region PR may be located between the first cell region CR1 and the second cell region CR2. Therefore, in the case where the cell structures CS1 and CS2 include the first cell structure CS1 and the second cell structure CS2, the first cell structure CS1, the pad structure PS, and the second cell structure CS2 may be sequentially arranged in the first direction II'. In addition, the semiconductor device may perform an erase operation based on a memory block. Each of the memory blocks MB may include a first cell region CR1, a second cell region CR2, and a pad region PR located between the first cell region CR1 and the second cell region CR2. The first cell region CR1 and the second cell region CR2 may share the pad structure PS.

[0024] The first unit structure CS1 and the second unit structure CS2 may be located in the first unit region CR1 and the second unit region CR2 of the substrate, respectively. The unit structures CS1 and CS2 may include conductive layers and insulating layers alternately stacked with each other. In other words, each unit structure CS1 and CS2 may have a series of conductive layers stacked alternately with insulating layers. In addition, the unit structures CS1 and CS2 may include a channel layer CH through the conductive layer and the insulating layer. The bottom one or more conductive layers may be used as source selection lines. The top one or more conductive layers may be used as drain selection lines. Other conductive layers may be used as word lines. Here, one or more source selection transistors, a plurality of memory cells, and one or more drain selection transistors connected in series with each other may form a single memory string. The memory string may be arranged in a vertical direction.

[0025] The first unit structure CS1 may include one or more first source selection lines, a plurality of first word lines, and one or more first drain selection lines. For example, a plurality of first word lines stacked on each other may be arranged on one or more first source selection lines, and one or more first drain selection lines may be arranged on the top first word line. The second unit structure CS2 may include one or more second source selection lines stacked on each other in sequence, a plurality of second word lines, and one or more second drain selection lines. For example, a plurality of second word lines stacked on each other may be arranged on one or more second source selection lines, and one or more second drain selection lines may be arranged on the top second word line. In addition, the first unit structure CS1 may include a first vertical memory string, and the second unit structure CS2 may include a second vertical memory string.

[0026] The pad structure PS may be located in a pad region PR of the substrate. For example, the pad structure PS may be located between the first unit structure CS1 and the second unit structure CS2. The pad structure PS may be in direct contact with the first unit structure CS1 and the second unit structure CS2, and may be electrically connected to the first unit structure CS1 and the second unit structure CS2. In addition, the circuit may be located below the pad structure PS, and at least a portion of the circuit may be exposed by at least one opening OP passing through the pad structure PS. The opening OP may be filled with an insulating pattern IP. In addition, a plurality of openings OP may be arranged in a row along a center line CL extending along a first direction II' on a center portion of the pad region PR. The opening OP may be located in a center portion of the pad region PR, and the number of the openings OP and their shapes may be modified in various ways.

[0027] The pad structure PS may include conductive layers and insulating layers alternately stacked with each other. For example, the pad structure PS may include a series of conductive layers stacked alternately with insulating layers. Among the conductive layers of the pad structure PS and the conductive layers of the first unit structure CS1 and the second unit structure CS2, the conductive layers arranged at the same level may be electrically connected to each other. In addition, the pad structure PS is partially patterned so that it has a stepped structure of various heights. In this way, pads P1 to P4 may be formed, wherein bias can be applied separately to the corresponding stacked conductive layers through the pads P1 to P4. In addition, the conductive layer of the unpatterned pad structure PS can be used as a wire (e.g., an interconnection) that electrically connects the pads P1 to P4 to the conductive layers of the unit structures CS1 and CS2.

[0028] The pad structure PS may include a first stepped structure S1 and a second stepped structure S2. In an embodiment, the first stepped structure S1 and the second stepped structure S2 may be disposed between each adjacent opening OP. The first stepped structure S1 and the second stepped structure S2 may be arranged along the center line CL. For example, the first stepped structure S1 may be disposed on one side of the center line CL, and the second stepped structure S2 may be disposed on the other side of the center line CL. In an embodiment, the first stepped structure S1 and the second stepped structure S2 may be symmetrical about the center line CL.

[0029] The first stepped structures S1 are arranged in the first direction II', and adjacent first stepped structures S1 can be isolated from each other by corresponding openings OP. The second stepped structures S2 are arranged in the first direction II', and adjacent second stepped structures S2 can also be isolated from each other by corresponding openings OP. In addition, adjacent first stepped structures S1 and second stepped structures S2 arranged symmetrically about the center line CL can be isolated from each other by third slits SL3A.

[0030] The pad structure PS may include a first line structure LS1 and a second line structure LS2. The first line structure LS1 may electrically couple the first pad P1 to the first unit structure CS1 and the second unit structure CS2. The second line structure LS2 may electrically couple the second pad P2 to the first unit structure CS1 and the second unit structure CS2. The first line structure LS1 may be disposed between the center line CL and the second slit SL2A. The second line structure LS2 may be disposed between the center line CL and the second slit SL2B. In this case, the first line structure LS1, the first step structure S1, the second step structure S2, and the second line structure LS2 may be sequentially arranged in the second direction II-II'. In addition, the first line structure LS1, the opening OP, and the second line structure LS2 may be sequentially arranged in the second direction II-II'.

[0031] The first line structure LS1 includes first lines L1 stacked on each other. Each of the first lines L1 electrically couples the first pad P1 to the first unit structure CS1 or the second unit structure CS2. Each of the first lines L1 may electrically couple the first pad P1 to the first unit structure CS1 and the second unit structure CS2. The height of the first line structure LS1 is equal to or greater than the height of the first step structure S1. The second line structure LS2 includes second lines L2 stacked on each other. Each of the second lines L2 electrically couples the second pad P2 to the first unit structure CS1 or the second unit structure CS2. Each of the second lines L2 may electrically couple the second pad P2 to the first unit structure CS1 and the second unit structure CS2. The height of the second line structure LS2 is equal to or greater than the height of the second step structure S2. The first line structure LS1 may include a first dummy step structure DS1 disposed on the stacked first line L1. The second line structure LS2 may include a second dummy step structure DS2 disposed on the stacked second line L2.

[0032] The pad structure PS may include a third stepped structure S3 in contact with the first unit structure CS1 and a fourth stepped structure S4 in contact with the second unit structure CS2. The third stepped structure S3 is disposed between the first unit structure CS1 and the corresponding opening OP, and includes a third pad P3 stacked on each other. The fourth stepped structure S4 is disposed between the second unit structure CS2 and the corresponding opening OP, and includes a fourth pad P4 stacked on each other. The third pad P3 may be electrically coupled to the first unit structure CS1. For example, the third pad P3 may be in direct contact with the first unit structure CS1. The fourth pad P4 may be electrically coupled to the second unit structure CS2. For example, the fourth pad P4 may be in direct contact with the second unit structure CS2.

[0033] The semiconductor device may include first to fifth slits SL1 to SL5 passing through the first unit structure CS1, the pad structure PS, or the second unit structure CS2 in a stacking direction (e.g., a direction in which layers included in each of the first unit structure CS1, the pad structure PS, and the second unit structure CS2 are stacked). The first to fifth slits SL1 to SL5 may be filled with first to fifth slit insulating layers, respectively. Each of the first to fifth slits SL1 to SL5 may have a depth that completely passes through the corresponding stacked structure. Alternatively, each of the first to fifth slits SL1 to SL5 may have a depth that partially penetrates the corresponding stacked structure.

[0034] The first slits SL1 may separate the drain selection lines of the adjacent channel layers CH from each other and may be disposed in the memory block MB. Each of the first slits SL1 may pass through the second unit structure CS2 in the stacking direction and may have a depth passing through the second drain selection line. The first slits SL1 may extend in the first direction II' to pass through the fourth stepped structure S4. The first slits SL1 may isolate the fourth pads P4 coupled to the second drain selection line from each other. Similarly, the first slits SL1 may be disposed to pass through the first unit structure CS1 and the third stepped structure S3.

[0035] The second slits SL2A and SL2B may electrically separate adjacent memory blocks MB and may be disposed on boundaries between adjacent memory blocks MB. Each of the second slits SL2A and SL2B may have a depth that completely passes through the first and second cell structures CS1 and CS2 and the pad structure PS in the stacking direction.

[0036] The third slits SL3A and SL3B are disposed in the memory block MB, and each of the slits has a line shape extending in the first direction II'. Each of the third slits SL3A and SL3B may have a depth that completely passes through the first unit structure CS1 and the second unit structure CS2 in the stacking direction. The third slit SL3A may extend to the pad region PR and overlap with the center line CL. The third slit SL3A may traverse a plurality of openings OP and may be inserted between adjacent first stepped structures S1 and second stepped structures S2. Therefore, the adjacent first stepped structures S1 and second stepped structures S2 may be isolated from each other by the third slit SL3A. The third slit SL3B may be disposed between the center line CL and the second slits SL2A and SL2B, and each of the third slits SL3B may have a depth that passes through the first unit structure CS1 and the third stepped structure S3 or the second unit structure CS2 and the fourth stepped structure S4.

[0037] The fourth slit SL4 and the fifth slit SL5 isolate the conductive lines disposed at the same level from each other. The fourth slit SL4 and the fifth slit SL5 may be disposed in the pad structure PS. The fourth slit SL4 may extend in the first direction II-I' and may be connected to the third slit SL3B. The fifth slit SL5 may extend in the second direction II-II' and may cross the corresponding opening OP. The fifth slit SL5 may be connected to the fourth slit SL4. Therefore, the fourth slit SL4 and the fifth slit SL5 may be connected to each other in a C-shape.

[0038] Each of the fourth slits SL4 may have a depth that passes only through the line connected to the source selection line. Each of the fifth slits SL5 may have a depth that completely passes through the pad structure PS. The line connected to the source selection line is patterned through the second slits SL2A and SL2B, the third slit SL3A, the fourth slit SL4, and the fifth slit SL5. The line connected to the word line is patterned through the second slits SL2A and SL2B, the third slit SL3A, and the fifth slit SL5. Therefore, the source selection line and the word line can be patterned in different shapes by adjusting the depth of the fourth slit SL4.

[0039] Reference Figure 1C and Figure 1D , the pad structure PS may be arranged in the pad region PR of the substrate 20, and the circuit 21 may be arranged below the pad structure PS. The circuit 21 may include various components, such as transistors, capacitors, and resistors. In an embodiment, the circuit 21 may be an X-decoder X-DEC. The pad structure PS may include stacked layers 1 to 16, and each of the layers 1 to 16 may include a first layer A and a second layer B. For example, the first layer A may be a conductive layer, and the second layer B may be an insulating layer. Alternatively, the first layer A may be an insulating layer, and the second layer B may be a conductive layer.

[0040] Each of the first stepped structures S11 to S13 includes first pads P11 to P13. The first pads P11 to P13 are electrically coupled to first lines L11 to L13, respectively. The first lines L11 to L13 electrically couple the first pads P11 to P13 to a first source selection line of a first vertical memory string and / or a second source selection line of a second vertical memory string.

[0041] Each of the first stepped structures S14 includes a first pad P14. The first pads P14 are electrically coupled to first lines L14, respectively. The first lines L14 electrically couple the first pads P14 to a first word line of a first vertical memory string and a second word line of a second vertical memory string.

[0042] The first stepped structures S11 to S14 and the second stepped structures S21 to S24 may be symmetrically arranged about the center line CL. The first lines L11 to L14 and the second lines L21 to L24 may be symmetrically arranged about the center line CL.

[0043] The third stepped structure S3 may include a third pad P3 electrically coupled to a first drain selection line of the first vertical memory string. The fourth stepped structure S4 may include a fourth pad P4 electrically coupled to a second drain selection line of the second vertical memory string. For reference, the third pad P3 of the thirteenth layer 13 may be electrically coupled to a first word line of the first vertical memory string, and the fourth pad P4 of the thirteenth layer 13 may be electrically coupled to a second word line of the second vertical memory string.

[0044] Here, the first unit structure CS1 and the second unit structure CS2 are arranged on opposite sides of the pad structure PS. The first unit structure CS1 and the second unit structure CS2 can share the pad structure PS. Therefore, compared with the case where the circuit is arranged only on one side of the cell area, the distance between the circuit 21 and the unit structures CS1 and CS2 can be reduced by half, thereby reducing the RC delay. Therefore, the programming speed of the semiconductor device can be increased.

[0045] In addition, the circuit 21 and the plurality of openings OP may be disposed in the central portion of the pad region PR, and the pads may be distributed in the space between the plurality of openings OP. Thus, the pad region PR requires a smaller area. In addition, since the pad is formed by partially patterning the pad structure and the non-patterned area is used as a conductor (e.g., an interconnect), the manufacturing process can be simplified.

[0046] Figure 2A and Figure 2B is a diagram showing an example structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A is the layout diagram of the interconnect structure, Figure 2B is a cross-sectional view of the first stepped structure taken along a line II′ in the first direction. Figure 2A and Figure 2B The same or similar components are used in Figures 1A to 1D The same reference symbols as in the drawings are marked with the same reference symbols, and any repeated detailed description will be omitted or simplified.

[0047] Reference Figure 2A and Figure 2B , the first interconnect structure C1 may electrically couple the first pad P11 of the first stepped structure S11 to the first pad P13 of the first stepped structure S13. In addition, the first interconnect structure C1 may couple the first pads P11 and P13 to the circuit 21. For example, the first interconnect structure C1 may include first contact plugs 31 coupled to respective first pads P11, second contact plugs 32 coupled to respective first pads P13, third contact plugs 33 disposed in corresponding openings OP and coupled to the circuit 21, and conductive lines 34 electrically coupling the first to third contact plugs 31 to 33 to each other and extending in the first direction II'.

[0048] The second interconnect structure C2 may electrically couple the first pads P12 of the first stepped structure S12 to each other, and may couple the first pads P12 to the circuit 21. For example, the second interconnect structure C2 may include first contact plugs 35 coupled to the respective first pads P12, second contact plugs 36 disposed in the corresponding openings OP and coupled to the circuit 21, and conductive lines 37 electrically coupling the first contact plugs 35 and the second contact plugs 36 to each other and extending in the first direction II'.

[0049] The third interconnection structure C3 may electrically couple the second pad P21 of the second stepped structure S21 to the second pad P23 of the second stepped structure S23 and electrically couple the first and second pads P21 and P23 to the circuit 21. The fourth interconnection structure C4 may couple the second pad P22 of the second stepped structure S22 to the circuit.

[0050] The fifth interconnection structure C5 may electrically couple first pads P14 and second pads P24 of the first stepped structure S14 and the second stepped structure S24 adjacent to each other in the second direction II-II'. Among the first pads P14 and the second pads P24, the first pads P14 and the second pads P24 disposed at the same level are electrically coupled to each other.

[0051] The sixth interconnect structure C6 may electrically couple the third pad P3 of the third stepped structure S3 to the fourth pad P4 of the fourth stepped structure S4. For example, the sixth interconnect structure C6 may include fourth contact plugs 38 coupled to respective third pads P3, fifth contact plugs 39 coupled to respective fourth pads P4, and conductive lines 40 electrically coupling the fourth contact plugs 38 and the fifth contact plugs 39 to each other.

[0052] For reference, the connection method may be modified according to the respective numbers of source selection transistors, memory cells, and drain selection transistors included in a single memory string. In one example, Figure 2A and Figure 2B The vertical memory string shown in includes three source selection transistors, ten memory cells, and three drain selection transistors. Therefore, the first pad P11 of the fourth layer 4 of the first ladder structure S11 can be electrically connected to the second pad P21 of the fourth layer 4 of the second ladder structure S21 through the fifth interconnect structure C5. In addition, the third pads P3 of the thirteenth layer 13 of the third ladder structure S3 adjacent to each other in the second direction II-II' can be electrically connected to each other through the fifth interconnect structure C5. Although Figure 2A and Figure 2B An example of a vertical memory string including three source select transistors, ten memory cells, and three drain select transistors is shown, but it is intended only to illustrate and not to limit the present invention, and the number of stacked layers or the connection method of the interconnect structure may vary.

[0053] FIG. 3A to FIG. 3C is a layout diagram showing an example structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3A is a layout diagram showing conductive lines and pads coupled to source select lines. Figure 3B is a layout diagram showing conductive lines and pads connected to word lines. Figure 3C is a layout diagram showing pads coupled to drain select lines.

[0054] Reference Figure 3A The first cell structure CS1 includes first source selection lines SSL11 to SSL14, and the second cell structure CS2 includes second source selection lines SSL21 to SSL24. The first pads P11 to P13 and the second pads P21 to P23 of the pad structure PS are electrically coupled to the first source selection lines SSL11 to SSL14 and the second source selection lines SSL21 to SSL24.

[0055] The first pad P11 is electrically coupled to the first line L11. The first pad P12 is electrically coupled to the first line L12. The first pad P13 is electrically coupled to the first line L13. The first lines L11 to L13 disposed at the same level are isolated from each other by the slits SL.

[0056] The first line L11 electrically couples the first source selection line SSL12 to the first pad P11. The first line L12 is commonly coupled to the first source selection line SSL11 and the second source selection line SSL21. Therefore, the first line L12 electrically couples the first source selection line SSL11 and the second source selection line SSL21 to the first pad P12. The first line L13 electrically couples the second source selection line SSL22 to the first pad P13.

[0057] The second pad P21 is electrically coupled to the second line L21. The second pad P22 is electrically coupled to the second line L22. The second pad P23 is electrically coupled to the second line L23. The second lines L21 to L23 disposed at the same level are isolated from each other by the slits SL.

[0058] The second line L21 electrically couples the first source selection line SSL13 to the second pad P21. The second line L22 is commonly coupled to the first source selection line SSL14 and the second source selection line SSL24. Therefore, the second line L22 electrically couples the first source selection line SSL14 and the second source selection line SSL24 to the second pad P22. The second line L23 electrically couples the second source selection line SSL23 to the second pad P23.

[0059] Therefore, the first source selection lines SSL11 to SSL14 included in the first cell structure CS1 may be individually controlled. In addition, the second source selection lines SSL21 to SSL24 included in the second cell structure CS2 may be individually controlled.

[0060] Reference Figure 3B The first unit structure CS1 includes first word lines WL11 to WL14, and the second unit structure CS2 includes second word lines WL21 to WL24. The first and second pads P14 and P24 of the pad structure PS are electrically coupled to the first and second word lines WL11 to WL14 and WL21 to WL24.

[0061] The first pad P14 is electrically coupled to the first line L14, and the second pad P24 is electrically coupled to the second line L24. Among the first line L14 and the second line L24, the first line L14 and the second line L24 disposed at the same level are isolated from each other by the slit SL.

[0062] The first line L14 is commonly coupled to the first word lines WL11 to WL12 and the second word lines WL21 to WL22. Therefore, the first line L14 electrically couples the first word lines WL11 to WL12 and the second word lines WL21 to WL22 to the first pad P14. The second line L24 is commonly coupled to the first word lines WL13 to WL14 and the second word lines WL23 to WL24. Therefore, the second line L24 electrically couples the first word lines WL13 to WL14 and the second word lines WL23 to WL24 to the second pad P24.

[0063] Reference Figure 3C , the first unit structure CS1 includes first drain selection lines DSL11 to DSL18, and the second unit structure CS2 includes second drain selection lines DSL21 to DSL28. In addition, the third pads P31 to P38 of the pad structure PS are electrically coupled to the first drain selection lines DSL11 to DSL18, respectively. The fourth pads P41 to P48 are electrically coupled to the second drain selection lines DSL21 to DSL28, respectively. The third pads P31 to P38 may be in direct contact with the first drain selection lines DSL11 to DSL18, respectively. The fourth pads P41 to P48 may be in direct contact with the second drain selection lines DSL21 to DSL28, respectively.

[0064] FIG. 4A to FIG. 9 are a layout diagram and a cross-sectional diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9 It is a layout diagram. Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B is a cross-sectional view. FIG. 4A to FIG. 9 The same or similar elements in the drawings are marked with the same reference symbols as those in the previous drawings, and any repeated detailed description will be omitted or simplified.

[0065] Reference Figure 4A and Figure 4B, a circuit 61 is formed on a substrate 60 including a first cell region CR1, a second cell region CR2, and a pad region PR. For example, an X-decoder is formed on the pad region PR of the substrate 60, and then an interlayer insulating layer is formed. Subsequently, stacked layers 41 to 44 are formed on the substrate 60. The stacked layers 41 to 44 are formed on the first cell region CR1, the pad region PR, and the second cell region CR2 of the substrate 60 in a manner covering the circuit 61.

[0066] Then, although not shown, a channel layer passing through the stacked layers 41 to 44 of the first cell region CR1 and the second cell region CR2 and a data storage layer surrounding the sidewalls of each channel layer may be formed. Each of the data storage layers may include a floating gate containing a material such as silicon, a charge trapping material (e.g., nitride), a phase change material, nanodots, etc.

[0067] Then, first slits SL1 passing through the stacked layers 41 to 44 are formed, and first slit insulating layers SLI1 are formed in the first slits SL1. The first slits SL1 may be disposed in the pad region PR. Each first slit SL1 may have a line shape extending in the first direction II'. The first slits SL1 pass through the stacked layers 41 to 44 in the stacking direction (e.g., the direction in which the layers 41 to 44 are stacked). The first slits SL1 may be spaced apart from each other. The first slits SL1 may have the same length as each other. Optionally, the first slits SL1 may have different lengths.

[0068] For example, in forming a stack structure of n stacked groups, the first group G1 is formed, and then the first slit SL1 and the first slit insulating layer SLI1 are formed. In this way, the first group G1 may have a pattern different from the patterns of the remaining second to nth groups. Here, n is a natural number greater than or equal to 3.

[0069] Reference Figure 5A and Figure 5B , stacked layers 45 to 56 of the second to n-th groups are formed on the stacked layers 41 to 44 of the first group G1. In this way, the stacked layers 41 to 56 may form a stacked structure ST. The stacked structure ST may include a first unit structure and a second unit structure and a pad structure. The first unit structure may be a part of the stacked structure ST forming the first unit region CR1. The second unit structure may be a part of the stacked structure ST forming the second unit region CR2. The pad structure may be a part of the stacked structure ST forming the pad region PR. That is, different parts of a single stacked structure ST may perform different functions.

[0070] Each of the layers 41 to 56 may include a first material layer C and a second material layer D. For example, in each of the layers 41 to 56, the first material layer C may be disposed on the second material layer D. Alternatively, the second material layer D may be disposed on the first material layer C.

[0071] The first material layer C is provided to form a word line, a selection line, a pad, etc., and the second material layer D is provided to insulate the stacked conductive layers from each other. For example, each of the first material layers C may be formed of a sacrificial layer including a nitride material, etc., and each of the second material layers D may be formed of an insulating layer including an oxide material, etc. Alternatively, each of the first material layers C may be formed of a conductive layer including polysilicon, tungsten, etc., and each of the second material layers D may be formed of an insulating layer including an oxide material, etc. As a further option, each of the first material layers C may be formed of a conductive layer including doped polysilicon, etc., and each of the second material layers D may be formed of a sacrificial layer including undoped polysilicon, etc.

[0072] The stacked layers 41 to 56 may be grouped according to the shape of the line, the location of the pad, etc. Figure 5A and Figure 5B In the example shown, n is 3, and thus the stacked layers 41 to 56 are divided into three groups, namely the first group (41 to 44; G1), the second group (45 to 52; G2), and the third group (53 to 56; G3). Here, the shape of the wires in the first group G1 is different from the shape of the wires in the second group G2 or the third group G3 in that the first group G1 is additionally patterned by the first slit insulating layer SLI1. In addition, in the first group G1 and the second group G2, the pads are disposed at the central portion of the pad region PR, while the pads of the third group G3 are in contact with the cell structure. The number of stacked groups and the number of stacked layers included in each group may vary.

[0073] Subsequently, a first mask pattern 57 is formed on the stacked structure ST. The first mask pattern 57 includes first openings OP1, each of which has a line shape extending in the second direction II-II'. Thereafter, the nth group is partially patterned using the first mask pattern 57, and thus the plurality of stepped structures expose the layers of the nth group in a predetermined pattern.

[0074] For example, when n is 3, the first mask pattern 57 is used as an etch barrier to etch the layer 56 of the third group G3, and then the first mask pattern 57 is reduced so that the first opening OP1 extends in the first direction II'. Thereafter, the layers 55 and 56 of the third group G3 are etched using the reduced first mask pattern 57 as an etch barrier. In this way, by repeatedly performing the etching operation and the operation of reducing the first mask pattern 57, the layers 53 to 56 of the third group G3 of each stepped structure can be exposed in a predetermined pattern. Thus, a first line structure LS1 including a first line L1 and a first dummy stepped structure DS1, and a second line structure LS2 including a second line L2 and a second dummy stepped structure DS2 can be formed. In addition, a third stepped structure S3 in contact with the first unit structure CS1 and a fourth stepped structure S4 in contact with the second unit structure CS2 can be formed. Subsequently, the first mask pattern 57 is removed.

[0075] Reference Fig. 6A , Figure 6B , Fig. 7A and Figure 7B , partially patterning the first to (n-1)th groups of the stacked structure ST to form a plurality of stepped structures exposing the first to (n-1)th groups of layers in a predetermined pattern. For example, when n is 3, a plurality of stepped structures exposing the first and second groups of layers in a predetermined pattern may be formed.

[0076] First, a second mask pattern 58 including a second opening OP2 is formed on the stacked structure ST, and then the layers 50 to 53 are etched using the second mask pattern 58 as an etching barrier. Subsequently, the second mask pattern 58 is removed. Thereafter, a third mask pattern 59 including a third opening OP3 is formed on the stacked structure ST, and then the layers 42 to 49 are etched using the third mask pattern 59 as an etching barrier. Thus, a first stepped structure S1 and a second stepped structure S2 exposing the layers 41 to 52 in a predetermined pattern may be formed.

[0077] The second mask pattern 58 and the third mask pattern 59 are formed to cover the first line structure LS1 and the second line structure LS2 and the third stepped structure S3 and the fourth stepped structure S4. The second mask pattern 58 and the third mask pattern 59 include a second opening OP2 and a third opening OP3, which have an island shape and expose the area where the first stepped structure S1 and the second stepped structure S2 will be formed. According to the number of stacked layers, the second opening OP2 and the third opening OP3 may at least partially overlap each other. The second opening OP2 and the third opening OP3 may have the same width as each other. Alternatively, the second opening OP2 and the third opening OP3 may have different widths from each other. In addition, the number of etching layers may be changed.

[0078] Reference Fig. 8A and Figure 8B , an interlayer insulating layer 70 is formed on the stacked structure ST, and then a fourth opening OP4 is formed in a manner of passing through the interlayer insulating layer 70 and the stacked structure ST. Thereafter, an insulating pattern 71 is formed in the fourth opening OP4. For example, the fourth opening OP4 is formed in a manner of passing through the pad region PR, that is, the pad structure of the stacked structure ST. Each of the fourth openings OP4 has a depth that completely passes through the pad structure and exposes the circuit 61.

[0079] Reference Fig. 9 , the second to fifth slits SL2, SL3A, SL3B, SL4 and SL5 are formed in a manner of passing through the stack structure ST. The second to fourth slits SL2, SL3A, SL3B and SL4 extend in the first direction II-I', and the fifth slit SL5 extends in the second direction II-II'. In addition, the third slit SL3A and the fifth slit SL5 intersect with each other, and the third slit SL3B and the fifth slit SL5 are connected to each other in a C-shape with the first slit SL1.

[0080] The second slits SL2 electrically separate the adjacent memory blocks MB and are arranged on the boundaries between the adjacent memory blocks MB. Each of the second slits SL2 has a depth that completely passes through the stacked layers 41 to 56. The fourth slits SL4 separate the drain selection lines arranged at the same level from each other, and each fourth slit SL4 has a depth that passes through the layers 54 to 56 that are arranged to be used as drain selection lines. The third slits SL3A and SL3B separate the source selection lines arranged at the same level, separate the drain selection lines arranged at the same level, and have a depth that completely passes through the stacked layers 41 to 56. The third slit SL3A is arranged in the center of the memory block and crosses a plurality of fourth openings OP4. In addition, the fifth slit SL5 separates the source selection lines arranged at the same level and has a depth that completely passes through the stacked structures 41 to 56.

[0081] In an embodiment, source selection lines disposed at the same level are separated from each other by first slits SL1, third slits SL3A and SL3B, and fifth slits SL5. Also, drain selection lines disposed at the same level are separated from each other by third slits SL3A and SL3B and fourth slits SL4.

[0082] The second to fifth slits SL2, SL3A, SL3B, SL4, and SL5 may be formed simultaneously. Alternatively, the second to fifth slits SL2, SL3A, SL3B, SL4, and SL5 may be formed using two or more steps. For example, the second slit SL2, the fourth slit SL4, and the fifth slit SL5 are formed, and then the second slit insulating layer, the fourth slit insulating layer, and the fifth slit insulating layer are formed therein. Subsequently, the third slits SL3A and SL3B intersecting the fifth slit SL5 are formed, and then the third slit insulating layer is formed therein.

[0083] In addition, after forming the slit insulating layer configured to serve as a support in the second slit SL2, the fourth slit SL4, and the fifth slit SL5, an additional process using the third slits SL3A and SL3B may be performed. For example, in the case where the first material layer C is a sacrificial layer and the second material layer D is an insulating layer, the first material layer C may be replaced with a conductive layer. In another example, in the case where the first material layer C is a conductive layer and the second material layer D is an insulating layer, the first material layer C may be silicided. In addition, in the case where the first material layer C is a conductive layer and the second material layer D is a sacrificial layer, the first material layer C may be replaced with an insulating layer.

[0084] Fig.10 is a diagram showing an example configuration of a memory system according to an embodiment of the present disclosure.

[0085] Reference Fig.10 , a memory system 1000 according to an embodiment of the present invention includes a memory device 1200 and a controller 1100 .

[0086] The memory device 1200 is used to store data information having various types of data such as text, graphics, and software codes. The memory device 1200 may be a non-volatile memory and includes a reference Figures 1A to 9 The structure described. In addition, the memory device 1200 may include a first unit structure, a second unit structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first unit structure and the second unit structure, and may be electrically connected to the first unit structure and the second unit structure. The pad structure may have a plurality of step structures. The circuit may be disposed below the pad structure. One or more openings may pass through the pad structure and expose the circuit. One or more openings may be disposed between the plurality of step structures. The structure of the memory device 1200 and the method for manufacturing the same are the same as described above, so a detailed description thereof will be omitted.

[0087] The controller 1100 may be coupled to the host and the memory device 1200, and may access the memory device 1200 in response to a request from the host. For example, the controller 1100 may control read, write, remove, and background operations of the memory device 1200.

[0088] The controller 1100 may include a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , a memory interface 1150 , and the like.

[0089] The RAM 1110 may be used as a main memory of the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, etc. For reference, the RAM 1110 may be replaced with a static random access memory (SRAM), a read only memory (ROM), etc.

[0090] The CPU 1120 may control the overall operation of the controller 1100. For example, the CPU 1120 may operate firmware such as a flash translation layer (FTL) stored in the RAM 1110.

[0091] The host interface 1130 can interface with the host. For example, the controller 1100 can communicate with the host through at least one of various interface protocols such as the following: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, dedicated protocols, etc.

[0092] The ECC circuit 1140 may detect and correct errors included in data read from the memory device 1200 using an error correction code (ECC).

[0093] The memory interface 1150 may interface with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface. For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. The buffer memory may be used to temporarily store data to be transmitted from the host interface 1130 to an external device or data to be transmitted from the memory interface 1150 to the memory device 1200. The controller 1100 may further include a ROM for storing code data, which is used to interface with the host.

[0094] Since the memory system 1000 according to the embodiment includes the memory device 1200 having improved integration and characteristics, the memory system 1000 may be miniaturized while having good characteristics.

[0095] Fig.11is a diagram showing an example configuration of a memory system according to an embodiment of the present disclosure. Here, any repeated detailed description will be omitted or simplified.

[0096] Reference Fig.11 , the memory system 1000' according to the embodiment may include a memory device 1200' and a controller 1100. The controller 1100 may include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

[0097] The memory device 1200' may be a non-volatile memory device and may include the memory device 1200' described above with reference to FIG. Figures 1A to 9 The memory string described. In addition, the memory device 1200' may include a first unit structure, a second unit structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first unit structure and the second unit structure, and may be electrically coupled to the first unit structure and the second unit structure. The pad structure may have a plurality of step structures. The circuit may be disposed below the pad structure. One or more openings may pass through the pad structure and expose the circuit. One or more openings may be disposed between the plurality of step structures. The structure of the memory device 1200' and the method for manufacturing the same are the same as described above, so a detailed description thereof will be omitted.

[0098] In addition, the memory device 1200' may be a multi-chip package including a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups. The plurality of groups may communicate with the controller 1100 through the first to k-th channels CH1 to CHk. The memory chips of each group may be adapted to communicate with the controller 1100 through a common channel. The memory system 1000' may be modified so that each single memory chip is connected to a corresponding single channel.

[0099] As described above, according to the embodiment, since the memory system 1000' includes the memory device 1200' having improved integration and characteristics, the memory system 1000' can be miniaturized while having good characteristics. The memory device 1200' can be manufactured in the form of a multi-chip package to increase the data storage capacity of the memory system 1000' and to increase its driving speed.

[0100] Fig.12 is a diagram showing an example configuration of a computing system according to an embodiment of the present disclosure. Here, any repeated detailed description will be omitted or simplified.

[0101] Reference Fig.12 , the computing system 2000 according to an embodiment of the present disclosure may include a memory device 2100 , a CPU 2200 , a RAM 2300 , a user interface 2400 , a power supply 2500 , a system bus 2600 , and the like.

[0102] The memory device 2100 may store data provided via the user interface 2400, data processed by the CPU 2200, and the like. The memory device 2100 may be electrically coupled to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like through the system bus 2600. For example, the memory device 2100 may be coupled to the system bus 2600 via a controller (not shown). Alternatively, the memory device 2100 may be directly connected to the system bus 2600. In the case where the memory device 2100 is directly connected to the system bus 2600, the function of the controller may be performed by the CPU 2200, the RAM 2300, and the like.

[0103] The memory device 2100 may be a nonvolatile memory and includes the memory device 2100 described above. Figures 1A to 9 The memory string described. In addition, the memory device 2100 may include a first unit structure, a second unit structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first unit structure and the second unit structure, and may be electrically coupled to the first unit structure and the second unit structure. The pad structure may have a plurality of step structures. The circuit may be disposed below the pad structure. One or more openings may pass through the pad structure and expose the circuit. One or more openings may be disposed between the plurality of step structures. The structure of the memory device 2100 and the method for manufacturing the same are the same as described above, so a detailed description thereof will be omitted.

[0104] In addition, as mentioned above Fig.11 As described above, the memory device 2100 may be a multi-chip package configured with a plurality of memory chips.

[0105] The computing system 2000 having the above configuration may be provided as one of various elements of electronic devices such as: a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, an RFID device, etc.

[0106] As described above, since the computing system 2000 according to the embodiment includes the memory device 2100 having improved integration and characteristics, the computing system 2000 may be miniaturized while having good characteristics.

[0107] Fig.13 is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0108] Reference Fig.13 The computing system 3000 according to an embodiment of the present disclosure may include a software layer including an operating system 3200 , an application 3100 , a file system 3300 , a translation layer 3400 , etc. The computing system 3000 may include a hardware layer such as a memory device 3500 .

[0109] The operating system 3200 may manage software resources and hardware resources of the computing system 3000 and control program execution of the CPU. The application 3100 may include various application programs executed by the computing system 3000 and may be a utility program executed by the operating system 3200.

[0110] The file system 3300 may refer to a logical structure provided in the computing system 3000 to control data, files, etc. The file system 3300 may organize files or data to be stored in the memory device 3500, etc. according to a given rule. The file system 3300 may be determined according to the operating system 3200 used in the computing system 3000. For example, if the operating system 3200 is a Microsoft Windows-based system, the file system 3300 may be a file allocation table (FAT), an NT file system (NTFS), etc. If the operating system 3200 is a Unix / Linux-based system, the file system 3300 may be an extended file system (EXT), a Unix file system (UFS), a journaled file system (JFS), etc.

[0111] Although the operating system 3200 , the application 3100 , and the file system 3300 are represented as separate blocks in the drawing, the operating system 3200 may include the application 3100 and the file system 3300 .

[0112] The translation layer 3400 may convert the address into a form suitable for the memory device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 may convert the logical address generated by the file system 3300 into the physical address of the memory device 3500. The mapping information of the logical address and the physical address may be stored in the address translation table. For example, the translation layer 3400 may be a flash translation layer (FTL), a universal flash storage link layer (ULL), etc.

[0113] The memory device 3500 may be a non-volatile memory. The memory device 3500 may include the memory device described above. Figures 1A to 9The memory string described. In addition, the memory device 3500 may include a first unit structure, a second unit structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first unit structure and the second unit structure, and may be electrically coupled to the first unit structure and the second unit structure. The pad structure may have a plurality of step structures. The circuit may be disposed below the pad structure. One or more openings may pass through the pad structure and expose the circuit. One or more openings may be disposed between the plurality of step structures. The structure of the memory device 3500 and the method for manufacturing the same are the same as described above, so a detailed description thereof will be omitted.

[0114] The computing system 3000 having the above configuration may be divided into an operating system layer operating in a higher level region and a controller layer operating in a lower level region. The application 3100, the operating system 3200, and the file system 3300 may be included in the operating system layer and driven by an operating memory of the computing system 3000. The conversion layer 3400 may be included in the operating system layer or the controller layer.

[0115] As described above, since the computing system 3000 according to the embodiment includes the memory device 3500 having improved integration and characteristics, the computing system 3000 may be miniaturized while having good characteristics.

[0116] According to the embodiment, the programming speed can be improved by reducing the distance between the circuit and the cell structure. In addition, the integration degree can be improved by reducing the area of ​​the pad region, and the manufacturing process can be simplified.

[0117] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and interpreted in a general and descriptive sense only and not for limiting purposes. In some cases, as at the time of filing this application, it will be apparent to one of ordinary skill in the art that, unless otherwise specified, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as described in the appended claims.

Claims

1. A semiconductor device comprising: The first unit structure; Second unit structure; a pad structure disposed between the first unit structure and the second unit structure and electrically coupled to the first unit structure and the second unit structure, the pad structure having a plurality of step structures; one or more openings passing through the pad structure; A circuit is disposed below the one or more openings of the pad structure, The plurality of stepped structures include: a first stepped structure including first pads stacked on each other, the first pads being electrically coupled to the first unit structure and the second unit structure; a second stepped structure including second pads stacked on each other, the second pads being electrically coupled to the first unit structure and the second unit structure; and The third stepped structure includes third pads stacked on each other, the third pads being electrically coupled to the first unit structure.

2. The semiconductor device according to claim 1, wherein the opening comprises: a first opening disposed between the first stepped structure and the second stepped structure and formed to isolate the first pad and the second pad from each other; as well as The second opening is disposed between the second stepped structure and the third stepped structure and is formed to isolate the second pad and the third pad from each other.

3. The semiconductor device according to claim 1, further comprising: a first interconnect structure electrically coupling the first pad and the third pad to each other and coupling the first pad and the third pad to the circuit through the opening; as well as A second interconnect structure electrically couples the second pads to each other and couples the second pads to the circuit through the opening.

4. The semiconductor device according to claim 1, wherein the pad structure comprises: a first wire structure including first wires stacked on each other, the first wires being electrically coupled to respective first pads; a second wire structure including second wires stacked on each other, the second wires being electrically coupled to respective second pads; as well as a third line structure including third lines stacked on each other, the third lines being electrically coupled to respective third pads, and Among the first to third lines, the first to third lines disposed at the same level are isolated from each other.

5. The semiconductor device according to claim 4, wherein: The first unit structure includes first source selection lines stacked on each other and second source selection lines stacked on each other, and among the first source selection lines and the second source selection lines, the first source selection lines and the second source selection lines disposed at the same level are isolated from each other; as well as The second unit structure includes third source selection lines stacked on each other and fourth source selection lines stacked on each other, and among the third source selection lines and the fourth source selection lines, the third source selection lines and the fourth source selection lines disposed at the same level are isolated from each other.

6. The semiconductor device according to claim 5, wherein: the first lines are electrically coupled to respective first source select lines; Each of the second lines is commonly coupled to a second source selection line and a third source selection line disposed at the same level among the second source selection line and the third source selection line; as well as The third lines are electrically coupled to respective fourth source select lines.

7. The semiconductor device according to claim 1, further comprising: a slit insulating layer extending in one direction to traverse the opening and pass through the pad structure in a stacking direction; a fourth stepped structure facing the first stepped structure so that the slit insulating layer is disposed between the first stepped structure and the fourth stepped structure, the fourth stepped structure including fourth pads stacked on each other, the fourth pads being electrically coupled to the first unit structure; a fifth stepped structure facing the second stepped structure so that the slit insulating layer is disposed between the second stepped structure and the fifth stepped structure, the fifth stepped structure including fifth pads stacked on each other, the fifth pads being electrically coupled to the first unit structure and the second unit structure; as well as A sixth stepped structure faces the third stepped structure so that the slit insulation layer is disposed between the third stepped structure and the sixth stepped structure, the sixth stepped structure includes sixth pads stacked on each other, the sixth pads being electrically coupled to the second unit structure.

8. The semiconductor device according to claim 7, wherein the opening comprises: a first opening disposed between the first and fourth stepped structures and the second and fifth stepped structures and formed to isolate the first and fourth pads from the second and fifth pads; as well as The second opening is disposed between the second and fifth stepped structures and the third and sixth stepped structures and is formed to isolate the second and fifth pads from the third and sixth pads.

9. The semiconductor device according to claim 7, further comprising: a first interconnect structure electrically coupling the first pad and the third pad to each other and coupling the first pad and the third pad to the circuit through the opening; a second interconnect structure electrically coupling the second pads to each other and to the circuit through the opening; a third interconnect structure configured to electrically couple the fourth pad and the sixth pad to each other and to couple the fourth pad and the sixth pad to the circuit through the opening; as well as A fourth interconnect structure is configured to electrically couple the fifth pads to each other and to couple the fifth pads to the circuit through the opening.

10. The semiconductor device according to claim 7, wherein the pad structure comprises: a first wire structure including first wires stacked on each other, the first wires being electrically coupled to respective first pads; a second wire structure including second wires stacked on each other, the second wires being electrically coupled to respective second pads; a third wire structure including third wires stacked on each other, the third wires being electrically coupled to respective third pads; a fourth line structure comprising fourth lines stacked on each other, the fourth lines being electrically coupled to respective fourth pads; a fifth wire structure including fifth wires stacked on each other, the fifth wires being electrically coupled to respective fifth pads; as well as a sixth wire structure comprising sixth wires stacked on each other, the sixth wires being electrically coupled to respective sixth pads; Among the first to sixth lines, the first to sixth lines disposed at the same level are isolated from each other.

11. The semiconductor device according to claim 10, wherein: The first unit structure includes first to fourth source selection lines isolated from each other, and the second unit structure includes fifth to eighth source selection lines isolated from each other; the first lines are electrically coupled to respective second source select lines; Each of the second lines is commonly coupled to a first source selection line and a fifth source selection line disposed at the same level among the first source selection line and the fifth source selection line; The third lines are electrically coupled to respective sixth source select lines; The fourth lines are electrically coupled to respective third source select lines; Each of the fifth lines is commonly coupled to a fourth source selection line and an eighth source selection line disposed at the same level among the fourth source selection line and the eighth source selection line; and The sixth lines are electrically coupled to respective seventh source select lines. 12 . The semiconductor device according to claim 1 , wherein the first stepped structure is symmetrical to the second stepped structure, and the second stepped structure is symmetrical to the third stepped structure. 13 . The semiconductor device according to claim 1 , wherein the one or more openings are disposed between the plurality of stepped structures.

14. A semiconductor device comprising: A substrate, comprising a first unit region, a second unit region, and a pad region between the first unit region and the second unit region; a circuit on the substrate; A first unit structure formed above the first unit region, the first unit structure comprising a first source selection line; a second unit structure formed above the second unit region, the second unit structure comprising a second source selection line; as well as a pad structure formed above the pad region, wherein the pad structure comprises a first stepped structure, a line structure, and an opening exposing the circuit, the first stepped structure comprising first pads stacked on each other, and the line structure comprising first lines stacked on each other; The first source selection line and the second source selection line are electrically coupled to each other through a first line located at the same level, and the first line commonly couples the first source selection line and the second source selection line to the first pad.

15. The semiconductor device according to claim 14, further comprising: A first interconnect structure electrically couples the first pad to the circuit through the opening so that the first source select line and the second source select line are electrically coupled to the circuit in common. 16 . The semiconductor device according to claim 14 , wherein the pad structure comprises a second stepped structure comprising second pads stacked on each other and a third stepped structure comprising third pads stacked on each other. 17 . The semiconductor device of claim 16 , further comprising a second interconnect structure electrically coupling the second pad to the third pad and electrically coupling the second pad and the third pad to the circuit through the opening.

18. A method for manufacturing a semiconductor device, comprising: forming a circuit on a pad region of a substrate, the substrate comprising a first unit region, the pad region, and a second unit region arranged continuously in a first direction; forming a stack structure over the substrate having the circuit formed thereon, the stack structure comprising a first group to an nth group stacked on each other, wherein n is a natural number greater than or equal to 3; Partially patterning the pad region of the stacked structure, and forming a first unit structure disposed in the first unit region, a second unit structure disposed in the second unit region, and a pad structure disposed in the pad region, wherein the pad structure is disposed between the first unit structure and the second unit structure and is electrically coupled to the first unit structure and the second unit structure in common, and the pad structure includes a plurality of step structures; as well as forming one or more openings through the pad structure, The forming of the pad structure includes partially patterning the first to (n-1)th groups of stacked structures and forming a third stepped structure arranged between the openings, the third stepped structure including third pads stacked on each other, and the third pads are commonly connected to the second to (n-1)th groups of first unit structures and the second to (n-1)th groups of second unit structures.

19. The method according to claim 18, wherein forming the stacked structure comprises: forming the first group, the first group including first material layers and second material layers alternately stacked on each other; forming a first slit insulating layer, the first slit insulating layer passing through the first group in the pad region and extending in the first direction; and Second to n-th groups are formed over the first group, each of the second to n-th groups including first material layers and second material layers alternately stacked with each other.

20. The method according to claim 19 further includes, after forming the pad structure, forming a second slit insulation layer, the second slit insulation layer passing through the first group to the nth group in the pad area and extending in a second direction intersecting the first direction, the second slit insulation layer being connected to the first slit insulation layer.

21. The method according to claim 18, wherein forming the pad structure comprises partially patterning the nth group of stacked structures and forming a first stepped structure and a second stepped structure, and wherein: The first stepped structure includes first pads stacked on each other, the first pads contacting the first unit structures and electrically coupled to the nth group of first unit structures; as well as The second stepped structure includes second pads stacked on each other, the second pads contacting the second unit structures and electrically coupled to the n-th group of second unit structures.

22. The method of claim 21, further comprising forming a first interconnect structure electrically coupling the first pad to the second pad.

23. The method of claim 18, further comprising: forming a slit insulating layer extending in the first direction to traverse the third stepped structure so that the third pads of the third stepped structure are separated by the slit insulating layer; and A second interconnect structure is formed that electrically couples third pads disposed at the same level among the third pads of the third step structure separated by the slit insulating layer.

24. The method according to claim 18, wherein forming the pad structure comprises: The first to (n-1)th stacking structures are partially patterned to form a fourth stepped structure, a fifth stepped structure, and a sixth stepped structure, wherein the fourth stepped structure includes fourth pads stacked on each other and electrically connected to the first group of first unit structures, the fifth stepped structure includes fifth pads stacked on each other and electrically connected to the first group of first unit structures and the first group of second unit structures, and the sixth stepped structure includes sixth pads stacked on each other and electrically connected to the first group of second unit structures.

25. The method according to claim 24, further comprising: forming a third interconnect structure that electrically couples the fourth pad to the sixth pad and couples the fourth pad and the sixth pad to the circuit through the opening; and A fourth interconnect structure is formed, the fourth interconnect structure coupling the fifth pad to the circuit through the opening.

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