semiconductor devices

Abstract

A semiconductor device is provided, the semiconductor device comprising: an active pattern on a substrate, the active pattern including a recess having a "V" shape; a growth stop pattern on the recess; a gate structure on a portion of the active pattern on opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each channel extending through one of the gate structures; and a source / drain layer on the growth stop pattern, the source / drain layer contacting the channels.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0057955, filed on May 17, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to semiconductor devices. More specifically, exemplary embodiments of the present invention relate to semiconductor devices having channels stacked in a vertical direction. Background Technology

[0004] In fabricating a multi-bridge channel metal-oxide-semiconductor field-effect transistor (MBC MOSFET) that includes multiple channels stacked in a vertical direction, source / drain layers can be formed to commonly contact these channels. The source / drain layers can comprise multiple layers with different impurity concentrations. If the impurity concentrations of the source / drain layers near the channels are not properly controlled, the channels may exhibit inconsistent electrical characteristics. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: an active pattern on a substrate, the active pattern including a recess having a "V" shape; a growth stop pattern on the recess; a gate structure on a portion of the active pattern on opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each channel extending through one of the gate structures; and a source / drain layer on the growth stop pattern, the source / drain layer contacting the channels.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: an active pattern on a substrate; channels spaced apart from each other in a first direction perpendicular to a surface of the substrate; a gate structure on the active pattern, the gate structure surrounding at least a portion of the surface of each of the channels; and a source / drain layer located on portions of the active pattern on each side of the gate structure and contacting the channels, the source / drain layer comprising a semiconductor material doped with impurities, and the source / drain layer comprising: a first epitaxial layer on a sidewall of each of the channels, the first epitaxial layer having a first impurity concentration; and a second epitaxial layer on the active pattern, the second epitaxial layer surrounding the first epitaxial layer and having a second impurity concentration greater than the first impurity concentration, wherein a growth preventer pattern is formed between the active pattern and the source / drain layer.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: an active pattern on a substrate; a gate structure on the active pattern; channels spaced apart from each other in a direction perpendicular to an upper surface of the substrate, each channel disposed in the gate structure; a barrier layer on a portion of the active pattern on each side of an opposite side of the gate structure; a source / drain layer on the barrier layer, the source / drain layer being connected to the channel; a spacer on a sidewall of a first portion of the gate structure and on a sidewall of a second portion of the gate structure, the first portion being located between the channels, the second portion being located between the upper surface of the active pattern and the lowermost channel of the channels; and an air gap between the spacer and the source / drain layer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: an active pattern on a substrate, the active pattern including a groove on an upper surface of the active pattern; gate structures on a first portion and a second portion of the active pattern, the first portion being located on a first side of the groove and the second portion being located on a second side of the groove; channels spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, each channel extending through one of the gate structures; and a source / drain layer on the active pattern, the source / drain layer being connected to the channels and comprising a semiconductor material doped with impurities, wherein the impurity concentration of the source / drain layer between the channels at the same horizontal height is different from a first sidewall of a first channel in the channels to a second sidewall of a second channel in the channels facing the first sidewall of the first channel, the impurity concentration having a first impurity concentration, a second impurity concentration, and a third impurity concentration in order from the first sidewall to the second sidewall.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device including a first transistor and a second transistor, the first transistor including: a first active pattern located on a first region of a substrate, the first active pattern including a first groove located on an upper surface of the first active pattern, and the substrate including the first region and a second region; a first gate structure located on a portion of the first active pattern opposite to the first groove; first channels spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, each of the first channels extending through one of the first gate structures; and a first source / source located on the first groove of the first active pattern. The first source / drain layer is connected to the first channel; the second transistor includes: a second active pattern located on a second region of the substrate, the second active pattern including a second groove located on an upper surface of the second active pattern, the second groove having a "V" shape; a growth stop pattern located on the second groove of the second active pattern; a second gate structure located on a portion of the second active pattern on opposite sides of the second groove; second channels spaced apart from each other in the vertical direction, each second channel extending through one of the second gate structures; and a second source / drain layer located on the growth stop pattern, the second source / drain layer being connected to the second channel.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first channel located on a first region of a substrate, the first channel being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, the substrate including the first region and a second region; a first gate structure located on the first region of the substrate, the first gate structure being disposed adjacent to at least a portion of the surface of each of the first channels; a first source / drain layer located on a portion of each of opposite sides of the first gate structure of the substrate, the first source / drain layer being connected to the first channel and including a first epitaxial layer and a second epitaxial layer, the first epitaxial layer extending along the vertical direction on a sidewall of the first channel, the first epitaxial layer having a first impurity concentration, and the second epitaxial layer located on a surface of the first epitaxial layer. The second epitaxial layer has a second impurity concentration greater than the first impurity concentration; a second channel located on the second region of the substrate, the second channels being spaced apart from each other in the vertical direction; a second gate structure located on the second region of the substrate, the second gate structure being configured to be adjacent to at least a portion of the surface in each of the second channels; a second source / drain layer located on a portion of the substrate on each side of the opposite side of the second gate structure, the second source / drain layer being connected to the second channel and including a third epitaxial layer and a fourth epitaxial layer, the third epitaxial layer extending along the vertical direction on the sidewall of each of the second channels, the third epitaxial layer having a third impurity concentration, and the fourth epitaxial layer located on the surface of the third epitaxial layer, the fourth epitaxial layer having a fourth impurity concentration greater than the third impurity concentration. Attached Figure Description

[0011] Figure 1 , Figure 2 and Figure 3 These are top views and cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention.

[0012] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 These are top views and cross-sectional views illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention;

[0013] Figure 19 This is a cross-sectional view illustrating a semiconductor device according to a comparative embodiment;

[0014] Figure 20 , Figure 21 and Figure 22 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative embodiment;

[0015] Figure 23 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention;

[0016] Figure 24 and Figure 25 This is a cross-sectional view illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention;

[0017] Figure 26 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention;

[0018] Figure 27 and Figure 28 This is a cross-sectional view illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention;

[0019] Figure 29 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention;

[0020] Figure 30 and Figure 31 This is a cross-sectional view illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention;

[0021] Figure 32 , Figure 33 , Figure 34 and Figure 35 These are top views and cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention.

[0022] Figure 36 , Figure 37 , Figure 38 , Figure 39 , Figure 40 , Figure 41 , Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 , Figure 47 , Figure 48 , Figure 49 and Figure 50 These are top views and cross-sectional views illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention; and

[0023] Figure 51 This is a cross-sectional view illustrating an exemplary semiconductor device according to the concept of the present invention. Detailed Implementation

[0024] Figures 1 to 3 These are top views and cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention. Figure 1 It is a top view. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B'.

[0025] In the following text, two directions that are substantially parallel to and intersect each other with the upper surface of the substrate 100 may be referred to as the first direction and the second direction, respectively, and a direction that is substantially perpendicular to the upper surface of the substrate 100 may be referred to as the third direction. In an exemplary embodiment of the inventive concept, the first direction and the second direction may be substantially perpendicular to each other.

[0026] Reference Figures 1 to 3 The semiconductor device may include an active pattern 105, a growth barrier pattern 225, a gate structure 330, a semiconductor pattern 124, and a source / drain layer 250 on a substrate 100. The semiconductor device may also include a gate spacer 185, an inner spacer 220, an isolation pattern 130, and an insulating layer 270.

[0027] The substrate 100 may contain semiconductor materials such as silicon, germanium, silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, and GaSb.

[0028] An active pattern 105 may protrude from the substrate 100 along a third direction and may extend in a first direction. Two active patterns 105 are shown in the figures; however, the inventive concept is not limited to this. Therefore, more than two active patterns 105 may be spaced apart from each other in a second direction. The active pattern 105 may be formed by partially removing the upper portion of the substrate 100, and thus, the active pattern 105 may contain a material substantially the same as that of the substrate 100.

[0029] The sidewalls of the active pattern 105 can be covered by the isolation pattern 130. The isolation pattern 130 may contain oxides, such as silicon oxide.

[0030] The first groove 195 can be formed on the upper surface of the active pattern 105 to have a "V" shaped cross section in the first direction.

[0031] In an exemplary embodiment of the present invention, a growth stop pattern 225 may be formed on the first groove 195. The portion of the growth stop pattern 225 located at the center of the first groove 195 in a first direction may have the greatest thickness, and the portions of the growth stop pattern 225 located at each of the opposite edges of the first groove 195 in the first direction may have the least thickness. In other words, the growth stop pattern 225 located at the center of the first groove 195 may be thicker than the growth stop patterns 225 located at the opposite edges of the first groove 195 in the first direction. In an exemplary embodiment of the present invention, the growth stop pattern 225 may completely cover the upper surface of the active pattern 105 exposed by the first groove 195. The growth stop pattern 225 may comprise a nitride, such as silicon nitride.

[0032] Multiple semiconductor patterns 124 can be formed at multiple horizontal heights, spaced apart from each other in a third direction from the upper surface of the active pattern 105. The figures show semiconductor patterns 124 located at three different horizontal heights; however, the inventive concept is not limited to this.

[0033] In the figure, only two semiconductor patterns 124 spaced apart from each other in the first direction are shown at each horizontal height on the active pattern 105 extending along the first direction. However, the inventive concept is not limited to this. For example, more than two semiconductor patterns 124 may be spaced apart from each other in the first direction at each horizontal height on the active pattern 105.

[0034] In an exemplary embodiment of the present invention, the semiconductor pattern 124 may be a nanosheet or nanowire comprising a semiconductor material (e.g., silicon, germanium, etc.). In an exemplary embodiment of the present invention, the semiconductor pattern 124 may be used as a channel for a transistor. In this case, the semiconductor pattern 124 may be referred to as a channel.

[0035] The gate structure 330 may be formed on the substrate 100 and may surround the central portion of the semiconductor pattern 124 in a first direction. In the figures, the gate structure 330 is shown as covering the semiconductor pattern 124 on two active patterns 105; however, the inventive concept is not limited thereto. In other words, the gate structure 330 may extend along a second direction on the substrate 100 having an isolation pattern 130 thereon and may cover the semiconductor patterns 124 on more than two active patterns 105 spaced apart from each other in the second direction.

[0036] In the figure, two gate structures 330 are shown on the substrate 100; however, the inventive concept is not limited thereto. For example, more than two gate structures 330 spaced apart from each other in the first direction may be formed on the substrate 100.

[0037] In an exemplary embodiment of the present invention, the gate structure 330 may be formed on a portion of the active pattern 105 located on each side of the first recess 195 on opposite sides in a first direction.

[0038] The gate structure 330 may include an interface pattern 290, a gate insulating pattern 300, a work function control pattern 310, and a gate electrode 320, which are sequentially stacked from the surface of each semiconductor pattern 124 or the upper surface of the active pattern 105.

[0039] Interface pattern 290 can be formed on the upper surface of active pattern 105 and the surface of semiconductor pattern 124, and gate insulating pattern 300 can be formed on the surface of interface pattern 290 and on the inner sidewalls of gate spacer 185 and inner spacer 220. Work function control pattern 310 can be formed on gate insulating pattern 300. Gate electrode 320 can fill the space between semiconductor patterns 124 spaced apart in a third direction and between inner spacers 220 spaced apart in a first direction. Gate electrode 320 can also fill the space between gate spacers 185 spaced apart in a first direction on the uppermost semiconductor pattern 124.

[0040] Interface pattern 290 may contain oxides, such as silicon oxide, and gate insulating pattern 300 may contain metal oxides with a high k dielectric constant, such as hafnium oxide, tantalum oxide, zirconium oxide, etc. Work function control pattern 310 may contain, for example, titanium nitride, tantalum nitride, tungsten nitride, aluminum oxide, etc. Gate electrode 320 may contain metals (e.g., titanium, aluminum, etc.), metal alloys, or metal nitrides or carbides.

[0041] The gate structure 330 can be electrically insulated from the source / drain layer 250 by the gate spacer 185 and the inner spacer 220.

[0042] Gate spacer 185 may cover each sidewall of the upper portion of gate structure 330 in the first direction. Inner spacer 220 may cover each sidewall of the lower portion of gate structure 330 in the first direction. In an exemplary embodiment of the inventive concept, the cross-section of inner spacer 220 along the first direction may be a horseshoe shape or a semicircle with recesses on its outer sidewall. Alternatively, the cross-section of inner spacer 220 along the first direction may be a rounded rectangle with recesses on its outer sidewall.

[0043] The gate spacer 185 may contain nitrides, such as silicon oxynitride, silicon carbon oxynitride, etc., and the inner spacer 220 may contain nitrides, such as silicon nitride.

[0044] In an exemplary embodiment of the present invention, the inner spacer 220 may comprise substantially the same material as the growth stop pattern 225. In an exemplary embodiment of the present invention, the lowermost inner spacer 220 may contact and connect to the growth stop pattern 225.

[0045] The source / drain layer 250 may extend along a third direction on the growth stop pattern 225 and may collectively contact and connect with the respective sidewalls of the semiconductor pattern 124 in the first direction at multiple horizontal heights.

[0046] The source / drain layer 250 may include a first epitaxial layer 230 and a second epitaxial layer 240. In an exemplary embodiment of the present invention, each first epitaxial layer 230 may protrude from the sidewall of each semiconductor pattern 124 along a first direction, and the cross-section along the first direction may, for example, have a candle shape or an ellipse shape. In an exemplary embodiment of the present invention, the second epitaxial layer 240 may extend from the growth stop pattern 225 along a third third direction to contact the lower sidewall of the gate spacer 185.

[0047] In an exemplary embodiment of the present invention, each of the first epitaxial layer 230 and the second epitaxial layer 240 may comprise single-crystal silicon carbide or single-crystal silicon doped with n-type impurities. The first epitaxial layer 230 and the second epitaxial layer 240 may each have a first impurity concentration and a second impurity concentration, and the second impurity concentration may be greater than the first impurity concentration.

[0048] In an exemplary embodiment of the present invention, the first epitaxial layer 230, the second epitaxial layer 240, and the first epitaxial layer 230 may be sequentially arranged in the source / drain layer 250 between adjacent semiconductor patterns 124 located at the same horizontal height along a first direction. In this case, the source / drain layer 250 may have a varying impurity concentration in the first direction, for example, a first impurity concentration, a second impurity concentration, and a third impurity concentration in the first direction.

[0049] In an exemplary embodiment of the present invention, due to the crystallinity of the second epitaxial layer 240, a first air gap 260 may be formed between the source / drain layer 250 and the growth barrier pattern 225, and a second air gap 265 may be formed between the source / drain layer 250 and the inner spacer 220.

[0050] Since the source / drain layer 250 contains n-type impurities, the gate structure 330, the source / drain layer 250, and each semiconductor pattern 124 used as a channel can form an n-type metal-oxide-semiconductor (NMOS) transistor. Multiple semiconductor patterns 124 can be stacked sequentially in third-order upwards, so the semiconductor device can be a multi-bridge channel metal-oxide-semiconductor field-effect transistor (MBC MOSFET).

[0051] The insulating layer 270 may surround the outer wall of the gate spacer 185 to cover the source / drain layer 250. The insulating layer 270 may contain an oxide, such as silicon oxide.

[0052] The semiconductor device may also include contact plugs, wiring, etc., electrically connected to the source / drain layer 250 and / or gate structure 330.

[0053] As described above, in a semiconductor device, between channels located at the same horizontal height, the source / drain layer 250 may include not only a first epitaxial layer 230 with a relatively low impurity concentration, but also a second epitaxial layer 240 with a relatively high impurity concentration. Therefore, the performance of the transistor including the channel is not degraded due to the impurity concentration of the source / drain layer 250. This will be explained in more detail later.

[0054] Additionally, a growth barrier pattern 225 containing insulating material can be formed between the source / drain layer 250 and the active pattern 105, thereby preventing leakage current from the source / drain layer 250 to the active pattern 105.

[0055] Figures 4 to 18 These are top views and cross-sectional views illustrating an exemplary method for manufacturing a semiconductor device according to a concept conceived in this invention. Figure 4 , Figure 8 , Figure 11 and Figure 16 It is a top view. Figures 5 to 7 , Figures 9 to 10 , Figures 12 to 15 and Figures 17 to 18 It is a cross-sectional view.

[0056] Figure 5 , Figure 7 and Figure 9 It is a cross-sectional view taken along line A-A' of the corresponding top view, and Figure 10 , Figures 12 to 15 and Figures 17 to 18 It is a cross-sectional view taken along line B-B' of the corresponding top view.

[0057] Reference Figure 4 and Figure 5 The sacrificial layer 110 and the semiconductor layer 120 can be stacked alternately and repeatedly on the substrate 100.

[0058] In the figure, three sacrificial layers 110 and three semiconductor layers 120 are stacked on the substrate 100; however, the inventive concept is not limited to this.

[0059] The sacrificial layer 110 may contain a material that is etch-selective relative to the substrate 100 and the semiconductor layer 120. For example, the sacrificial layer 110 may contain, for example, silicon germanium.

[0060] Reference Figure 6 and Figure 7 An etching mask extending in a first direction can be formed on the uppermost semiconductor layer 120, and the etching mask can be used to etch the semiconductor layer 120, the sacrificial layer 110, and the upper part of the substrate 100.

[0061] Therefore, an active pattern 105 extending in a first direction can be formed on the substrate 100, and a fin structure including alternating and repeatedly stacked sacrificial lines 112 and semiconductor lines 122 can be formed on the active pattern 105. In an exemplary embodiment of the present invention, a plurality of fin structures spaced apart from each other in a second direction can be formed on the substrate 100.

[0062] An isolation pattern 130 can be formed on the substrate 100 to cover the sidewalls of the active pattern 105.

[0063] Reference Figures 8 to 10 A dummy gate structure 175 can be formed on the substrate 100 to partially cover the fin structure and the isolation pattern 130.

[0064] For example, a dummy gate insulating layer, a dummy gate electrode layer, and a dummy gate mask layer may be sequentially formed on a substrate 100 having a fin structure and an isolation pattern 130 thereon; an etch mask may be formed on the dummy gate mask layer; and the dummy gate mask layer may be etched using the etch mask to form a dummy gate mask 165.

[0065] The dummy gate insulating layer may contain oxides, such as silicon oxide; the dummy gate electrode layer may contain, for example, polysilicon; and the dummy gate mask layer may contain nitrides, such as silicon nitride.

[0066] The dummy gate mask 165 can be used as an etching mask to etch the dummy gate electrode layer and the dummy gate insulating layer to form the dummy gate electrode 155 and the dummy gate insulating pattern 145 on the substrate 100, respectively.

[0067] A dummy gate insulating pattern 145, a dummy gate electrode 155, and a dummy gate mask 165, sequentially stacked on the portion of the active pattern 105 adjacent to the isolation pattern 130, can form a dummy gate structure 175. In an exemplary embodiment of the present invention, the dummy gate structure 175 may extend along a second direction over the fin structure and the isolation pattern 130 to cover the upper surface of the fin structure and the opposite sidewalls in the second direction.

[0068] Reference Figure 11 and Figure 12 Gate spacers 185 can be formed on the sidewall of the dummy gate structure 175.

[0069] For example, a first spacer layer may be formed on a substrate 100 having a fin structure, an isolation pattern 130 and a dummy gate structure 175 thereon, and the first spacer layer may be anisotropically etched to form gate spacers 185 covering each of the sidewalls of the dummy gate structure 175 in the opposite sidewalls in the first direction.

[0070] The fin structure can be etched using the dummy gate structure 175 and the gate spacer 185 as an etching mask to form a first opening 190 that exposes the upper part of the active pattern 105 and the portion of the isolation pattern 130 adjacent to the active pattern 105 in the second direction. The exposed upper part of the active pattern 105 can also be etched to form a first groove 195 connected to the first opening 190.

[0071] Therefore, the sacrificial line 112 and semiconductor line 122 below the dummy gate structure 175 and the gate spacer 185 can be transformed into sacrificial pattern 114 and semiconductor pattern 124, respectively, and the fin structure extending along the first direction can be divided into multiple parts spaced apart from each other in the first direction.

[0072] In the following text, the dummy gate structure 175, the gate spacers 185 on each opposite sidewall of the dummy gate structure 175, and the fin-shaped structure below the dummy gate structure 175 and the gate spacers 185 may be referred to as the first structure. In an exemplary embodiment of the inventive concept, the first structure may extend along a second direction and may be formed as a plurality of first structures spaced apart from each other in a first direction.

[0073] In an exemplary embodiment of the present invention, the cross-section of the first groove 195 along the first direction may have a "V" shape.

[0074] Reference Figure 13 The opposing sidewalls of the sacrificial pattern 114 exposed by the first opening 190 in the first direction can be etched to form the second grooves 200 respectively.

[0075] In an exemplary embodiment of the present invention, the second groove 200 can be formed by performing a wet etching process on the sacrificial pattern 114. Therefore, each second groove 200 can have a convex shape facing the center portion of each sacrificial pattern 114 in a first direction. In an exemplary embodiment of the present invention, the cross-section of each second groove 200 along the first direction can be semi-circular. Alternatively, the cross-section of each second groove 200 along the first direction can be a rounded rectangle.

[0076] A second spacer layer 210 can be formed on the dummy gate structure 175, gate spacer 185, fin structure, active pattern 105, and isolation pattern 130 to fill the first groove 195 and the second groove 200.

[0077] In an exemplary embodiment of the present invention, the cross-section of the first groove 195 may be "V" shaped, therefore, the portion of the second spacer layer 210 located on the central portion of the first groove 195 in the first direction may have a relatively large thickness. For example, the portion of the second spacer layer 210 located on the central portion of the first groove 195 in the first direction may be thicker than the portion of the second spacer layer 210 located on the side portion of the first groove 195 in the first direction.

[0078] Reference Figure 14 The second spacer layer 210 can be etched anisotropically to form an inner spacer 220 that at least partially fills each second groove 200, and a third groove 205 can be formed on the outer wall of the inner spacer 220. The third groove 205 may be concave in the first direction.

[0079] During the anisotropic etching process, the portion of the second spacer layer 210 located in the first groove 195 having a “V” cross-section may not be completely removed. In this case, the remaining portion of the second spacer layer 210 may be referred to hereinafter as the growth stop pattern 225.

[0080] The portion of the growth-stopping pattern 225 located at the center of the first groove 195 in the first direction can have the greatest thickness, and the portion of the growth-stopping pattern 225 located at each opposite edge of the first groove 195 in the first direction can have the least thickness.

[0081] In an exemplary embodiment of the present invention, the growth-blocking pattern 225 can completely cover the upper surface of the active pattern 105 exposed by the first groove 195, and thus can be connected to the inner spacer 220.

[0082] Reference Figure 15 The first selective epitaxial growth (SEG) process can be performed using the sidewalls of the semiconductor pattern 124 exposed by the first opening 190 as seed crystals to form a first epitaxial layer 230 on each sidewall of the semiconductor pattern 124.

[0083] Prior to the first SEG process, a growth barrier pattern 225 is formed on the upper surface of the active pattern 105, and an inner spacer 220 is formed on each sidewall of the sacrificial pattern 114. Therefore, during the first SEG process, the active pattern 105 and the sacrificial pattern 114 are not used as seed crystals.

[0084] A first SEG process can be performed using a silicon source gas (e.g., silane (Si₂H₆)), a carbon source gas (e.g., SiH₃CH₃), and an n-type impurity source gas (e.g., POCl₃, P₂O₅, etc.) to form a single-crystal silicon carbide (SiC) layer doped with n-type impurities. Alternatively, a first SEG process can be performed using both a silicon source gas and an n-type impurity source gas to form a single-crystal silicon layer doped with n-type impurities. The first epitaxial layer 230 may have a first impurity concentration.

[0085] In an exemplary embodiment of the present invention, the first epitaxial layer 230 may protrude from each opposite sidewall of the semiconductor pattern 124 in a first direction, and the cross section of the first epitaxial layer 230 along the first direction may have, for example, a candle shape or an ellipse shape.

[0086] Reference Figure 16 and Figure 17 A second SEG process can be performed to form a second epitaxial layer 240.

[0087] A second SEG process can be performed using silicon source gas, carbon source gas, and n-type impurity source gas, or using silicon source / drain gas and n-type impurity source gas, to form a single-crystal silicon carbide layer doped with n-type impurities or a single-crystal silicon layer doped with n-type impurities. The second epitaxial layer 240 can have a second impurity concentration greater than the first impurity concentration.

[0088] In an exemplary embodiment of the present invention, the second epitaxial layer 240 may fill the first opening 190 on the growth stop pattern 225 and may be further grown along a third direction to contact the lower sidewall of the gate spacer 185.

[0089] In an exemplary embodiment of the present invention, due to the crystallinity of the second epitaxial layer 240, the second epitaxial layer 240 may not completely fill the first groove 195 on the growth stop pattern 225, thus a first air gap 260 can be formed on the growth stop pattern 225. In an exemplary embodiment of the present invention, due to the crystallinity of the second epitaxial layer 240, the second epitaxial layer 240 may not completely fill the third groove 205 on the outer wall of the inner spacer 220, thus a second air gap 265 can be formed on the outer wall of the inner spacer 220.

[0090] The first epitaxial layer 230 and the second epitaxial layer 240 formed by the above process can form the source / drain layer 250.

[0091] Reference Figure 18An insulating layer 270 can be formed on the substrate 100 to cover the first structure and the source / drain layer 250, and the insulating layer 270 can be planarized until the upper surface of the dummy gate electrode 155 of the first structure is exposed. During the planarization process, the dummy gate mask 165 can also be removed, and the upper part of the gate spacer 185 can also be removed.

[0092] Planarization can be performed using chemical mechanical polishing (CMP) and / or etching back processes.

[0093] The exposed dummy gate electrode 155 and the dummy gate insulating pattern 145 and sacrificial pattern 114 below it can be removed by, for example, wet etching and / or dry etching processes to form a second opening 280 on the inner sidewall of the exposed gate spacer 185, the inner sidewall of the inner spacer 220, the surface of the semiconductor pattern 124 and the upper surface of the active pattern 105.

[0094] Refer again Figures 1 to 3 A gate structure 330 can be formed on the substrate 100 to fill the second opening 280.

[0095] For example, after performing a thermal oxidation process on the upper surface of the active pattern 105 exposed by the second opening 280 and the surface of the semiconductor pattern 124 to form an interface pattern 290, a gate insulating layer and a work function control layer can be sequentially formed on the surface of the interface pattern 290, the inner sidewalls of the gate spacer 185 and the inner spacer 220, and the upper surface of the insulating layer 270. Additionally, a gate electrode layer can be formed to fill the remaining portion of the second opening 280.

[0096] The gate insulating layer, work function control layer, and gate electrode layer can be formed using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). The interface pattern 290 can also be formed using CVD, ALD, or PVD processes instead of thermal oxidation. In this case, the interface pattern 290 can also be formed on the inner sidewalls of the gate spacer 185 and the inner spacer 220.

[0097] The gate electrode layer, work function control layer, and gate insulating layer can be planarized until the upper surface of the insulating layer 270 is exposed to form the gate electrode 320, work function control pattern 310, and gate insulating pattern 300, respectively. The interface pattern 290, gate insulating pattern 300, work function control pattern 310, and gate electrode 320 can form the gate structure 330.

[0098] Semiconductor devices according to exemplary embodiments of the present invention can be manufactured using the above-described process.

[0099] Figure 19This illustrates a cross-sectional view of a semiconductor device according to a comparative embodiment, for example, along... Figure 1 A cross-sectional view taken along line B-B'. Aside from some components, this semiconductor device can be used with... Figures 1 to 3 The semiconductor devices are similar. Therefore, the same reference numerals can refer to the same elements, and repeated descriptions can be omitted.

[0100] Reference Figure 19 Instead of the first groove 195 with a "V" shaped cross section, a fourth groove 197 with a shallow curved shape can be formed on the active pattern 105. Alternatively, a growth barrier pattern 225 may not be formed on the active pattern 105.

[0101] In addition to the first epitaxial layer 230 and the second epitaxial layer 240, the source / drain layer 250 may also include a third epitaxial layer 233. The third epitaxial layer 233 may be grown from the upper surface of the active pattern 105 exposed by the fourth groove 197 along a third direction, and may have an uppermost surface higher than the bottom surface of the lowermost semiconductor pattern 124. In some cases, the third epitaxial layer 233 is fused with the lowermost semiconductor pattern 124.

[0102] The third epitaxial layer 233 can have a relatively low first impurity concentration, similar to that of the first epitaxial layer 230. Therefore, between the lowermost semiconductor patterns 124 adjacent to each other along the first direction, the lower portion of the source / drain layer 250 can have only the first impurity concentration; thus, a transistor including one of the semiconductor patterns 124 may have degraded performance. However, according to reference... Figures 1 to 3 In the semiconductor device of the exemplary embodiment of the present invention shown, the source / drain layer 250 may include portions with a relatively high second impurity concentration located between semiconductor patterns 124 at each horizontal height, thereby preventing transistor performance degradation.

[0103] Figures 20 to 22 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a comparative embodiment, for example, a cross-sectional view taken along line B-B' of a respective top view. The method may include reference to... Figures 4 to 18 and Figures 1 to 3 The process shown is similar to the process described above, therefore, repeated descriptions can be omitted.

[0104] Reference Figure 20 It can be executed and referenced. Figures 4 to 13 The process shown is similar to that of the process described.

[0105] However, a fourth groove 197 with a shallowly curved shape can be formed on the active pattern 105 instead of the first groove 195 with a "V" shaped cross section in the first direction. Therefore, a second spacer layer 210 can be conformally formed on the fourth groove 197.

[0106] Reference Figure 21 It can be executed and referenced. Figure 14 The process shown is similar to that of the process described above. However, the second spacer layer 210 may not be retained on the fourth groove 197, and therefore, a growth inhibitor pattern may not be formed.

[0107] Reference Figure 22 It can be executed and referenced. Figure 15 The process shown is similar to that of the process described.

[0108] However, since the growth barrier pattern 225 is not formed on the fourth groove 197, the upper surface of the active pattern 105 exposed by the fourth groove 197 can also be used as a seed crystal during the first SEG process, so that a third epitaxial layer 233 with a first impurity concentration can be formed.

[0109] The growth rate of the third epitaxial layer 233 can be greater than that of the first epitaxial layer 230. Therefore, the uppermost surface of the third epitaxial layer 233 can be at least higher than the bottom surface of the lowermost semiconductor pattern 124. In addition, the first epitaxial layer 230 can be fused with the lowermost semiconductor pattern 124.

[0110] Executable and referenced Figures 16 to 18 and Figures 1 to 3 The process shown is similar to that used to manufacture semiconductor devices.

[0111] Figure 23 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention, for example, along... Figure 1 A cross-sectional view taken along line B-B'. Aside from some components, this semiconductor device can be used with... Figures 1 to 3 The semiconductor devices are similar. Therefore, the same reference numerals refer to the same elements, and repeated descriptions can be omitted.

[0112] Reference Figure 23 In addition to the first epitaxial layer 230 and the second epitaxial layer 240, the source / drain layer 250 may also include a fourth epitaxial layer 235.

[0113] In an exemplary embodiment of the present invention, the growth-stopping pattern 225 on the first groove 195 may not completely cover the upper surface of the active pattern 105 exposed by the first groove 195. In this case, the opposite edges of the upper surface of the active pattern 105 in the first direction may be exposed in the first groove 195, and therefore may not be connected to the inner spacer 220.

[0114] The fourth epitaxial layer 235 can be grown from the surface of the active pattern 105 not covered by the growth barrier pattern 225, and can have a first impurity concentration similar to that of the first epitaxial layer 230. The surface from which the fourth epitaxial layer 235 of the active pattern 105 grows can be tilted relative to the upper surface of the substrate 100. The uppermost surface of the fourth epitaxial layer 235 can be lower than the bottom surface of the lowermost semiconductor pattern 124, so that each semiconductor pattern 124 is not affected by the low impurity concentration of the fourth epitaxial layer 235. Therefore, performance degradation of the transistors including the semiconductor pattern 124 can be prevented.

[0115] Figure 24 and Figure 25 This is a cross-sectional view illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention, for example, a cross-sectional view taken along line B-B' of a respective top view. The method may include reference to... Figures 4 to 18 and Figures 1 to 3 The process shown is similar to the process described above, therefore, repeated descriptions can be omitted.

[0116] Reference Figure 24 It can be executed and referenced. Figures 4 to 14 The process shown is similar to that of the process described.

[0117] However, the growth-stopping pattern 225 grown on the first groove 195 may not completely cover the upper surface of the active pattern 105 exposed in the first groove 195. In this case, the opposite edges of the upper surface of the active pattern 105 in the first direction are exposed in the first groove 195, and therefore may not be connected to the inner spacer 220.

[0118] Reference Figure 25 It can be executed and referenced. Figure 15 The process shown is similar to that of the process described.

[0119] However, the exposed opposite edges of the upper surface of the active pattern 105 can be used as seed crystals, and thus a fourth epitaxial layer 235 with a first impurity concentration can also be formed.

[0120] A growth stop pattern 225 has been formed on the central portion of the first groove 195 in the first direction. Therefore, only the opposite edge of the upper surface of the source pattern 105, which is inclined relative to the upper surface of the substrate 100, can be used as a seed. As a result, the fourth epitaxial layer 235 can have a low height relative to the substrate 100. Therefore, the uppermost surface of the fourth epitaxial layer 235 can be lower than the bottom surface of the lowermost semiconductor pattern 124. In an exemplary embodiment of the present invention, the height of the uppermost surface of the fourth epitaxial layer 235 can be similar to the height of the top surface of the active pattern 105.

[0121] Executable and referenced Figures 16 to 18 and Figures 1 to 3 The process shown is similar to that used to manufacture semiconductor devices.

[0122] Figure 26 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention, for example, along... Figure 1 A cross-sectional view taken along line B-B'. Aside from some components, this semiconductor device can be used with... Figures 1 to 3 The semiconductor devices are similar. Therefore, the same reference numerals can refer to the same elements, and repeated descriptions can be omitted.

[0123] Reference Figure 26 A fifth groove 199 with a U-shaped cross-section and being quite deep can be formed on the active pattern 105, instead of the first groove 195 with a V-shaped cross-section. Furthermore, the growth barrier pattern 225 may not completely cover the portion of the active pattern 105 exposed by the fifth groove 199. The growth barrier pattern 225 allows the vertically opposing sidewalls of the active pattern 105 in the first direction to be exposed in the fifth groove 199, thus eliminating the need for connection to the inner spacer 220.

[0124] The fifth epitaxial layer 237 can be grown from each of the vertically opposing sidewalls of the active pattern 105 that are not covered by the growth stop pattern 225, and can have a first impurity concentration similar to that of the first epitaxial layer 230. However, the uppermost surface of the fifth epitaxial layer 237 can be lower than the bottom surface of the lowermost semiconductor pattern 124. In this case, each semiconductor pattern in the semiconductor pattern 124 can be unaffected by the low impurity concentration of the fifth epitaxial layer 237. Therefore, performance degradation of the transistor including the semiconductor pattern 124 can be prevented.

[0125] Figure 27 and Figure 28 This is a cross-sectional view illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention, for example, a cross-sectional view taken along line B-B' of a respective top view. The method may include reference to... Figures 4 to 18 and Figures 1 to 3 The process shown is similar to the process described above, therefore, repeated descriptions can be omitted.

[0126] Reference Figure 27 It can be executed and referenced. Figures 4 to 14 The process shown is similar to that of the process described.

[0127] However, a fifth groove 199 with a "U"-shaped cross-section can be formed on the active pattern 105 instead of the first groove 195 with a "V"-shaped cross-section, and the fifth groove 199 can be larger than... Figures 19 to 21 The fourth groove is 197 deep.

[0128] Therefore, when the second spacer layer 210 is anisotropically etched, the second spacer layer 210 can be at least partially retained, and a growth stop pattern 225 can be formed to at least fill the lower portion of the fifth groove 199. However, the growth stop pattern 225 may not completely cover the portion of the active pattern 105 exposed by the fifth groove 199. In this case, the growth stop pattern 225 may allow the opposing sidewalls of the active pattern 105 in the first direction to be exposed and may not be connected to the lowermost inner spacer 220. The opposing sidewalls of the active pattern 105 not covered by the growth stop pattern 225 may extend vertically in the third direction.

[0129] Reference Figure 28 It can be executed and referenced. Figure 15 The process shown is similar to that of the process described.

[0130] However, the exposed opposite sidewalls of the active pattern 105 can be used as seed crystals, thus forming a fifth epitaxial layer 237 with a first impurity concentration.

[0131] A growth stop pattern 225 has already been formed along the first direction at the lower part of the fifth groove 199, so only the vertically opposite sidewalls of the source pattern 105 can be used as seed crystals. As a result, the fifth epitaxial layer 237 can have a low height relative to the substrate 100. Therefore, the uppermost surface of the fifth epitaxial layer 237 can be lower than the bottom surface of the lowermost semiconductor pattern 124.

[0132] Executable and referenced Figures 16 to 18 and Figures 1 to 3 The process shown is similar to that used to manufacture semiconductor devices.

[0133] Figure 29 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention, for example, along... Figure 1 A cross-sectional view taken along line B-B'. Aside from some components, this semiconductor device can be used with... Figures 1 to 3The semiconductor devices are similar. Therefore, the same reference numerals can refer to the same elements, and repeated descriptions can be omitted.

[0134] Reference Figure 29 The source / drain layer 250 may include a sixth epitaxial layer 228, a seventh epitaxial layer 234, an eighth epitaxial layer 244, and a ninth epitaxial layer 248.

[0135] The sixth epitaxial layer 228 may be thinly formed on each of the opposite sidewalls of the semiconductor pattern 124 in the first direction; the seventh epitaxial layer 234 may protrude from the sixth epitaxial layer 228 in the first direction to have, for example, a pentagonal cross-section in the first direction; the eighth epitaxial layer 244 may be grown to fill the first opening 190 and contact the lower outer sidewall of the gate spacer 185; and the ninth epitaxial layer 248 may be thinly formed on the eighth epitaxial layer 244.

[0136] In an exemplary embodiment of the present invention, the sixth epitaxial layer 228, the seventh epitaxial layer 234, and the eighth epitaxial layer 244 may comprise single-crystal silicon germanium doped with p-type impurities, and may respectively have a fourth impurity concentration, a fifth impurity concentration, and a sixth impurity concentration. The sixth impurity concentration may be greater than the fifth impurity concentration, and the fifth impurity concentration may be greater than the fourth impurity concentration. The germanium concentrations of the sixth epitaxial layer 228, the seventh epitaxial layer 234, and the eighth epitaxial layer 244 may gradually increase in this order. In other words, the germanium concentration of the eighth epitaxial layer 244 may be greater than the germanium concentration of the seventh epitaxial layer 234, and the germanium concentration of the seventh epitaxial layer 234 may be greater than the germanium concentration of the sixth epitaxial layer 228.

[0137] The ninth epitaxial layer 248 may include undoped single-crystal silicon.

[0138] and Figures 1 to 3 Unlike other semiconductor devices, this semiconductor device can be an MBCFET that includes a p-type metal-oxide-semiconductor (PMOS) transistor. The source / drain layer 250 of this semiconductor device can include not only a sixth epitaxial layer 228 and a seventh epitaxial layer 234 with relatively low impurity concentration, but also an eighth epitaxial layer 244 with relatively high impurity concentration located between channels at each horizontal height, thus preventing performance degradation of the transistor including the channel.

[0139] Figure 30 and Figure 31 This is a cross-sectional view illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention, for example, a cross-sectional view taken along line B-B' of a respective top view. The method may include reference to... Figures 4 to 18 and Figures 1 to 3 The process shown is similar to the process described above, therefore, repeated descriptions can be omitted.

[0140] Reference Figure 30 It can be executed and referenced. Figures 4 to 15 The process shown is similar to that of the process described.

[0141] However, a third SEG process can be performed instead of the first SEG process. The third SEG process can be performed using a silicon source gas (e.g., dichlorosilane (SiH2Cl2)), a germanium source gas (e.g., germanane (GeH4)), and a p-type impurity source gas (e.g., diborane (B2H6)) to form a single-crystal silicon-germanium (SiGe) layer doped with p-type impurities. The sixth epitaxial layer 228 can have a third impurity concentration.

[0142] In an exemplary embodiment of the present invention, each of the sixth epitaxial layers 228 may be formed on each of the sidewalls of the opposing sidewalls of the sacrificial pattern 114 in the first direction.

[0143] A fourth SEG process can be performed using silicon source gas, germanium source gas, and p-type impurity source gas to form a seventh epitaxial layer 234 comprising single-crystal silicon-germanium (SiGe) doped with p-type impurities. The seventh epitaxial layer 234 can have a fourth impurity concentration greater than the third impurity concentration. The germanium concentration of the seventh epitaxial layer 234 can be greater than the germanium concentration of the sixth epitaxial layer 228.

[0144] In an exemplary embodiment of the present invention, the seventh epitaxial layer 234 may protrude from the sixth epitaxial layer 228 along a first direction and may have, for example, a pentagonal cross section.

[0145] Reference Figure 31 It can be executed and referenced. Figure 16 The process shown is similar to that of the process described.

[0146] However, a fifth SEG process can be performed instead of the second SEG process to form the eighth epitaxial layer 244. The fifth SEG process can be performed using silicon source gas, germanium source gas, and p-type impurity source gas to form the eighth epitaxial layer 244, which comprises single-crystal silicon-germanium (SiGe) doped with p-type impurities. The eighth epitaxial layer 244 can have a fifth impurity concentration greater than the fourth impurity concentration. The germanium concentration of the eighth epitaxial layer 244 can be greater than the germanium concentration of the seventh epitaxial layer 234.

[0147] In an exemplary embodiment of the present invention, the eighth epitaxial layer 244 may fill the first opening 190 on the growth stop pattern 225 and may contact the lower outer sidewall of the gate spacer 185. For example, the eighth epitaxial layer 244 may be configured to surround the seventh epitaxial layer 234.

[0148] The sixth SEG process can be performed using only silicon source gas to form a ninth epitaxial layer 248 containing monocrystalline silicon. The ninth epitaxial layer 248 can be formed thinly on the eighth epitaxial layer 244. For example, the ninth epitaxial layer 248 can be formed on the uppermost surface of the eighth epitaxial layer 244.

[0149] Through the above process, a source / drain layer 250 including a sixth epitaxial layer 228, a seventh epitaxial layer 234, an eighth epitaxial layer 244 and a ninth epitaxial layer 248 can be formed.

[0150] Executable and referenced Figure 17 and Figure 18 as well as Figures 1 to 3 The process shown is similar to that used to manufacture semiconductor devices.

[0151] Figures 32 to 35 These are top views and cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention. Figure 32 It is a top view. Figure 33 It is along Figure 32 A cross-sectional view taken from line A-A'. Figure 34 It is along Figure 32 A cross-sectional view taken from line B-B'. Figure 35 It is along Figure 32 A cross-sectional view taken from line C-C'.

[0152] The semiconductor device may be a complementary metal-oxide-semiconductor (CMOS) transistor, including a PMOS transistor and an NMOS transistor employing an exemplary embodiment of the present invention. Therefore, a detailed description of the NMOS transistor can be omitted.

[0153] Reference Figures 32 to 35 The semiconductor device may include a first MBCFET and a second MBCFET located on a first region I and a second region II of the substrate 400, respectively.

[0154] The first region I and the second region II of the substrate 400 can be a PMOS region and an NMOS region, respectively. Therefore, the first MBCFET can include a PMOS transistor, and the second MBCFET can include an NMOS transistor.

[0155] The first MBCFET may be formed on a first active pattern 402 in a first region I of the substrate 400, and may include a first gate structure 632, a first semiconductor pattern 426, a first source / drain layer 860, a first gate spacer structure 902, and a leakage blocking pattern 403.

[0156] The sidewalls of the first active pattern 402 may be covered by the first isolation pattern 432. A sixth groove 815 having a concave curved shape may be formed on the upper surface of the first active pattern 402 located between the first gate structures 632, and a leakage blocking pattern 403 may be formed on the upper part of the first active pattern 402 adjacent to the sixth groove 815. The leakage blocking pattern 403 may comprise, for example, silicon doped with n-type impurities.

[0157] First semiconductor patterns 426 may be formed at multiple horizontal heights on the upper surface of the first active pattern 402 at intervals from each other, and each first semiconductor pattern 426 may extend through the first gate structure 632 along a first direction. Each first semiconductor pattern 426 may be used as a channel of a PMOS transistor, and therefore may be referred to as a first channel.

[0158] The first gate structure 632 may be formed on the portion of the first active pattern 402 and the first isolation pattern 432 adjacent to the first active pattern 402 in the second direction. Additionally, the first gate structure 632 may cover the first semiconductor pattern 426.

[0159] The first gate structure 632 may include a first interface pattern 592, a first gate insulating pattern 602, a first work function control pattern 612, and a first gate electrode 622, which are sequentially stacked from the surface of each first semiconductor pattern 426 or the upper surface of the first active pattern 402.

[0160] The first gate spacer structure 902 may include a first gate spacer 482 covering each of the opposite sidewalls in a first direction of the upper portion of the first gate structure 632, and a second gate spacer 872 on the outer sidewall of the first gate spacer 482. In an exemplary embodiment of the present invention, the bottom surface of the first gate spacer 482 may be lower than the bottom surface of the second gate spacer 872.

[0161] For ease of explanation, the first gate structure 632, the first gate spacer 482, and the first semiconductor pattern 426 can be collectively referred to as the third structure.

[0162] The first source / drain layer 860 may extend along a third direction on the first active pattern 402 and may commonly contact and connect with the respective sidewalls of the first semiconductor pattern 426 at multiple horizontal heights in the first direction. Additionally, the first source / drain layer 860 may contact the lower outer sidewall of the first gate spacer 482.

[0163] The first source / drain layer 860 may include the tenth epitaxial layer 820, the eleventh epitaxial layer 830, the twelfth epitaxial layer 840, and the thirteenth epitaxial layer 850.

[0164] In an exemplary embodiment of the present invention, a tenth epitaxial layer 820 may be thinly formed on each of the opposite sidewalls in the first direction of the upper surface of the first active pattern 402, the lower portion of the first gate structure 632, and each of the opposite sidewalls in the first direction of the first semiconductor pattern 426. An eleventh epitaxial layer 830 may be formed on the tenth epitaxial layer 820 to fill most of the space between adjacent third structures in the first direction. The upper surface of the eleventh epitaxial layer 830 may have a "V" shaped cross-section in the first direction, and the uppermost surface of the eleventh epitaxial layer 830 may be substantially coplanar with the uppermost surface of the uppermost first semiconductor pattern 426. A twelfth epitaxial layer 840 may be formed on the eleventh epitaxial layer 830 to fill the space between adjacent third structures in the first direction and to contact the lower outer sidewall of the first gate spacer 482. A thirteenth epitaxial layer 850 may be thinly formed on the upper surface of the twelfth epitaxial layer 840.

[0165] In an exemplary embodiment of the present invention, the tenth epitaxial layer 820, the eleventh epitaxial layer 830, and the twelfth epitaxial layer 840 may comprise single-crystal silicon germanium doped with p-type impurities. The impurity concentration and germanium concentration of the tenth epitaxial layer 820, the eleventh epitaxial layer 830, and the twelfth epitaxial layer 840 may gradually increase sequentially. For example, the germanium concentration of the eleventh epitaxial layer 830 may be greater than that of the tenth epitaxial layer 820, and the germanium concentration of the twelfth epitaxial layer 840 may be greater than that of the eleventh epitaxial layer 830. The thirteenth epitaxial layer 850 may comprise undoped single-crystal silicon.

[0166] In an exemplary embodiment of the present invention, the first source / drain layer 860 may have a polygonal cross-section, such as a pentagon, in the second direction.

[0167] The second MBCFET may be formed on the second active pattern 404 in the second region II of the substrate 400, and may include a second gate structure 634, a second semiconductor pattern 428, a second source / drain layer 930, a second gate spacer structure 904, an inner spacer 520, and a growth stop pattern 525.

[0168] The sidewalls of the second active pattern 404 may be covered by the second isolation pattern 434. A seventh groove 895 having a "V" shaped cross-section may be formed on the upper surface of the second active pattern 404 located between the second gate structures 634. A growth stop pattern 525 may be formed on the seventh groove 895.

[0169] The second semiconductor patterns 428 may be formed at multiple horizontal heights on the upper surface of the second active pattern 404 at intervals from each other, and each second semiconductor pattern 428 may extend through the second gate structure 634 along a first direction. Each second semiconductor pattern 428 may be used as a channel of an NMOS transistor, and therefore may be referred to as a second channel.

[0170] The second gate structure 634 may be formed on the portion of the second active pattern 404 and the second isolation pattern 434 adjacent to the second active pattern 404 in the second direction. The second gate structure 634 may cover the second semiconductor pattern 428.

[0171] The second gate structure 634 may include a second interface pattern 594, a second gate insulating pattern 604, a second work function control pattern 614, and a second gate electrode 624, which are sequentially stacked from the surface of each second semiconductor pattern 428 or the upper surface of the second active pattern 404.

[0172] The second gate spacer structure 904 may include a third gate spacer 484 and a fourth gate spacer 874. The third gate spacer 484 covers each of the opposite sidewalls in the first direction of the upper part of the second gate structure 634 and has an "L" shaped cross section in the first direction. The fourth gate spacer 874 is on the outer sidewall of the third gate spacer 484.

[0173] For ease of explanation, the second gate structure 634, the second gate spacer structure 904, and the second semiconductor pattern 428 can be collectively referred to as the fourth structure.

[0174] The inner spacer 520 may be formed on each of the opposing sidewalls of the portion of the second gate structure 634 located between the second semiconductor patterns 428 in the first direction. Alternatively, the inner spacer 520 may be formed on each of the opposing sidewalls of the portion of the second gate structure 634 located between the upper surface of the second active pattern 404 and the lowermost second semiconductor pattern 428 in the first direction. The cross-section of the inner spacer 520 in the first direction may be a horseshoe shape or a semi-circle with recesses on its outer sidewalls. Alternatively, the cross-section of the inner spacer 520 in the first direction may be a rounded rectangle with recesses on its outer sidewalls.

[0175] The second source / drain layer 930 may extend along a third direction on the second active pattern 404 and may commonly contact and connect with the respective sidewalls of the second semiconductor pattern 428 at multiple horizontal heights in the first direction. Additionally, the second source / drain layer 930 may contact the lower outer sidewall of the second gate spacer structure 904.

[0176] The second source / drain layer 930 may include the fourteenth epitaxial layer 910 and the fifteenth epitaxial layer 920.

[0177] In an exemplary embodiment of the present invention, each fourteenth epitaxial layer 910 may protrude from the sidewall of each second semiconductor pattern 428 along a first direction and may have a cross-section, for example, candle-shaped or elliptical, in the first direction. In an exemplary embodiment of the present invention, a fifteenth epitaxial layer 920 may fill the space between adjacent fourth structures in the first direction to contact the lower sidewall of the second gate spacer structure 904.

[0178] In an exemplary embodiment of the present invention, both the fourteenth epitaxial layer 910 and the fifteenth epitaxial layer 920 may comprise single-crystal silicon carbide doped with n-type impurities or single-crystal silicon doped with n-type impurities. The impurity concentration of the fifteenth epitaxial layer 920 may be greater than that of the fourteenth epitaxial layer 910.

[0179] In an exemplary embodiment of the present invention, the second source / drain layer 930 may have a cross-section, for example, candle-shaped or elliptical, in the second direction.

[0180] A first air gap 560 may be formed between the source / drain layer 930 and the growth barrier pattern 525, and a second air gap 565 may be formed between the second source / drain layer 930 and the inner spacer 520.

[0181] In the second MBCFET of the semiconductor device, the portion of the second source / drain layer 930 between the second semiconductor patterns 428 at the same horizontal height may include not only a fourteenth epitaxial layer 910 with a relatively low impurity concentration, but also a fifteenth epitaxial layer 920 with a relatively high impurity concentration. As a result, performance degradation of the NMOS transistor including the second semiconductor pattern 428 can be prevented. Furthermore, a growth stop pattern 525 can be formed between the second source / drain layer 930 and the second active pattern 404, thus preventing leakage current from occurring between them.

[0182] In the first MBCFET of the semiconductor device, a leakage prevention pattern 403 can be formed between the first source / drain layer 860 and the first active pattern 402, so that no leakage current is generated between them.

[0183] Figures 36 to 50 These are top views and cross-sectional views illustrating an exemplary embodiment of a method for manufacturing a semiconductor device according to the concept of the present invention. For example, Figure 36 , Figure 38 , Figure 41 , Figure 45 and Figure 48 It is a top view, and Figure 37 , Figures 39 to 40 , Figures 42 to 44, Figures 46 to 47 and Figures 49 to 50 It is a cross-sectional view.

[0184] Figure 37 and Figure 39 These are cross-sectional views taken along line A-A' in the corresponding top view. Figure 40 , Figure 42 , Figure 44 , Figure 46 and Figure 49 These are cross-sectional views taken along line B-B' in the corresponding top view. Figure 43 , Figure 47 and Figure 50 These are cross-sectional views taken along line C-C' of the corresponding top view.

[0185] This method may include references Figures 4 to 18 and Figures 1 to 3 The process shown is similar to the process described above, therefore, repeated descriptions can be omitted.

[0186] Reference Figure 36 and Figure 37 The sacrificial layer 410 and the semiconductor layer 420 can be stacked alternately and repeatedly on the substrate 400, which includes the first region I and the second region II.

[0187] Reference Figures 38 to 40 A first etch mask and a second etch mask extending in a first direction can be formed on the uppermost semiconductor layer 420, and the semiconductor layer 420, the sacrificial layer 410 and the upper part of the substrate 400 can be etched using the first etch mask and the second etch mask to form a first active pattern 402 and a second active pattern 404 on the first region I and the second region II of the substrate 400, respectively.

[0188] Therefore, a first fin structure including alternating and repeatedly stacked first sacrificial lines 412 and first semiconductor lines 422 can be formed on the first active pattern 402, and a second fin structure including alternating and repeatedly stacked second sacrificial lines 414 and second semiconductor lines 424 can be formed on the second active pattern 404.

[0189] A first isolation pattern 432 and a second isolation pattern 434 can be formed on the first region I and the second region II of the substrate 400, respectively, to cover the sidewalls of the first active pattern 402 and the second active pattern 404, respectively.

[0190] A first dummy gate structure 472 and a second dummy gate structure 474 can be formed on the first isolation pattern 432 and the second isolation pattern 434, respectively, to partially cover the first fin structure and the second fin structure.

[0191] The first dummy gate structure 472 may include a first dummy gate insulating pattern 442, a first dummy gate electrode 452, and a first dummy gate mask 462 sequentially stacked on the first fin structure and a portion of the adjacent first isolation pattern 432. The second dummy gate structure 474 may include a second dummy gate insulating pattern 444, a second dummy gate electrode 454, and a second dummy gate mask 464 sequentially stacked on the second fin structure and a portion of the second isolation pattern 434.

[0192] Reference Figures 41 to 43 A first spacer layer 480 can be formed on a substrate 400 having a first fin structure and a second fin structure, a first isolation pattern 432 and a second isolation pattern 434, and a first dummy gate structure 472 and a second dummy gate structure 474. A first photoresist pattern 800 covering a second region II of the substrate 400 can be formed on the first spacer layer 480, and the first photoresist pattern 800 can be used as an etching mask to etch the portion of the first spacer layer 480 located on the first region I of the substrate 400.

[0193] Therefore, a first gate spacer 482 can be formed to cover each sidewall of the first dummy gate structure 472 in the opposite sidewalls in the first direction.

[0194] The first fin structure can be etched using the first dummy gate structure 472 and the first gate spacer 482 as etching masks to form a third opening 810 that exposes the upper surface of the first active pattern 402, and a sixth groove 815 can be formed on the upper surface of the first active pattern 402 exposed by the third opening 810.

[0195] Therefore, the first sacrificial line 412 and the first semiconductor line 422 below the first dummy gate structure 472 and the first gate spacer 482 can be transformed into a first sacrificial pattern 416 and a first semiconductor pattern 426, respectively, and the first fin structure extending in the first direction can be divided into multiple portions spaced apart from each other in the first direction. In the following text, the first dummy gate structure 472, the first gate spacer 482, and the first fin structure can be collectively referred to as the first structure.

[0196] In an exemplary embodiment of the present invention, the sixth groove 815 may be shallow and may have a curved shape.

[0197] A leakage prevention pattern 403 can be formed on the upper surface of the first active pattern 402 exposed by the sixth groove 815.

[0198] Reference Figure 44After removing the first photoresist pattern 800, a first source / drain layer 860 can be formed on the upper surface of the first active pattern 402 exposed by the sixth groove 815.

[0199] In an exemplary embodiment of the present invention, the exposed upper surface of the first active pattern 402 and the sidewalls of the first sacrificial pattern 416 and the first semiconductor pattern 426 can be used as seed crystals to form the first source / drain layer 860 through a first SEG process, a second SEG process, a third SEG process and a fourth SEG process.

[0200] Each of the first through third SEG processes can be performed using silicon source gas, germanium source gas, and p-type impurity source gas to form a tenth epitaxial layer 820, an eleventh epitaxial layer 830, and a twelfth epitaxial layer 840 comprising single-crystal silicon germanium doped with p-type impurities. The tenth, eleventh, and twelfth epitaxial layers 820, 830, and 840 can have impurity concentrations and germanium concentrations that gradually increase in this order. A fourth SEG process can be performed using only silicon source gas, thus forming a thirteenth epitaxial layer 850 comprising undoped single-crystal silicon.

[0201] Reference Figures 45 to 47 A second spacer layer 870 can be formed on a substrate 400 having a first structure, a first source / drain layer 860, a first isolation pattern 432 and a first spacer layer 480. A second photoresist pattern 880 covering a first region I of the substrate 400 can be formed on the second spacer layer 870. The second photoresist pattern 880 can be used as an etching mask to etch the portion of the second spacer layer 870 located on the second region II of the substrate 400.

[0202] Therefore, a fourth gate spacer 874 can be formed to cover each sidewall of the first spacer layer 480 on the second dummy gate structure 474 in the opposite sidewall in the first direction.

[0203] The first spacer layer 480 can be anisotropically etched to form a third gate spacer 484 covering each sidewall of the opposing sidewalls of the second dummy gate structure 474 in the first direction. The portion of the third gate spacer 484 below the fourth gate spacer 874 can be retained, thus the third gate spacer 484 can have an "L"-shaped cross-section in the first direction. The sequentially stacked third gate spacer 484 and fourth gate spacer 874 can form the second gate spacer structure 904.

[0204] The second fin structure can be etched using the second dummy gate structure 474 and the second gate spacer structure 904 as an etching mask to form a fourth opening 890 that exposes the upper surface of the second active pattern 404. The exposed upper surface of the second active pattern 404 can also be etched to form a seventh groove 895 in the fourth opening 890.

[0205] Therefore, the second sacrificial line 414 and the second semiconductor line 424 located below the second dummy gate structure 474 and the second gate spacer structure 904 can be transformed into a second sacrificial pattern 418 and a second semiconductor pattern 428, respectively, and the second fin structure extending along the first direction can be divided into multiple portions spaced apart from each other in the first direction. In the following text, the second dummy gate structure 474, the second gate spacer structure 904, and the second fin structure can be collectively referred to as the second structure.

[0206] In an exemplary embodiment of the present invention, the seventh groove 895 may have a "V" shaped cross section in the first direction.

[0207] Reference Figures 48 to 50 After removing the second photoresist pattern 880, the opposite sidewalls of the second sacrificial pattern 418 exposed by the fourth opening 890 can be etched in the first direction to form the eighth groove, and inner spacers 520 can be formed to fill each eighth groove.

[0208] In an exemplary embodiment of the present invention, the inner spacer 520 can be formed by forming a third spacer layer on the substrate 400 to fill the eighth groove and by anisotropically etching the third spacer layer. A growth stop pattern 525 can be formed on the seventh groove 895.

[0209] A second source / drain layer 930 can be formed on the growth barrier pattern 525 to fill the fourth opening 890.

[0210] In an exemplary embodiment of the inventive concept, a second semiconductor pattern 428 can be used as a seed crystal to form a second source / drain layer 930 through a fifth SEG process and a sixth SEG process.

[0211] Each of the fifth and sixth SEG processes can be performed using either a silicon source gas, a carbon source gas, and an n-type impurity source gas, or a silicon source gas and an n-type impurity source gas. Therefore, a fourteenth epitaxial layer 910 and a fifteenth epitaxial layer 920 comprising single-crystal silicon carbide doped with n-type impurities or single-crystal silicon doped with n-type impurities can be formed. The impurity concentration of the fifteenth epitaxial layer 920 can be greater than the impurity concentration of the fourteenth epitaxial layer 910.

[0212] In an exemplary embodiment of the present invention, the fourteenth epitaxial layer 910 may protrude from each sidewall of the opposing sidewalls of the second semiconductor pattern 428 along a first direction and may have a cross-section, for example, candle-shaped or elliptical. The fifteenth epitaxial layer 920 may fill the fourth opening 890 and may contact the lower outer sidewall of the second gate spacer structure 904.

[0213] In an exemplary embodiment of the present invention, a first air gap 560 may be formed between the second source / drain layer 930 and the growth barrier pattern 525, and a second air gap 565 may be formed between the second source / drain layer 930 and the inner spacer 520.

[0214] Refer again Figures 32 to 35 An insulating layer 570 can be formed on the second isolation pattern 434 to cover the first structure and the second structure, the second spacer layer 870, and the first source / drain layer 860 and the second source / drain layer 930. Additionally, the first dummy gate structure 472 of the first structure and the second dummy gate structure 474 of the second structure can be replaced by the first gate structure 632 and the second gate structure 634, respectively, to complete the fabrication of the semiconductor device.

[0215] During the replacement of the first gate structure 632 and the second gate structure 634, the upper part of the second spacer layer 870 may be removed to form the second gate spacer 872 on the outer sidewall of the first gate spacer 482, and the first gate spacer 482 and the second gate spacer 872 may form the first gate spacer structure 902.

[0216] The first gate structure 632 may include a first interface pattern 592, a first gate insulating pattern 602, a first work function control pattern 612, and a first gate electrode 622, and the second gate structure 634 may include a second interface pattern 594, a second gate insulating pattern 604, a second work function control pattern 614, and a second gate electrode 624.

[0217] Figure 51 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention, for example, along... Figure 32 The cross-sectional view is taken along line B-B'. The semiconductor device may be a CMOS transistor comprising PMOS and NMOS transistors applied in exemplary embodiments of the present invention. Therefore, detailed descriptions of the PMOS and NMOS transistor components can be omitted.

[0218] Reference Figure 51 A ninth groove 817 having a "V" shaped cross section in the first direction can be formed on the first active pattern 402 between the first gate structures 632, and a growth stop pattern 525 can be formed on the ninth groove 817.

[0219] The first source / drain layer 860 may extend along a third direction on the growth stop pattern 525 and may contact the sidewall of the first semiconductor pattern 426 in the first direction for connection. The first source / drain layer 860 may contact the lower outer sidewall of the first gate spacer 482.

[0220] The first source / drain layer 860 may include the tenth epitaxial layer 820, the eleventh epitaxial layer 830, the twelfth epitaxial layer 840, and the thirteenth epitaxial layer 850.

[0221] In an exemplary embodiment of the present invention, a tenth epitaxial layer 820 may be thinly formed on each sidewall of the first semiconductor pattern 426 in a first direction; an eleventh epitaxial layer 830 may be formed on the tenth epitaxial layer 820 to protrude along the first direction and may have a polygonal cross-section, such as a pentagon. A twelfth epitaxial layer 840 may be formed on the growth stop pattern 525 to fill the space between adjacent third structures to contact the lower outer sidewall of the first gate spacer 482; a thirteenth epitaxial layer 850 may be thinly formed on the upper surface of the twelfth epitaxial layer 840.

[0222] Although the concept of the invention has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the concept of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: An active pattern located on a substrate, the active pattern including a groove having a "V" shape; Growth inhibition pattern located on the groove; A gate structure located on the portion of the active pattern opposite to the groove; Channels spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, each of the channels extending through one of the gate structures; as well as The source / drain layer is located on the growth barrier pattern, and the source / drain layer contacts the channel. The top surface of the growth inhibition pattern is not higher than the bottom surface of the gate structure.

2. The semiconductor device according to claim 1, wherein, The source / drain layer includes: A first epitaxial layer located on the sidewall of each of the channels; and A second epitaxial layer is located on the growth barrier pattern, and the second epitaxial layer is adjacent to the first epitaxial layer.

3. The semiconductor device according to claim 2, wherein, The source / drain layer comprises silicon doped with n-type impurities or silicon carbide doped with n-type impurities, and The impurity concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

4. The semiconductor device according to claim 2, wherein, The first epitaxial layer has a candle-shaped or elliptical shape projecting horizontally from the sidewall of each of the channels, the horizontal direction being parallel to the upper surface of the substrate.

5. The semiconductor device according to claim 1, wherein, The source / drain layer includes: The first epitaxial layer located on the sidewall of each of the channels; A second epitaxial layer protrudes horizontally from the first epitaxial layer, the horizontal direction being parallel to the upper surface of the substrate; and A third epitaxial layer is located on the growth barrier pattern, and the third epitaxial layer is adjacent to the second epitaxial layer.

6. The semiconductor device according to claim 5, wherein, The source / drain layer comprises silicon-germanium doped with p-type impurities, and Wherein, the impurity concentration of the third epitaxial layer is greater than that of the second epitaxial layer, and the impurity concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

7. The semiconductor device according to claim 6, wherein, The germanium concentration of the third epitaxial layer is greater than that of the second epitaxial layer, and the germanium concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

8. The semiconductor device according to claim 5, wherein, The first epitaxial layer, the second epitaxial layer, and the third epitaxial layer all contain silicon germanium doped with p-type impurities, and The source / drain layer further includes a fourth epitaxial layer located on the third epitaxial layer, the fourth epitaxial layer comprising silicon.

9. The semiconductor device according to claim 5, wherein, The second epitaxial layer has a polygon protruding horizontally from the first epitaxial layer, the horizontal direction being parallel to the upper surface of the substrate.

10. The semiconductor device of claim 1, further comprising a first air gap located between the growth barrier pattern and the source / drain layer.

11. The semiconductor device according to claim 1, further comprising: Inner spacers are located on the sidewalls of each of the gate structures between the channels and on the sidewalls of each of the gate structures between the upper surface of the active pattern and the lowermost channel in the channels.

12. The semiconductor device according to claim 11, wherein, The inner spacers contain substantially the same material as the growth-inhibiting pattern.

13. The semiconductor device of claim 11, further comprising a second air gap located between the inner spacer and the source / drain layer.

14. The semiconductor device according to claim 11, wherein, The inner spacer on the sidewall of the gate structure located between the upper surface of the active pattern and the lowermost channel contacts the growth barrier pattern.

15. The semiconductor device according to claim 11, wherein, The inner spacer on the sidewall of the gate structure located between the upper surface of the active pattern and the lowermost channel is spaced apart from the growth stop pattern.

16. The semiconductor device according to claim 15, wherein, The source / drain layer comprises silicon doped with n-type impurities or silicon carbide doped with n-type impurities, and The source / drain layer includes: A first epitaxial layer located on the sidewall of each of the channels, the first epitaxial layer having a first impurity concentration; A third epitaxial layer, having the first impurity concentration, is located on the portion of the active pattern between the upper surface of the active pattern and the lowermost channel, on the portion between the growth barrier pattern and the inner spacer of the gate structure. A second epitaxial layer adjacent to the first epitaxial layer and the third epitaxial layer, the second epitaxial layer having a second impurity concentration greater than the first impurity concentration.

17. The semiconductor device according to claim 1, wherein, The active pattern extends in a first direction parallel to the upper surface of the substrate. Each of the gate structures extends in a second direction perpendicular to the first direction, and The source / drain layers are formed between the gate structures along the first direction.

18. A semiconductor device, comprising: Active patterns located on the substrate; Channels spaced apart from each other in a first direction perpendicular to the surface of the substrate; A gate structure located on the active pattern, the gate structure surrounding at least a portion of the surface of each of the channels; as well as A source / drain layer, located on a portion of the active pattern on each side of the gate structure and contacting the channel, the source / drain layer comprising a semiconductor material doped with n-type or p-type impurities, and including: A first epitaxial layer located on the sidewall of each of the channels, the first epitaxial layer having a first impurity concentration; and A second epitaxial layer is located on the active pattern, the second epitaxial layer surrounds the first epitaxial layer and has a second impurity concentration greater than the first impurity concentration. The growth-preventing pattern is formed between the active pattern and the source / drain layer.

19. The semiconductor device according to claim 18, wherein, The source / drain layer comprises silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

20. The semiconductor device according to claim 19, wherein, The first epitaxial layer has a candle-shaped or elliptical shape protruding from the sidewall of each of the channels along a second direction parallel to the surface of the substrate.

21. The semiconductor device of claim 18, further comprising a first air gap located between the growth barrier pattern and the source / drain layer.

22. The semiconductor device of claim 18, further comprising an inner spacer on the sidewall of the portion of the gate structure between the upper surface of the active pattern and the lowermost channel in the channel.

23. The semiconductor device according to claim 22, wherein, The inner spacers contain substantially the same material as the growth-inhibiting pattern.

24. A semiconductor device, comprising: Active patterns located on the substrate; Gate structure located on the active pattern; Channels spaced apart from each other in a direction perpendicular to the upper surface of the substrate, each channel being disposed in the gate structure; A barrier layer located on a portion of the active pattern on each side of the gate structure, the barrier layer not overlapping the uppermost surface of the active pattern; A source / drain layer located on the barrier layer, the source / drain layer being connected to the channel; Spacers located on the sidewalls of a first portion and a second portion of the gate structure, the first portion being located between the channels, and the second portion being located between the upper surface of the active pattern and the lowermost channel in the channel; and The air gap located between the spacer and the source / drain layer.

Images