Semiconductor device

Abstract

A semiconductor device includes a substrate having a first region and a second region, first fin groups spaced apart in a first direction on the first region, each of the first fin groups including adjacent first and second fins extending lengthwise in a second direction intersecting the first direction, and third to fifth fins spaced apart in a third direction on the second region, the third to fifth fins extending lengthwise in a fourth direction intersecting the third direction. The third to fifth fins have a first pitch, the first and second fins have a second pitch equal to or smaller than the first pitch, adjacent first fin groups have a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first fin and a width of the second fin are the same as a width of the third fin.

Description

[0001] Cross-reference to related applications

[0002] The entire contents of Korean Patent Application No. 10-2019-0057279, entitled "Semiconductor Device and Method for Fabricating The Same," filed with the Korean Intellectual Property Office on May 16, 2019, are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the same. More specifically, this disclosure relates to a semiconductor device with improved operating performance and a method for manufacturing the same. Background Technology

[0004] As one of the scaling techniques for increasing the density of semiconductor devices, a multi-gate transistor has been proposed, in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and the gate is formed on the surface of the silicon body. Since this multi-gate transistor utilizes a three-dimensional channel, it is easy to scale. Furthermore, current control capability can be improved even without increasing the gate length of the multi-gate transistor. In addition, the short-channel effect (SCE), where the channel potential is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate having a first region and a second region; a plurality of first fin groups arranged in the first region along a first direction, each first fin group having a first fin and a second fin that are adjacent to each other and extend in a second direction intersecting the first direction; and a third fin, a fourth fin, and a fifth fin arranged sequentially in the second region along a third direction, being adjacent to each other and extending in a fourth direction intersecting the third direction, wherein the third fin and the fourth fin and the fourth fin and the fifth fin are respectively disposed with a first fin pitch, the first fin and the second fin are disposed with a second fin pitch equal to or less than the first fin pitch, adjacent first fin groups are disposed with a first set of pitches, the first set of pitches being greater than three times and less than four times the first fin pitch, and the width of each of the first fin and the second fin is the same as the width of the third fin.

[0006] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate having a first region and a second region; a plurality of first fin groups arranged in the first region along a first direction, each first fin group having a first fin and a second fin that are adjacent to each other and extend in a second direction intersecting the first direction; and a plurality of second fin groups arranged in the second region along a third direction, each second fin group including a third fin, a fourth fin, and a fifth fin that are adjacent to each other and extend in a fourth direction intersecting the third direction, wherein the third fin and the fourth fin and the fourth fin and the fifth fin are respectively arranged with a first fin pitch, adjacent second fin groups are arranged with a first set pitch, the first set pitch being m times the first fin pitch, where m is a natural number equal to or greater than 4, adjacent first fin groups are arranged with a second set pitch, the second set pitch being greater than three times and less than four times the first fin pitch, and the width of each of the first fin and the second fin is the same as the width of the third fin.

[0007] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate having a first region and a second region; a first fin, a second fin, and a third fin arranged sequentially and adjacent to each other in a first direction and extending in a second direction intersecting the first direction in the first region; and a fourth fin, a fifth fin, and a sixth fin arranged sequentially and adjacent to each other in a third direction and extending in a fourth direction intersecting the third direction in the second region, wherein the fourth fin and the fifth fin are disposed with a first fin pitch, the fifth fin and the sixth fin are disposed with a second fin pitch, the second fin pitch being n times the first fin pitch, where n is a natural number equal to or greater than 2, the first fin and the second fin are disposed with a third fin pitch equal to or less than the first fin pitch, the second fin and the third fin are disposed with a fourth fin pitch greater than twice the first fin pitch and less than three times the first fin pitch, and the width of each of the first fin, the second fin, and the third fin is the same as the width of the fourth fin.

[0008] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a plurality of first mandrel patterns on a substrate; forming upper spacers on two sidewalls of the first mandrel patterns; forming lower spacers on two sidewalls of the upper spacers on which a pattern of the upper spacers is transferred; patterning the substrate using the lower spacers to form a first fin group and a first dummy fin group arranged alternately along a first direction; and removing the first dummy fin group, wherein the first fin group includes a first fin and a second fin arranged adjacent to each other along the first direction and extending in a second direction intersecting the first direction, the first dummy fin group includes a first dummy fin and a second dummy fin arranged adjacent to each other along the first direction and extending in the second direction, the first fin and the second fin being arranged with a first fin pitch, the second fin and the first dummy fin being arranged with the first fin pitch, the first dummy fin and the second dummy fin being arranged with a second fin pitch different from the first fin pitch, and the second dummy fin and the first fin being arranged with the first fin pitch.

[0009] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate including a first region and a second region; forming a plurality of first die patterns disposed at a first die pitch on the first region of the substrate; forming a plurality of second die patterns disposed at a second die pitch on the second region of the substrate, the first die pitch being smaller than the second die pitch; and performing a self-aligned quadruple patterning (SAQP) process using the first die patterns and the second die patterns to form a plurality of first fin groups on the first region and a plurality of second fin groups on the second region, wherein each first fin group includes a first fin and a second fin that are adjacent to each other and extend side by side, and each second fin group includes a third fin, a fourth fin, and a fifth fin that are adjacent to each other and extend side by side, the third fin and the fourth fin and the fourth fin and the fifth fin being disposed at a first fin pitch, and the second die pitch being four times the first fin pitch. Attached Figure Description

[0010] The features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0011] Figure 1 A layout diagram of a semiconductor device according to some embodiments is shown.

[0012] Figure 2 It shows along Figure 1 Cross-sectional views of lines A1-A1 and A2-A2.

[0013] Figure 3 A layout diagram of a semiconductor device according to some embodiments is shown.

[0014] Figure 4 It shows along Figure 3 Cross-sectional views of lines B1-B1 and B2-B2.

[0015] Figure 5 A layout diagram of a semiconductor device according to some embodiments is shown.

[0016] Figure 6 It shows along Figure 5 Cross-sectional views of lines C1-C1 and C2-C2.

[0017] Figure 7 It shows along Figure 5 Cross-sectional views of lines D1-D1 and D2-D2.

[0018] Figure 8 A conceptual diagram of a method for manufacturing a semiconductor device according to some embodiments is shown.

[0019] Figures 9 to 17 The various stages of a method for manufacturing a semiconductor device according to some embodiments are shown.

[0020] Figure 18 A conceptual diagram of a method for manufacturing a semiconductor device according to some embodiments is shown.

[0021] Figure 19 A conceptual diagram of a method for manufacturing a semiconductor device according to some embodiments is shown.

[0022] Figure 20 A conceptual diagram of a method for manufacturing a semiconductor device according to some embodiments is shown. Detailed Implementation

[0023] In the following text, reference will be made to Figure 1 and Figure 2 Describes a semiconductor device according to some embodiments.

[0024] Figure 1 It is a layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 Cross-sectional views of lines A1-A1 and A2-A2.

[0025] Reference Figure 1 and Figure 2According to some embodiments, a semiconductor device may include a substrate 100, a plurality of fins (e.g., first fins F1 to thirteenth fins F13), a first field insulating film 110, and a second field insulating film 115. The substrate 100 may include a first region I and a second region II, so the first field insulating film 110 and the second field insulating film 115 may be located in the first region I and the second region II, respectively.

[0026] Substrate 100 may include, for example, a base substrate and an epitaxial layer grown on the base substrate. For example, substrate 100 may consist only of a base substrate without an epitaxial layer. For example, substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, etc., and may be an SOI (semiconductor on insulator) substrate.

[0027] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be regions separated from each other or regions connected to each other. A portion of the plurality of fins may protrude from the substrate 100 in the first region I, while the remaining portion of the plurality of fins may protrude from the substrate in the second region II.

[0028] For example, such as Figure 2 As shown, multiple fins (e.g., first fin F1 to thirteenth fin F13) may protrude upward from the substrate 100. The multiple fins (e.g., first fin F1 to thirteenth fin F13) may be formed by etching a portion of the substrate 100, or may be an epitaxial layer grown from the substrate 100.

[0029] For example, a first portion of a plurality of fins (e.g., each of fins F1 to F6) may be formed on a first region I and extend side-by-side, and a second portion of a plurality of fins (e.g., each of fins F7 to F13) may be formed on a second region II and extend side-by-side. For example, fins F1 to F6 may be arranged sequentially spaced apart from each other along a first direction X1 and may extend longitudinally in a second direction Y1 intersecting the first direction X1. Additionally, for example, fins F7 to F13 may be arranged sequentially spaced apart from each other along a third direction X2 and may extend longitudinally in a fourth direction Y2 intersecting the third direction X2.

[0030] exist Figure 1 and Figure 2 In this illustration, the first direction X1 and the third direction X2 are shown as the same direction, but this is only for illustrative purposes and the present disclosure is not limited thereto. For example, the first direction X1 and the third direction X2 may be different from each other.

[0031] In some embodiments, the widths of the fins formed on the first region I may be the same as each other. For example, the widths W1 of the first fin F1, W2 of the second fin F1, and W3 of the third fin F3 may all be the same as each other. Here, width refers to the width in the first direction X1. In some embodiments, the widths W1 of the first fin F1, W2 of the second fin F1, and W3 of the third fin F3 may all be 10 nm or less.

[0032] However, it should be noted that in this specification, the term "same" not only refers to completely identical things, but also to minor differences that may occur due to process margins, etc. For example, in fine processes where the pitch between fins is 30 nm or less, an error range of ±1 nm can be considered the same range to those skilled in the art. As an example, a fin having the same width as a fin with a width of 7 nm can refer to a fin with a width of 6 nm to 8 nm.

[0033] In some embodiments, the widths of the fins formed on the second region II can be the same as each other. For example, the widths W7 of the seventh fin F7, W8 of the eighth fin F8, W9 of the ninth fin F9, and W10 of the tenth fin F10 can all be the same as each other. Here, width refers to the width in the third direction X2. In some embodiments, the widths W7 of the seventh fin F7, W8 of the eighth fin F8, W9 of the ninth fin F9, and W10 of the tenth fin F10 can all be 10 nm or less.

[0034] In some embodiments, the width of the fin formed on the first region I may be the same as the width of the fin formed on the second region II. For example, each of the widths W1 of the first fin F1, W2 of the second fin F1, and W3 of the third fin F3 may be the same as the width W7 of the seventh fin F7.

[0035] In some embodiments, multiple fins (e.g., first fin F1 to thirteenth fin F13) may be formed at the same level. As used herein, the term "same level" refers to a level formed by the same manufacturing process.

[0036] Multiple fins (e.g., first fins F1 to thirteenth fins F13) can constitute multiple first fin groups FG1 and multiple second fin groups FG2. The multiple first fin groups FG1 can be formed on a first region I of the substrate 100 and can be arranged along a first direction X1. The multiple second fin groups FG2 can be formed on a second region II of the substrate 100 and can be arranged along a third direction X2.

[0037] Each first fin group FG1 may include multiple fins. In some embodiments, each first fin group FG1 may include two fins. For example, one first fin group FG1 may include a first fin F1 and a second fin F2, another first fin group FG1 may include a third fin F3 and a fourth fin F4, and yet another first fin group FG1 may include a fifth fin F5 and a sixth fin F6.

[0038] Each second fin group FG2 may include multiple fins. In some embodiments, each second fin group FG2 may include more than three fins. For example, one second fin group FG2 may include fins 7 through 9, while another second fin group FG2 may include fins 10 through 12.

[0039] Each fin in each second fin group FG2 can be configured with the same pitch. For example, the seventh fin F7 and the eighth fin F8 can be configured with a first fin pitch FP1, and the eighth fin F8 and the ninth fin F9 can also be configured with a first fin pitch FP1. In some embodiments, the first fin pitch FP1 can be 30 nm or less. As mentioned above, in this specification, the term "same" means not only identical things, but also minor differences that may occur due to process margins, etc.

[0040] The adjacent second fin group FG2 can be set with a pitch that is an integer multiple of the first fin pitch FP1. For example, as Figure 2 As shown, adjacent second fin groups FG2 can be set relative to each other with a first pitch GP1. For example, the first pitch GP1 can be measured as the distance between the individual first fins in adjacent second fin groups FG2. For instance, adjacent second fin groups FG2 can be set with a first pitch GP1 that is m times the first fin pitch FP1 (where m is a natural number of 4 or greater), for example, GP1 = m·FP1 (where "m" is 4 or greater). Thus, as... Figure 2 As shown, the pitch between the outermost facing fins of adjacent second fin groups FG2 (i.e., the second fin pitch FP2) can be greater than the first fin pitch FP1. For example, the ninth fin F9 and the tenth fin F10 (i.e., the outermost facing fins of adjacent second fin groups FG2) can be set with a second fin pitch FP2, which is n times the first fin pitch FP1 (here, n is a natural number of 2 or greater), for example, FP2 = n·FP1 ("n" is 2 or greater). For example, in some embodiments, the first group pitch GP1 can be five times the first fin pitch FP1, and the second fin pitch FP2 can be three times the first fin pitch FP1.

[0041] Each fin in each first fin group FG1 can be set with the same pitch. For example, first fin F1 and second fin F2 can be set with a third fin pitch FP3, and third fin F3 and fourth fin F4 can be set with a third fin pitch FP3. Fins in the first fin group FG1 can be set with a pitch equal to or less than the first fin pitch FP1. For example, as... Figure 1 As shown, the first fin F1 and the second fin F2 can be set with a third fin pitch FP3 that is equal to the first fin pitch FP1.

[0042] For example, such as Figure 2 As shown, adjacent first fin groups FG1 can be set relative to each other with a second pitch GP2. Each first fin group FG1 can be set with a second pitch GP2 that is less than four times the first fin pitch FP1, for example, 3·FP1 < GP2 < 4·FP1. Thus, as... Figure 2 As shown, the pitch between the outermost facing fins of adjacent first fin groups FG1 (i.e., the fourth fin pitch FP4) can be greater than the first fin pitch FP1. For example, the second fin F2 and the third fin F3 (i.e., the outermost facing fins of adjacent first fin groups FG1) can be set with a fourth fin pitch FP4, which is greater than twice the first fin pitch FP1 and less than three times the first fin pitch FP1, for example, 2·FP1 < FP4 < 3·FP1.

[0043] A first field insulating film 110 may be formed on a first region I of the substrate 100. The first field insulating film 110 may cover at least some sidewalls of a portion of the plurality of fins located on the first region I (i.e., at least some sidewalls of the first fin F1 to the sixth fin F6). For example, as... Figure 2 As shown, some sidewalls of each of the first fins F1 to the sixth fin F6 can be defined by the first field insulating film 110. In addition, the first field insulating film 110 can separate the individual first fin groups FG1.

[0044] A second field insulating film 115 may be formed on a second region II of the substrate 100. The second field insulating film 115 may cover at least some sidewalls of a portion of the fins located on the second region II (i.e., at least some sidewalls of the seventh fin F7 to the thirteenth fin F13). For example, as... Figure 2 As shown, some sidewalls of each of the seventh fins F7 to the thirteenth fin F13 can be defined by a second field insulating membrane 115. Additionally, the second field insulating membrane 115 can separate the individual second fin groups FG2.

[0045] In some embodiments, the width FW1 of the first field insulating film 110 separating each first fin group FG1 can be smaller than the width FW2 of the second field insulating film 115 separating each second fin group FG2. For example, the second fin F2 and the third fin F3 can be configured with a fourth fin pitch FP4 that is less than three times the first fin pitch FP1, and the ninth fin F9 and the tenth fin F10 can be configured with a second fin pitch FP2 that is three times the first fin pitch FP1. Since the width W2 of the second fin F2 can be the same as the width W9 of the ninth fin F9, the width FW1 of the first field insulating film 110 separating the second fin F2 and the third fin F3 can be smaller than the width FW2 of the second field insulating film 115 separating the ninth fin F9 and the tenth fin F10.

[0046] Figure 3 It is a layout diagram of a semiconductor device according to some embodiments. Figure 4 It is along Figure 3 The cross-sectional views taken by lines B1-B1 and B2-B2 are shown. For ease of description, only brief descriptions or omissions of the above will be provided. Figures 1 to 2 The part described.

[0047] Reference Figure 3 and Figure 4 In a semiconductor device according to some embodiments, the fins in the first fin group FG1 are arranged with a pitch smaller than the first fin pitch FP1. For example, the first fin F1 and the second fin F2 may be arranged with a third fin pitch FP3 that is smaller than the first fin pitch FP1.

[0048] In some embodiments, each first fin group FG1 may be configured with a second pitch GP2, which is greater than three times and less than four times the first fin pitch FP1. For example, Figure 3 The second pitch GP2 can be with Figure 1 The second pitch GP2 is the same. In this case... Figure 3 The third fin pitch FP3 can be less than Figure 1 The first fin pitch FP3. Figure 3 The fourth fin pitch FP4 can be greater than Figure 1 The fourth fin segment FP4.

[0049] In some embodiments, Figure 3 The width FW1 of the first field insulating film 110 separating each first fin group FG1 can be greater than Figure 1 The width FW1 of the first field insulating film 110 that separates each first fin group FG1.

[0050] Figure 5 It is a layout diagram of a semiconductor device according to some embodiments. Figure 6 It is along Figure 5The cross-sectional view taken from lines C1-C1 and C2-C2. Figure 7 It is along Figure 5 The cross-sectional views taken by lines D1-D1 and D2-D2. For ease of description, only brief descriptions or omissions of the above will be provided. Figure 1 and Figure 2 The part described.

[0051] Reference Figures 5 to 7 According to some embodiments, the semiconductor device may further include a first gate electrode 130, a first gate dielectric film 120, a first gate spacer 135, a first source / drain region 140, a first interlayer insulating film 150, a second gate electrode 230, a second gate dielectric film 220, a second gate spacer 235, a second source / drain region 240, and a second interlayer insulating film 250.

[0052] The first gate electrode 130 may be formed on the first fin F1 to the sixth fin F6. The first gate electrode 130 may extend in a direction intersecting the first fin F1 to the sixth fin F6. For example, the first gate electrode 130 may extend along a first direction X1.

[0053] The second gate electrode 230 can be formed on the seventh fin F7 to the thirteenth fin F13. The second gate electrode 230 can extend in the direction intersecting the seventh fin F7 to the thirteenth fin F13. For example, the second gate electrode 230 can extend along a third direction X2.

[0054] The first gate electrode 130 and the second gate electrode 230 may include a conductive material. In some embodiments, the first gate electrode 130 and the second gate electrode 230 may be formed at the same level. For example, the first gate electrode 130 and the second gate electrode 230 may have the same material configuration.

[0055] The first gate dielectric film 120 may be disposed between the first fin F1 to the sixth fin F6 and the first gate electrode 130. For example, the first gate dielectric film 120 may extend along the sidewall and upper surface of each of the first fins F1 to the sixth fin F6. In some embodiments, the first gate dielectric film 120 may also be disposed between the first field insulating film 110 and the first gate electrode 130. For example, the first gate dielectric film 120 may further extend along the upper surface of the first field insulating film 110.

[0056] The second gate dielectric film 220 may be disposed between the seventh fin F7 to the thirteenth fin F13 and the second gate electrode 230. For example, the second gate dielectric film 220 may extend along the sidewalls and upper surfaces of the respective seventh fin F7 to the thirteenth fin F13. In some embodiments, the second gate dielectric film 220 may also be disposed between the second field insulating film 115 and the second gate electrode 230. For example, the second gate dielectric film 220 may further extend along the upper surface of the second field insulating film 115.

[0057] The first gate dielectric film 120 and the second gate dielectric film 220 may include at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a high-k material with a dielectric constant higher than that of silicon oxide.

[0058] The semiconductor device according to some embodiments may further include a first interface film 125 and a second interface film 225. The first interface film 125 may be disposed between the first fin F1 to the sixth fin F6 and the first gate dielectric film 120, and the second interface film 225 may be disposed between the seventh fin F7 to the thirteenth fin F13 and the second gate dielectric film 220.

[0059] The first gate spacer 135 may extend along the two sidewalls of the first gate electrode 130. The second gate spacer 235 may extend along the two sidewalls of the second gate electrode 230.

[0060] The first source / drain region 140 can be formed in the first fin F1 to the sixth fin F6. The second source / drain region 240 can be formed in the seventh fin F7 to the thirteenth fin F13.

[0061] The first interlayer insulating film 150 may be formed on the first region I of the substrate 100. The first interlayer insulating film 150 may cover the first field insulating film 110, the first source / drain region 140 and the first gate spacer 135.

[0062] The second interlayer insulating film 250 can be formed on the second region II of the substrate 100. The second interlayer insulating film 250 can cover the second field insulating film 115, the second source / drain region 240, and the second gate spacer 235.

[0063] In the following text, reference will be made to Figures 8 to 17 Describes a semiconductor device according to some embodiments. Figure 8 This is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. Figures 9 to 17 It is based on Figure 8 This diagram illustrates intermediate stages of a method for manufacturing semiconductor devices. For ease of description, only brief descriptions or omissions will be provided above. Figure 1 and Figure 2 The part described.

[0064] like Figures 8 to 17 As shown, a method for manufacturing a semiconductor device according to some embodiments may include performing a self-aligned quadruple patterning (SAQP) process using a first mandrel pattern 300 and a second mandrel pattern 400. For example, the first mandrel pattern 300 and the second mandrel pattern 400 may be used to form a first upper spacer 310 and a second upper spacer 410; the first upper spacer 310 and the second upper spacer 410 may be used to form a first lower spacer 320 and a second lower spacer 420; the first lower spacer 320 and the second lower spacer 420 may be used to form a plurality of first fin groups FG1 and a plurality of second fin groups FG2.

[0065] For details, refer to Figure 8 and Figure 9 A hard mask film 500 and a sacrificial film 510 can be sequentially formed on a substrate 100. Subsequently, a plurality of first mandrel patterns 300 can be formed on a first region I, and a plurality of second mandrel patterns 400 can be formed on a second region II. The first mandrel patterns 300 and the second mandrel patterns 400 can be formed, for example, on the sacrificial film 510.

[0066] For example, the multiple layers of the hard mask film 500 may include at least one of the following: silicon-containing materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, TEOS (tetraethyl orthosilicate) or polycrystalline silicon), carbon-containing materials (e.g., ACL (amorphous carbon layer) or SOH (spin-coated hard mask)) or metals.

[0067] In some embodiments, the hard mask film 500 may be formed of a multilayer film. For example, the lower layer of the multilayer film may be formed of a silicon nitride layer, the intermediate layer may be formed of silicon oxide, and the upper layer may be formed of polysilicon. The lower layer may further include, for example, a thin layer of silicon oxide beneath the silicon nitride. However, this is merely an example, and the technical concept of this disclosure is not limited thereto.

[0068] The sacrificial film 510 may include, for example, polycrystalline silicon, amorphous carbon layer (ACL), or spin-coated hard mask (SOH).

[0069] The formation of the first mold pattern 300 and the second mold pattern 400 can be performed, for example, by a photolithography process. For example, the first mold pattern 300 and the second mold pattern 400 can be patterns on which photoresist has been transferred.

[0070] In some embodiments, the pitch between the first mandrel patterns 300 may be smaller than the pitch between the second mandrel patterns 400. For example, the second mandrel patterns 400 may be set with a first mandrel pitch MP1, and the first mandrel patterns 300 may be set with a second mandrel pitch MP2 that is smaller than the first mandrel pitch MP1.

[0071] In some embodiments, such as Figure 8 As shown, the first mandrel pitch MP1 can be determined to be four times the first fin pitch FP1, and the second mandrel pitch MP2 can be determined to be less than four times the first fin pitch FP1. For example, the second mandrel pitch MP2 can be determined to be greater than three times the first fin pitch FP1 and less than four times the first fin pitch FP1.

[0072] In some embodiments, the width AW1 of the first core pattern 300 may be the same as the width AW2 of the second core pattern 400.

[0073] Reference Figure 8 and Figure 10 A first upper spacer 310 can be formed on the two sidewalls of the first core mold pattern 300, and a second upper spacer 410 can be formed on the two sidewalls of the second core mold pattern 400.

[0074] For example, a first spacer film can be formed extending along the sidewalls and top surface of the first mandrel pattern 300, the sidewalls and top surface of the second mandrel pattern 400, and the top surface of the sacrificial film 510. The first spacer film can be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like. Subsequently, an anisotropic etching process can be performed. Therefore, a first upper spacer 310 can be formed on the two sidewalls of the first mandrel pattern 300, and a second upper spacer 410 can be formed on the two sidewalls of the second mandrel pattern 400. The first upper spacer 310 and the second upper spacer 410 can comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0075] The width BW1 of the first upper spacer 310 can be appropriately adjusted to form the first fin group FG1 and the first dummy fin group DFG1. Similarly, the width BW2 of the second upper spacer 410 can be appropriately adjusted to form the second fin group FG2 and the second dummy fin group DFG2. In some embodiments, the width BW1 of the first upper spacer 310 may be the same as the width BW2 of the second upper spacer 410.

[0076] Subsequently, referring to Figure 11 It can remove the first core mold pattern 300 and the second core mold pattern 400 on the sacrificial film 510.

[0077] Reference Figure 8 and Figure 12The sacrificial film 510 can be patterned using the first upper spacer 310 and the second upper spacer 410 as etching masks. Therefore, a first sacrificial pattern 510P1 can be formed on the hard mask film 500 in the first region I, and a second sacrificial pattern 510P2 can be formed on the hard mask film 500 in the second region II. That is, the first sacrificial pattern 510P1 can be a pattern on which the first upper spacer 310 is transferred, and the second sacrificial pattern 510P2 can be a pattern on which the second upper spacer 410 is transferred. After forming the first sacrificial pattern 510P1 and the second sacrificial pattern 510P2, the first upper spacer 310 and the second upper spacer 410 can be removed.

[0078] Reference Figure 8 and Figure 13 A first lower spacer 320 can be formed on the two sidewalls of the first sacrificial pattern 510P1, and a second lower spacer 420 can be formed on the two sidewalls of the second sacrificial pattern 510P2.

[0079] For example, a second spacer film can be formed extending along the sidewalls and top surface of the first sacrificial pattern 510P1, the sidewalls and top surface of the second sacrificial pattern 510P2, and the top surface of the sacrificial film 510. Subsequently, an anisotropic etching process can be performed. Therefore, a first lower spacer 320 can be formed on the two sidewalls of the first sacrificial pattern 510P1, and a second lower spacer 420 can be formed on the two sidewalls of the second sacrificial pattern 510P2. The first lower spacer 320 and the second lower spacer 420 can comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0080] The width CW1 of the first lower spacer 320 can be appropriately adjusted to form the first fin group FG1 and the first dummy fin group DFG1. Similarly, the width CW2 of the second lower spacer 420 can be appropriately adjusted to form the second fin group FG2 and the second dummy fin group DFG2. In some embodiments, the width CW1 of the first lower spacer 320 may be the same as the width CW2 of the second lower spacer 420.

[0081] Subsequently, referring to Figure 14 It can remove the first sacrificial pattern 510P1 and the second sacrificial pattern 510P2 on the hard mask film 500.

[0082] Subsequently, referring to Figure 15 The hard mask film 500 can be patterned using the first sacrificial pattern 510P1 and the second sacrificial pattern 510P2 as etching masks. Therefore, the first hard mask pattern 500P1 can be formed on the substrate 100 in the first region I, and the second hard mask pattern 500P2 can be formed on the substrate 100 in the second region II.

[0083] After forming the first hard mask pattern 500P1 and the second hard mask pattern 500P2, the first lower spacer 320 and the second lower spacer 420 can be removed.

[0084] Reference Figure 8 and Figure 16 The substrate 100 can be patterned using the first hard mask pattern 500P1 and the second hard mask pattern 500P2 as etching masks. Therefore, multiple fins F1 to F13 and DF1 to DF4 can be formed on the substrate 100.

[0085] In some embodiments, the plurality of fins F1 to F6 and DF1, DF2 formed on the first region I of the substrate 100 can be divided into a plurality of first fin groups FG1 and a plurality of first dummy fin groups DFG1. Each first fin group FG1 may consist of a plurality of fins. In some embodiments, each first fin group FG1 may include two fins. In some embodiments, as Figure 8 As shown, the first fin group FG1 can be formed in the area overlapping with the first core mold pattern 300.

[0086] In some embodiments, the first fin group FG1 can be a group of fins with the same pitch as the fins adjacent to it on both sides. For example, the first fin F1 in the first fin group FG1 can be configured such that both the second dummy fin DF2 and the second fin F2 adjacent to it are separated by a third fin pitch FP3. Alternatively, for example, as shown in the figure, the second fin F2 in the first fin group FG1 can be configured such that both the first fin F1 and the first dummy fin DF1 adjacent to it are separated by a third fin pitch FP3.

[0087] Each first dummy fin group DFG1 can be arranged between corresponding first fin groups FG1. For example, multiple first fin groups FG1 and multiple first dummy fin groups DFG1 can be arranged alternately along a first direction X1. In some embodiments, such as Figure 8 As shown, the first dummy fin group DFG1 can be formed in an area that does not overlap with the first core mold pattern 300.

[0088] In some embodiments, the first dummy fin group DFG1 can be a group of fins whose pitch differs from the pitch of the fins on its adjacent sides. For example, such as Figure 16As shown, the first dummy fin DF1 in the first dummy fin group DFG1 can be configured such that it is a distance of three fin pitches FP3 from the second fin F2 adjacent to it on one side, and can also be configured such that it is a distance of five fin pitches FP5 from the second dummy fin F2 adjacent to it on the other side, where the fifth fin pitch FP5 is smaller than the third fin pitch FP3. Alternatively, for example, as shown in the figure, the second dummy fin DF2 in the first dummy fin group DFG1 can be configured such that it is a distance of five fin pitches FP5 from the first dummy fin DF1 adjacent to it on one side, and can also be configured such that it is a distance of three fin pitches FP3 from the third fin F3 adjacent to it on the other side.

[0089] Because the pitches of the fins DF1 and DF2 constituting the first dummy fin group DFG1 are different from those of the fins on either side, a load effect may occur during the transfer process from the first lower spacer 320. In contrast, because the pitches of the fins F1 to F6 constituting the first fin group FG1 are the same as those of the fins on either side, no load effect occurs during the transfer process from the first lower spacer 320.

[0090] The plurality of fins F7 to F13, DF3, and DF4 formed on the second region II of the substrate 100 can be divided into a plurality of second fin groups FG2 and a plurality of second dummy fin groups DFG2. Each second fin group FG2 may consist of a plurality of fins. In some embodiments, each second fin group FG2 may include more than three fins. Each second dummy fin group DFG2 may be arranged between corresponding second fin groups FG2. For example, the plurality of second fin groups FG2 and the plurality of second dummy fin groups DFG2 may be arranged alternately along a third direction X2.

[0091] The multiple fins F7 to F13, DF3, and DF4 formed on the second region II of the substrate 100 can be arranged with the same pitch. For example, as Figure 16 As shown, the seventh to ninth fins F7 to F9, the third dummy fin DF3, the fourth dummy fin DF4, and the tenth fin F10 can all be set with the first fin pitch FP1. Since each fin F7 to F13, DF3, and DF4 formed on the second region II of the substrate 100 has the same pitch as the fins on both sides, no loading effect will occur during the transfer process from the second lower spacer 420.

[0092] In some embodiments, the fins in the first fin group FG1 may be configured with a pitch equal to or less than the first fin pitch FP1. For example, as shown in the figure, the third fin pitch FP3 may be the same as the first fin pitch FP1.

[0093] After forming multiple fins F1 to F13 and DF1 to DF4, the first hard mask pattern 500P1 and the second hard mask pattern 500P2 can be removed.

[0094] Reference Figure 8 and Figure 17 The first dummy fin group DFG1 and the second dummy fin group DFG2 can be removed. This can be achieved, for example, by a fin cutting process.

[0095] As described above, since no load effect occurs during the process of transferring the first fin group FGl from the first lower spacer 320, the widths of the fins formed on the first region I can be the same. For example, the widths W1 to W3 of the first fin F1 to the third fin F3 can be the same.

[0096] Furthermore, as described above, since no load effect occurs during the process of transferring the second fin group FG2 from the second lower spacer 420, the widths of the fins formed on the second region II can be the same. For example, the widths W7, W8, W9, and W10 of the seventh fin F7, eighth fin F8, ninth fin F9, and tenth fin F10 can be the same.

[0097] Furthermore, in some embodiments, since the width CW1 of the first lower spacer 320 can be the same as the width CW2 of the second lower spacer 420, the width of the fin formed on the first region I can be the same as the width of the fin formed on the second region II. For example, the widths W1, W2, and W3 of the first fin F1, the second fin F2, and the third fin F3 can be the same as the width W7 of the seventh fin F7.

[0098] Subsequently, referring to Figure 1 A first field insulating film 110 and a second field insulating film 115 can be formed on the substrate 100. For example, the first field insulating film 110 can be formed on a first region I of the substrate 100 to cover the side surfaces of the first fin F1 to the sixth fin F6, and the second field insulating film 115 can be formed on a second region II of the substrate 100 to cover the side surfaces of the seventh fin F7 to the thirteenth fin F13.

[0099] Subsequently, a recessing process is performed on the upper portion of the first field insulating film 110 and the upper portion of the second field insulating film 115, exposing the upper portions of the first fins F1 to the sixth fins F6 and the upper portions of the seventh fins F7 to the thirteenth fins F13. The recessing process may include, for example, a selective etching process. Therefore, the first field insulating film 110 may cover at least some of the sidewalls of the first fins F1 to the sixth fins F6. Additionally, the second field insulating film 115 may cover at least some of the sidewalls of the seventh fins F7 to the thirteenth fins F13.

[0100] Methods for manufacturing semiconductor devices according to some embodiments can provide semiconductor devices with reduced cell sizes that are unaffected by loading effects. For example, the first fin pitch FP1 of the first group pitch GP1 of the first fin group FG1 formed on the first region I of the substrate 100 can be reduced by a factor of four. Therefore, the size of the cell including the first fin group FG1 can be reduced. In addition, since the fins constituting the first fin group FG1 (e.g., the first fin F1 and the second fin F2) can be manufactured without being affected by loading effects, the increase in CD (critical dimensions; e.g., W1 and W2) due to loading effects can be prevented. For example, the width W1 of the first fin F1 and the width W2 of the second fin F2 can be the same as the width W7 of the seventh fin F7. As a result, the short-channel effect (SCE) of the cell including the first fin group FG1 can be effectively suppressed, and a semiconductor device with improved operating performance can be provided.

[0101] Figure 18 This is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. For ease of description, only brief descriptions or omissions of references will be provided. Figures 1 to 17 The part described.

[0102] Reference Figure 18 In a method of manufacturing a semiconductor device according to some embodiments, a first fin group FG1 may be formed in a region that does not overlap with the first die pattern 300, and a first dummy fin group DFG1 may be formed in a region that overlaps with the first die pattern 300.

[0103] In some embodiments, the width AW3 of the first core mold pattern 300 may be smaller than the width AW3 of the second core mold pattern 400. Therefore, the first dummy fin DF1 may be positioned a third fin pitch FP3 away from the second fin F2 adjacent to it on one side, and may be positioned a fifth fin pitch FP5 away from the second dummy fin DF2 adjacent to it on the other side, where the fifth fin pitch FP5 is smaller than the third fin pitch FP3. Additionally, the second dummy fin DF2 may be positioned a fifth fin pitch FP5 away from the first dummy fin DF1 adjacent to it on one side, and may be positioned a third fin pitch FP3 away from the third fin F3 adjacent to it on the other side.

[0104] However, in some embodiments, the first fin group FG1 may be composed of fins having the same pitch as the fins on its adjacent sides. For example, the first fin F1 may be configured such that both the second dummy fin DF2 and the second fin F2 adjacent to it are separated by a third fin pitch FP3. Alternatively, for example, the second fin F2 may be configured such that both the first fin F1 and the first dummy fin DF1 adjacent to it are separated by a third fin pitch FP3.

[0105] In some embodiments, the third fin pitch FP3 may be the same as the first fin pitch FP1. In some embodiments, the width BW3 of the first upper spacer 310 may be the same as the width BW2 of the second upper spacer 410. In some embodiments, the width CW3 of the first lower spacer 320 may be the same as the width CW2 of the second lower spacer 420.

[0106] Figure 19 This is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. For ease of description, only brief descriptions or omissions of references will be provided. Figures 1 to 17 The part described.

[0107] Reference Figure 19 In a method of manufacturing a semiconductor device according to some embodiments, the width AW4 of the first die pattern 300 may be smaller than the width AW2 of the second die pattern 400.

[0108] In some embodiments, the width BW4 of the first upper spacer 310 can be appropriately adjusted to form the first fin group FG1 and the first dummy fin group DFG1. For example, the width BW4 of the first upper spacer 310 can be smaller than the width BW2 of the second upper spacer 410.

[0109] As a result, the first fin group FG1 can be composed of fins with the same pitch as the fins on its two adjacent sides. For example, the first fin F1 can be configured such that both the second dummy fin DF2 and the second fin F2 adjacent to it are separated by a sixth fin pitch FP6. Similarly, for example, the second fin F2 can be configured such that both the first fin F1 and the first dummy fin DF1 adjacent to it are separated by a sixth fin pitch FP6.

[0110] However, the first dummy fin group DFG1 can be composed of fins with different pitches from the fins on its two adjacent sides. For example, the first dummy fin DF1 can be positioned at a distance of six fin pitches FP6 from the second fin F2, and can be positioned at a distance of seven fin pitches FP7 from the second dummy fin DF2, where the seventh fin pitch FP7 is greater than the sixth fin pitch FP6. Similarly, for example, the second dummy fin DF2 can be positioned at a distance of seven fin pitches FP7 from the first dummy fin DF1, and can be positioned at a distance of six fin pitches FP6 from the third fin F3.

[0111] In some embodiments, the sixth fin pitch FP6 may be smaller than the first fin pitch FP1. Therefore, a semiconductor device comprising fins having a further reduced fin pitch can be provided. In some embodiments, the width CW4 of the first lower spacer 320 may be the same as the width CW2 of the second lower spacer 420.

[0112] Figure 20This is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. For ease of description, only brief descriptions or omissions of references will be provided. Figures 1 to 18 The part described.

[0113] Reference Figure 20 In a method of manufacturing a semiconductor device according to some embodiments, the width AW5 of the first die pattern 300 may be greater than the width AW2 of the second die pattern 400.

[0114] In some embodiments, the first fin group FG1 may be formed in a region that does not overlap with the first core mold pattern 300, and the first dummy fin group DFG1 may be formed in a region that overlaps with the first core mold pattern 300.

[0115] In some embodiments, the width BW5 of the first upper spacer 310 can be appropriately adjusted to form the first fin group FG1 and the first dummy fin group DFG1. For example, the width BW5 of the first upper spacer 310 can be smaller than the width BW2 of the second upper spacer 410.

[0116] As a result, the first fin group FG1 can be composed of fins with the same pitch as the fins on its two adjacent sides. For example, the first fin F1 can be configured such that it is at a distance of eight fin pitches FP8 from both the second dummy fin DF2 and the second fin F2 adjacent to it. In addition, for example, the second fin F2 can be configured such that it is at a distance of eight fin pitches FP8 from both the first fin F1 and the first dummy fin DF1 adjacent to it.

[0117] However, the first dummy fin group DFG1 can be composed of fins with different pitches on its two adjacent sides. For example, the first dummy fin DF1 can be positioned at an eighth fin pitch FP8 from the second fin F2, and at a ninth fin pitch FP9 from the second dummy fin DF2, where the ninth fin pitch FP9 is greater than the eighth fin pitch FP8. Alternatively, for example, the second dummy fin DF2 can be positioned at a ninth fin pitch FP9 from the first dummy fin DF1, and at an eighth fin pitch FP8 from the third fin F3.

[0118] In some embodiments, the eighth fin pitch FP8 may be smaller than the first fin pitch FP1. Therefore, a semiconductor device comprising fins having a further reduced fin pitch can be provided. In some embodiments, the width CW5 of the first lower spacer 320 may be the same as the width CW2 of the second lower spacer 420.

[0119] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first region and a second region; A plurality of first fin groups, the plurality of first fin groups being spaced apart from each other in a first direction in the first region, wherein there are no elements parallel to the plurality of first fin groups and connected to the substrate between any two adjacent first fin groups, and each of the plurality of first fin groups includes a first fin and a second fin that are adjacent to each other and extend longitudinally in a second direction intersecting the first direction. as well as A third, fourth, and fifth fin are spaced apart from each other along a third direction in the second region. The third, fourth, and fifth fins extend longitudinally in a fourth direction intersecting the third direction. The third, fourth, and fifth fins constitute a second fin group arranged along the third direction, and multiple second fin groups are arranged along the third direction. The third fin and the fourth fin, and the fourth fin and the fifth fin, are respectively positioned by a first fin pitch. The first fin and the second fin are positioned with a second fin pitch that is equal to or less than the pitch of the first fin. Among the plurality of first fin groups, adjacent first fin groups are positioned by a first set of pitches, wherein the first set of pitches is greater than three times and less than four times the first fin pitch. Wherein, adjacent second fin groups among the plurality of second fin groups are positioned by a second set of pitches, the second set of pitches being m times the first fin pitch, where m is a natural number equal to or greater than 4, and The width of each of the first fin and the second fin is the same as the width of the third fin.

2. The semiconductor device according to claim 1, wherein, The third fin, the fourth fin, and the fifth fin have the same width.

3. The semiconductor device according to claim 1, wherein, There are no elements parallel to and connected to the substrate between any two adjacent second fin groups in the plurality of second fin groups.

4. The semiconductor device according to claim 1, further comprising: A first field insulating film located on the first region, the first field insulating film covering at least a portion of the sidewall of each of the first fin and the second fin; as well as A second field insulating film is located on the second region, the second field insulating film covering at least a portion of the sidewall of each of the third, fourth and fifth fins.

5. The semiconductor device according to claim 1, further comprising: A first gate electrode extends along the first direction on the first fin and the second fin; as well as The second gate electrode extends along the third direction on the third, fourth, and fifth fins.

6. The semiconductor device according to claim 1, wherein, The first fin pitch is 30 nm or less.

7. The semiconductor device according to claim 1, wherein, The width of the third fin is 10 nm or less.

8. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first region and a second region; A plurality of first fin groups, the plurality of first fin groups being spaced apart from each other in a first direction in the first region, wherein there are no elements parallel to the plurality of first fin groups and connected to the substrate between any two adjacent first fin groups, and each of the plurality of first fin groups includes a first fin and a second fin that are adjacent to each other and extend longitudinally in a second direction intersecting the first direction. A plurality of second fin groups, the plurality of second fin groups being spaced apart from each other along a third direction in the second region, each of the plurality of second fin groups including a third fin, a fourth fin and a fifth fin that are adjacent to each other and extend longitudinally in a fourth direction intersecting the third direction; A first gate electrode extends continuously over the plurality of first fin groups along the first direction; as well as A second gate electrode, which extends continuously in a third direction above the plurality of second fin groups. The third fin and the fourth fin, and the fourth fin and the fifth fin, are respectively positioned by a first fin pitch. Wherein, adjacent second fin groups among the plurality of second fin groups are positioned by a first set of pitches, the first set of pitches being m times the first fin pitch, where m is a natural number greater than or equal to 4. Among these, adjacent first fin groups are positioned by a second set of pitches, wherein the second set of pitches is greater than three times and less than four times the pitch of the first fin, and The width of each of the first fin and the second fin is the same as the width of the third fin.

9. The semiconductor device according to claim 8, further comprising: A first field insulating film located on the first region, the first field insulating film separating adjacent first fin groups among the plurality of first fin groups; as well as A second field insulating film located on the second region, the second field insulating film separating adjacent second fin groups among the plurality of second fin groups.

10. The semiconductor device according to claim 9, wherein, There are no elements parallel to and connected to the substrate between any two adjacent second fin groups in the plurality of second fin groups.

11. The semiconductor device according to claim 9, wherein, The first fin and the second fin are positioned at a second fin pitch equal to the first fin pitch, and the width of the first field insulating film between adjacent first fin groups in the plurality of first fin groups is smaller than the width of the second field insulating film between adjacent second fin groups in the plurality of second fin groups.

12. The semiconductor device according to claim 8, wherein, The first fin and the second fin are configured with a second fin pitch that is smaller than the pitch of the first fin.

13. A semiconductor device, said semiconductor device comprising: A substrate, the substrate comprising a first region and a second region; A first fin, a second fin, and a third fin, the first fin, the second fin, and the third fin being spaced apart from each other in a first direction in the first region, and the first fin, the second fin, and the third fin extending longitudinally in a second direction intersecting the first direction; as well as The fourth, fifth, and sixth fins are spaced apart from each other along a third direction in the second region, and extend longitudinally in a fourth direction intersecting the third direction. The fourth fin and the fifth fin are positioned by the first fin pitch. The fifth fin and the sixth fin are positioned by a second fin pitch, which is n times the first fin pitch, where n is a natural number equal to or greater than 2. The first fin and the second fin are positioned with a third fin pitch that is smaller than the pitch of the first fin. The second fin and the third fin are positioned with a fourth fin pitch that is greater than twice the first fin pitch and less than three times the first fin pitch, wherein the fourth fin pitch is less than the second fin pitch. The width of each of the first fin, the second fin, and the third fin is the same as the width of the fourth fin.

14. The semiconductor device of claim 13, wherein the fourth fin, the fifth fin, and the sixth fin all have the same width.

15. The semiconductor device according to claim 13, wherein, The second fin pitch is three times the first fin pitch.

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