Level shifter for spmi bus

Abstract

A bidirectional level shifter with fast rise and fall times and low current leakage is suitable for use with devices connected using an SPMI bus. The level shifter transfers signals between a first voltage domain and a second voltage domain operating at different voltage levels. The level shifter has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is between a first voltage source and the first terminal, and a second switch is between a second voltage source and the second terminal. The first switch and the second switch are operable to reduce current leakage of the level shifter.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to a mixed voltage logic circuit, and more particularly to a level shifter circuit. BACKGROUND

[0002] Voltage level shifters or level shifters are circuits that address voltage incompatibilities between different parts of a system operating in different voltage domains, which is very common in today's systems, especially in systems interfacing with legacy devices. Level shifters can be designed to span a wide range of voltages, frequencies, bit widths, and IO types (open-drain or push-pull) at various performance levels. Level shifters are also designed for standard interfaces such as I2C bus, SD card, and SIM card.

[0003] For mobile devices that operate using energy stored in a battery, low power and low leakage are important circuit design considerations. Today's mobile devices typically include an SPMI (System Power Management Interface) bus, which is a 2-wire bidirectional interface for communicating signals (SDATA and SCLK) between multiple master devices and multiple slave devices.

[0004] This would be beneficial to have a fast, accurate level shifter suitable for use with an SPMI bus. SUMMARY

[0005] In one embodiment, the present invention provides a level shifter that receives an input signal at an input terminal and generates an output signal at an output terminal. The level shifter includes a first monoflop circuit, a second monoflop circuit, a third monoflop circuit, and a fourth monoflop circuit, wherein the first and third monoflop circuits each have an output connected to the output terminal, and the second and fourth monoflop circuits each have an output connected to the input terminal. A first transistor has a source connected to a first voltage source, a drain connected to the input terminal, and a gate connected to an input of the first monoflop circuit. A second transistor has a drain connected to a second voltage source different from the first voltage source, a source connected to the output terminal, and a gate connected to an input of the second monoflop circuit. A third transistor has a source connected to the input terminal, a drain connected to ground, and a gate connected to an input of the third monoflop circuit. A fourth transistor has a source connected to ground, a drain connected to the output terminal, and a gate connected to an input of the fourth monoflop circuit. A first switch is connected in parallel with the first transistor and has a first terminal connected to the first voltage source and a second terminal connected to the input terminal. A second switch is connected in parallel with the second transistor and has a first terminal connected to the second voltage source and a second terminal connected to the output terminal.

[0006] In another embodiment, the invention is an output driver circuit for a level shifter, where the level shifter receives an input signal at an input terminal and generates an output signal at an output terminal. The output driver circuit includes first and second monostable circuits and first through tenth transistors. Each of the first and second monostable circuits has an input and an output. The first transistor has a source connected to a first voltage source (VCCA) and a gate that receives a buffered version of the input signal. The second transistor has a source connected to ground and a gate that receives the buffered version of the input signal. The third and fourth transistors are connected in series, with the source of the third transistor connected to the first voltage source (VCCA), the source of the fourth transistor connected to the drain of the second transistor, the drains of the third and fourth transistors connected together, and the gates of the third and fourth transistors receiving an output enable signal (OE). The fifth and sixth transistors are connected in series between the first voltage source (VCCA) and ground, with the drains of the fifth and sixth transistors connected together and to the outputs of the first and second monostable circuits. The seventh and eighth transistors are connected in series between the first voltage source (VCCA) and ground, with the seventh and eighth transistors having drains connected together and gates connected to respective ones of the outputs of the first and second monostable circuits. The ninth transistor has a source connected to the input terminal, a drain connected to the output terminal, and a gate activated by the output enable signal (OE). The tenth transistor has a source connected to the first voltage source (VCCA), a drain connected to the output terminal, and a gate activated by the output enable signal (OE).

[0007] In yet another embodiment, the invention provides a system comprising: a first voltage domain connected to a first voltage source to operate at a first voltage level (VCCA); a second voltage domain connected to a second voltage source to operate at a second voltage level (VCCB) different from the first voltage level; and a level shifter between the first and second voltages to transfer signals therebetween such that a voltage level of a first signal A transferred from the first voltage domain to the second voltage domain changes to the second voltage level and a voltage level of a second signal B transferred from the second voltage domain to the first voltage domain changes from the second voltage level to the first voltage level. The level shifter includes a first terminal that receives the first signal A and outputs the second signal B, and a second terminal that receives the second signal B and outputs the first signal A. A first switch is between the first voltage source and the first terminal, and a second switch is between the second voltage source and the second terminal. The first and second switches are operable to reduce current leakage of the level shifter.

[0008] Various embodiments of the present invention provide a level shifter. The level shifter has low leakage current and is fast enough (fast rise and fall times) to be suitable for use in a system that uses the SPMI protocol to allow multiple master devices to communicate with multiple slave devices. BRIEF DESCRIPTION OF DRAWINGS

[0009] The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.

[0010] Figure 1 is a schematic block diagram of a system having a master device that communicates with multiple slave devices using the SPMI protocol;

[0011] Figure 2 is a schematic circuit diagram of a known open-drain level shifter;

[0012] Figure 3 is a truth table for logical states for an SPMI bus;

[0013] Figure 4 is a simplified schematic diagram of a single-channel level shifter according to a preferred embodiment of the present invention; and

[0014] Figure 5 is a schematic circuit diagram of an output driver circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The detailed description of the drawings is intended for purposes of illustration only and is not intended to represent the only form of the present invention. It is understood that the same or equivalent functions can be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention.

[0016] The terms "input" and "output" are used for convenience and do not necessarily mean that the signal or terminal with that designation is strictly one or the other. For example, in a bidirectional level shifter, sometimes the A terminal is the input and in that case the B terminal is the output, but at other times the B is the input and A is the output. Thus, although the A terminal can be labeled as an input terminal, one skilled in the art will understand that the A terminal is an output terminal at other times.

[0017] The term "one-shot" refers to a one-shot multivibrator, which is a circuit that generates an output pulse of a predetermined width in response to a trigger signal. As will be appreciated by those skilled in the art, such a circuit can be implemented using a pair of transistors connected to a resistor and a capacitor or an operational amplifier with feedback to inputs A and B. One-shot circuits are standard circuits used in level shifters. The present invention will work with any one-shot circuit, so a preferred one-shot circuit design is not provided.

[0018] Referring now to Figure 1 , a schematic block diagram of a system 10 is shown having a master device 12 operating at 1.2V that communicates with a first slave device 14 also operating at 1.2V and a plurality of second slave devices 16 operating at 1.8V. The master device 12 communicates directly with the first slave device 14 because they both operate at 1.2V. However, because the master device 12 and the second slave devices 16 have different operating voltages, signals passed between the master device 12 and the second slave devices 16 are sent through a level shifter 18 according to an embodiment of the present invention. The level shifter 18 converts the voltage of signals provided by the master device 12 from 1.2V to 1.8V and converts the voltage of signals provided by the second slave devices 16 to the master device 12 from 1.8V to 1.2V. The master device 12 communicates with the second slave devices 16 using a bus 20 disposed between the level shifter 18 and the second slave devices 16, and because the master device 12 communicates with a plurality of slave devices 14 and 16, the SPMI protocol can be used.

[0019] Figure 2 is a schematic circuit diagram of a known open-drain level shifter 22. The level shifter 22 includes first and second output transistors Tl and T2, a bias transistor T3, first and second one-shot circuits 24 and 26, first and second resistors Rl and R2, and a gate bias circuit 28. The level shifter 22 converts an input signal at a first voltage level to an output signal at a second voltage level. The level shifter 22 has two I / O terminals labeled A and B, so if A is on the higher voltage side (e.g., 1.8V) and B is on the lower voltage side (e.g., 1.2V), an input signal on terminal A when high is converted from 1.8V and output at 1.2V on terminal B, while an input signal on terminal B when high is converted from 1.2V and output at 1.8V on terminal A.

[0020] A first resistor R1 is connected between a first supply voltage VCCA and a first I / O terminal A, and a second resistor R2 is connected between a second supply voltage VCCB and a second I / O terminal B. A first transistor has a source connected to the first supply voltage VCCA, a drain connected to the first I / O terminal A, and a gate terminal connected to a first monoflop circuit 24, and a second transistor has a source connected to the second supply voltage VCCB, a drain connected to the second I / O terminal B, and a gate terminal connected to a second monoflop circuit 26.

[0021] A bias transistor T3 has source and drain terminals connected to the first I / O terminal A and the second I / O terminal B, respectively, and a gate terminal connected to a gate bias circuit 28. The gate bias circuit 28 generates a gate voltage (i.e., V T +V cc(A) where VT is the threshold voltage of the bias transistor T3) to bias the gate of the bias transistor T3. More details and description of the operation of the level shifter 22 can be found in U.S. Patent No. 10,181,852 assigned to NXP B.V.

[0022] When the level shifter 22 is working well, the first pull-up resistor R1 and the second pull-up resistor R2 are always on, resulting in a leakage current. In addition, the signal rise and fall times are not fast enough to meet the SPMI bus specification.

[0023] Figure 3 is a truth table 30 for the SPMI bus. Figure 3 shows that when the input signal goes from low to high or from high to low, the output signal follows the input signal; when the input signal is high or low, then the output signal should be the same (high or low); when the input signal goes from high to Z, then the output signal should remain high; when the input signal goes from low to Z, then the output signal should follow the input signal.

[0024] Figure 4 is a simplified schematic diagram of a single-channel level shifter 40 according to a preferred embodiment of the present invention. The level shifter 40 receives an input signal “A” from a first voltage domain at a first terminal 42 and generates an output signal “B” for a second voltage domain at a second terminal 44.

[0025] The level shifter 40 has a first monoflop circuit 46, a second monoflop circuit 48, a third monoflop circuit 50, and a fourth monoflop circuit 52. The first monoflop circuit 46 and the third monoflop circuit 50 each have an input connected to the output terminal 44, and the second monoflop circuit 48 and the fourth monoflop circuit 52 each have an input connected to the input terminal 42.

[0026] A first transistor Tl has a source connected to a first voltage source VCCA, a drain connected to the first terminal 42, and a gate connected to the output of the first monostable circuit 46. A second transistor T2 has a drain connected to a second voltage source VCCB different from the first voltage source VCCA, a source connected to the second terminal 44, and a gate connected to the output of the second monostable circuit 48. A third transistor T3 has a drain connected to the first terminal 42, a source connected to ground, and a gate connected to the output of the third monostable circuit 50. A fourth transistor T4 has a source connected to ground, a drain connected to the second terminal 44, and a gate connected to the output of the fourth monostable circuit 52.

[0027] A first switch SI is connected in parallel with the first transistor Tl. The first switch SI has a first terminal connected to the first voltage source VCCA and a second terminal connected to the first terminal 42 through a first resistor Rl. Thus, it can be seen that the first switch SI and the first resistor Rl are connected in parallel with the first transistor Tl. A second switch S2 is connected in parallel with the second transistor T2. The second switch S2 has a first terminal connected to the second voltage source VCCB and a second terminal connected to the second terminal 44 through a second resistor R2. Thus, the second switch S2 and the second resistor R2 are connected in parallel with the second transistor T2.

[0028] The first switch SI is operated to be conductive during the rising time of the input signal A. Similarly, the second switch S2 is operated to be conductive during the rising time of the input signal B. Conversely, at other times, the first switch SI and the second switch S2 are non-conductive, thus in this way, the first switch SI and the second switch S2 are configured to reduce the leakage current. The control of the switches SI and S2 will be described in more detail with reference to Figure 5 in more detail.

[0029] In operation, when the input signal A goes from low to high, the output signal B is pulled high; when the input signal A is high, the output signal B remains high; when the input signal A goes from high to low, the output signal B is pulled low; when the input signal A is low, the output signal B remains low. The level translator 40 works similarly in the opposite direction when B is the input signal and A is the output signal. More specifically, in this case, when B (terminal 44) goes from low to high, A (terminal 42) is pulled high; when B is high, A remains high; when B goes from high to low, A is pulled low; when B is low, A remains low.

[0030] The level shifter 40 additionally includes some control circuitry 54 that includes a fifth transistor T5, a sixth transistor T6, a third resistor R3 and a fourth resistor R4, and inverters 56 and 58. The fifth transistor T5 has a source connected to the first terminal 42 through the third resistor R3, a drain connected to the second terminal 44, and a gate connected to the first terminal 42 through the first inverter 56, where the input of the inverter 56 is connected to the first terminal 42 and the output of the inverter 56 is connected to the gate of T5. The sixth transistor T6 has a source connected to the first terminal 42, a drain connected to the second terminal 44 through the fourth resistor R4, and a gate connected to the second terminal 44 through the second inverter 58, where the input of the inverter 58 is connected to the second terminal 44 and the output of the inverter 58 is connected to the gate of T6.

[0031] The control circuitry 54 is representative of how the level shifter works, but is not strictly the structure, which will be referred to Figure 5 shown and discussed. However, Figure 4 how the individual switches S1 and S2 are controlled by their respective inputs A and B.

[0032] When the input A at the first terminal 42 changes state from logic low to logic high, the second one-shot 48 and the second transistor T2 will cause the second terminal 44 to be pulled high. Once the second one-shot 48 expires, the second terminal 44 is held in the high state via the pull-up resistor R2. The fifth transistor T5 and the sixth transistor T6 will be off, and the level shifter 40 will pass the high signal (the second terminal 44 will be high). On the other hand, when the input signal A at the first terminal 42 changes state from high to low, the fourth one-shot 52 and the fourth transistor T4 will turn on, and the second terminal 44 is pulled low. Once the fourth one-shot 52 expires, the fifth transistor T5 and the sixth transistor T6 hold the second terminal 44 in the low state. The switches T5 and T6 are only enabled when the first terminal 42 is low. When the first terminal 42 is low, the second switch S2 will be off (i.e., open), which reduces the leakage current. When the one-shot 52 expires, the SPMI bus should have a high Z state, and any master or slave device can begin to use the bus.

[0033] When the second terminal 44 is an input, then when the input B changes the state from logic low to logic high, the first one-shot 46 and the first transistor Tl will cause the first terminal 42 to be pulled high. Once the first one-shot 46 expires, the first terminal 42 is held in the high state via the pull-up resistor Rl. The fifth transistor T5 and the sixth transistor T6 will be off, and the level shifter 40 will pass a high signal (the first terminal 42 will be high). On the other hand, when the input signal B at the second terminal 44 changes the state from high to low, the third one-shot 50 and the third transistor T3 will turn on, and the first terminal 42 is pulled low. Once the third one-shot 50 expires, the fifth transistor T5 and the sixth transistor T6 hold the first terminal 42 in the low state. The switches T5 and T6 are only enabled when the first terminal 42 is low. When the input signal (B) is low, the first switch SI will be off (i.e., open), which reduces the leakage current. When the one-shot 50 expires, the SPMI bus should have a high Z state, and any master or slave can start using the bus.

[0034] In one embodiment of the present invention, the first voltage source VCCA can be less than or equal to the second voltage source VCCB, and in one embodiment, the level shifter 40 is used in a system having one or more masters coupled to one or more slaves using the SPMI protocol, such as Figure 1 as shown, where the level shifter 40 is between a master operating at 1.2V and one or more slaves operating at 1.8V, so in this case, VCCA is 1.2V and VCCB is 1.8V.

[0035] Figure 5 is a schematic diagram of an output driver circuit 60 of a level shifter according to a preferred embodiment of the present invention. The output driver circuit includes IO terminals 62 and 64 for IO signals "A" and "B", and a first one-shot 66 and a second one-shot 68. The IO terminals 62 and 64 are also referred to as input and output nodes, respectively. The output driver circuit 60 also includes first through tenth transistors Tl through TlO and first through fourth resistors Rl through R4.

[0036] It will be apparent to those skilled in the art that the output driver circuit 60 is half of a level shifter circuit. For example, Figure 5 the first one-shot 66 and the second one-shot 68 of the output driver circuit 60 are compared to Figure 4 the first one-shot 46 and the third one-shot 50 of the level shifter 40 (or to Figure 4 the second one-shot 48 and the fourth one-shot 52 of the level shifter 42), and the switch SI is similar to TlO. The output driver circuit 60 receives an input signal A at the IO terminal 62, and generates an output signal B at the IO terminal 64.

[0037] The circuitry for converting B-levels to A-levels is similar, with the difference that the input will be VCCB instead of VCCA, B_buff instead of A_buff, B instead of A, and then the output will be A instead of B, so a separate but essentially identical schematic is not shown.

[0038] The first transistor T1 has a source connected to a first voltage source (VCCA) and a gate that receives a buffered version of the input signal A (A_buff). As will be appreciated by those skilled in the art, the buffered input signal A_buff can be generated using one or more inverter pairs or buffer circuits, or by inputting the signal A through a Schmitt trigger for noise tolerance and then through a buffer circuit. The second transistor T2 has a source connected to ground and a gate that receives the buffered input signal A_buff. Thus, the gates of the first transistor T1 and the second transistor T2 are connected together.

[0039] The third transistor T3 and the fourth transistor T4 are connected in series between the first voltage source VCCA and the drain of the second transistor T2. That is, the source of the third transistor T3 is connected to the first voltage source (VCCA), the source of the fourth transistor is connected to the drain of the second transistor T2, the drains of the third transistor T3 and the fourth transistor T4 are connected together, and the gates of the third transistor and the fourth transistor receive the output enable signal (OE).

[0040] The output enable signal OE is a signal generated by control circuitry for enabling the output driver circuit 60. In the current embodiment, when OE is high, then the circuit 60 is enabled and functions as a level shifter, and when OE is low, the circuit 60 is disabled.

[0041] The fifth transistor T5 and the sixth transistor T6 are connected in series between the first voltage source (VCCA) and ground, with the drains of the fifth transistor T5 and the sixth transistor T6 connected together and to the inputs of the first monoflop circuit 66 and the second monoflop circuit 68, the source of the fifth transistor T5 connected to VCCA, and the source of the sixth transistor T6 connected to ground. The gates of the fifth transistor T5 and the sixth transistor T6 are connected together and to the drains of the first transistor T1, the third transistor T3, and the fourth transistor T4.

[0042] The seventh transistor T7 and the eighth transistor T8 are connected in series between the first voltage source (VCCA) and ground. The seventh transistor T7 and the eighth transistor T8 have drains connected together through resistors R3 and R4, and gates connected to respective ones of the outputs of the first monoflop circuit 66 and the second monoflop circuit 68. The ninth transistor T9 has a source connected to the input 62, a drain connected to the output 64, and a gate activated by the output enable signal (OE). That is, the gate is connected to the node between the drains of the third transistor T3 and the fourth transistor T4, and also to the drain of the first transistor Tl. The tenth transistor T10 has a source connected to the first voltage source (VCCA), a drain connected to the output 64, and a gate activated by the output enable signal (OE). Thus, like the transistor T9, the gate of the transistor T10 is connected to the node between the drains of the third transistor T3 and the fourth transistor T4, and also to the drain of the first transistor Tl.

[0043] The first resistor Rl is connected between the drain of the tenth transistor T10 and the output 64 (i.e., the same as Rl in Figure 4 The second resistor R2 is connected between the drain of the ninth transistor and the output 64. The third resistor R3 and the fourth resistor R4 are connected in series between the drains of the seventh transistor T7 and the eighth transistor T8, and the node between the third resistor R3 and the fourth resistor R4 is connected to the output 64.

[0044] The first monoflop circuit 66 and the second monoflop circuit 68 use transistors T7 and T8, respectively, to drive the output signal B at the output node 64 from low to high and from high to low. That is, the seventh transistor T7 works with the first monoflop circuit 66 to pull the output signal (i.e., the output node 64) from low to high, and the eighth transistor T8 works with the second monoflop circuit 68 to pull the output signal (i.e., the output node 64) from high to low. For example, SPMI bus timing can be achieved by using a monoflop duration of less than 10 nanoseconds.

[0045] When the output node 64 is high, the tenth transistor T10 and the first resistor Rl pull up the output node 64 after the expiration of the first monoflop circuit 66, while the ninth transistor T9 and the second resistor R2 hold the output node 64 low after the expiration of the second monoflop circuit 68. Thus, during the SPMI bus park period, the ninth transistor T9 and the second resistor R2 hold the output node 64 in the low high-Z state. When the output node 64 is low, the tenth transistor T10 cuts off the pull-up path, while the ninth transistor T9 will cut off the path from B to A (or from A to B) during the high period. The OE signal is used to control the pull-up logic as well as the switch for the bus park period.

[0046] As mentioned above, to implement the level shifter, another of the output buffer circuits 60 will be provided. In the case where the circuit 60 generates the signal B upon receiving the signal A, when B is provided, the second buffer circuit will be used to generate A, and the circuit 60 will receive the B_buff signal instead of the A_buff signal.

[0047] Referring again to Figure 1 The level shifter 18 of the present application is beneficial in a system having one or more master devices 12 in a first voltage domain connected to a plurality of slave devices 16 in a second voltage domain, for example, where the one or more master devices 12 operate at 1.2V and the plurality of slave devices 16 operate at 1.8V, and the slave devices 16 are coupled to the master devices by an SPMI bus 20. There can also be one or more additional slave devices 14 coupled to the master devices 12 that operate at 1.2V.

[0048] In this case, the system 10 includes a first voltage domain connected to a first voltage source to operate at a first voltage level (VCCA), a second voltage domain connected to a second voltage source to operate at a second voltage level (VCCB) different from the first voltage level, and a level shifter 18 between the first and second voltage domains to transfer signals therebetween such that a voltage level of a first signal A transferred from the first voltage domain to the second voltage domain is changed by the level shifter 18 to the second voltage level, and a voltage level of a second signal B transferred from the second voltage domain to the first voltage domain is changed by the level shifter 18 from the second voltage level to the first voltage level.

[0049] The level shifter 18 includes a first terminal that receives the first signal A and outputs the second signal B, and a second terminal that receives the second signal B and outputs the first signal A, and a first switch between the first voltage source VCCA and the first terminal (S1) and a second switch between the second voltage source (VCCB) and the second terminal (S2), wherein the first switch S1 and the second switch S2 are operable to reduce current leakage of the level shifter. Thus, the first switch S1 and the second switch S2 are turned on during a rising time of the input signal, thereby preventing current leakage from the first terminal to the second terminal and from the second terminal to the first terminal. Figure 4 Figure 4

[0050] ​​The level shifter of the present invention has the advantage of being able to operate according to the SPMI bus protocol, where for example the Hi-Z state is maintained and the signal rise and fall times are within specification. Another advantage is that the circuit has a low leakage current due to the use of switches S1 and S2. The circuit also consumes less power than a traditional level shifter, as there is no DC path to ground. The level shifter of the present invention can be used in a push-pull application or an open-drain application. While the present invention is primarily designed as a level shifter for SPMI, operating from 1.2V to 1.8V and vice versa, the circuit can be used in an open-drain configuration for I2C applications. The level shifter of the present invention can also be used as a bus driver or buffer for a high capacitive bus. The present invention can also be used for I3C applications, where there is a combination of push-pull and open-drain. The circuit of the present invention can also be used as a buffer in I2C applications to improve the rise and fall times if there is a high capacitive load.

[0051] In describing the transistors, the terms gate terminal and gate, drain terminal and drain, and source terminal and source have been used interchangeably. The terms high and low have been used to refer to high and low logic states. As will be appreciated by those skilled in the art, the circuits shown in the drawings can be implemented using p-channel or n-channel MOS transistors (PMOS or NMOS). The terms "about" and "approximately", when used in reference to a numerical value, e.g., about 1.2V, mean within ±10% of the numerical value.

[0052] As used herein, the terms "comprising", "including", "containing", "having" and their derivatives, are open-ended, while the term "consisting of" is a closed term.

[0053] While various embodiments of the present invention have been shown and described, it is to be understood that the invention is not limited to the embodiments described, since modifications, changes, variations, substitutions and equivalents can be made therein by those skilled in the art without departing from the spirit and scope of the present invention as described in the claims.

Claims

1. A level converter, characterized in that, The level converter receives an input signal at input terminal A and generates an output signal at output terminal B. The level converter includes: The circuit comprises a first single-trigger circuit, a second single-trigger circuit, a third single-trigger circuit, and a fourth single-trigger circuit, wherein the first single-trigger circuit and the third single-trigger circuit each have an output connected to the input terminal A, and the second single-trigger circuit and the fourth single-trigger circuit each have an output connected to the output terminal B. The first transistor has a source connected to a first voltage source, a drain connected to the input terminal A, and a gate connected to the output of the first single-trigger circuit. The second transistor has a drain connected to a second voltage source different from the first voltage source, a source connected to the output terminal B, and a gate connected to the output of the second single trigger circuit. The third transistor has a source connected to the input terminal A, a drain connected to ground, and a gate connected to the output of the third single-trigger circuit; The fourth transistor has a source connected to ground, a drain connected to the output terminal B, and a gate connected to the output of the fourth single-trigger circuit. A first switch, connected in parallel with the first transistor, wherein the first switch has a first terminal connected to the first voltage source and a second terminal connected to the input terminal A; and A second switch is connected in parallel with the second transistor, wherein the second switch has a first terminal connected to the second voltage source and a second terminal connected to the output terminal B; The first switch and the second switch are turned on during the rise time of the input signal.

2. The level converter according to claim 1, characterized in that, It also includes a first resistor connected between the first switch and the input terminal A, and a second resistor connected between the second switch and the output terminal B.

3. The level converter according to claim 2, characterized in that: When the input signal goes from low to high, the output signal is pulled high. When the input signal is high, the output signal remains high; When the input signal goes from high to low, the output signal is pulled low, and When the input signal is low, the output signal remains low.

4. The level converter according to claim 1, characterized in that, The first voltage source is smaller than the second voltage source.

5. The level converter according to claim 4, characterized in that, The first voltage source is approximately 1.2V, and the second voltage source is approximately 1.8V.

6. The level converter according to claim 1, characterized in that, In addition, including: The fifth transistor has a source connected to the input terminal A via a third resistor and a drain connected to the output terminal B; The sixth transistor has a source connected to the input terminal A and a drain connected to the output terminal B through a fourth resistor; A first inverter has an input connected to the input terminal A and an output connected to the gate of the fifth transistor; as well as The second inverter has an input connected to the output terminal B and an output connected to the gate of the sixth transistor.

7. The level converter according to claim 1, characterized in that, In addition, including: A first resistor is connected between the first switch and the input terminal A; A second resistor is connected between the second switch and the output terminal B; The fifth transistor has a source connected to the input terminal A via a third resistor and a drain connected to the output terminal B; The sixth transistor has a source connected to the input terminal A and a drain connected to the output terminal B through a fourth resistor; A first inverter has an input connected to the input terminal A and an output connected to the gate of the fifth transistor; as well as The second inverter has an input connected to the output terminal B and an output connected to the gate of the sixth transistor. The first switch and the second switch are turned on during the rise time of the input signal, thereby preventing current leakage from the input terminal A to the output terminal B and from the output terminal B to the input terminal A. The first voltage source is smaller than the second voltage source.

8. An output driver circuit for a level converter, characterized in that, The level converter receives an input signal at its input terminal and generates an output signal at its output terminal. The output driver circuit includes: The first single-trigger circuit has both input and output; The second single-trigger circuit has both input and output; The first transistor has a source connected to a first voltage source (VCCA) and a buffered version of the gate for receiving the input signal; The second transistor has a source connected to ground and a buffered version of the gate that receives the input signal; A third transistor and a fourth transistor are connected in series, wherein the source of the third transistor is connected to the first voltage source (VCCA), the source of the fourth transistor is connected to the drain of the second transistor, the drains of the third transistor and the fourth transistor are connected together, and the gates of the third transistor and the fourth transistor receive an output enable signal (OE). A fifth transistor and a sixth transistor are connected in series between the first voltage source (VCCA) and ground, wherein the drains of the fifth transistor and the sixth transistor are connected together and connected to the inputs of the first single-trigger circuit and the second single-trigger circuit; A seventh transistor and an eighth transistor, the seventh transistor and the eighth transistor being connected in series between the first voltage source (VCCA) and ground, wherein the seventh transistor and the eighth transistor have drains connected together and gates connected to the respective outputs of the first single-trigger circuit and the second single-trigger circuit; A ninth transistor having a source connected to the input terminal, a drain connected to the output terminal, and a gate activated by the output enable signal (OE); and The tenth transistor has a source connected to the first voltage source (VCCA), a drain connected to the output terminal, and a gate activated by the output enable signal (OE).

9. A system, characterized in that, include: A first voltage domain, which is connected to a first voltage source to operate at a first voltage level (VCCA); A second voltage domain is connected to a second voltage source to operate at a second voltage level (VCCB) different from the first voltage level; as well as The level converter according to any one of claims 1-7, located between the first voltage domain and the second voltage domain to transmit a signal therebetween, such that the voltage level of a first signal A transmitted from the first voltage domain to the second voltage domain is changed by the level converter to the second voltage level, and the voltage level of a second signal B transmitted from the second voltage domain to the first voltage domain is changed by the level converter from the second voltage level to the first voltage level. The level converter mentioned above includes: The first end receives the first signal A and outputs the second signal B; and The second terminal receives the second signal B and outputs the first signal A; and A first switch is located between the first voltage source and the first terminal; and a second switch is located between the second voltage source and the second terminal, wherein the first switch and the second switch are operable to reduce current leakage of the level converter.

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