System and method for power mode management of a processor

Abstract

A system and method for power mode management of a processor, the system and method providing a safe and robust transition between a normal mode and a low power mode to meet low current requirements and ensure accurate power mode transition communication. The two-step process includes receiving a digital code, starting a standby entry timer, receiving a low power request indication before the standby entry timer times out to ensure a valid request, and otherwise resetting when the timer times out. A watchdog timer ensures that a maximum standby duration is not exceeded. A confirmation timer ensures valid communication between modules of a power management IC. A memory element ensures and maintains a valid state of a reset status pin and a safe status pin during standby. A self-test is performed, wherein a test failure prevents transition to the low power mode. A power good indication ensures that the supply voltage of the processor is suitable for low power operation and normal operation.

Description

Technical Field

[0001] The present invention relates generally to processor power mode management, and more particularly to systems and methods for ensuring that power mode transitions occur in a robust and safe manner to reduce the likelihood of failure. Background Art

[0002] Safety is a concern for certain applications, such as automotive applications or industrial applications. A processor or processing unit (e.g., a microprocessor, a microcontroller, a system on a chip, or any other processing configuration) can be used to process any type of data or information to control certain parameters, functions, or operations associated with a specific application. Automotive applications may include, for example, gateways (e.g., in-car networking and telematics), adaptive driver assistance systems (ADAS), infotainment (audio and / or video entertainment, information, navigation, hands-free control, etc.), clusters (digital instruments, head-up displays, etc.), vehicles to everything (V2X) (e.g., communication between vehicles and external entities, traffic sign recognition, etc.), radar, vision (e.g., cameras, proximity sensors, collision avoidance, blind spot monitoring, etc.). Industrial applications may include, for example, industrial tablets or laptops, etc., Internet Protocol Television (IPTV), industrial control, medical monitoring, home automation and / or alarm systems, etc.

[0003] The processor may have a low power mode (e.g., standby mode, etc.) to minimize power consumption during all inactivity periods except for a minimal amount of logic power down. An external power management IC (PMIC) may be used to provide a supply voltage to the processor, and may further be used to control the power mode of the processor, including transitions between a normal power mode and a low power mode. In such a configuration, any erroneous communication between the processor and the PMIC may result in power down at an incorrect time, resulting in unexpected power down of the processor and any corresponding peripherals. For safety-related applications, including safety-critical applications, the consequences of an unexpected power down may be inconvenient or even dangerous if the system cannot transition to a safe state. Summary of the invention

[0004] Aspects of the disclosure are defined in the following claims.

[0005] In a first aspect, a processing system is provided, the processing system comprising:

[0006] A power management circuit having a normal mode and a low power mode, the power management circuit comprising:

[0007] A power management processing module, the power management processing module comprising:

[0008] a communication interface; and

[0009] a power control circuit that, when a low power exit request is received during the low power mode, switches the power management circuit from the low power mode to the normal mode; and

[0010] A security processing module, the security processing module comprising:

[0011] Standby memory;

[0012] Standby entry timer; and

[0013] A safety control circuit starts the standby entry timer during the normal mode when a predetermined digital value is written into the standby memory, and provides a standby start indication to convert the power management processing module to the low power mode only when a low power request indication is received before the standby entry timer times out.

[0014] In one or more embodiments, when the standby entry timer times out before receiving the standby request indication, the safety control circuit may perform a reset process.

[0015] In one or more embodiments, the power management processing module may further include: a power converter that provides a power supply voltage; and the power control circuit may initiate power off of the power converter in response to the standby start indication from the safety control circuit, and provide a standby response indication.

[0016] In one or more embodiments, the power management processing module may further include: a watchdog timer; and the power control circuit may start the watchdog timer in response to the standby start indication from the safety control circuit, wherein when the watchdog timer times out, the power processing circuit may perform a reset process, and wherein when the power supply voltage is charged to above a predetermined high threshold level, the power control circuit may assert a power good pin in a first state, and when the power supply voltage is discharged to below a predetermined low threshold level, the power control circuit may assert a power good pin in a second state.

[0017] In one or more embodiments, the power control circuit may stop the watchdog timer, reactivate the power converter, and prompt the security control circuit to wake up the security processing module in response to receiving the low power exit request.

[0018] In one or more embodiments, when the standby start indication is provided, the security processing circuit may start a confirmation timer, wherein when the confirmation timer times out before the standby response indication is provided, the security processing circuit may perform a reset process, and wherein when the standby response indication is provided before the confirmation timer times out, the security processing circuit may enter the low power mode and stop the confirmation timer.

[0019] In one or more embodiments, the security processing module may further include at least one storage element that maintains a state of each of the at least one external pin during the low power mode.

[0020] In one or more embodiments, the security processing module may further include: a test circuit, which can perform a self-test of the security processing module during power-on and can provide a pass indication indicating the self-test; and wherein, when the pass indication indicates a test failure, the security processing circuit can prevent entry into the standby mode.

[0021] In one or more embodiments, the processing system according to claim 1 may further include: a processor having a normal processor mode and a low power processor mode, wherein the processor may include: a low power control circuit, which requests to enter the low power processor mode by providing the predetermined digital value to the power management circuit via the communication interface; and a low power request circuit, which provides the low power request indication after providing the predetermined digital value.

[0022] In one or more embodiments, the processor may further include a low power domain circuit, which provides the low power exit request to request re-entry into the normal processing mode, and initiates re-entry into the normal processing mode only when a power good pin of the power management circuit indicates that the power supply voltage is above a predetermined threshold level.

[0023] In one or more embodiments, the processor may further include a low power domain circuit, which enables the processor to switch from the normal processing mode to the low power processing mode only when the power good pin of the power management circuit indicates that the power supply voltage is below a predetermined threshold level.

[0024] In a second aspect, a method for power mode management is provided, the method comprising: receiving a digital code during a normal operating mode; comparing the received digital code with a predetermined digital value; starting a standby entry timer when the received digital code matches the predetermined digital value; providing a standby start indication to start transitioning from a normal mode to a low power operating mode only when a standby request indication is received before the standby entry timer times out; and transitioning from the low power mode to the normal mode in response to receiving a low power exit request.

[0025] In one or more embodiments, the method may further include: performing a reset process when the standby entry timer times out before receiving the low power request indication.

[0026] In one or more embodiments, the method may further include: providing a power supply voltage; and in response to receiving a standby start indication, discharging the power supply voltage and providing a standby response indication.

[0027] In one or more embodiments, the method may further include: starting a watchdog timer in response to receiving the standby start indication; performing a reset process when the watchdog timer times out; and asserting a power good pin in a first state when the power supply voltage is charged to above a predetermined high threshold level, and asserting a power good pin in a second state when the power supply voltage is discharged to below a predetermined low threshold level.

[0028] In one or more embodiments, the method may further include, in response to receiving the low power exit request, stopping the watchdog timer, reactivating the power converter, and prompting a wakeup.

[0029] In one or more embodiments, the method may further include: starting a confirmation timer when a standby start indication is provided; performing a reset process when the confirmation timer times out before a standby response indication is provided; and entering a low power mode and stopping the confirmation timer when a standby response indication is provided before the confirmation timer times out.

[0030] In one or more embodiments, the method may further include providing at least one storage element that maintains a state of each of the at least one external pin during the low power mode.

[0031] In one or more embodiments, the method may further include: performing a self-test during power-up and providing a pass indication indicating the self-test; and preventing the entry into the low power mode when the pass indication indicates a test failure.

[0032] In one or more embodiments, the method may further include: the processor requests to enter the low power mode by providing the digital code during the normal mode; after providing the digital code, the processor provides a low power request; when the power good indication indicates that the power supply voltage is lower than a predetermined low threshold level, the processor enters the low power mode; by providing a low power exit request, the processor requests to enter the normal mode; and when the power good indication indicates that the power supply voltage is higher than a predetermined high threshold level, the processor enters the normal mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The embodiments of the present invention are described by way of example and are not limited by the accompanying drawings. Similar symbols in the accompanying drawings may represent similar elements. The elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0034] Figure 1 is a simplified block diagram of a processing system implemented according to one embodiment of the present disclosure.

[0035] Figure 2 According to one embodiment of the present disclosure Figure 1 A more detailed block diagram of a PMIC connected to a processor to control power mode transitions.

[0036] Figure 3 is a diagram showing a method according to an embodiment of the present disclosure Figure 2 State diagram of the PM control circuit that controls the operation of the power management processing module.

[0037] Figure 4 is a diagram showing a method according to an embodiment of the present disclosure Figure 2 A state diagram of the safety control circuit that controls the operation of the safety processing module. DETAILED DESCRIPTION

[0038] The inventors have recognized that it would be advantageous to provide a robust and safe method to transition between normal operating modes and low power operating modes between a processor and a power management IC (PMIC), while also ensuring that communications across the interface are accurate. Normal mode means that the system is fully powered on to perform the functions and operations for which the system is designed. Low power mode refers to any reduced power mode (e.g., reduced power mode, sleep mode, standby mode, etc.) that reduces quiescent current in order to reduce overall power consumption. The systems and methods of power mode management as described herein provide dedicated interactions to ensure that transitions between different operating modes are safe and robust, such as ensuring that a processor does not accidentally transition to a low power mode of the processor when performing system critical functions.

[0039] Figure 11 is a simplified block diagram of a processing system 102 implemented according to one embodiment of the present disclosure. The processing system 102 may be implemented in a discrete manner, or may be integrated onto a single module such as a system on a chip (SoC). The processing system 102 includes a power management IC (PMIC) 104, a processor 106, a peripheral system 108, and a memory and storage module 110. The PMIC 104 cooperates with the processor 106 to ensure that power mode transitions of the processor 106 (as well as transitions of any other device powered by the PMIC 104) occur in a robust and safe manner to reduce the possibility of failure, as further described herein. The processor 106 may include any type of processing device or system, such as a programmable integrated circuit, a microprocessor, a microcontroller or MCU, a central processing unit (CPU), an application processor, etc., and may include multiple processing devices. The memory and storage module 110 may include one or more of any type of memory or storage device or any combination thereof, including, for example, random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), low power double data rate (DDR) (LPDDR4), such as serial peripheral interface (SPI) flash memory 190, NVRAM, flash memory, solid state drive (SSD), hard drive, optical drive, or any other suitable form of internal or external storage. The memory and storage device may be incorporated on the processing system 102, or alternatively, the memory and storage module 110 may be configured as an interface to an external memory or drive, etc.

[0040] The processing system 102 may be used to implement or may be part of an automotive application or an industrial application, etc., where safety and robustness are of concern. The peripheral system 108 may be used to interface sensors, communication devices, detectors, display devices, keyboards, controllers, mice, etc., to enable the processor 106 to process any type of data or information to control certain parameters, functions, or operations associated with a particular application. In many such applications, the processor 106 includes a low power mode to reduce power consumption, in which only a minimum amount of logic and circuitry remains powered, sufficient to reawaken the processing system 102 to resume normal operation. The PMIC 104 controls the supply voltage provided to the PROC 106 (and any other peripherals), and further facilitates the transition of the processor 106 between the normal mode and the low power mode, as further described herein. The PMIC 104 also has a low power mode referred to herein as a "standby" mode, in which the PMIC 104 maintains a very low but sufficient operating level to detect a request by the processor 106 to reawaken the system.

[0041] Figure 21 is a more detailed block diagram of a PMIC 104 connected to a processor 106 to control power mode transitions according to one embodiment of the present disclosure. The PMIC 104 is divided into two different modules for two different domains, the two different modules including a power management processing module 202 and a security processing module 204. The power management processing module 202 includes a power management (PM) control circuit 203, which generally controls the operation of the power management processing module 202. The power management processing module 202 includes a power converter 206, the power converter 206 includes at least one switchable regulator, the at least one switchable regulator converts an input voltage VIN to at least one supply voltage (SV) provided on at least one voltage rail 207 sufficient to operate the processor 106. The input voltage VIN can be provided by any type of power supply, depending on the specific application. For automotive and truck applications, for example, VIN can be provided by a 12 volt (V), 24V or 48V battery, etc. Industrial applications may be powered by a battery or by a converter or inverter, etc. providing VIN converted from an alternating current (AC) source voltage, etc. Depending on the specific application and configuration of the processor 106 and other provided devices, SV may be a single voltage or may include multiple voltages, such as 0.8V, 1.1V, 1.8V, 3.3V, 5V, etc. For purposes of discussion, SV is referred to herein as a single source voltage, where it should be understood that SV may include multiple different voltage levels. The power converter 206 may include at least one non-switching regulator that remains on during the standby mode of the PMIC 104 to power the circuits of the PMIC 104.

[0042] The power management processing module 202 also includes a standby timing window (STW) counter 208, which is programmed with a standby timing value that defines the maximum amount of time that the processing system 102 remains in the standby mode. The standby timing value is configured for different configurations. The power management processing module 202 includes a communication interface (COMM I / F) 210, which is coupled to a communication bus 211 capable of communicating with the processor 106. In one embodiment, the communication interface 210 and the communication bus 211 are configured as a serial communication interface, such as an inter-integrated circuit (I2C) serial communication interface configured according to the I2C protocol, although any suitable communication interface may be used, such as a serial peripheral interface (SPI) or the like.

[0043] The PMIC 104 further includes a standby exit (STBY_EXIT) pin and a standby power good (STBY_PGOOD) pin, both of which are monitored and controlled by the PM control circuit 203, as further described herein. The processor 106 asserts the STBY_EXIT pin high to request exiting the low power mode of the processor by requesting the PMIC 104 to exit its standby mode. Note that, as used throughout this disclosure, depending on the logical context, a pin or signal is "asserted" high and "de-asserted" low, or else is asserted low and de-asserted high. The state of the STBY_PGOOD pin indicates the voltage level of the SV. The STBY_PGOOD pin can be asserted high to indicate to the processor 106 that the SV is charged to above a high voltage threshold level HVTH to enter the normal mode. The STBY_PGOOD pin can be asserted low to indicate to the processor 106 that the SV is discharged to below a configurable low voltage threshold level LVTH to enter its low power mode from the normal mode. The HVTH level is determined to indicate that the switchable regulator is fully charged and the SV is above the minimum level for fully powering the processor 106. The LVTH level is determined to verify that the switchable regulator is sufficiently discharged to ensure that the powered-down portion of the processor 106 can restart without residual internal bias.

[0044] Note that if more than one SV is provided, then each individual source voltage can have different low threshold voltage levels and different high threshold voltage levels. In this case, STBY_PGOOD indicates that each source voltage is above the corresponding one of a plurality of high voltage threshold levels or below the corresponding one of a plurality of low voltage threshold levels. Note that STBY_PGOOD can be a single pin with a hysteresis function, where STBY_PGOOD starts low and transitions to high only after SV > LVTH, and then transitions back to low only after SV < LVTH. In an alternative embodiment, STBY_PGOOD can be implemented as two separate pins, such as PHI and PLO (not shown). For example, the state of PLO indicates whether the SV is below LVTH, while the state of PHI indicates whether the SV is above HVTH. In other embodiments, a separate power good signal or signal pair can be provided for each SV. The operation in each of these alternative embodiments is similar, where multiple status signals can be considered in combination.

[0045] The security processing module 204 includes a security control circuit 205 that generally controls the operation of the security processing module 204. The security processing module 204 includes a cyclic redundancy check (CRC) logic 212 connected to the communication interface 210 to protect the integrity of the end-to-end communication with the processor 106. The security processing module 204 includes a standby (STBY) register 214, which is used for the first step in the two-step standby process to transition to the standby mode, as further described herein. The security processing module 204 includes a standby entry timing (SET) counter 216, which is programmed with a standby entry timing value, which defines the maximum time between the first step and the second step of the two-step standby process, as further described herein. The security processing module 204 includes a memory circuit 217, which includes a first memory element (ME) 218 ​​coupled to the reset pin RSTB and a second memory element 219 coupled to the fail-safe pin FS0B of the PMIC 104. The fail-safe pin FS0B is coupled to an external application security state logic (ASSL) 240 to maintain the security state of the application, which is not further described herein. The security processing module 204 includes a security processing power supply (SPS) 220 and a memory element security processing power supply (MESPS) 222, wherein the memory element security processing power supply 222 supplies power to the memory element 218 and the memory element 219 of the memory circuit 217.

[0046] The security processing module 204 includes a standby entry pin (FS_STBY_ENTRY) coupled to the STBY pin of the processor 106. The processor 106 requests to enter its low power mode by asserting its STBY pin low, as further described herein, thereby asserting the FS_STBY_ENTRY pin of the PMIC 104 high. The security processing module 204 includes a logic built-in self-test (LBIST) circuit 224 to check the integrity of the logic of the security processing module 204, and also includes an analog built-in self-test (ABIST) circuit 226 to check the integrity of the memory circuit 217 and the state of the FS0B pin and the RSTB pin. The security processing module 204 includes an acknowledgement (ACK) timer counter 227 to ensure that the processor 106 is not stalled if the power management processing module 202 fails to transition to the standby mode.

[0047] STBY and STBY_EXIT are shown as two separate outputs of the processor 106, for example, provided by two separate pins of the processor 106. Note, however, that the two outputs may be combined into a single pin of the processor 106 having two different states including a first state indicating STBY and a second state indicating STBY_EXIT. If a single pin of the processor 106 is used, the single STBY / STBY_EXIT pin of the processor 106 is coupled to the STBY_EXIT pin and the FS_STBY_ENTRY pin of the PMIC 104, wherein the STBY / STBY_EXIT pin is asserted low to request an exit from the normal mode and enter the low power mode, and the STBY / STBY_EXIT pin is asserted high to request an exit from the low power mode and enter the normal mode. In yet another embodiment, the STBY_EXIT pin and the FS_STBY_ENTRY pin of the PMIC 104 may be combined into a single pin in a similar manner.

[0048] The secure processing power supply 220 may be powered off during the standby mode, but the memory element secure processing power supply 222 remains powered on during the standby period to maintain power to the memory element 218 and the memory element 219 of the memory circuit 217 during the standby mode. The memory element 218 holds the RSTB pin high during the standby period to prevent an accidental reset of the processor 106. The memory element 219 holds the FS0B pin low during the standby period to keep the processing system 102 in a secure state until the processor 106 requests a standby exit or when the standby timing window counter 208 times out, as further described herein.

[0049] The processor 106 includes a supply voltage circuit (SVC) 228 coupled to the supply voltage rail 207 for receiving SV (which includes one or more supply voltages) to power the circuits of the processor 106. The processor 106 includes a low power (LP) domain 230 that remains powered during a low power mode of the processor 106. The low power domain 230 is coupled to the STBY_PGOOD pin of the PMIC 104 that indicates the SV state, and is also coupled to the STBY_EXIT of the PMIC 104 to request an exit from the standby mode. The processor 106 includes a low power (LP) entry control circuit 232 coupled to a communication interface (COMMI / F) 234, which is further connected to the communication bus 211 to enable communication with the PMIC 104. The communication interface 234 can also be configured according to the I2C protocol, etc. LP entry control circuit 232 is connected to LP request circuit 236, which controls the STBY pin of processor 106. Processor 106 also includes a reset pin RESET_B coupled to the RSTB pin of PMIC 104, where PMIC 104 can assert its RSTB pin low to reset processor 106 under certain conditions, as further described herein.

[0050] The LP entry control circuit 232 and the LP request circuit 236 cooperate with the PMIC 104 to initiate a two-step standby process to convert from normal mode to standby mode. In one embodiment, when the processor 106 determines to enter its low power mode, the LP entry control circuit 232 sends a predetermined digital code to the PMIC 104 via the communication bus 211. The processor 106 then performs a power domain isolation sequence to internally ensure that its non-switchable power domain including the low power domain 230 has been completely isolated from the switchable power domain that is turned off during the standby mode. After successfully completing the power domain isolation sequence, the LP request circuit 236 asserts the STBY pin to be low to complete the request to enter the low power mode. At the same time, the PMIC 104 receives a predetermined digital code via the communication interface 210 and stores the digital code in the STBY register 214. Assuming that the CRC passes, the standby control circuit 205 performs verification, wherein the standby control circuit 205 compares the received digital code with a predetermined digital value. If the digital code matching the predetermined digital value is valid, the standby control circuit 205 starts the standby entry timing counter 216 and monitors the FS_STBY_ENTRY pin. If the FS_STBY_ENTRY pin is pulled low before the standby entry timing counter 216 times out, the low power request is considered valid and the standby control circuit 205 proceeds to the standby mode as further described herein. If the standby entry timing counter 216 times out before FS_STBY_ENTRY is asserted low, the standby control circuit 205 determines an error condition and asserts the RSTB pin low to reset the processor 106.

[0051] Figure 3 2 is a state diagram illustrating the operation of the power management processing module 202 of the PMIC 104 controlled by the PM control circuit 203 according to one embodiment of the present disclosure. In general, the power management processing module 202 converts VIN to SV provided to the processor 106; indicates the state of the SV (e.g., via the STBY_PGOOD pin or the RSTB pin); communicates with the processor 106 via the communication bus 211 (e.g., receives a digital code as part of a two-step standby entry process); ensures a maximum duration of a low power mode of the processor 106 (e.g., via the standby timing window counter 208); and detects a request (e.g., STBY_EXIT) from the processor 106 to exit its low power mode and return to a normal operating mode.

[0052] The first OFF state 302 is a state in which the switchable regulators are turned off (or otherwise held in reset) and the system is in a "safe" state while keeping the processor 106 in its off state or reset state. In response to an ON indication in which the PM control circuit 203 executes a predetermined startup sequence including activating one or more switchable regulators in the power converter 206, the operation transitions to the POWER UP state 304. During the startup sequence, STBY_PGOOD remains low when SV is below the high threshold level HVTH or SV < HVTH. When the switchable regulators have stabilized and SV ≥ HVTH, the operation transitions to the NORMAL state 306, and the PM control circuit 203 asserts STBY_PGOOD high and also asserts the signal STBY_RESP low. In response to both RSTB and STBY_PGOOD being asserted high, the processor 106 continues to remove the isolation between the power domains and execute the reset sequence of the switchable power domains. The power management processing module 202 remains in the NORMAL state 306 operating in the normal mode while the signal STBY_START remains low.

[0053] When the security processing module 204 asserts the STBY_START signal high, indicating that the processor 106 has successfully requested a transition to the low power mode, the PM control circuit 203 transitions to the POWER DOWN state 308, in which the PM control circuit 203 starts the standby timing window counter 208 and begins deactivating the switchable regulators of the power converter 206 such that SV begins to decrease. Additionally, the PM control circuit 203 asserts the STBY_RESP signal high to indicate to the security processing module 204 that the power management processing module 202 is transitioning to its standby mode. The POWER DOWN state 308 is not a complete power-off of the PMIC 104 but a state in which the power is reduced from the full power normal mode to the low power standby mode. The STBY_START signal serves as a standby start indication from the security control circuit 205 to the PM control circuit 203 to transition to the standby mode. In response to the STBY_START signal, the STBY_RESP signal serves as a standby response indication from the PM control circuit 203 to the security control circuit 205. The operation remains in the POWER DOWN state 308 when SV ≥ LVTH. When deactivating the switchable regulators of the power converter 206 causes SV < LVTH, then the PM control circuit 203 transitions to the STANDBY state 310 by placing the power management processing module 202 in its standby mode, in which the STBY_PGOOD pin is asserted low. In the standby state 310, both the PMIC 104 and the processor 106 are fully in their respective low power states, consuming as low a static current as possible for low power operation.

[0054] The operation of the power management processing module 202 remains in its STANDBY state 310 until the processor 106 asserts STBY_EXIT high to request a transition back to normal mode or when the timer standby timing window counter 208 times out. If the standby timing window counter 208 times out during either state 308 or state 310 before STBY_EXIT is asserted high, the PM control circuit 203 initiates a full reset and a new power-on sequence to reset the entire system, including asserting RSTB low to reset the processor 106. The standby timing window counter 208 is programmed with a timing value that determines the maximum amount of time to stay in a low power mode to prevent the processor 106 from being trapped in its low power mode or being unable to wake up in some way. The processor 106 can perform periodic wake-up and power-down sequences, such as during longer periods of inactivity, etc., to ensure that the system is ready to power up and perform normal operating functions. If for any reason, the processor 106 fails to wake up the system, the timeout of the standby timing window counter 208 will cause the system's power cycle.

[0055] When the STBY_EXIT pin of the PMIC 104 is asserted high before the standby timing window counter 208 times out, the PM control circuit 203 transitions to the STANDBY EXIT state 312, where the PM control circuit 203 stops the standby timing window counter 208 and begins the power-up process. The STBY_PGOOD pin remains negated low during the STANDBY EXIT state 312. The operation then transitions back to the POWER UP state 304, where the PM control circuit 203 performs a predetermined startup sequence, which includes activating the switchable regulator of the power converter 206, as described above. As described above, when SV≥HVTH, the operation again transitions to the NORMAL state 306 and asserts STBY_PGOOD high to wake up the processor 106.

[0056] Figure 42 is a state diagram illustrating the operation of the security processing module 204 of the PMIC 104 controlled by the security control circuit 205 according to one embodiment of the present disclosure. In general, the security processing module 204 performs integrity testing of the PMIC 104; controls the states of the FS0B pin and the RSTB pin (e.g., freezes the pin states during standby mode); monitors the state of the FS_STBY_ENTRY pin; resets the processor 106 under certain conditions; monitors the SV for overvoltage or undervoltage; times the duration between the two steps of the two-step standby entry process to detect a valid standby transition request; times the activation of the memory elements of the memory circuit 217; and performs CRC to protect the integrity of the communication between the processor 106 and the PMIC 104 via the communication bus 211. Note that the security processing module 204 and the power management processing module 202 operate independently but in parallel with each other. The STBY_START signal and the STBY_RESP signal are handshake signals used to control the transition from the normal mode to the standby mode, as described herein.

[0057] The first OFF state 402 corresponds to the OFF state 302 of the power management processing module 202. When the power management processing module 202 transitions to the POWER UP state 304, the security control circuit 205 transitions to the LBIST state 404, wherein the LBIST circuit 224 is activated to check the integrity of the control logic of the security processing module 204. After the LBIST integrity test (LBIST OK or LBIST NOK) is completed, the operation transitions to the ABIST state 406, wherein the ABIST circuit 226 is activated to check the integrity of the memory circuit 217 and the state of the FS_STBY_ENTRY pin, the FS0B pin, the RSTB pin and the analog monitor (not shown). After the ABIST integrity test (ABIST OK or ABIST NOK) is completed, the security control circuit 205 transitions to the NORMAL state 408 of the security processing module 204, which indicates that the security control circuit 205 is operating in its normal mode. As long as LBIST OK and ABIST OK are all true, RSTB pin is deasserted high so that processor 106 can power on, and FS0B pin is also deasserted high.When processor 106 is in its normal mode and performs its normal function, operation remains on NORMAL state 408.If LBIST NOK or ABIST NOK (any test failure), then it is not allowed to enter standby mode, and operation remains on NORMAL state 408, which prevents processor 106 from entering its low power mode.Note that RSTB can be released to allow PMIC104 and processor 106 to perform a certain additional integrity test to correct conditions or indicate errors.

[0058] The processor 106 starts the two-step standby process by causing the LP entry control circuit 232 to send a digital code to the PMIC 104 via the communication bus 211. The PMIC 104 receives the predetermined digital code via the communication bus 211 and stores the digital code in the STBY register 214 of the security processing module 204. If the security control circuit 205 determines that the digital code is valid (meaning it is equal to the predetermined digital code value), and if both the LBIST and ABIST integrity tests pass (LBIST OK and ABIST OK), the operation transitions to the SAFE state 410, where the security control circuit 205 starts the standby entry timing counter 216. Note that if one or both of the LBIST and ABIST indicate a fault, the PMIC 104 prevents the processor 106 from entering the standby mode. The FS0B pin, which is coupled to the external application safe state logic 240, is asserted low to enter the safe state of operation. Operation remains in the SAFE state 410 until the standby entry timing counter 216 times out or until the FS_STBY_ENTRY pin is asserted low, completing the two-step standby process. If a timeout of the standby entry timing counter 216 occurs before the FS_STBY_ENTRY pin is asserted low, indicating a possible failure of the processor 106 such that the two-step standby process is not completed, then in one embodiment, the safety control circuit 205 returns operation to the OFF state 402 and forces a complete power down followed by a full system power up, which also results in a power cycle of the power management processing module 202. In essence, operation transitions back to the OFF state 402 of the safety processing module 204, and back to the OFF state 302 of the power management processing module 202, and then the system is powered back on. In an alternative embodiment as indicated by the dashed line, upon the timeout of the standby entry timing counter 216, operation may instead return to the NORMAL state 408, with RSTB additionally asserted low to reset only the processor 106 without performing a complete power down. Note that RSTB is asserted low during the transition and then deasserted back high in the NORMAL state 408, which causes the processor 106 to be reset.

[0059] Conversely, if the LP request circuit 236 of the processor 106 asserts the FS_STBY_ENTRY pin low before the standby entry timing counter 216 times out, the security control circuit 205 transitions to the VALID state 412, in which the security control circuit 205 asserts the STBY_START signal high, causing the power management processing module 202 to transition to the POWER DOWN state 308. The security control circuit 205 also starts the ACK timing counter 227 in the VALID state 412 and then transitions to the MEMORY state 414, in which the security control circuit 205 activates the memory circuit 217 to hold the RSTB pin high in its released state and the FS0B pin low to maintain the system in a safe state. Operation remains in the VALID state 414 until the ACK timing counter 227 times out or until the STBY_RESP signal is asserted high, which indicates that the power management processing module 202 successfully transitioned to the standby mode. The response to the timeout of the ACK timing counter 227 can be similar to the response to the timeout of the standby entry timing counter 216. In one embodiment, the timeout of the ACK timing counter 227 causes the security control circuit 205 to return operation to the OFF state 402 and force a complete power off, followed by power on of the entire system, which also causes a power cycle of the power management processing module 202. In essence, the operation transitions back to the OFF state 402 of the security processing module 204, and back to the OFF state 302 of the power management processing module 202, and then the system is powered back on. In an alternative embodiment as indicated by the dotted line, the operation can return to the NORMAL state 408, where RSTB is additionally asserted low to only reset the processor 106 without performing a complete power off. As described above, RSTB is asserted low during the transition and then de-asserted back to high in the NORMAL state 408, which causes the processor 106 to be reset.

[0060] If the STBY_RESP signal is asserted high before the ACK timing counter 227 times out, the operation transitions to the STANDBY state 416, where the security control circuit 205 transitions the security processing module 204 to its standby mode and stops the ACK timing counter 227. The security processing module 204 is powered down in its standby mode, except that the memory element security processing power supply 222 remains minimally powered to power the memory circuit 217 to maintain the states of the RSTB pin and the FS0B pin during the standby mode.

[0061] When the security control circuit 205 detects the assertion of the STBY_EXIT pin as high (e.g., directly or via another signal (not shown) in response to STBY_EXIT), the security control circuit 205 wakes up and transitions back to the LBIST state 404 to eventually transition to the NORMAL state 408, as described above. In addition, if the standby timing window counter 208 times out during the standby mode, the security processing module 204 is reset and powered on.

[0062] A system and method for power mode management of a processor, the system and method providing safe and robust transitions between normal mode and low power mode to meet low current requirements and ensure accurate power mode transition communication. The two-step process includes receiving a digital code, starting a standby entry timer, receiving a low power request indication before the standby entry timer times out to ensure a valid request, and otherwise resetting when the timer times out. A watchdog timer ensures that a maximum standby duration is not exceeded. A confirmation timer ensures valid communication between modules of a power management IC. A memory element ensures and maintains valid states of a reset status pin and a safe status pin during standby. A self-test is performed, where a failure of the test prevents transition to a low power mode. A power good indication ensures that the supply voltage of the processor is suitable for low power operation and normal operation.

[0063] Although the present invention has been described in conjunction with several embodiments, the present invention is not intended to be limited to the specific forms set forth herein. On the contrary, the present invention is intended to cover such replacements, modifications and equivalents that may be reasonably included within the scope of the present invention as defined by the appended claims. For example, variations of positive logic or negative logic may be used in various embodiments, wherein the present invention is not limited to specific logic polarities, device types, or voltage levels, etc. For example, logic states (e.g., logic low and logic high) may be reversed depending on whether a pin or signal is implemented in positive logic or negative logic, etc. In some cases, the logic state may be programmable, wherein for a given logic function, the logic state may be reversed.

[0064] The term "a / an" as used herein is defined as one or more than one. In addition, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a / an" will limit any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a / an". The use of definite articles is also the same. Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of these elements.

Claims

1. A processing system, characterized in that: include: A power management circuit having a normal mode and a low power mode, the power management circuit comprising: A power management processing module, the power management processing module comprising: a communication interface; and a power control circuit that, when a low power exit request is received during the low power mode, switches the power management circuit from the low power mode to the normal mode; and A security processing module, the security processing module comprising: Standby memory; Standby entry timer; and a safety control circuit that starts the standby entry timer during the normal mode when a predetermined digital value is written into the standby memory, and provides a standby start indication to transition the power management processing module to the low power mode only when a low power request indication is received before the standby entry timer times out; A processor having a normal processor mode and a low power processor mode, wherein the processor comprises: a low power control circuit that requests entry into the low power processor mode by providing the predetermined digital value to the power management circuit via the communication interface; and A low power request circuit is provided to provide the low power request indication after providing the predetermined digital value.

2. The processing system according to claim 1, characterized in that When the standby entry timer times out before receiving a standby request indication, the safety control circuit performs a reset process.

3. A processing system according to any of the preceding claims, characterized in that The power management processing module further includes: a power converter providing a power supply voltage; and The power control circuit initiates power off of the power converter in response to the standby start indication from the safety control circuit and provides a standby response indication.

4. The processing system according to claim 3, characterized in that The power management processing module further includes: Watchdog timer; and wherein the power control circuit starts the watchdog timer in response to the standby start indication from the safety control circuit, wherein when the watchdog timer times out, the power management processing module performs a reset process, and wherein when the power supply voltage is charged to above a predetermined high threshold level, the power control circuit asserts a power good pin in a first state, and when the power supply voltage is discharged to below a predetermined low threshold level, the power control circuit asserts a power good pin in a second state.

5. The processing system according to claim 4, characterized in that In response to receiving the low power exit request, the power control circuit stops the watchdog timer, reactivates the power converter, and prompts the security control circuit to wake up the security processing module.

6. The processing system according to claim 1 or 2, characterized in that: When the standby start indication is provided, the security processing module starts a confirmation timer, wherein when the confirmation timer times out before the standby response indication is provided, the security processing module performs a reset process, and wherein when the standby response indication is provided before the confirmation timer times out, the security processing module enters the low power mode and stops the confirmation timer.

7. The processing system according to claim 6, characterized in that The security processing module further includes at least one memory element that maintains a state of each of the at least one external pin during the low power mode.

8. The processing system according to claim 1 or 2, characterized in that: The security processing module further includes: a test circuit that performs a self-test of the security processing module during power-up and provides a pass indication of the self-test; and Wherein when the pass indication indicates a test failure, the safety processing module prevents entry into the standby mode.

9. A method for power mode management, characterized in that: include: receiving a digital code during normal mode; comparing the received digital code to a predetermined digital value; When the received digital code matches the predetermined digital value, starting a standby entry timer; providing a standby start indication to initiate transition from the normal mode to the low power mode only when a standby request indication is received before the standby entry timer times out; as well as transitioning from the low power mode to a normal mode in response to receiving a low power exit request; the processor requests entry into said low power mode by providing said digital code during said normal mode; After providing the digital code, the processor provides a low power request; the processor entering a low power mode when the power good indicator indicates that the power supply voltage is below a predetermined low threshold level; The processor requests entry into normal mode by providing a low power exit request; And the processor enters the normal mode when the power good indication indicates that the power supply voltage is above a predetermined high threshold level.

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