Wafer level method of testing semiconductor devices with internally generated test enable signals

Abstract

A wafer-level method of testing integrated circuit (IC) devices and an integrated circuit wafer are provided. The method includes (i) applying a plurality of test operation signals to a wafer containing the IC devices, (ii) generating a test enable signal in response to detecting a toggle of at least one of the plurality of test operation signals on the wafer, and subsequently (iii) testing at least a portion of the IC devices in response to the generation of the test enable signal. The step of generating can further include generating the test enable signal in response to detecting a transition from inactive to active of a toggle detection signal on the wafer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0059130, filed on May 20, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to integrated circuit devices, and more specifically, to wafer-level methods for testing integrated circuit devices. Background Technology

[0004] Semiconductor devices formed on a silicon substrate are typically fabricated using a series of discrete processes, including but not limited to film lamination, impurity doping, photolithography to pattern these films, and etching. Testing is usually performed to determine whether the semiconductor device fabricated on the wafer using fabrication by assembly (FAB) processes operates correctly to meet a specific design.

[0005] During wafer-level testing of semiconductor devices, testers with probe arrays may experience test pad failures because these test pads, which are in physical and electrical contact with probes when a test enable signal is applied through one or more test pads to perform the test, can cause the semiconductor device to remain in test mode during the expected normal operating mode. Summary of the Invention

[0006] The present invention provides a wafer-level testing method for semiconductor devices, which uses an internal test enable signal generated inside the wafer of the semiconductor device instead of receiving the test enable signal from the tester through test pads.

[0007] According to one aspect of the present invention, a wafer-level testing method for semiconductor devices included in a wafer formed on the top surface of a wafer is provided. In some embodiments of the present invention, the wafer-level testing method includes: (i) receiving test operation signals provided on the wafer by an external tester via test pads of the wafer; (ii) detecting a switching of any of the test operation signals on the wafer; (iii) generating an internal test enable signal on the wafer in response to the detected switching; and (iv) performing tests on the semiconductor device on the wafer based on the internal test enable signal.

[0008] According to another aspect of the inventive concepts, there is provided a wafer-level test method for a stacked semiconductor chip in which a plurality of core wafers including semiconductor devices configured to operate independently and a buffer wafer configured to provide a channel interface (independent of each of the core wafers) are stacked. The wafer-level test method includes: (i) setting a test mode register set (TMRS) bit signal on the buffer wafer, the signal being assigned to indicate that an external tester is not to use access signal pads, (ii) receiving, on the buffer wafer, main test operation signals provided by the external tester via main test pads of the buffer wafer, (iii) detecting, on the buffer wafer, toggling of any of the main test operation signals, (iv) generating, on the buffer wafer, an internal main test enable signal in response to the detected toggling (after receiving the TMRS bit signal), (v) transmitting, on the buffer wafer, the internal main test enable signal to an internal test enable signal line of a channel of a core wafer selected from the core wafers via a pass-through electrode of the core wafer, and (vi) performing a test on the semiconductor devices in the selected channel based on the internal main test enable signal.

[0009] According to another aspect of the inventive concepts, there is provided a semiconductor device included in a wafer formed on a top surface of a wafer. The semiconductor device includes: (i) a test circuit configured to perform a test on the semiconductor device, and (ii) a test pad connected to the test circuit. The test pad is configured to receive test operation signals provided by an external tester for a probe test. The test circuit is configured to: detect toggling of any of the test operation signals, generate an internal test enable signal in response to the detected toggling, and perform the test on the semiconductor device based on the internal test enable signal.

[0010] According to another aspect of the inventive concepts, there is provided a stacked semiconductor chip including: (i) a plurality of core wafers including semiconductor devices (each configured to operate independently), and (ii) a buffer wafer configured to provide a channel interface independent of each of the core wafers via pass-through electrodes of the core wafers. The buffer wafer includes: (i) main test pads configured to receive main test operation signals provided by an external tester for a probe test, (ii) a mode register configured to set a bit signal assigned to indicate that the external tester is not to use test access signals of the test access signal pads, and (iii) a main test circuit. The main test circuit is configured to output a toggle detection signal by detecting toggling of any of the main test operation signals, generate an internal main test enable signal in response to the bit signal of the mode register and the toggle detection signal, and transmit the internal main test enable signal to an internal test enable signal line of a channel selected from the core wafers via the pass-through electrodes.

[0011] According to another aspect of the inventive concepts, a wafer-level method of testing an integrated circuit (IC) device includes (i) applying a plurality of test operating signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting a toggle of at least one of the plurality of test operating signals on the wafer, and subsequently (iii) testing at least a portion of the IC device in response to the generation of the test enable signal. In these aspects, the wafer includes a plurality of IC dies separated from one another by a plurality of scribe lines, and a first IC die of the plurality of IC dies includes the IC device. The generating step can further include generating the test enable signal in response to detecting a non-active to active transition of a toggle detection signal on the wafer. Alternatively, the generating step can include generating the test enable signal in response to detecting (i) a non-active to active transition of a toggle detection signal on the wafer, and (ii) a power supply stable signal at an active level during the non-active to active transition of the toggle detection signal. And, in other aspects, the generating step can include generating a test detection signal in response to detecting a plurality of toggles of a first test operating signal of the plurality of test operating signals on the wafer. Similarly, in other aspects, the generating step can include generating a test detection signal in response to detecting (i) a plurality of toggles of a first test operating signal of the plurality of test operating signals, and (ii) a reset signal at a non-active level during the plurality of toggles of the first test operating signal of the plurality of test operating signals.

[0012] According to yet another aspect of the inventive concepts, an integrated circuit wafer includes a plurality of integrated circuit (IC) dies separated from one another by a plurality of scribe lines on the wafer. The plurality of IC dies includes a first IC die having a plurality of test pads thereon and a plurality of ICs therein. The plurality of ICs includes test circuitry configured to generate a test enable signal in response to detecting a toggle of at least one of a plurality of test operating signals applied to the plurality of test pads by an external tester electrically coupled to the plurality of test pads by a plurality of probes. The test circuitry can also be configured to generate the test enable signal in response to detecting a non-active to active transition of a toggle detection signal within the test circuitry. Additionally, the test circuitry can be configured to generate the non-active to active transition of the toggle detection signal in response to detecting a plurality of transitions of a first test operating signal of the plurality of test operating signals. BRIEF DESCRIPTION OF DRAWINGS

[0013] Embodiments of the inventive concepts will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1is a schematic diagram of a wafer on which a plurality of semiconductor devices are formed;

[0015] Figure 2 is a close-up view of a wafer of semiconductor devices according to an embodiment of the inventive concept;

[0016] Figure 3 is a configuration of semiconductor devices on a wafer in Figure 2 is a block diagram of a configuration of internal test enable signal generation circuitry in

[0017] Figure 4 is a block diagram of a test circuit in Figure 2 is a block diagram of a test circuit in

[0018] Figure 5 is a detailed diagram of a configuration of internal test enable signal generation circuitry in Figure 4 is a detailed diagram of a configuration of internal test enable signal generation circuitry in

[0019] Figure 6A and Figure 6B is a timing diagram illustrating operation of the test circuit in Figure 4 is a timing diagram illustrating operation of the test circuit in

[0020] Figure 7A and Figure 7B is a close-up view of a wafer of semiconductor devices according to an embodiment of the inventive concept;

[0021] Figure 8A and Figure 8B is a diagram of a package of semiconductor devices according to an embodiment of the inventive concept;

[0022] Figure 9 is a block diagram of a buffer wafer for probe testing in a high bandwidth memory (HBM) including semiconductor devices according to an embodiment of the inventive concept;

[0023] Figure 10 is a block diagram of a master test circuit in a buffer wafer in Figure 9 is a block diagram of a master test circuit in a buffer wafer in

[0024] Figure 11 is a detailed diagram of a configuration of internal master test enable signal generation circuitry in Figure 10 is a detailed diagram of a configuration of internal master test enable signal generation circuitry in

[0025] Figure 12A and Figure 12B is a timing diagram illustrating operation of the master test circuit of Figure 10 is a timing diagram illustrating operation of the master test circuit of

[0026] Figure 13 is a diagram of an HBM implemented as a stacked semiconductor chip according to an embodiment of the inventive concept; and

[0027] Figure 14This is a block diagram illustrating an application example of HBM, implemented as a stacked semiconductor chip according to an embodiment of the present invention, in a data center. Detailed Implementation

[0028] Figure 1 It is a schematic diagram of a wafer on which multiple semiconductor devices are formed, and Figure 2 This is an enlarged view of a wafer in a semiconductor device according to an embodiment of the present invention. (Refer to...) Figure 1 and Figure 2 Multiple wafers 200 can be formed on wafer 100 by a fabrication (FAB) process, and after the multiple wafers 200 are divided along scribing line 110, the multiple wafers 200 can be manufactured into individual unit chips or packages by an assembly process.

[0029] Between the FAB process and the assembly process, wafer-level testing or electronic wafer sorting (EDS) processes can be performed, that is, testing the semiconductor devices formed in each of the multiple wafers 200. Figure 2 The electrical characteristics of 230 in the figure. A wafer-level testing process can be a process in which a test operation signal is applied to a wafer 200 formed on wafer 100, and the wafer 200 determines whether it has defects by outputting a test result signal in response to the test operation signal. The tester 300 can provide a test operation signal, transmit the test operation signal to the wafer 200 via a probe card, and determine whether the wafer 200 has defects by receiving a test result signal from the wafer 200 in response to the test operation signal via the probe card.

[0030] Each chip 200 may include test pads on it. Figure 2 Test pads 210 (as shown in section 210) support wafer-level testing. When the probe card physically and electrically contacts test pads 210, the wafer 200 can execute a test mode in response to a test operation signal. In this case, electrostatic discharge (ESD) or noise may occur via test pads 210. ESD can be accompanied by the potentially destructive effects of large transient voltages. ESD protection circuitry can be connected to each test pad 210 to prepare for ESD.

[0031] The tester 300 can provide the test enable signal from the test operation signal to the test enable signal pad in test pad 210. The test enable signal can be used as a test command signal indicating the test mode, and when activated to a logic high level, it can be set to have a relatively high voltage level. However, when a large transient voltage from the tester 300 is applied to the test enable signal pad, the ESD protection circuit connected to the test enable signal pad can be short-circuited to reach the power supply voltage level. The test enable signal pad can then be fixed at the power supply voltage level.

[0032] Furthermore, after wafer-level testing is completed, when each wafer 200 is individually diced by performing a sawing process on wafer 100 along scribing line 110 and each wafer is realized as a stacked semiconductor chip by performing a packaging process of stacking high-quality wafers 200, the semiconductor devices in the stacked semiconductor chip may only operate in test mode and may not be able to operate in normal write / read operation mode because the test enable signal pad remains at the power supply voltage level.

[0033] The following describes in detail an example of a wafer-level testing method for semiconductor device 230 that does not receive a test enable signal from tester 300 via test pad 210 by using an internal test enable signal generated in wafer 200 of semiconductor device 230.

[0034] Reference Figure 2 The wafer 200 may include at least one or more test pads 210, test circuitry 220, and semiconductor devices 230. For ease of illustration, Figure 2 The wafer 200 is shown with test pads 210 and test circuitry 220 separated from the semiconductor device 230. However, the wafer 200 can be substantially regarded as the semiconductor device 230, and the test pads 210 and test circuitry 220 can be understood as being included in the semiconductor device 230.

[0035] Test pad 210 may not include a pad for receiving signals from the tester ( Figure 1 The test enable signal pad 210 provides the test enable signal TEST_EN from the tester 300. Test pad 210 can receive test operation signals (in addition to the test enable signal TEST_EN) from the tester 300. Test operation signals may include test clock signals, test command signals, test pattern signals, etc., for controlling the operation of the semiconductor device 230. Test pad 210 can be connected to test circuitry 220, and test circuitry 220 can be connected to semiconductor device 230.

[0036] According to embodiments of the inventive concept, the test pads 210 can include a test enable signal pad TEST_EN PAD. In this case, the tester 300 can be configured not to use the test enable signal pad TEST_EN PAD. The semiconductor devices 230 can include volatile memory devices or non-volatile memory devices. The volatile memory devices can include dynamic random access memory (RAM) (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus DRAM (RDRAM), etc. The non-volatile memory devices can include flash memory devices having flash memory cells, or memory devices such as resistive RAM (ReRAM), magnetic RAM (MRAM), and phase change RAM (PRAM) having resistive memory cells.

[0037] In addition, the semiconductor devices 230 can include a processor or a power management integrated circuit (PMIC). The processor can include a microprocessor (or micro control unit) or a central processing unit (CPU) that performs various computing functions such as specific computations and tasks. The processor can include a single core processor or a plurality of multi-core processors such as dual core processors, quad core processors, and hexa core processors. The processor can further include a cache memory. The PMIC can be configured to reduce power consumption of mobile devices such as smartphones and tablet personal computers (PCs) and to improve power efficiency.

[0038] As described herein, the wafer 200 can be coupled to the tester 300 including probes via the test pads 210 to perform wafer level testing. In the wafer level testing, the test circuit 220 can provide the test clock signal, the test command signal, the test address signal, and / or the test pattern signal received via the test pads 210 to the semiconductor devices 230. For simplicity of the drawing, the test circuit 220 and the semiconductor devices 230 are shown as being connected to each other via one signal line, but can actually be connected to each other via a plurality of signal lines.

[0039] The test circuit 220 can be configured to detect a switching of any of the test operation signals applied to the test pads 210, and can include an iTEST_EN generator 222 that generates an internal test enable signal (iTEST_EN) in response to the detected switching. According to embodiments, the iTEST_EN generator 222 can be configured to detect a switching of a second test operation signal a certain number of times (e.g., “n” times (where n is a natural number)) in a time interval in which a first test operation signal is at a certain logic level, and in response to the “n” times of switching of the second test operation signal, can generate the internal test enable signal iTEST_EN, as described below.

[0040] Figure 3 is a block diagram of a configuration of a semiconductor device 230 on a wafer 200 in accordance with an embodiment of the inventive concept. In this embodiment, a case where the semiconductor device 230 is implemented as a DRAM is described, but other non-DRAM memory devices can be provided in other embodiments of the inventive concept. Figure 2

[0041] Referring to Figure 3 , the semiconductor device 230 can include control logic 2010, refresh address generator 2015, address buffer 2020, bank control logic 2030, row address (RA) multiplexer (MUX) 2040, column address (CA) latch 2050, row decoder 2060, column decoder 2070, memory cell array 2080, sense amplifier 2085, input / output (I / O) gating circuit 2090, and data I / O buffer 2095.

[0042] The memory cell array 2080 can include first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d. Each of the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d can include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit lines.

[0043] The row decoder 2060 can include first to fourth memory bank row decoders 2060a, 2060b, 2060c, and 2060d connected to a corresponding one of the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d. The column decoder 2070 can include first to fourth memory bank column decoders 2070a, 2070b, 2070c, and 2070d connected to a corresponding one of the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d. Also, the sense amplifier 2085 can include first to fourth memory bank sense amplifiers 2085a, 2085b, 2085c, and 2085d connected to a corresponding one of the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d.

[0044] ​The first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d, the first to fourth memory bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth memory bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth memory bank sense amplifiers 2085a, 2085b, 2085c, and 2085d can constitute first to fourth memory banks, respectively. In the illustrated embodiment, an example of a semiconductor device 230 including four memory banks is shown, but according to other embodiments, the semiconductor device 230 can include a different number of memory banks.

[0045] The control logic 2010 can control the operation of the semiconductor device 230. When the level of the power supply voltage for driving the semiconductor device 230 is stably maintained, the control logic 2010 can generate a power voltage stabilization signal PVCCH and control the semiconductor device 230 to be in an operable state by using the power voltage stabilization signal PVCCH. The control logic 2010 can generate a control signal so that the semiconductor device 230 performs a write operation or a read operation. The control logic 2010 can include a command decoder 2011 for decoding a command CMD received from a memory controller, and a mode register 2013 for setting an operation mode of the semiconductor device 230. The command decoder 2011 can generate a control signal corresponding to the command CMD by decoding a write enable signal ( / WE), a row address strobe signal ( / RAS), a column address strobe signal ( / CAS), a chip select signal ( / CS), and the like. The mode register 2013 can provide a plurality of operation options of the semiconductor device 230, and program various functions, characteristics, and modes of the semiconductor device 230.

[0046] The control logic 2010 can control the refresh address generator 2015 to perform an auto-refresh operation in response to a refresh command, or can control the refresh address generator 2015 to perform a self-refresh operation in response to a self-refresh input command. The refresh address generator 2015 can generate a refresh address REF_ADDR corresponding to a row of memory cells on which a refresh operation is to be performed. The refresh address generator 2015 can generate the refresh address REF_ADDR by a refresh period defined in a standard of a volatile memory device. However, when the semiconductor device 230 includes a non-volatile memory device as described above, the refresh address generator 2015 can be omitted.

[0047] The address buffer 2020 can receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller. In addition, the address buffer 2020 can provide the received bank address BANK_ADDR to the bank control logic 2030, the received row address ROW_ADDR to the RA MUX 2040, and the received column address COL_ADDR to the CA latch 2050.

[0048] The bank control logic 2030 can generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, one of the first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d corresponding to the bank address BANK_ADDR can be activated, and one of the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d corresponding to the bank address BANK_ADDR can be activated.

[0049] The RA MUX 2040 can receive the row address ROW_ADDR from the address buffer 2020 and the refresh row address REF_ADDR from the refresh address generator 2015. The RA MUX 2040 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR. The row address ROW_ADDR output from the RA MUX 2040 can be applied to each of the first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d.

[0050] The bank row decoder activated by the bank control logic 2030 among the first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d can decode the row address ROW_ADDR output from the RA MUX 2040 and activate a word line corresponding to the row address ROW_ADDR. For example, the activated bank row decoder can apply a word line driving voltage to a word line corresponding to the row address.

[0051] CA latch 2050 can receive column address COL_ADDR from address buffer 2020 and temporarily store the received column address COL_ADDR therein. CA latch 2050 can gradually increment the received column address COL_ADDR in burst mode. CA latch 2050 can apply the temporarily stored or gradually incremented column address COL_ADDR to each of the first bank column decoders 2070a, 2070b, 2070c, and 2070d. The bank column decoder activated by bank control logic 2030 in the first bank column decoders 2070a, 2070b, 2070c, and 2070d can activate a sense amplifier corresponding to the bank address BANK_ADDR and column address COL_ADDR.

[0052] The I / O gating circuit 2090 and the circuitry for gating I / O data DQ may include: input data masking logic; a read data latch for storing read data output from the first memory array to the fourth memory arrays 2080a, 2080b, 2080c and 2080d; and a write driver for writing data from the first memory array to the fourth memory arrays 2080a, 2080b, 2080c and 2080d.

[0053] Read data output from one of the memory arrays 2080a, 2080b, 2080c, and 2080d (from the first to the fourth memory arrays 2080a, 2080b, 2080c, and 2080d) can be sensed by a sense amplifier corresponding to that memory array and stored in a read data latch. Write data to be written to the memory cell array of one of the memory arrays 2080a, 2080b, 2080c, and 2080d can be provided from the memory controller to the data I / O buffer 2095. Data provided to the data I / O buffer 2095 can be written to a memory array via a write driver.

[0054] The data I / O buffer 2095 can receive data from the tester during wafer-level testing. Figure 1 The test pattern signal provided by the 300 in the memory cell array 2080 is used as I / O data DQ, and can be provided to the I / O gate circuit 2090. The I / O gate circuit 2090 can write the test pattern signal to the target page of the memory cell array 2080 during wafer-level testing, read the test pattern signal from the target page, and provide the test pattern signal to the data I / O buffer 2095 as a test result signal. The data I / O buffer 2095 can output the test result signal as I / O data DQ.

[0055] Figure 4This is an embodiment of the concept of the present invention. Figure 2 A block diagram of the test circuit 220 in chip 200. (Refer to...) Figure 4 The test circuit 220 may include an iTEST_EN generator 222, which receives data from the tester via test pad 210. Figure 1 The test operation signal applied by the circuit 300 in the circuit generates iTEST_EN. The iTEST_EN generator 222 may include a switching detection circuit 410 and an iTEST_EN generation circuit 420.

[0056] The tester 300 can be configured such that a clock signal TCK is applied to a first test pad 211, a clock enable signal TCKE is applied to a second test pad 212, a reset signal TRESETn is applied to a third test pad 213, a row access strobe (RAS) signal TRASn is applied to a fourth test pad 214, a column access strobe (CAS) signal TCASn is applied to a fifth test pad 215, and a write enable signal TWEn is applied to a sixth test pad 216. The reset signal TRESETn, RAS signal TRASn, CAS signal TCASn, and write enable signal TWEn of the third to sixth test pads 213 to 216 can be signals used to control the operation of the semiconductor device 230. The reset signal TRESETn can include a signal that initializes the semiconductor device 230 to a reset state for calibration operations of the semiconductor device 230.

[0057] The switching detection circuit 410 can be connected to the second to sixth test pads 212 to 216, detecting the switching of any of the signals applied to the second to sixth test pads 212 to 216, and outputting a switching detection signal T_DET. The switching detection circuit 410 can detect the switching of any of the clock enable signal TCKE, reset signal TRESETn, RAS signal TRASn, CAS signal TCASn, and write enable signal TWEn, and can output the switching detection signal T_DET as the detection result. As shown in the figure, the switching detection signal T_DET can be triggered to a logic high level. The switching detection signal T_DET can be provided to the iTEST_EN generation circuit 420.

[0058] The iTEST_EN generation circuit 420 can be configured to generate an internal test enable signal iTEST_EN in response to a switching detection signal T_DET and a power supply voltage stabilization signal PVCCH. Semiconductor device 230 can provide the power supply voltage stabilization signal PVCCH. When the level of the power supply voltage used to drive semiconductor device 230 remains stably constant, the control logic of semiconductor device 230 ( Figure 3The power voltage stabilization signal PVCCH can be generated by the iTEST_EN generation circuit 420 in the test circuit 220. Illustratively, the power voltage stabilization signal PVCCH can be configured to be triggered to a logic high level.

[0059] The internal test enable signal iTEST EN can be a signal indicating that the test circuit 220 is used for wafer level testing of the semiconductor devices 230. The test circuit 220 can test electrical characteristics of the semiconductor devices 230 on the wafer 100 based on the internal test enable signal iTEST EN. The test circuit 220 can be configured to test items related to voltage I / O characteristics, current I / O characteristics, leakage characteristics, functional characteristics, operational characteristics, and / or timing characteristics of the semiconductor devices 230 based on the internal test enable signal iTEST EN.

[0060] Figure 5 is Figure 4 A detailed diagram of a configuration of the iTEST EN generation circuit 420 in the test circuit 220. Referring to Figure 5 , the iTEST EN generation circuit 420 can include a first transistor 502, a second transistor 504, and a latch 506. The first transistor 502 and the second transistor 504 can be connected in series with each other between a power voltage VDD node and a ground voltage VSS node, and the first transistor 502 can be implemented as a p-type channel metal oxide semiconductor (PMOS) transistor, while the second transistor 504 can be implemented as an n-type channel metal oxide semiconductor (NMOS) transistor. The power voltage stabilization signal PVCCH can be provided to a gate of the first transistor 502, and the switching detection signal T DET can be provided to a gate of the second transistor 504. The latch 506 can receive a voltage level of a connection node 503 of the first transistor 502 and the second transistor 504, and output the internal test enable signal iTEST EN as an output signal.

[0061] When the power voltage stabilization signal PVCCH is at a logic low level, the first transistor 502 can be turned on, the connection node 503 can have a level of the power voltage VDD, and the latch 506 can output the internal test enable signal iTEST EN at a logic low level. When the internal test enable signal iTEST EN is output at a logic low level, the test circuit 220 can be configured to be in a non-activated state, not testing the semiconductor devices 230.

[0062] When the power voltage stable signal PVCCH is at a logic high level, the first transistor 502 can be turned off. Thereafter, when the toggle detection signal T_DET is triggered to a logic high level, the second transistor 504 can be turned on, the connection node 503 can have a ground voltage VSS level, and the latch 506 can output the internal test enable signal iTEST EN at a logic high level. When the internal test enable signal iTEST EN is output at a logic high level, the test circuit 220 can be configured in an active state for testing the semiconductor device 230.

[0063] Figure 6A and Figure 6B is a timing diagram illustrating the operation of the test circuit 220 in Figure 4 . Figure 6A illustrates the operation of outputting the internal test enable signal iTEST EN based on toggling of the reset signal TRESETn in the test operation signals to a logic high level. Figure 6B illustrates the operation of outputting the internal test enable signal iTEST EN based on four toggles of the test clock enable signal TCKE in a time interval in which the reset signal TRESETn is at a logic low level.

[0064] Referring to Figure 1 , Figure 2 , Figure 4 and Figure 5 , Figure 6A at a time point TO, the test operation signals can be applied from the tester 300 to the dies 200 formed on the wafer 100 via a probe card. When the power voltage of the semiconductor device 230 is raised, the semiconductor device 230 can be initialized to a reset state in response to the reset signal TRESETn transitioning to a logic low level.

[0065] At a time point Tl, when the level of the power voltage for driving the semiconductor device 230 is stably maintained constant, the semiconductor device 230 can trigger the power voltage stable signal PVCCH to a logic high level. When the power voltage stable signal PVCCH is at a logic low level between the time point TO and the time point Tl, the iTEST EN generation circuit 420 can disable the internal test enable signal iTEST EN to be at a logic low level.

[0066] At a time point T2, the toggle detection circuit 410 can detect toggling of the reset signal TRESETn in the test operation signals. According to an embodiment, as an alternative to the reset signal TRESETn, the toggle detection circuit 410 can detect toggling of any one of the clock enable signal TCKE, the RAS signal TRASn, the CAS signal TCASn, and the write enable signal TWEn.

[0067] At the time point T3, as a result of the switching detection of the reset signal TRESETn, the switching detection circuit 410 can trigger the switching detection signal T_DET to the logic high level. Also, at the time point T4, the iTEST_EN generation circuit 420 can output the internal test enable signal iTEST_EN of the logic high level in response to both of the power voltage stabilization signal PVCCH of the logic high level and the switching detection signal T_DET. The internal test enable signal iTEST_EN of the logic high level can be configured so that the test circuit 220 performs the wafer level test on the semiconductor device 230. The semiconductor device 230 can be tested in response to the internal test enable signal iTEST_EN of the logic high level.

[0068] With respect to Figure 6A With respect to Figure 6B Between the time point T1 and the time point T2, the switching detection circuit 410 can detect the switching of any one of the other test operation signals of the test operation signals of the test pad 210 while the reset signal TRESETn is at the logic low level. The switching detection circuit 410 can detect the switching of the clock enable signal TCKE for a specific number of times while the reset signal TRESETn is at the logic low level.

[0069] Although the present embodiment shows an example of detecting the switching of the clock enable signal TCKE to the logic high level for a specific number of times (i.e., 4 times), the number of times of the switching can be differently set to n (where n is a natural number). According to an embodiment, the switching detection circuit 410 can detect the switching of the RAS signal TRASn, the CAS signal TCASn, or the write enable signal TWEn for a specific number of times (i.e., n times) while the reset signal TRESETn is at the logic low level, as an alternative to the clock enable signal TCKE.

[0070] At the time point T3, the switching detection circuit 410 can trigger the switching detection signal T_DET to the logic high level based on the switching of the clock enable signal TCKE to the logic high level for a specific number of times or 4 times while the reset signal TRESETn is at the logic low level.

[0071] At the time point T4, the iTEST_EN generation circuit 420 can output the internal test enable signal iTEST_EN of the logic high level in response to both of the power voltage stabilization signal PVCCH of the logic high level and the switching detection signal T_DET. The semiconductor device 230 can be tested in response to the internal test enable signal iTEST_EN of the logic high level.

[0072] Figure 7A and Figure 7B is a magnified view of the wafer 200_a of the semiconductor device 230 according to an embodiment of the inventive concept. With reference toFigure 7A and Figure 7B With Figure 2 compared to the wafer 200, the wafer 200_a can further include a through silicon via TSV formed through the semiconductor substrate to make external electrical contact. The through silicon via TSV penetrating the semiconductor substrate can be surrounded by an insulating layer. The through silicon via TSV can be separated from the test circuit 220 and the semiconductor device 230, and can be electrically connected to the test circuit 220 or the semiconductor device 230 via conductive pads (701 and 702). The through silicon via TSV can be at an edge of the wafer 200_a. Alternatively, the through silicon via TSV can be in a central portion of the wafer 200_a.

[0073] Figure 8A and Figure 8B is a diagram of a package of the semiconductor device 230 according to an embodiment of the inventive concept. In Figure 8A and Figure 8B , an example is shown in which a stacked semiconductor chip 800 in which a plurality of wafers 200_a of Figure 7A is mounted on a package substrate 810. According to an embodiment, the stacked semiconductor chip 800 can be in a chip scale package.

[0074] Referring to Figure 8A , the stacked semiconductor chip 800 is shown in which each of the plurality of wafers 200_a1, 200_a2, 200_a3, and 200_a4 including the test pads 210, the test circuit 220, and the semiconductor device 230 formed therein is connected to a buffer wafer 802. The through silicon vias TSVs of the stacked semiconductor chip 800 can be in direct contact with each other, or can be electrically connected to each other by using solder bumps.

[0075] Referring to Figure 8B , the stacked semiconductor chip 800 can be mounted on a package substrate 810. The stacked semiconductor chip 800 can be mounted by using a flip chip bonding method. The package substrate 810 can include various types of substrates, such as a printed circuit board, a flexible substrate, and a tape substrate. The package substrate 810 can include a flexible printed circuit board, a rigid printed circuit board, or a combination thereof in which internal wiring is formed.

[0076] The package substrate 810 may have a top surface and a bottom surface, and may include bonding pads, connection pads, and internal wiring. The bonding pads may be on the top surface of the package substrate 810 and may be electrically connected to the stacked semiconductor chip 800 via bumps 820. In other words, the bonding pads on the top surface of the package substrate 810 may be connected to the through-silicon vias (TSVs) of wafers 802, 200_a1, 200_a2, 200_a3, and 200_a4 via bumps 820. The connection pads may be on the bottom surface of the package substrate 810 and may be electrically connected to the bonding pads via internal wiring. Additionally, external connection terminals 840 (e.g., solder balls) for connecting the semiconductor package to external electronics may be attached to the connection pads. The stacked semiconductor chip 800 mounted above the package substrate 810 may be molded using a molding layer 830. The molding layer 830 may include, for example, an epoxy molding compound and may provide underfill between the package substrate 810 and the stacked semiconductor chip 800.

[0077] According to an embodiment, a stacked semiconductor chip 800 comprising stacked wafers 802, 200_a1, 200_a2, 200_a3, and 200_a4 can be packaged at the chip level. In this case, an external connection terminal 840 for connection to external electronic devices can be attached to a buffer wafer 802, which is the bottommost wafer among the stacked wafers 802, 200_a1, 200_a2, 200_a3, and 200_a4. The stacked semiconductor chip 800 can be configured as a high-bandwidth memory (HBM). HBM can provide wide I / O of multi-channel interface types to support various systems requiring high performance and low power, such as graphics cards, servers, supercomputers, and networks.

[0078] In the HBM stacked semiconductor chip 800, a DRAM semiconductor device is formed. Figure 3 The multiple chips 200_a1, 200_a2, 200_a3, and 200_a4 (230 in the original text) can be separated from the buffer chip 802, and are therefore referred to as core chips. Each of the core chips 200_a1, 200_a2, 200_a3, and 200_a4 can constitute an independent interface called a channel. A typical HBM of the four core chips 200_a1, 200_a2, 200_a3, and 200_a4 can be configured to include a total of eight I / O channels, two 128-bit channels per chip, for a total width of 1024 bits. The buffer chip 802 can provide an interface with eight independently operating I / O channels. The buffer chip 802 can, for example, be used as a master chip that independently provides clock frequency, command sequence, and data to each of the eight I / O channels.

[0079] Several types of tests are performed on HBM. Below, an example is described in detail of performing probe tests on a stacked semiconductor chip 800 using each I / O channel in the test buffer wafer 802. For example, as... Figure 9 The diagram illustrates a buffer wafer for probe testing in an HBM including a semiconductor device 230, according to an embodiment of the present invention. Specifically, Figure 9 The first core wafer 200_a1, the second core wafer 200_a2, and the buffer wafer 802 of the stacked semiconductor chip 800 shown in FIG8 are illustrated. Illustratively, the first core wafer 200_a1 may correspond to the first channel CHa, and the second core wafer 200_a2 may correspond to the second channel CHb.

[0080] Reference Figure 9 The buffer chip 802 may include a main test pad 910, a main test circuit 920, and a mode register 930. The main test pad 910 may be coupled to a tester ( Figure 1 The 300 in the diagram is used for probe testing on the first channel CHa or the second channel CHb. During probe testing, the main test pad 910 can receive the main test operation signal.

[0081] The main test circuit 920 can detect a switch in any of the test operation signals applied to the main test pad 910 and generate an internal main test enable signal iDA_EN based on the detected switch. The internal main test enable signal iDA_EN can be provided to either the first channel CHa or the second channel CHb via a through-silicon via (TSV). In an embodiment, the tester 300 can be configured to test a channel, for example, the first channel CHa, via the main test pad 910. Therefore, the internal main test enable signal iDA_EN can be provided to the first channel CHa.

[0082] The Mode Register 930 can be programmed for various operational options such as HBM functions, features, and modes. The Mode Register 930 can be divided into fields according to function and / or mode, and can be programmed via Mode Register Setting (MRS) commands or using user-defined variables. The Mode Register 930 can be configured to support test modes. The contents of the Mode Register 930 can be set or updated after power-on and / or reset for appropriate operation.

[0083] Mode register 930 can control the pads in test mode that have the test access signal DA_EN applied to them (with or without use of the main test pad 910). Figure 10The mode register 930 can be set or programmed by the tester 300 via the mode register input pin 917. The mode register 930 can assign a test mode register setting (TMRS) bit that indicates the use / non-use of the DA EN pad 917. Illustratively, when the TMRS bit is programmed to a value of "0", it can indicate that the DA EN pad 917 is not used in the probe test. In this case, the main test circuit 920 can generate an internal main test enable signal iDA EN as a logic high level. The internal main test enable signal iDA EN of the logic high level can be provided to the first channel CHa via the through silicon via TSV. The first channel CHa can be configured to test the semiconductor devices 230 based on the internal main test enable signal iDA EN of the logic high level.

[0084] However, when the TMRS bit is programmed to a value of "1", it can indicate that the DA EN pad 917 is used in the probe test. In this case, the main test circuit 920 can generate the internal main test enable signal iDA EN as a logic low level. Although the internal main test enable signal iDA EN is also provided to the first channel CHa via the through silicon via, the first channel CHa can be configured to be unaffected by the internal main test enable signal iDA EN of the logic low level. In this case, the first channel CHa can be directly or indirectly provided with the test access signal DA EN applied via the DA EN pad 917, and can be configured to test the semiconductor devices 230 of the first channel CHa based on the test access signal DA EN.

[0085] Figure 10 is according to an embodiment of the inventive concept Figure 9 A block diagram of the main test circuit 920 in the buffer wafer 802 according to an embodiment of the inventive concept is shown in FIG. 10. Referring to FIGS. 8 and 10, Figure 10 The main test circuit 920 can include a main switch detection circuit 1010 and an iTEST EN generation circuit 1020. The main test circuit 920 can receive signals related to the main test operation from the tester 300 (FIG. 9) via the main test pads 910. The main test operation can be referred to as a probe test operation for selected channels of the stacked semiconductor chip 800 performed by the buffer wafer 802. Figure 1 The main test circuit 920 can include a main switch detection circuit 1010 and an iTEST EN generation circuit 1020. The main test circuit 920 can receive signals related to the main test operation from the tester 300 (FIG. 9) via the main test pads 910. The main test operation can be referred to as a probe test operation for selected channels of the stacked semiconductor chip 800 performed by the buffer wafer 802.

[0086] The tester 300 can be configured to apply a main clock signal MCK to the first main test pad 911, a main clock enable signal MCKE to the second main test pad 912, and a main reset signal MRESETn to the third main test pad 913. The main reset signal MRESETn can be configured to initialize the stacked semiconductor chip 800 of the HBM to a full chip reset.

[0087] Row command and address signals MR can be applied to the fourth main test pad 914, and column command and address signals MC can be applied to the fifth main test pad 915. The row command and address signals MR can include command codes related to an activate command, a free charge command, and a refresh command, a bank and a row address. The column command and address signals MC can include command codes related to a write operation and a read operation, a mode register address and a code, a bank and a column address.

[0088] Core test instruction signals WSP can be applied to the sixth main test pad 916, and test access signals DA EN can be applied to the seventh main test pad 917. The core test instruction signals WSP and the test access signals DA EN can be included in signals defined by the Institute of Electrical and Electronics Engineers (IEEE) Standard 1500 protocol interface. The core test instruction signals WSP can include a channel selection code, a mask applied to a data word of a selected channel, serial and / or parallel test access instructions, and a timing. The test access signals DA EN can include a main test enable signal that directly enables testing of cores and related circuits embedded in the stacked semiconductor chip 800 of the HBM.

[0089] The main switch detection circuit 1010 can be connected to the second main test pad 912 to the sixth main test pad 916, and can output a main switch detection signal M DET by detecting a switch of any one of the signals applied to the second main test pad 912 to the sixth main test pad 916. The main switch detection circuit 1010 can detect a switch of any one of the main clock enable signal MCKE, the main reset signal MRESETn, the row command and address signals MR, the column command and address signals MC, and the core test instruction signals WSP, and can output the main switch detection signal M DET as a detection result. Illustratively, the main switch detection circuit 1010 can detect that the main reset signal MRESETn is switched to a logic high level, and can trigger the main switch detection signal M DET to a logic high level. The main switch detection signal M DET can be provided to the iTEST EN generation circuit 1020.

[0090] According to an embodiment, the main toggle detection circuit 1010 can detect a specific number of toggles or n toggles (where n is a natural number) of any of the signals applied to the second to sixth main test pads 912 to 916, and output a main toggle detection signal M_DET. Illustratively, the main toggle detection circuit 1010 can detect a specific number of toggles or n toggles of the core test instruction signal WSP during the main reset signal MRESETn is at a logic low level, and can output the main toggle detection signal M_DET. The main toggle detection signal M_DET can be triggered to a logic high level based on a specific number of toggles (e.g., four (4) toggles) of the core test instruction signal WSP during the main reset signal MRESETn is at a logic low level.

[0091] The iTEST_EN generation circuit 1020 can be configured to generate an internal main test enable signal iDA_EN in response to the main toggle detection signal M_DET, a main power voltage stable signal MPVCCH, and a TMRS bit signal. The main power voltage stable signal MPVCCH can be provided to the buffer wafer 802, and can be configured to be triggered to a logic high level when a level of a power voltage used to drive the stacked semiconductor chip 800 is stably maintained constant. The TMRS bit signal can be provided from the mode register (930) in the Figure 9

[0092] Figure 11 Figure 10 A detailed diagram of the configuration of the iTEST_EN generation circuit 1020 in the Figure 11 The iTEST_EN generation circuit 1020 can include an NAND logic circuit 1110, a first inverter circuit 1112, a toggler circuit 1114, a second inverter circuit 1116, and an NOR logic circuit 1118, with reference to FIG. 11A.

[0093] The toggler circuit 1114 can include a data input terminal D connected to a power voltage VDD node and a clock signal input terminal connected to an output signal of the first inverter circuit 1112, and can provide a toggler operation output signal to the second inverter circuit 1116. The second inverter circuit 1116 can receive an output signal of the toggler circuit 1114, and can provide an inverted output signal to the NOR logic circuit 1118.​​

[0094] The NOR gate logic circuit 1118 can receive the output signal of the second inverter circuit 1116 and the TMRS bit signal, and can output the internal main test enable signal iDA_EN as the NOR operation output signal. When the DA_EN pad is indicated ( Figure 9 When the TMRS bit signal of (917) is set to logic high, the NOR gate logic circuit 1118 can output a logic low internal master test enable signal iDA_EN, thus disabling the internal master test enable signal iDA_EN. In this case, the test access signal DA_EN applied via the DA_EN pad 917 can be provided directly or indirectly to the first channel CHa via the silicon through-hole (TSV), and the first channel CHa can be configured to test the semiconductor device 230 based on the test access signal DA_EN. (Refer to...) Figure 12A and Figure 12B Describes when the logical DA_EN pad is not used ( Figure 9 The operation when the TMRS bit signal of 917 is set to logic low.

[0095] Figure 12A and Figure 12B It is shown Figure 10 Timing diagram of the operation of the main test circuit 920. Figure 12A This demonstrates the operation of outputting the internal master test enable signal iDA_EN based on the master reset signal MTRESETn switching to a logic high level. Figure 12B The operation of outputting the internal master test enable signal iDA_EN is shown by switching the core test instruction signal WSP four times during the time interval when the master reset signal MTRESETn is at a logic low level.

[0096] Combination Figure 8A , Figure 9 , Figure 10 and Figure 11 Reference Figure 12A At time point Ta0, data can be obtained from the tester via the probe card. Figure 1 In step 300, the power supply voltage VDD and the test operation signal are applied to the buffer wafer 802 of the stacked semiconductor chip 800. In the mode register 930, the TMRS bit indicating that the DA_EN pad 917 is not used can be reserved, and the TMRS bit signal can be set to logic low. When the power supply voltage VDD of the stacked semiconductor chip 800 rises, the stacked semiconductor chip 800 can be initialized to a full chip reset in response to the main reset signal MRESETn transitioning to logic low.

[0097] At time point Ta1, when the level of the power supply voltage VDD for driving the stacked semiconductor chip 800 is stably kept constant, the buffer wafer 802 can toggle the main power voltage stable signal PVCCH to a logic high level. When the main power voltage stable signal MPVCCH is at a logic low level between the time point Ta0 and the time point Ta1, the iDA_EN generation circuit 1020 can disable the internal main test enable signal iDA_EN to be at a logic low level, which is a default value.

[0098] At time point Ta2, the main toggle detection circuit 1010 can detect a toggle of the main reset signal MRESETn in the test operation signals of the main test pad 910. According to an embodiment, as an alternative to the main reset signal MRESETn, the main toggle detection circuit 1010 can detect a toggle of any one of the main clock enable signal MCKE, the row command and address signal MR, the column command and address signal MC, and the core test instruction signal WSP.

[0099] At time point Ta3, the main toggle detection circuit 1010 can toggle the main toggle detection signal M_DET to a logic high level as a result of detecting the toggle of the main reset signal MRESETn. Also, at time point Ta4, the iDA_EN generation circuit 1020 can output the output signal of the NAND gate logic circuit 1110 at a logic low level, the output signal of the first inverter circuit 1112 and the output signal of the switch circuit 1114 at a logic high level, and the output signal of the second inverter circuit 1116 at a logic low level in response to the main power voltage stable signal MPVCCH and the main toggle detection signal M_DET at a logic high level. The NOR gate logic circuit 1118 can output the internal main test enable signal iDA_EN at a logic high level as its output signal in response to the TMRS bit signal at a logic low level and the output signal of the second inverter circuit 1116 at a logic low level.

[0100] The buffer wafer 802 having performed the above operations can provide the internal main test enable signal iDA_EN at a logic high level to the first channel CHa via the through silicon via TSV. The first channel CHa can be configured to test the semiconductor device 230 based on the internal main test enable signal iDA_EN at a logic high level.

[0101] Referring to Figure 12B , with Figure 12AIn comparison, between the time point Ta1 and the time point Ta2, the main switching detection circuit 1010 can detect a switching of any one of the remaining test operation signals of the test operation signals of the main test pad 910 during the main reset signal MRESETn is at a logic low level. The main switching detection circuit 1010 can detect a specific number of switching of the core test instruction signal WSP during the main reset signal MRESETn is at a logic low level.

[0102] Although the present embodiment shows an example of detecting a specific number of switching (e.g., 4 times of switching) of the core test instruction signal WSP set to a logic low level, the number of switching can be differently set to n (where n is a natural number). According to an embodiment, as an alternative to the core test instruction signal WSP, the main switching detection circuit 1010 can detect a specific n number of switching of the main clock enable signal MCKE, the row command and signal MR, or the column command and address signal MC in the time interval in which the main reset signal MRESETn is at a logic low level.

[0103] At the time point Ta3, the main switching detection circuit 1010 can trigger the main switching detection signal M_DET to a logic high level based on the 4 times of switching of the core test instruction signal WSP at a logic low level in the time interval in which the main reset signal MRESETn is at a logic low level. Also, at the time point Ta4, in response to the main power voltage stable signal MPVCCH and the main switching detection signal M_DET at a logic high level and the TMRS bit signal at a logic low level, the iDA_EN generation circuit 1020 can output the internal main test enable signal iDA_EN as its output signal. The internal main test enable signal iDA_EN at a logic high level can be provided to the first channel CHa via the through silicon via TSV, and the first channel CHa can be configured to test the semiconductor device 230 based on the internal main test enable signal iDA_EN at a logic high level.

[0104] Figure 13 is a diagram of an HBM implemented as a stacked semiconductor chip according to an embodiment of the inventive concept. Referring to Figure 13HBM 1300 can include a plurality of core wafers 200_al, 200_a2, 200_a3, and 200_a4 and a buffer wafer 802, and through silicon vias TSVs can be at central portions of the plurality of core wafers 200_al, 200_a2, 200_a3, and 200_a4. Each of the plurality of core wafers 200_al, 200_a2, 200_a3, and 200_a4 can include two channels CHa-CHb, CHc-CHd, CHe-CHf, and CHg-CHh, respectively, and thus, the HBM 1300 can have eight channels CHa to CHh. Each of the channels CHa to CHh can include channel pads 1310 connected to the electrodes 1320 and the through silicon vias TSVs via wires for signal routing. A single channel can include two pseudo channels. When 128 DQ pads are included in the channel pads 1310, the 128 DQ pads can be divided into two groups of pseudo channels, and the number of DQ pads for each pseudo channel can be 64.

[0105] Each of the channels CHa to CHh can include a semiconductor device 230, a test pad 210 receiving a test operation signal provided by a tester 300 for probe testing, and a test circuit 220 for testing the semiconductor device 230, which are independently operated. Figure 1

[0106] The test circuit 220 can output a toggle detection signal by detecting toggling of any of the first test operation signals or by detecting toggling of the second test operation signal a certain number of times or n times in a time interval in which the first test operation signal among the test operation signals is set to a certain logic level. The test circuit 220 can be configured to generate an internal test enable signal iTEST_EN in response to the toggle detection signal and test the semiconductor device 230 based on the internal test enable signal iTEST_EN.

[0107] The buffer wafer 802 can provide an independent interface to each of the channels CHa to CHh via the through silicon vias TSVs of the core wafers 200_al, 200_a2, 200_a3, and 200_a4. The buffer wafer 802 can include a main test pad 910 receiving a main test operation signal provided by the tester 300 for probe testing, a mode register 930 setting a bit signal TMRS allocated to indicate that a test access signal DA_EN among the main test pads 910 is not used, and a main test circuit 920 generating an internal main test enable signal iDA_EN.

[0108] ​The main test circuit 920 can output a main switching detection signal by detecting a switching of any one of the main test operation signals or by detecting a switching of the second main test operation signal a certain number of times in a time interval in which the first main test operation signal among the main test operation signals is set to a certain logic level. The main test circuit 920 can generate an internal main test enable signal iDA_EN in response to a bit signal TMRS of the mode register 930 and the main switching detection signal M_DET, and transmit the internal main test enable signal iDA_EN to an internal test enable signal iTEST_EN line of a selected channel in the core wafer 200_a1, 200_a2, 200_a3, and 200_a4 via a through silicon via TSV.

[0109] Figure 14 is a block diagram of an application example to which an HBM implemented as a stacked semiconductor chip according to an embodiment of the inventive concept is applied to a data center 1400. Referring to Figure 14 , the data center 1400 can integrate a plurality of computing resources distributed in a network 1410 and provide a service required by a user. The data center 1400 can include a plurality of server systems 1401, 1402, and 1403. Each of the plurality of server systems 1401, 1402, and 1403 can communicate with various nodes 1420, 1430, and 1440 through the network 1410 such as the Internet. Although the network 1410 is illustrated as a single separate network, the network can be any type of network generally understood by one of ordinary skill in the art. The network 1410 can be a personal or public network, a wired or wireless network, or a complete or partial network. The nodes 1420, 1430, and 1440 can be any one of a client computer, another server, a remote data center, or a storage system.

[0110] The plurality of server systems 1401, 1402, and 1403 and / or the nodes 1420, 1430, and 1440 can include an HBM implemented as a stacked semiconductor chip of the inventive concept. The stacked semiconductor chip can be implemented by using Figures 1 to 13 embodiments illustrated. The stacked semiconductor chip can include a plurality of core wafers including semiconductor devices each of which independently operates, and a buffer wafer providing an independent channel interface for each of the plurality of core wafers through a through electrode of the plurality of core wafers.

[0111] Each core wafer can output a switching detection signal by detecting switching of any one of test operation signals applied from an external tester or by detecting n times of switching of a second test operation signal in a time interval in which a first test operation signal among the test operation signals is at a specific logic level, an internal test enable signal can be generated in response to the switching detection signal, and a probe test can be performed on the semiconductor devices 230 based on the internal test enable signal.

[0112] The buffer wafer can output a main switching detection signal by detecting switching of any one of main test operation signals applied from an external tester or by detecting n times of switching of a second main test operation signal in a time interval in which a first main test operation signal among the main test operation signals is at a specific logic level, generate an internal main test enable signal in response to a bit signal of a mode register allocated by the external tester to indicate that a test access signal pad among the main test pads is not used, transfer the internal main test enable signal to an internal test enable signal line of a selected lane among the core wafers via a through electrode, and perform a probe test on semiconductor devices of the selected lane based on the internal main test enable signal.

[0113] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A wafer-level method of testing an integrated circuit device, comprising the steps of: applying a plurality of test operation signals to a wafer containing the integrated circuit device; generating a test enable signal in response to detecting a toggling of at least one of the plurality of test operation signals on the wafer; then testing at least a portion of the integrated circuit device in response to the step of generating the test enable signal, wherein the step of detecting the toggling of at least one of the plurality of test operation signals comprises detecting a toggling of a second test operation signal of the plurality of test operation signals in a time interval in which a first test operation signal of the plurality of test operation signals is at a particular logic level, the first test operation signal being a reset signal used to initialize the at least a portion of the integrated circuit device, and the second test operation signal being any one of the other signals of the plurality of test operation signals other than the first test operation signal, wherein the toggling of the second test operation signal is detected after the second test operation signal is toggled n times to a particular logic level, where n is a natural number greater than 1.

2. The method of claim 1, wherein, the wafer includes a plurality of integrated circuit dies therein, the plurality of integrated circuit dies being separated from one another by a plurality of scribe lines; and wherein a first integrated circuit die of the plurality of integrated circuit dies includes the integrated circuit device.

3. The method of claim 1, wherein, the step of generating comprises generating the test enable signal in response to detecting a non-active to active transition of a toggle detection signal on the wafer.

4. The method of claim 1, wherein, the step of generating comprises generating the test enable signal in response to detecting on the wafer: (i) a non-active to active transition of a toggle detection signal, and (ii) an active level of a power supply stabilization signal during the non-active to active transition of the toggle detection signal.

5. The method of claim 1, wherein, the step of generating comprises generating the test detection signal in response to detecting a toggling of the second test operation signal in a time interval in which the first test operation signal is at a particular logic level on the wafer.

6. The method of claim 2, wherein, after the testing, separating the plurality of integrated circuit dies from one another by singulating the wafer along the plurality of scribe lines.

7. An integrated circuit wafer, comprising: a plurality of integrated circuit dies separated from one another by a plurality of scribe lines on the integrated circuit wafer, the plurality of integrated circuit dies including a first integrated circuit die having a plurality of test pads thereon and a plurality of integrated circuits therein, the plurality of integrated circuits including test circuitry configured to generate a test enable signal in response to detecting a toggling of at least one of a plurality of test operation signals applied to the plurality of test pads by an external tester, the external tester electrically coupled to the plurality of test pads by a plurality of probes, wherein the step of detecting the switching of at least one of the plurality of test operation signals includes detecting the switching of a second test operation signal of the plurality of test operation signals in a time interval in which a first test operation signal of the plurality of test operation signals is at a specific logic level, the first test operation signal being a reset signal for initializing semiconductor devices other than the test circuit in the plurality of integrated circuits, and the second test operation signal being any one of other signals of the plurality of test operation signals other than the first test operation signal, wherein the switching of the second test operation signal is detected after the second test operation signal is switched to the specific logic level n times, where n is a natural number greater than 1.

8. The integrated circuit wafer of claim 7, wherein, the test circuit is configured to generate the test enable signal in response to detecting a non-activation to activation transition of the switching detection signal within the test circuit.

9. The integrated circuit wafer of claim 8, wherein, the test circuit is configured to generate the non-activation to activation transition of the switching detection signal in response to detecting the switching of the second test operation signal in a time interval in which the first test operation signal is at the specific logic level.

10. A wafer level test method of a semiconductor device included in a die formed on a top surface of a wafer, the wafer level test method comprising: receiving test operation signals provided by an external tester on the die via test pads of the die; detecting a switching of any one of the test operation signals on the die; generating an internal test enable signal on the die in response to the detected switching; and performing a test on the semiconductor device on the die based on the internal test enable signal, wherein the step of detecting the switching of any one of the test operation signals includes detecting the switching of a second test operation signal of the test operation signals in a time interval in which a first test operation signal is at a specific logic level, the first test operation signal being a reset signal for initializing the semiconductor device, and the second test operation signal being any one of other signals of the test operation signals other than the first test operation signal, wherein the switching of the second test operation signal is detected after the second test operation signal is switched to the specific logic level n times, where n is a natural number greater than 1.

11. The wafer level testing method of claim 10, wherein, the second test operation signal is any one of a clock enable signal, a row access strobe signal, a column access strobe signal, and a write enable signal that control operations of the semiconductor device.

12. The wafer level testing method of claim 10, wherein, the switching of the second test operation signal is detected after a level of a power supply voltage that drives the semiconductor device is stably maintained constant.

13. A wafer level test method of a stacked semiconductor chip in which a plurality of core dies each configured to independently operate and a buffer die configured to provide a channel interface independent of each of the core dies are stacked, the wafer level test method comprising the steps of: setting a mode register set bit signal on the buffer wafer, the mode register set bit signal being assigned to indicate that an external tester is not to use test access signal pads; receiving, on the buffer wafer, main test operation signals provided by the external tester via main test pads of the buffer wafer; detecting, on the buffer wafer, toggling of any of the main test operation signals; generating, on the buffer wafer, an internal main test enable signal in response to the detected toggling, after receiving the mode register set bit signal; on the buffer wafer, transmitting the internal main test enable signal to an internal test enable signal line of a selected lane from the core wafer via a pass-through electrode of the core wafer; and performing, in the selected lane, a test on the semiconductor device based on the internal main test enable signal, wherein the step of detecting toggling of any of the main test operation signals includes detecting toggling of a second main test operation signal in a time interval in which a first main test operation signal is at a specific logic level, the first main test operation signal being a main reset signal for initializing the semiconductor device, and the second main test operation signal being any of other signals among the main test operation signals other than the first main test operation signal, wherein the toggling of the second main test operation signal is detected after the second main test operation signal is toggled to a specific logic level n times, where n is a natural number greater than 1.

14. The wafer level test method of claim 13, wherein: the second main test operation signal is any of a main clock enable signal, a row command and address signal, a column command and address signal, and a core test instruction signal that control operation of the stacked semiconductor chip, and the core test instruction signal includes a lane selection code, a mask applied to a data word of the selected lane, a serial and / or parallel test access instruction, and a timing.

15. The wafer level testing method of claim 13, wherein, the toggling of the second main test operation signal is detected after a level of a power supply voltage that drives the stacked semiconductor chip is stably kept constant.

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