Integrated circuit devices and their manufacturing methods

Abstract

An integrated circuit device and a method for manufacturing the same are provided. The integrated circuit device includes: an embedded insulating layer; a semiconductor layer located on the embedded insulating layer, the semiconductor layer having a main surface and a plurality of fin-type active regions protruding from the main surface and extending parallel to each other in a first horizontal direction; a separating insulating layer dividing the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction; source / drain regions located on the plurality of fin-type active regions; a first conductive plug located on and electrically connected to the source / drain regions; a buried track passing through the separating insulating layer and the semiconductor layer and electrically connected to the first conductive plug; and a power delivery structure disposed in the embedded insulating layer, the power delivery structure contacting and electrically connected to the buried track.

Description

[0001] Cross-references to related applications

[0002] This document incorporates in its entirety Korean patent application No. 10-2019-0059129 entitled "Integrated Circuit Device and Method of Manufacturing the Same", which was filed with the Korean Intellectual Property Office on May 20, 2019. Technical Field

[0003] This disclosure relates to integrated circuit devices and methods of manufacturing such integrated circuit devices, and more specifically, to integrated circuit devices having a power transmission network and methods of manufacturing such integrated circuit devices. Background Technology

[0004] With the development of electronic technology, the size of integrated circuit devices has shrunk. Highly integrated integrated circuit devices have to arrange many wiring layers in a small area while consistently ensuring the insulation distance between the wiring layers. Summary of the Invention

[0005] According to one aspect of an embodiment, an integrated circuit device is provided, comprising: an embedded insulating layer; a semiconductor layer disposed on the embedded insulating layer, the semiconductor layer having a main surface, wherein a plurality of fin-type active regions protrude from the main surface, wherein the plurality of fin-type active regions extend parallel to each other in a first horizontal direction within a plurality of element regions defined by a separating insulating layer; source / drain regions located on the plurality of fin-type active regions; a first conductive plug located on and electrically connected to the source / drain regions; a buried track passing through the separating insulating layer and the semiconductor layer and electrically connected to the first conductive plug; and a power delivery structure disposed in the embedded insulating layer and contacting the buried track for electrical connection to the buried track.

[0006] According to one aspect of the embodiments, an integrated circuit device is also provided, comprising an embedded insulating layer; a semiconductor layer disposed on the embedded insulating layer, the semiconductor layer having a plurality of finned active regions projecting therefrom, wherein the plurality of finned active regions extend parallel to each other along a first horizontal direction in a plurality of element regions defined by a separating insulating layer; a gate structure extending on the semiconductor layer along a second horizontal direction intersecting the first horizontal direction, the gate structure comprising a stacked structure having a gate insulating layer and gate lines; a plurality of source / drain regions located on opposite sides of the gate structure on the plurality of finned active regions; and a first conductive plug, wherein... The first conductive plug is located on the plurality of source / drain regions and is electrically connected to at least some of the plurality of source / drain regions; a buried track passes through the separating insulating layer and the semiconductor layer and is electrically connected to the first conductive plug; a power delivery structure is disposed in the embedded insulating layer and contacts the buried track to be electrically connected to the buried track; a back wiring structure is disposed on the lower surface of the embedded insulating layer opposite to the semiconductor layer and is electrically connected to the power delivery structure; and a back wiring inter-insulation layer partially surrounds the back wiring structure.

[0007] According to one aspect of the embodiments, a method for manufacturing an integrated circuit device is also provided, the method comprising: preparing a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a substrate layer, an embedded insulating layer, and a semiconductor layer sequentially stacked; forming a deep trench defining a plurality of element regions by partially removing the semiconductor layer; forming a preliminary separating insulating layer filling the deep trench; forming buried track vias through the preliminary separating insulating layer and the semiconductor layer, a buried track partially filling the lower portion of the buried track vias, and a preliminary covering insulating layer filling the upper portion of the buried track vias; exposing the embedded insulating layer by removing the substrate layer; and forming a power delivery structure in the embedded insulating layer, the power delivery structure contacting the buried track. Attached Figure Description

[0008] The features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figures 1A to 1C Plan view and cross-sectional view of an integrated circuit device according to an embodiment are shown respectively;

[0010] Figures 2A to 19D Plan layout and cross-sectional views of each stage in a method for manufacturing an integrated circuit device according to an embodiment are shown;

[0011] Figure 20 A cross-sectional view of an integrated circuit device according to an embodiment is shown; and

[0012] Figure 21 A cross-sectional view of an integrated circuit device according to an embodiment is shown. Detailed Implementation

[0013] Figure 1A This is a planar layout diagram of integrated circuit device 1 according to an embodiment. Figure 1B and Figure 1C They are along Figure 1A Cross-sectional views of lines X1-X1' and X2-X2'.

[0014] Reference Figures 1A to 1C Integrated circuit device 1 may include a FinFET device. FinFET devices can form logic units. A logic unit may include multiple circuit elements, such as transistors and resistors, and may have various structures. Logic units may be, for example, AND, NAND, OR, NOR, XOR, XNOR, inverters (INV), adders (ADD), buffers (BUF), delay units (ELY), filters (FIL), multiplexers (MXT / MXIT), OR / AND / INVERTER (AOI), AND / OR (AO), AND / OR / INVERTER (AOI), D flip-flops, reset flip-flops, master-slave flip-flops, latches, etc., and logic units may include standard units that perform the desired logic function, such as counters and buffers.

[0015] The integrated circuit device 1 may include a semiconductor layer 110 having a plurality of element regions including a first element region RX1 and a second element region RX2, and a plurality of fin-type active regions FA protruding upward from the first element region RX1 and the second element region RX2 in the semiconductor layer 110. The semiconductor layer 110 may have a main surface 110M extending horizontally (in the XY plane direction) at a first vertical height LV1. The plurality of fin-type active regions FA may protrude vertically (in the Z direction) upward from the main surface 110M of the semiconductor layer 110. The semiconductor layer 110 may include a semiconductor material (e.g., Si) or a compound semiconductor material (e.g., SiGe, SiC, GaAs, InAs, or InP). The semiconductor layer 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0016] Multiple finned active regions FA are arranged in a first horizontal direction (X direction) with a constant pitch, and the multiple finned active regions FA can extend parallel to each other in a second horizontal direction (Y direction). A separating insulating structure 112 can be disposed in the region between the finned active regions FA. An isolation layer 112a of the separating insulating structure 112 can cover the opposing sidewalls of the lower portion of the multiple finned active regions FA; for example, the isolation layer 112a can separate each two adjacent finned active regions FA from each other. In the first element region RX1 and the second element region RX2, the multiple finned active regions FA can protrude in a fin shape above the isolation layer 112a.

[0017] A deep trench DT can be formed in the semiconductor layer 110 around the first element region RX1 and the second element region RX2, and a separation insulating structure 112 can be formed in the deep trench DT. The separation insulating layer 112b of the separation insulating structure 112 can fill the deep trench DT.

[0018] A buried rail 150 may be disposed within a buried rail hole BRH, which passes through the separating insulating layer 112b and the semiconductor layer 110 and extends to the embedded insulating layer 105. The buried rail 150 may include a buried barrier layer 152 and a buried conductive layer 154. The buried barrier layer 152 may conformally cover the inner wall and bottom surface of the lower portion of the buried rail hole BRH, and the buried conductive layer 154 may fill the lower portion of the buried rail hole BRH while covering the buried barrier layer 152. The lower portion of the buried rail hole BRH is filled with the buried rail 150, and the remaining portion of the buried rail hole BRH (i.e., the upper portion above the buried rail 150) may be filled with the separating insulating structure 112. That is, the covering insulation layer 112c of the separating insulation structure 112 can fill the upper part of the buried track hole BRH, that is, the covering insulation layer 112c can fill the upper part of the top of the buried track hole BRH located above the buried track 150.

[0019] like Figure 1A As shown, the first width W1 of the deep trench DT filled with the separating insulating layer 112b between the first element region RX1 and the second element region RX2 (e.g., measured along a first horizontal direction (along the X direction) between the opposing sidewalls of the deep trench DT) can be greater than the second width W2 of the buried track hole BRH that accommodates the buried track 150 extending through the separating insulating layer 112b (e.g., measured along a first horizontal direction (along the X direction) between the opposing sidewalls of the buried track hole BRH). Therefore, the integrated circuit device 1 can be used without having an additional area for arranging the buried track 150.

[0020] The separating insulating structure 112 may include, for example, a silicon oxide layer, but is not limited thereto. In some example embodiments, at least a portion of the separating insulating structure 112 may include a first insulating pad, a second insulating pad, and a buried insulating layer sequentially stacked on the semiconductor layer 110. The isolation layer 112a, the separating insulating layer 112b, and the cover insulating layer 112c included in the separating insulating structure 112 may be formed separately from each other, and interfaces may exist between the isolation layer 112a and the separating insulating layer 112b and / or between the separating insulating layer 112b and the cover insulating layer 112c.

[0021] Reference Figure 1A and Figure 1C Multiple gate structures GS can extend on semiconductor layer 110 along a first horizontal direction (X direction) intersecting with multiple finned active regions FA. The multiple gate structures GS can have the same width in a second horizontal direction (Y direction) and can be arranged, for example, spaced apart in the second horizontal direction (Y direction), wherein they have a constant pitch. Figure 1C As shown, multiple gate structures GS can each have a stacked structure including a gate insulating layer 140 and a gate line GL. In some example embodiments, the gate insulating layer 140 can cover the lower surface and opposite sidewalls of the gate line GL. The upper surface of each gate structure GS can be covered by a gate masking layer 142.

[0022] Multiple gate structures GS can extend while covering the upper surface and opposite sidewalls of each of the multiple fin active regions FA, as well as the upper surface of the separating insulating structure 112. Multiple MOS transistors can be formed along the multiple gate structures GS in the first element region RX1 and the second element region RX2. Each of the multiple MOS transistors can have a three-dimensional (3D) structure, and channels are formed on the upper surface and opposite sidewalls of each fin active region FA.

[0023] In some embodiments, at least one of the plurality of gate structures GS may extend across the buried track 150, for example, at least one of the plurality of gate structures GS may extend across the top of the buried track 150. A covering insulating layer 112c may be located between the gate line GL of the gate structure GS and the buried track 150, thereby electrically insulating the gate line GL from the buried track 150, for example, the covering insulating layer 112c may cover the entire top of the buried track 150 facing the gate line GL of the gate structure GS.

[0024] exist Figure 1A and Figure 1CIn this embodiment, multiple gate structures GS extend along a first horizontal direction (X direction) through the entire first element region RX1 and the second element region RX2, but one or more embodiments are not limited thereto. The extension length of each of the multiple gate structures GS can be varied depending on the logic cell to be formed by the FinFET device included in the integrated circuit device 1. For example, some gate structures of the multiple gate structures GS may extend along the first horizontal direction (X direction) in the first element region RX1 without extending into the second element region RX2, and other gate structures of the multiple gate structures GS may extend along the first horizontal direction (X direction) in the second element region RX2 without extending into the first element region RX1.

[0025] Multiple insulating spacers 120 ( Figure 17C The insulating spacers 120 can cover the opposing sidewalls of multiple gate structures GS. That is, the opposing sidewalls of a gate structure GS can be covered by a pair of insulating spacers 120. The multiple insulating spacers 120 extend as lines together with the multiple gate structures GS in a first horizontal direction (X direction). The multiple insulating spacers 120 can each include, for example, a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof.

[0026] Multiple source / drain regions 130 may be formed in multiple finned active regions FA on opposite sides of the gate structure GS. In some embodiments, the multiple source / drain regions 130 may each have an embedded SiGe structure comprising multiple epitaxially grown SiGe layers. The multiple SiGe layers may have different Ge contents. In some embodiments, the multiple source / drain regions 130 may each comprise an epitaxially grown Si layer or an epitaxially grown SiC layer. The source / drain regions 130 and the gate structure GS may be insulated from each other by an insulating spacer 120 disposed between them.

[0027] The first inter-gate insulating layer 126 and the second inter-gate insulating layer 128 can be disposed between multiple gate structures GS. The first inter-gate insulating layer 126 may have a through hole VH filled with a via contact VC and a first contact hole CH1 filled with a first conductive plug CP1.

[0028] The first conductive plug CP1 can be electrically connected to the source / drain region 130 by at least partially contacting the upper surface of the source / drain region 130. A path contact VC can electrically connect the first conductive plug CP1 to the burial track 150. The upper surface of the path contact VC can contact (e.g., directly contact) the lower surface of the first conductive plug CP1, and the lower surface of the path contact VC can contact (e.g., directly contact) the upper surface of the burial track 150.

[0029] The first conductive plug CP1 may be covered by the second inter-gate insulating layer 128. The first inter-gate insulating layer 126 and the second inter-gate insulating layer 128 may include, for example, a silicon oxide layer. The first inter-gate insulating layer 126 and the second inter-gate insulating layer 128 may be collectively referred to as the inter-gate insulating layer.

[0030] The second conductive plug CP2 can fill the second contact hole CH2 that passes through the gate capping layer 142 and can be electrically connected to the gate line GL. For example, as Figure 1C As shown, the bottom of the second conductive plug CP2 can penetrate into the gate line GL, and the top surface of the gate cover layer 142 and the top surface of the second conductive plug CP2 can be flush.

[0031] The buried track 150 may extend into the embedded insulating layer 105 after passing through the separating insulating layer 112b and the semiconductor layer 110. The buried track 150 may extend from the semiconductor layer 110 while protruding into the embedded insulating layer 105.

[0032] A power transmission structure 160 may be disposed within an embedded insulating layer 105 and may contact the buried track 150 for electrical connection. The power transmission structure 160 extends from the lower surface of the embedded insulating layer 105 and fills a power transmission aperture PDH exposing the buried track 150. The power transmission structure 160 may include a power transmission barrier layer 162 and a power transmission conductive layer 164. The power transmission barrier layer 162 may conformally cover the inner surface of the power transmission aperture PDH, and the power transmission conductive layer 164 may cover the power transmission barrier layer 162 and fill the power transmission aperture PDH.

[0033] In some embodiments, at the portion where the burial track 150 and the power transmission structure 160 contact each other, the third width W3 of the burial track 150 in the first horizontal direction (X direction) may be smaller than the fourth width W4 of the power transmission structure 160. As described later, the burial track 150 is formed first, and then the power transmission structure 160 can be formed to contact the burial track 150. Because the fourth width W4 of the power transmission structure 160 is greater than the third width W3 of the burial track 150, the burial track 150 and the power transmission structure 160 can have excellent reliability in terms of electrical connection.

[0034] On the lower surface of the embedded insulating layer 105 opposite to the upper surface facing the semiconductor layer 110, a rear wiring structure 180 including a rear wiring layer 182 and a rear via plug 184, and a rear wiring inter-insulation layer 170 partially surrounding the rear wiring layer 182 and the rear via plug 184, can be disposed. In integrated circuit devices, the surface on which a transistor (e.g., a FinFET device) is disposed between opposing surfaces of a semiconductor layer or semiconductor substrate can be referred to as the front surface, and the surface opposite to the front surface can be referred to as the rear surface. The rear wiring inter-insulation layer 170 and the rear wiring structure 180 can be disposed on the surface of the semiconductor layer 110 opposite to the surface on which a plurality of finned active regions FA are formed. An external connection terminal 200 can be attached to the portion of the rear wiring structure 180 exposed through the lower surface of the rear wiring inter-insulation layer 170.

[0035] When the main surface 110M of the semiconductor layer 110 is at a first vertical height LV1, the upper surface of the buried track 150 is at a second vertical height LV2, which is higher than the first vertical height LV1, and the upper surface of the separating insulating structure 112 can be at a third vertical height LV3, which is higher than the second vertical height LV2. That is, the upper surface of the buried track 150 can be at the height between the main surface 110M of the semiconductor layer 110 and the upper surface of the separating insulating structure 112. The lower surface of the via contact VC can be at the second vertical height LV2.

[0036] The upper surface of the first conductive plug CP1 can be at a fourth vertical height LV4, and the upper surface of the second conductive plug CP2 can be at a fifth vertical height LV5, which is higher than the fourth vertical height LV4. Therefore, the upper surface of the second conductive plug CP2 can be at a higher height than the upper surface of the first conductive plug CP1.

[0037] In the integrated circuit device 1 according to one or more embodiments, power supplied via external connection terminals can be delivered to the source / drain region 130 via a back wiring structure 180, a power delivery structure 160, a buried track 150, and a first conductive plug CP1. The buried track 150 is disposed in a separating insulating layer 112b defining a first element region RX1 and a second element region RX2, and the power delivery structure 160 and the back wiring structure 180 are disposed on the rear surface of the semiconductor layer 110. Therefore, the buried track 150, the power delivery structure 160, and the back wiring structure 180 do not occupy additional area in the integrated circuit device 1. Thus, in the integrated circuit device 1, a back wiring layer 182 located on the rear surface of the semiconductor layer 110 and other wiring layers located on the front surface of the semiconductor layer 110 can be disposed, while having an insulating distance between them.

[0038] In addition, since the upper surface of the second conductive plug CP2 can be at a higher height than the upper surface of the first conductive plug CP1, the degree of freedom in arranging the first conductive plug CP1 and the second conductive plug CP2 can be improved.

[0039] Figures 2A to 19D This is a plan view and a cross-sectional view showing the various stages of a method for manufacturing an integrated circuit device according to an embodiment. Figures 2A to 19D The lines X1-X1', X2-X2', Y1-Y1', and Y2-Y2' correspond to respectively Figure 1A Lines X1-X1', X2-X2', Y1-Y1', and Y2-Y2'.

[0040] Figures 2A to 2C This is a plan view and cross-sectional view illustrating the process for forming multiple preliminary finned active regions F2 according to one or more embodiments. In detail, Figure 2B It is along Figure 2A A cross-sectional view taken by line X1-X1'. Figure 2C It is along Figure 2A The cross-sectional view taken from line Y1-Y1'.

[0041] Reference Figures 2A to 2C A semiconductor-on-insulator (SOI) substrate is prepared, comprising a substrate layer 100, an embedded insulating layer 105, and a semiconductor layer 110 sequentially stacked. The semiconductor layer 110 is then partially etched to form a plurality of preliminary fin-type active regions F2 protruding from the main surface 110M along a vertical direction (Z direction). The preliminary fin-type active regions F2 may be arranged, for example, spaced apart in a first horizontal direction (X direction) with a constant pitch, and the preliminary fin-type active regions F2 may extend in a second horizontal direction (Y direction). In some embodiments, the first horizontal direction (X direction) and the second horizontal direction (Y direction) may be perpendicular to each other.

[0042] The substrate layer 100 may include a semiconductor material, such as Si or Ge. The embedded insulating layer 105 may include an insulating layer having a composition comprising semiconductor atoms, an insulating layer comprising a metal oxide, an insulating layer comprising a metal nitride, or a stacked structure thereof. For example, the embedded insulating layer 105 may include: a layer comprising silicon oxide (SiO2). x Silicon nitride (SiN), silicon oxynitride (SiON), gallium oxide (GeO) x Gallium nitride (GeN) xThe semiconductor layer 110 may contain an insulating layer selected from aluminum oxide (Al2O3), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and aluminum nitride (AlN); or a stacked structure comprising at least two of these insulating layers. The semiconductor layer 110 may comprise a semiconductor (e.g., Si) or a compound semiconductor (e.g., SiGe, SiC, GaAs, InAs, or InP). The semiconductor layer 110 may comprise conductive regions, such as impurity-doped wells or impurity-doped structures.

[0043] Figure 3A and Figure 3B This is a cross-sectional view illustrating the process of forming the initial isolation layer 112ap according to one or more embodiments. In detail, Figure 3A Is along with Figure 2A The cross-sectional view of the portion corresponding to X1-X1' in the figure. Figure 3B Is along with Figure 2A The cross-sectional view of the part corresponding to Y1-Y1' in the diagram.

[0044] Reference Figure 3A and Figure 3B A preliminary isolation layer 112ap is formed on the semiconductor layer 110, covering a plurality of preliminary fin active regions F2. The preliminary isolation layer 112ap may cover the opposing sidewalls and upper surfaces of the plurality of preliminary fin active regions F2. In some embodiments, the upper surface of the preliminary isolation layer 112ap may be located at a height higher than the upper ends of the plurality of preliminary fin active regions F2.

[0045] The initial isolation layer 112ap may include, for example, a silicon oxide layer, but is not limited thereto. In some embodiments, the initial isolation layer 112ap may include a first insulating pad, a second insulating pad, and an embedded insulating layer sequentially stacked on the semiconductor layer 110.

[0046] Figures 4A to 4C This illustrates a plan view and a cross-sectional view of a process for forming deep trenches (DTs) according to one or more embodiments. In detail, Figure 4B It is along Figure 4A A cross-sectional view taken by line X1-X1'. Figure 4C It is along Figure 4A The cross-sectional view taken from line Y1-Y1'.

[0047] Reference Figures 4A to 4C The initial isolation layer 112ap and the semiconductor layer 110 are partially etched to form a deep trench DT defining a plurality of element regions RX1 and RX2. The plurality of element regions RX1 and RX2 may include a first element region RX1 and a second element region RX2.

[0048] A deep trench DT can be formed between a first element region RX1 and a second element region RX2, having a first width W1 in a first horizontal direction (X direction). The deep trench DT can extend from the upper surface of the initial isolation layer 112ap into the interior of the semiconductor layer 110. The bottom surface of the deep trench DT can be at a height lower than the main surface 110M of the semiconductor layer 110 and higher than the lower surface of the semiconductor layer 110.

[0049] In this specification, for ease of description, the description is based on the first element region RX1; however, the description of the first element region RX1 can also be applied to the second element region RX2. Elements that are the same as or similar to those connected to the first element region RX1 can also be connected to the second element region RX2.

[0050] Figure 5A and Figure 5B This is a cross-sectional view showing the process of forming an initial separating insulating layer of 112 bp according to one or more embodiments. In detail, Figure 5A Is along with Figure 4A The cross-sectional view of the portion corresponding to X1-X1' in the figure. Figure 5B Is along with Figure 4A The cross-sectional view of the part corresponding to Y1-Y1' in the diagram.

[0051] Reference Figure 5A and Figure 5B A preliminary insulating layer 112bp is formed to fill the deep trench DT. The preliminary insulating layer 112bp may include, for example, a silicon oxide layer, but is not limited thereto. The upper surface of the preliminary insulating layer 112bp and the upper surface of the preliminary insulating layer 112ap may be at the same height, but is not limited thereto. For example, the upper surface of the preliminary insulating layer 112bp may be formed at a height higher than the upper surface of the preliminary insulating layer 112ap, so that the upper surface of the preliminary insulating layer 112ap can be covered.

[0052] Figures 6A to 6C This is a plan view and a cross-sectional view illustrating the process of forming a buried track hole BRH according to one or more embodiments. Figure 6D This is a cross-sectional view illustrating the process of forming a buried track hole (BRHa) according to one or more embodiments. In detail, Figure 6B It is along Figure 6A A cross-sectional view taken by line X1-X1'. Figure 6C and Figure 6D It is along Figure 6A The cross-sectional view taken from line Y1-Y1'.

[0053] Reference Figures 6A to 6CThe buried via BRH can extend to the embedded insulating layer 105 after passing through the initial separating insulating layer 112bp and the semiconductor layer 110. The embedded insulating layer 105 can be exposed from the bottom surface of the buried via BRH. The buried via BRH extends to the embedded insulating layer 105 after passing through the initial separating insulating layer 112bp and the semiconductor layer 110, but may not extend to the lower surface of the embedded insulating layer 105 (i.e., the substrate layer 100). The bottom surface of the buried via BRH is at the same height as or lower than the lower surface of the semiconductor layer 110, but may be at a height higher than the lower surface of the embedded insulating layer 105 (i.e., the upper surface of the substrate layer 100).

[0054] The buried track hole BRH can have a second width W2 in the first horizontal direction (X direction) between the first element region RX1 and the second element region RX2, and can extend in the second horizontal direction (Y direction). The extension length of the buried track hole BRH in the second horizontal direction (Y direction) can be greater than its second width W2, such as... Figure 1A As shown. The second width W2 can be smaller than the first width W1. That is, in the first horizontal direction (X direction), the second width W2 of the buried track hole BRH can be smaller than the first width W1 of the deep trench DT.

[0055] Reference Figure 6D The buried track hole BRHa can extend to the embedded insulating layer 105 after passing through the initial separating insulating layer 112bp and the semiconductor layer 110. Figure 6D The buried track hole BRHa may include a main hole MH and an extension hole EH connected to the main hole MH.

[0056] That is, in Figures 6A to 6C The buried track hole BRH shown has a constant extension length in the second horizontal direction (Y direction) and extends from the upper surface of the initial separating insulation layer 112 bp to the embedded insulation layer 105. However, Figure 6D The buried track hole BRHa has a constant extension length in the second horizontal direction (Y direction) and may include a main hole MH extending from the upper surface of the initial separating insulation layer 112bp toward the embedded insulation layer 105 and an extension hole EH connected to the main hole MH and extending from the bottom surface of the main hole MH to the embedded insulation layer 105. In some embodiments, in Figure 6DIn a buried via BRHa, the master via MH can extend from the upper surface of the initial separating insulating layer 112bp to the semiconductor layer 110. For example, the bottom surface of the master via MH in the buried via BRHa may be at the same height as or lower than the upper surface of the semiconductor layer 110, but may be at a height higher than the lower surface of the semiconductor layer 110 (i.e., the upper surface of the embedded insulating layer 105). For example, the bottom surface of the extension via EH in the buried via BRHa may be at the same height as or lower than the lower surface of the semiconductor layer 110, but may be at a height higher than the lower surface of the embedded insulating layer 105 (i.e., the upper surface of the substrate layer 100).

[0057] exist Figure 6D In this embodiment, two extension holes EH are connected to the main hole MH, but one or more embodiments are not limited thereto. For example, a buried track hole BRHa may include one extension hole EH connected to the main hole MH or three or more extension holes EH connected to the main hole MH.

[0058] exist Figures 6A to 6C The buried track hole BRH shown can be formed by using a mask via an etching process. Figure 6D The buried track hole BRHa can be formed by using two masks via two etching processes. Here, one etching process or one of the two etching processes can refer not only to etching processes under the same etching atmosphere, but also to continuous etching processes performed while changing the etching atmosphere.

[0059] Figure 7 This is a cross-sectional view showing the process of forming the initial burial track 150p according to one or more embodiments. In detail, Figure 7 It is along Figure 6A A cross-sectional view of the portion intercepted by line X1-X1' in the diagram.

[0060] Reference Figure 7 The initial buried track 150p is filled into the buried track hole BRH. The initial buried track 150p may cover the upper surface of the initial isolation layer 112ap and the upper surface of the initial separating insulation layer 112bp. In some embodiments, a padding insulation layer conformally covering the inner wall and bottom surface of the buried track hole BRH may be formed before forming the initial buried track 150p. The padding insulation layer may include, for example, SiO2. x At least one of SiN and SiOCN.

[0061] The initial buried track 150p may include an initial buried barrier layer 152p and an initial buried conductive layer 154p. The initial buried barrier layer 152p may be formed to conformally cover the inner wall and bottom surface of the buried track hole BRH, the upper surface of the initial isolation layer 112ap, and the upper surface of the initial separating insulation layer 112bp. The initial buried conductive layer 154p may cover the surface of the initial buried barrier layer 152p and may fill the buried track hole BRH.

[0062] The initial buried barrier layer 152p may include, for example, Ti, Ta, TiN, TaN, or combinations thereof. The initial buried conductive layer 154p may include, for example, W, Mo, Ru, Nb, Hf, or combinations thereof.

[0063] Figure 8A and Figure 8B This is a cross-sectional view illustrating the process of forming the burial track 150 according to one or more embodiments. Figure 8C This shows a cross-sectional view of the burial track 150a according to one or more embodiments. In detail, Figure 8A It is along Figure 6A A cross-sectional view of the portion intercepted by line X1-X1' in the diagram. Figure 8B and Figure 8C It is along Figure 6A The cross-sectional view taken from line Y1-Y1' in the diagram.

[0064] Reference Figure 8A and Figure 8B Partial removal of the initially buried track ( Figure 7 The initial burial track 150 can be formed by partially removing the initial burial track 150p (i.e., the portion covering the upper surface of the initial isolation layer 112ap and the upper surface of the initial separating insulation layer 112bp, as well as the portion filling the upper part of the burial track hole BRH).

[0065] The buried track 150 may include a buried barrier layer 152 and a buried conductive layer 154. The buried barrier layer 152 may conformally cover the inner wall and bottom surface of the lower part of the buried track hole BRH, and the buried conductive layer 154 may cover the buried barrier layer 152 and fill the lower part of the buried track hole BRH.

[0066] The upper surface of the buried track 150 can be at a height lower than the upper ends of the plurality of preliminary fin active regions F2 and higher than the main surface 110M of the semiconductor layer 110. The buried track 150 can have a plate-like structure in the YZ plane.

[0067] After the buried track 150 is formed, a preliminary covering insulation layer 112cp is formed to fill the remaining portion of the buried track hole BRH, i.e., the upper portion of the buried track hole BRH. The preliminary covering insulation layer 112cp may include, for example, a silicon oxide layer, but is not limited thereto. The upper surface of the preliminary covering insulation layer 112cp may be at the same height as the upper surface of the preliminary insulating layer 112ap and / or the upper surface of the preliminary separating insulation layer 112bp, but is not limited thereto. For example, the upper surface of the preliminary covering insulation layer 112cp may be at a higher height than the upper surfaces of the preliminary insulating layer 112ap and the preliminary separating insulation layer 112bp, thus the preliminary covering insulation layer 112cp covers the upper surfaces of the preliminary insulating layer 112ap and the preliminary separating insulation layer 112bp. The preliminary insulating layer 112ap, the preliminary separating insulation layer 112bp, and the preliminary covering insulation layer 112cp may be collectively referred to as the preliminary separating insulation structure 112p.

[0068] Reference Figure 8C Partial removal of the initially buried track ( Figure 7 The initial burial track 150p is formed by partially removing the upper surface of the initial insulating layer 112ap and the upper surface of the initial separating insulation layer 112bp, and filling the space between the initial burial track 150p and the initial burial track 150a. Figure 6D The upper part of the burial track hole BRHa is used to form the burial track 150a.

[0069] The buried track 150a may include a buried barrier layer 152a and a buried conductive layer 154a. The buried barrier layer 152a may conformally cover the inner wall and bottom surface of the lower part of the buried track hole BRHa, and the buried conductive layer 154a may cover the buried barrier layer 152a and fill the lower part of the buried track hole BRHa.

[0070] The upper surface of the buried track 150a can be at a height lower than the upper end of the multiple preliminary fin active regions F2 and at a height higher than the main surface 110M of the semiconductor layer 110.

[0071] The buried track 150a may include a main track portion MR filled in the lower part of the main hole MH and an extension track portion ER filled in the extension hole EH and extending from the lower surface of the main track portion MR. The main track portion MR may have a plate-shaped structure in the YZ plane, and the extension track portion ER may have a passage structure connected to the lower surface of the main track portion MR.

[0072] In some embodiments, the lower surface of the main track portion MR may be at the same height as or lower than the upper surface of the semiconductor layer 110, but may be at a height higher than the lower surface of the semiconductor layer 110 (i.e., the upper surface of the embedded insulating layer 105). For example, the lower surface of the extension hole EH may be at the same height as or lower than the lower surface of the semiconductor layer 110, but may be at a height higher than the lower surface of the embedded insulating layer 105 (i.e., the upper surface of the substrate layer 100).

[0073] exist Figure 6D In this embodiment, two extension holes EH are connected to the main hole MH, but one or more embodiments are not limited thereto. For example, a buried track hole BRHa may include one extension hole EH connected to the main hole MH or three or more extension holes EH connected to the main hole MH.

[0074] exist Figure 8C In this embodiment, two extension track sections ER are connected to the main track section MR, but one or more embodiments are not limited thereto. For example, the burial track 150a may include the main track section MR and an extension track section ER connected to the main track section MR, or the main track section MR and three or more extension track sections ER connected to the main track section MR.

[0075] After the buried track 150a is formed, a preliminary covering insulation layer 112cp is formed to fill the remaining portion of the buried track hole BRH, i.e., the upper portion of the buried track hole BRH. The preliminary covering insulation layer 112cp may include, for example, a silicon oxide layer, but is not limited thereto. The upper surface of the preliminary covering insulation layer 112cp may be at the same height as the upper surface of the preliminary insulating layer 112ap and / or the upper surface of the preliminary separating insulation layer 112bp, but is not limited thereto. For example, the upper surface of the preliminary covering insulation layer 112cp may be at a higher height than the upper surfaces of the preliminary insulating layer 112ap and the preliminary separating insulation layer 112bp, thus the preliminary covering insulation layer 112cp covers the upper surfaces of the preliminary insulating layer 112ap and the preliminary separating insulation layer 112bp. The preliminary insulating layer 112ap, the preliminary separating insulation layer 112bp, and the preliminary covering insulation layer 112cp may be collectively referred to as the preliminary separating insulation structure 112p.

[0076] Figure 9 This illustrates the use of one or more embodiments. Figures 8A to 8C A cross-sectional view of the process by which the structure is attached to the carrier substrate 10. In detail, Figure 9 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0077] Reference Figure 9 ,Will Figures 8A to 8C The structure is inverted (i.e., upside down) so that the substrate layer 100 faces upward, and the initial separating insulating structure 112p faces the carrier substrate 10. Figures 8A to 8C The structure is attached to the carrier substrate 10. The adhesion film 12 can be arranged between the initial separating insulating structure 112p and the carrier substrate 10.

[0078] The area of ​​the carrier substrate 10 may be substantially equal to or larger than the area of ​​the base substrate layer 100. The carrier substrate 10 may include, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate. The adhesive film 12 may include a base film and adhesive layers attached to two opposing surfaces of the base film. The base film may include, for example, a polyethylene film (e.g., polyethylene terephthalate (PET) or polyethylene 2,6-naphthalate (PEN)) or a polyolefin film. The base film can be obtained by coating the polyethylene film or polyolefin film with silicone resin or Teflon. The adhesive layers may all include, for example, acrylic polymer resins, epoxy resins, or mixtures thereof.

[0079] Figure 10 This illustrates the removal of the substrate layer according to one or more embodiments. Figure 9 A cross-sectional view of the process (100%). In detail, Figure 10 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0080] Reference Figure 10 Remove substrate layer 100 (see Figure 9 The substrate layer 100 can be completely removed to expose the embedded insulating layer 105. The substrate layer 100 can be removed by back-side grinding or back-side polishing processes. For example, to expose the embedded insulating layer 105, the substrate layer 100 can be removed by chemical mechanical polishing (CMP), etching back, or a combination thereof.

[0081] Figure 11 This is a cross-sectional view illustrating the process of forming a mask pattern 50 according to one or more embodiments. In detail, Figure 11 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0082] Reference Figure 11A mask pattern 50 with an opening 55 is formed on an embedded insulating layer 105 using a photomask MK having a light-transmitting portion MO. The mask pattern 50 can be formed by forming a photoresist layer on the embedded insulating layer 105 and performing a photolithography process, in which exposure and development are performed using a photomask MK having a light-transmitting portion MO. Figure 11 The mask pattern 50 is shown to be formed using a positive photoresist layer, but one or more embodiments are not limited thereto. For example, the mask pattern 50 can be formed using a negative photoresist layer.

[0083] During the photolithography process using a photomask MK, the buried track 150 can be used as an alignment key (AK). That is, the embedded insulating layer 105 has relatively excellent light transmittance, so the buried track 150 extending to the embedded insulating layer 105 after passing through the semiconductor layer 110 can be used as an alignment key AK. Therefore, even if no additional alignment key is formed in the semiconductor layer 110 and / or the embedded insulating layer 105, the mask pattern 50 can be formed so that the openings 55 of the mask pattern 50 can be aligned in a direction perpendicular to the buried track 150 (Z direction).

[0084] Figure 12 This is a cross-sectional view illustrating the process of forming a power transmission port (PDH) according to one or more embodiments. In detail, Figure 12 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0085] Reference Figure 11 and Figure 12 An etching process that partially removes the embedded insulating layer 105 can be performed by using mask pattern 50 as an etching mask, thereby forming a power transmission via (PDH) that exposes the buried track 150. The PDH can also be formed by removing a portion of the embedded insulating layer 105 located at the bottom surface of the opening 55 in mask pattern 50.

[0086] exist Figure 12 In this embodiment, the buried track 150 is exposed on the bottom surface of the power delivery aperture PDH, but the semiconductor layer 110 is not exposed, and the embedded insulating layer 105 is partially retained. However, one or more embodiments are not limited thereto. In some embodiments, the semiconductor layer 110 may be exposed on the bottom surface of the power delivery aperture PDH.

[0087] Figure 13 This is a cross-sectional view illustrating the process of forming the power transmission structure 160 according to one or more embodiments. In detail, Figure 13 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0088] Reference Figure 13 A power transmission structure 160 is formed, filling the power transmission aperture PDH and electrically connected to the buried track 150. The power transmission structure 160 may include a power transmission blocking layer 162 and a power transmission conductive layer 164. The power transmission blocking layer 162 may conformally cover the inner wall and bottom surface of the power transmission aperture PDH, and the power transmission conductive layer 164 may cover the power transmission blocking layer 162 and fill the power transmission aperture PDH.

[0089] The power transmission structure 160 can be formed by the following steps: forming a preliminary barrier layer and a preliminary conductive layer, wherein the preliminary barrier layer covers the inner wall and bottom surface of the power transmission aperture PDH and the embedded insulating layer 105, and the preliminary conductive layer fills the power transmission aperture PDH and covers the preliminary barrier layer; then, removing portions of the preliminary barrier layer and the preliminary conductive layer covering the embedded insulating layer 105. The preliminary barrier layer may include, for example, TiN, TaN, TaC, WCN, or combinations thereof. The preliminary conductive layer may include, for example, Cu, Co, Ru, Mo, or combinations thereof.

[0090] In some embodiments, at the portion where the buried track 150 and the power transmission structure 160 contact each other, the third width W3 of the buried track 150 in the first horizontal direction (X direction) may be smaller than the fourth width W4 of the power transmission structure 160. Therefore, even if there are errors in aligning the buried track 150 and the power transmission hole PDH when forming the power transmission hole PDH for forming the power transmission structure 160, the buried track 150 can still contact the power transmission structure 160, resulting in excellent reliability of the electrical connection between them. For example, the third width W3 of the buried track 150 may be equal to the second width W2 of the buried track hole PDH.

[0091] Figure 14 This is a cross-sectional view illustrating the process of forming the post-wiring structure 180 according to one or more embodiments. In detail, Figure 14 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0092] Reference Figure 14 A rear wiring structure 180 electrically connected to the power transmission structure 160 is formed on the embedded insulating layer 105. The rear wiring structure 180 may include a rear wiring layer 182 and a rear access plug 184. A rear wiring interlayer insulating layer 170 may partially surround the rear wiring layer 182 and the rear access plug 184 forming the rear wiring structure 180 on the embedded insulating layer 105.

[0093] Both the rear wiring layer 182 and the rear access plug 184 may include a barrier layer for rear wiring and a metal layer for rear wiring. The barrier layer for rear wiring may include at least one of, for example, Ti, TiN, Ta, and TaN. The metal layer for rear wiring may include at least one metal of, for example, W, Al, and Cu. The rear wiring inter-insulation layer 170 may include, for example, silicon oxide and / or a low-k dielectric layer with a dielectric constant lower than that of silicon oxide. In some embodiments, the rear wiring inter-insulation layer 170 may also include a surface located away from the embedded insulation layer 105 (i.e., Figure 14 A passivation layer on the upper surface of the back wiring inter-insulation layer 170. In some embodiments, the passivation layer may include silicon nitride.

[0094] Figure 15 This illustrates a method based on one or more embodiments. Figure 14 A cross-sectional view of the process for removing the carrier substrate 10. In detail, Figure 15 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0095] Reference Figure 15 From Figure 14 After removing the carrier substrate 10 and the adhesion film 12, the structure will be... Figure 14 The structure is inverted so that the initial separating insulation structure 112p faces upward. Although in Figure 15 Not shown in the image, but it can be... Figure 14 The structure is inverted and attached to a carrier substrate, wherein the carrier substrate is attached with... Figure 9 The adhesive film shown is similar to the adhesive film shown in the figure.

[0096] Figure 16 This is a cross-sectional view illustrating the process of forming multiple finned active regions (FAs) according to one or more embodiments. In detail, Figure 16 It is along Figure 6A A cross-sectional view of the portion corresponding to line X1-X1'.

[0097] Reference Figure 15 and Figure 16The upper portion of the initial separating insulation structure 112p is partially removed to form the separating insulation structure 112. When the separating insulation structure 112 is formed by partially removing the upper portion of the initial separating insulation structure 112p, the upper portions of the plurality of initial fin active regions F2 exposed above the upper surface of the separating insulation structure 112 are partially removed. Then, a plurality of fin active regions FA can be formed, and the upper portion of each fin active region FA has a reduced width in the first horizontal direction (X direction), thus being smaller than the width of its lower portion. That is, the width of the upper portion of each of the plurality of fin active regions FA in the first horizontal direction (X direction) can be smaller than the width of the lower portion in the first horizontal direction (X direction). The separating insulation structure 112 can cover the opposing sidewalls of the lower portions of the plurality of fin active regions FA. In the plurality of element regions RX1 and RX2, the plurality of fin active regions FA can protrude above the upper surface of the separating insulation structure 112.

[0098] The separation insulation structure 112 can be obtained by partially removing the initial separation insulation structure 112p, that is, by removing the portion located at a height higher than the upper surface of the buried track 150. Therefore, the upper surface of the separation insulation structure 112 can be located at a height higher than the upper surface of the buried track 150. The separation insulation structure 112 may include an isolation layer 112a as part of the initial isolation layer 112ap, a separation insulation layer 112b as part of the initial separation insulation layer 112bp, and a cover insulation layer 112c as part of the initial cover insulation layer 112cp. The isolation layer 112a in the separation insulation structure 112 covers the opposing sidewalls of the lower portions of the plurality of finned active regions FA, the separation insulation layer 112b in the separation insulation structure 112 fills the deep trench DT, and the cover insulation layer 112c in the separation insulation structure 112 can cover the upper surface of the buried track 150, for example, it can fill the upper part of the buried track hole BRH. The buried track 150 fills the lower part of the buried track hole BRH, while the remaining part of the buried track hole BRH (i.e., the upper part of the buried track hole BRH) may be filled with the covering insulation layer 112c.

[0099] When the main surface 110M of the semiconductor layer 110 is at a first vertical height LV1, the upper surface of the buried track 150 is at a second vertical height LV2, which is higher than the first vertical height LV1, and the upper surface of the separating insulating structure 112 can be at a third vertical height LV3, which is higher than the second vertical height LV2. Therefore, the buried track 150 is not exposed during the process of forming the separating insulating structure 112 by partially removing the upper part of the preliminary separating insulating structure 112p.

[0100] Figures 17A to 17CThis illustrates a plan view and a cross-sectional view of the process for forming a dummy gate structure (DGS) according to one or more embodiments. In detail, Figure 17B It is along Figure 17A A cross-sectional view taken from line X2-X2'. Figure 17C It is along Figure 17A The cross-sectional view taken from the line Y2-Y2'.

[0101] Reference Figures 17A to 17C Multiple dummy gate structures (DGS) are formed on multiple fin-type active regions (FA) to extend intersecting with the multiple fin-type active regions (FA). Each of the multiple dummy gate structures (DGS) may include a dummy gate insulating layer (D12), a dummy gate line (D14), and a dummy gate insulating masking layer (D16) sequentially stacked on the multiple fin-type active regions (FA). The dummy gate insulating layer (D12) may include silicon oxide. The dummy gate line (D14) may include polysilicon. The dummy gate insulating masking layer (D16) may include silicon nitride.

[0102] Insulating spacers 120 can be formed on opposite sidewalls of the dummy gate structure (DGS). The insulating spacers 120 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes. The insulating spacers 120 may include, for example, silicon nitride.

[0103] Figure 18 This is a cross-sectional view illustrating the process of forming the source / drain region 130 according to one or more embodiments. In detail, Figure 18 It is along Figure 17A A cross-sectional view of the portion corresponding to line X1-X1'.

[0104] Reference Figures 17A to 18 Multiple finned active regions FA are partially removed from the opposite side of the dummy gate structure DGS to form a recess 130R, and a semiconductor material layer is formed from the exposed portion of the multiple finned active regions FA exposed through the recess 130R by epitaxial growth to form a source / drain region 130.

[0105] The source / drain region 130 may have an embedded SiGe structure comprising multiple epitaxially grown SiGe layers. The multiple SiGe layers may have different Ge contents. In some embodiments, the source / drain region 130 may each comprise an epitaxially grown Si layer or an epitaxially grown SiC layer.

[0106] In some embodiments, the source / drain region 130 may be covered by an insulating pad. The insulating pad may conformally cover the separating insulating structure 112, the insulating spacer 120, and the source / drain region 130. The insulating pad may include a silicon nitride layer.

[0107] Figure 19AThis is a plan view illustrating the process of forming the first conductive plug CP1 and the gate structure GS according to one or more embodiments. Figures 19B to 19D This is a cross-sectional view showing the process of forming the first conductive plug CP1 and the gate structure GS according to one or more embodiments. In detail, Figure 19B It is along Figure 19A A cross-sectional view taken by line X1-X1'. Figure 19C It is along Figure 19A A cross-sectional view taken from line X2-X2'. Figure 19D It is along Figure 19A The cross-sectional view taken from the line Y2-Y2'.

[0108] Reference Figures 19A to 19D A first inter-gate insulating layer 126 is formed between the dummy gate structures DGS. The source / drain regions 130 can be covered by the first inter-gate insulating layer 126. The first inter-gate insulating layer 126 may include, for example, a silicon oxide layer or a stacked structure including a silicon insulating layer and a silicon nitride layer.

[0109] Subsequently, a via VH is formed through the covering insulating layer 112c and the first gate inter-insulating layer 126, and a first contact hole CH1 is formed through the first gate inter-insulating layer 126, exposing the source / drain region 130. A via contact VC is formed filling the via VH, and a first conductive plug CP1 is formed filling the first contact hole CH1 and electrically connected to the via contact VC. In some embodiments, the via VH and the first contact hole CH1 may be formed separately and sequentially. In other embodiments, the via VH and the first contact hole CH1 may be formed together.

[0110] Both the via contact VC and the first conductive plug CP1 may include a conductive barrier layer and a conductive core layer covering the conductive barrier layer. The conductive barrier layer may include, for example, Ti, Ta, TiN, TaN, or combinations thereof, and the conductive core layer may include, for example, Co, W, or combinations thereof. In some embodiments, the via contact VC and the first conductive plug CP1 may be formed separately and sequentially. In other embodiments, the via contact VC and the first conductive plug CP1 may be formed together.

[0111] The first conductive plug CP1 may extend in a direction intersecting with multiple finned active regions FA. For example, the first conductive plug CP1 may extend in a first horizontal direction (X direction). The first conductive plug CP1 may be electrically connected to the source / drain region 130. A pass contact VC may electrically connect the first conductive plug CP1 to the buried track 150. The upper surface of the first conductive plug CP1 may be at a fourth vertical height LV4.

[0112] The burial track 150 is shown as electrically connected via a via contact VC to a first conductive plug CP1 connected to a source / drain region 130 formed in a first element region RX1, but one or more embodiments are not limited thereto. For example, the burial track 150 and the via contact VC may be formed separately to electrically connect the first conductive plug CP1 connected to the source / drain region 130 formed in a second element region RX2. Alternatively, for example, the burial track 150 and the via contact VC may electrically connect the first conductive plug CP1 connected to the source / drain region 130 formed in the first element region RX1 to the first conductive plug CP1 connected to the source / drain region 130 formed in the second element region RX2.

[0113] Forming a 130-fold coverage of the source / drain region and multiple dummy gate structures ( Figure 17A and Figure 17B The second gate-to-gate insulating layer 128 includes the source / drain regions 130, the plurality of dummy gate structures DGS, and the insulating spacers 120. To form the second gate-to-gate insulating layer 128, an insulating layer covering the source / drain regions 130, the plurality of dummy gate structures DGS, and the insulating spacers 120 is formed to a sufficient thickness. Afterward, the resulting material including this insulating layer can be planarized until the dummy gate masking layer D16 (see...) Figure 17A and Figure 17B The upper surface of the ) can be exposed.

[0114] Next, multiple dummy gate structures (DGS) are removed. A wet etching process can be performed to remove the multiple dummy gate structures (DGS). In the wet etching process, an etching solution including, for example, HNO3, diluted fluorine acid (DHF), NH4OH, tetramethylammonium hydroxide (TMAH), KOH, or combinations thereof can be used.

[0115] Subsequently, a gate insulating layer 140 and a gate conductive layer can be formed in the space from which the multiple dummy gate structures DGS have been removed. Before forming the gate insulating layer 140, a process for forming an interface layer on the surface of the fin active region FA exposed by the space from which the multiple dummy gate structures DGS have been removed can be performed. To form the interface layer, the fin active region FA exposed by the space from which the multiple dummy gate structures DGS have been removed can be partially oxidized.

[0116] A gate insulating layer 140 and a gate conductive layer can be formed to cover the upper surface of the second inter-gate insulating layer 128 and fill the space from which multiple dummy gate structures (DGS) have been removed. The gate insulating layer 140 and the gate conductive layer can be formed by, for example, ALD, CVD, physical vapor deposition (PVD), metal-organic ALD (MOALD), or metal-organic CVD (MOCVD) processes.

[0117] Unnecessary portions of the gate insulating layer 140 and the gate conductive layer are removed to expose the upper surface of the second inter-gate insulating layer 128, and multiple gate structures GS, each including the gate insulating layer 140 and the gate line GL, can be formed. Multiple source / drain regions 130 can be located on multiple finned active regions FA on opposite sides of the multiple gate structures GS.

[0118] The gate line GL can be formed such that its upper surface is lower than the upper surface of the insulating spacer 120, and then a gate cover layer 142 can be formed in the space defined between pairs of adjacent insulating spacers 120. The gate cover layer 142 can cover the upper surface of the gate structure GS.

[0119] The gate insulating layer 140 may include a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The high-k dielectric layer may include a material with a dielectric constant greater than that of the silicon oxide layer. The high-k dielectric layer may include a metal oxide or a metal oxynitride. The interface layer may include an oxide layer, a nitride layer, or an oxide nitride layer.

[0120] The gate line GL may have a structure in which a metal nitride layer, a metal layer, a conductive masking layer, and a gap-filling metal layer are sequentially stacked. The metal nitride layer and the metal layer may each include at least one of, for example, Ti, Ta, W, Ru, Nb, Mo, and Hf. The gap-filling metal layer may include, for example, a W layer or an Al layer. The gate line GL may include a layer of a metal with a work function. The layer of the metal with a work function may include at least one of, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, the gate line GL may include, for example, a stacked structure including TiAlC / TiN / W, a stacked structure including TiN / TaN / TiAlC / TiN / W, or a stacked structure including TiN / TaN / TiN / TiAlC / TiN / W, but is not limited thereto. The gate masking layer 142 may include, for example, a silicon nitride layer.

[0121] After that, as Figures 1A to 1C As shown, a second contact hole CH2 can be formed through the gate cover layer 142 and expose the gate line GL, and a second conductive plug CP2 can be filled in the second contact hole CH2 and electrically connected to the gate line GL.

[0122] In some embodiments, the upper surface of the second inter-gate insulating layer 128, the upper surface of the gate capping layer 142, and the upper surface of the second conductive plug CP2 are at a fifth vertical height LV5 to form a coplanar structure. The fifth vertical height LV5 may be higher than the fourth vertical height LV4. Therefore, the upper surface of the second conductive plug CP2 may be at a higher height than the upper surface of the first conductive plug CP1.

[0123] External connection terminals 200 are attached to a rear wiring structure 180 exposed from the lower surface of the rear wiring interlayer insulation layer 170 to form an integrated circuit device 1. External connection terminals 200 may include, for example, solder balls or bumps.

[0124] Figure 20 This is a cross-sectional view of the integrated circuit device 1a according to an embodiment. Figure 20 It is along Figure 1A The cross-sectional view taken by line X1-X1', and the reference above can be omitted. Figures 1A to 1C The description provided.

[0125] Reference Figure 20 The integrated circuit device 1a may include a buried track 150 and a power delivery structure 160 electrically connected to the buried track 150. The lower surface of the buried track 150 and the upper surface of the power delivery structure 160 may be at the same height as the upper surface of the embedded insulating layer 105. Therefore, the buried track 150 extends into the embedded insulating layer 105 after passing through the separating insulating layer 112b and the semiconductor layer 110, but may not extend into the embedded insulating layer 105. The power delivery structure 160 may extend from the lower surface to the upper surface of the embedded insulating layer 105.

[0126] Figure 21 This is a cross-sectional view of the integrated circuit device 1b according to an embodiment. Figure 21 It is along Figure 1A The cross-sectional view taken by line X1-X1', and the reference above can be omitted. Figures 1A to 1C The description provided.

[0127] Reference Figure 21 The integrated circuit device 1b may include a buried track 150 and a power delivery structure 160 electrically connected to the buried track 150. The upper surface of the buried track 150 and the main surface 110M of the semiconductor layer 110 may be at the same height, i.e., a first vertical height LV1. Therefore, the lower surface of the via contact VC may be at the first vertical height LV1.

[0128] By summarizing and reviewing, this disclosure provides an integrated circuit device having a structure and a method for manufacturing the integrated circuit device in which power can be stably supplied to the integrated circuit device even when numerous wirings and contacts are arranged in the integrated circuit device according to a scaled-down integrated circuit device size. Specifically, according to this disclosure, a semiconductor-on-insulator (SOI) wafer is used, and buried power tracks (BPRs) can be used as alignment marks in the process of forming the backside power delivery network (BS-PDN), thereby preventing misalignment. Furthermore, the BPRs and BS-PDN can be directly connected without the use of through-silicon vias (TSVs), thereby improving the reliability of the electrical connection.

[0129] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated at the time of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: Embedded insulating layer; A semiconductor layer located on the embedded insulating layer, the semiconductor layer having a main surface and a plurality of fin-shaped active regions protruding from the main surface of the semiconductor layer to extend in a second horizontal direction and parallel to each other; A separating insulating layer that divides the semiconductor layer into at least two element regions that are adjacent to each other in a first horizontal direction intersecting the second horizontal direction; Source / drain regions located on the plurality of finned active regions; A first conductive plug is located on the source / drain region and electrically connected to the source / drain region; A buried track, which passes through the insulating layer and the semiconductor layer and is electrically connected to the first conductive plug; as well as A power transmission structure is disposed in the embedded insulating layer and contacts the buried track for electrical connection to the buried track.

2. The integrated circuit device as claimed in claim 1, wherein, The first width of the separating insulating layer between the at least two element regions in the first horizontal direction is greater than the second width of the buried track in the first horizontal direction.

3. The integrated circuit device as described in claim 1, wherein, At the contact area between the buried track and the power transmission structure, the third width of the buried track in the first horizontal direction is smaller than the fourth width of the power transmission structure in the first horizontal direction.

4. The integrated circuit device of claim 1, further comprising: An isolation layer covers the lower opposing sidewalls of each of the plurality of fin active regions on the semiconductor layer, and the upper surface of the buried track is at a height lower than the upper surface of the isolation layer.

5. The integrated circuit device as claimed in claim 4, wherein, The upper surface of the buried track is at a height higher than the main surface of the semiconductor layer.

6. The integrated circuit device as claimed in claim 4, wherein, The upper surface of the buried track is at the same height as the main surface of the semiconductor layer.

7. The integrated circuit device of claim 1, further comprising: Multiple gate structures having a constant pitch and extending along the first horizontal direction on the semiconductor layer, each of the multiple gate structures having a stacked structure including a gate insulating layer and gate lines; as well as At least one second conductive plug is electrically connected to the gate line of a corresponding gate structure in the plurality of gate structures, and the at least one second conductive plug passes through a gate cover layer located on the corresponding gate line.

8. The integrated circuit device as claimed in claim 7, wherein, The upper surface of the at least one second conductive plug is at a height higher than the upper surface of the first conductive plug.

9. The integrated circuit device of claim 7, further comprising: An insulating cover is provided between the buried track and the corresponding gate line, the insulating cover providing electrical insulation between the buried track and the corresponding gate line.

10. The integrated circuit device of claim 9, further comprising: A pathway contact is provided that passes through the covering insulation layer and connects the lower surface of the first conductive plug to the upper surface of the buried track.

11. The integrated circuit device as claimed in claim 1, wherein, The burial track includes a main track and at least one extension track having a passage structure connected to the lower surface of the main track.

12. The integrated circuit device of claim 11, wherein, The height of the lower surface of the main track is the same as or lower than the height of the upper surface of the semiconductor layer, and the height of the lower surface of the main track is higher than the height of the upper surface of the embedded insulating layer.

13. An integrated circuit device, the integrated circuit device comprising: An embedded insulating layer; A semiconductor layer located on the embedded insulating layer, the semiconductor layer having a plurality of fin-shaped active regions protruding from the semiconductor layer and extending parallel to each other in a second horizontal direction; A partition insulating layer that partitions the semiconductor layer into at least two element regions adjacent to each other in a first horizontal direction intersecting the second horizontal direction; A gate structure extending in the first horizontal direction on the semiconductor layer, the gate structure including a stacked structure having a gate insulating layer and a gate line; A plurality of source / drain regions located on the plurality of fin-shaped active regions on opposite sides of the gate structure; A first conductive plug located on the plurality of source / drain regions, the first conductive plug being electrically connected to at least some of the source / drain regions among the plurality of source / drain regions; A buried track passing through the partition insulating layer and the semiconductor layer while being electrically connected to the first conductive plug; A power delivery structure located in the embedded insulating layer and in contact with the buried track to be electrically connected to the buried track; A post-wiring structure located on the lower surface of the embedded insulating layer opposite to the semiconductor layer, the post-wiring structure being electrically connected to the power delivery structure; And A post-wiring interlayer insulating layer that partially surrounds the post-wiring structure.

14. The integrated circuit device of claim 13, further comprising: An external connection terminal attached to a part of the post-wiring structure, the part being exposed from the lower surface of the post-wiring interlayer insulating layer.

15. The integrated circuit device of claim 13, wherein, The width of the buried track in the first horizontal direction is smaller than the width of the partition insulating layer in the first horizontal direction and the width of the power delivery structure in the first horizontal direction.

16. The integrated circuit device of claim 13, further comprising: A second conductive plug electrically connected to the gate line on the gate line, and the height of the upper surface of the second conductive plug is higher than the height of the upper surface of the first conductive plug.

17. A method of manufacturing an integrated circuit device, the method comprising: Preparing a semiconductor-on-insulator substrate including a matrix substrate layer, an embedded insulating layer, and a semiconductor layer stacked in sequence; Forming a deep trench defining at least two element regions by partially removing the semiconductor layer; Forming a preliminary partition insulating layer to fill the deep trench; Forming a buried track hole passing through the preliminary partition insulating layer and the semiconductor layer, a buried track partially filled in the lower part of the buried track hole, and a preliminary covering insulating layer filled in the upper part of the buried track hole; Exposing the embedded insulating layer by removing the matrix substrate layer; And A power transmission structure is formed in the embedded insulating layer, and the power transmission structure is in contact with the buried track.

18. The method of claim 17, wherein, The width of the buried track in the direction between the at least two element regions is less than the width of the deep trench in that direction.

19. The method of claim 17, wherein, The power transmission structure includes: Power transmission holes are formed to expose the buried track by partially removing the embedded insulation layer; and The power transmission structure is formed by filling the power transmission hole. The power transmission aperture is formed by performing an etching process in which the embedded insulating layer is partially removed using a mask pattern as an etching mask. The mask pattern is obtained through a photolithography process, in which the buried track is an alignment mark.

20. The method of claim 19, wherein, The power transmission structure has a width in the direction between the at least two element regions, and the width of the power transmission structure is greater than the width of the buried track in that direction.

Images