Display device and electronic device

Abstract

The present disclosure relates to a display device and an electronic device, wherein the display device includes: a display panel including a plurality of pixels, a first panel pad and a second panel pad; and a circuit board including a first substrate pad and a second substrate pad, the first substrate pad and the second substrate pad applying a first power supply voltage to the first panel pad and the second panel pad. The display panel also includes a first power line pattern and a second power line pattern, the first power line pattern being connected to the second substrate pad to apply the first power supply voltage to the plurality of pixels, and the second power line pattern being connected to the first substrate pad. The circuit board also includes: a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad; a substrate power pattern electrically connected to the first substrate pad; a ground pattern receiving a ground voltage; and a second electrostatic discharge protection circuit connected between the substrate power pattern and the ground pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0059021, filed on May 20, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device having an electrostatic discharge protection function and an electronic device having the display device. Background Art

[0004] In recent years, various electronic devices such as smartphones, tablet computers, notebook computers, and smart TVs have been developed. The electronic devices include display devices to provide information. In addition to the display devices, the electronic devices also include various electronic modules.

[0005] The electronic device is manufactured by assembling the display device and the electronic module. In some cases, the electronic module is arranged using a housing and a bracket of the electronic device.

[0006] Organic light emitting display devices display images using organic light emitting diodes that generate light through electron-hole recombination. Compared to related art display devices, organic light emitting display devices can have a fast response speed and low power consumption.

[0007] Typically, an organic light emitting display device includes a plurality of pixels, each pixel including a driving transistor and an organic light emitting diode, and each pixel controls the amount of current flowing to a corresponding organic light emitting diode, thereby displaying a grayscale (eg, grayscale value) corresponding to each pixel.

[0008] The display panel of the organic light emitting display device is operated by receiving a power supply voltage and a driving signal from an external source such as a printed circuit board.

[0009] When static electricity is introduced into signal lines or pads through which power supply voltage and driving signals are transmitted, circuit elements in the organic light emitting display device may face the risk of being damaged. Summary of the Invention

[0010] The present disclosure provides a display device with an electrostatic discharge protection function.

[0011] The present disclosure provides an electronic device including a display device.

[0012] Some embodiments of the present disclosure provide a display device, comprising: a display panel including a plurality of pixels, a first panel pad, and a second panel pad; and a circuit board including a first substrate pad and a second substrate pad, the first substrate pad and the second substrate pad being connected to the first panel pad and the second panel pad, respectively, to apply a first power supply voltage to the first panel pad and the second panel pad. The display panel further comprises a first power supply line pattern and a second power supply line pattern, the first power supply line pattern being connected to the second substrate pad to apply the first power supply voltage to the plurality of pixels, and the second power supply line pattern being connected to the first substrate pad. The circuit board further comprises: a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad; a substrate power supply pattern electrically connected to the first substrate pad; a ground pattern receiving a ground voltage; and a second electrostatic discharge protection circuit connected between the substrate power supply pattern and the ground pattern.

[0013] In some embodiments, the first power supply voltage has a less negative voltage level than the ground voltage.

[0014] In some embodiments, the display panel includes a display area in which the multiple pixels are arranged and a non-display area in which the first power line pattern, the second power line pattern, the first panel pad and the second panel pad are arranged, and the non-display area is adjacent to the display area.

[0015] In some embodiments, the non-display area of the display panel further includes: an edge area, wherein the first power line pattern is located in the edge area, and the edge area is adjacent to the display area; a sealing area, wherein a sealing member is located in the sealing area, and the sealing area is adjacent to the edge area; and a power line area, wherein the second power line pattern is located in the power line area, and the power line area is adjacent to the sealing area. The sealing area surrounds the edge area and the display area, and the edge area and the power line area are spaced apart from each other, with the sealing area interposed between the edge area and the power line area.

[0016] In some embodiments, the first electrostatic discharge protection circuit includes a transient voltage suppressor diode including a first terminal connected to the first substrate pad and a second terminal connected to the second substrate pad.

[0017] In some embodiments, the second electrostatic discharge protection circuit includes a transient voltage suppressor diode including a first terminal connected to the substrate power pattern and a second terminal connected to the ground pattern.

[0018] In some embodiments, the circuit board comprises a flexible circuit board.

[0019] Some embodiments of the present disclosure provide an electronic device, the electronic device comprising: a display panel comprising a plurality of pixels, a first panel pad, and a second panel pad; a circuit board comprising a first substrate pad and a second substrate pad, the first substrate pad and the second substrate pad being connected to the first panel pad and the second panel pad, respectively, to apply a first power supply voltage to the first panel pad and the second panel pad; and a bracket coupled to the display panel. The display panel further comprises a first power supply line pattern and a second power supply line pattern, the first power supply line pattern being connected to the second substrate pad to apply the first power supply voltage to the plurality of pixels, and the second power supply line pattern being connected to the first substrate pad. The circuit board further comprises: a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad; a first substrate power supply pattern being electrically connected to the first substrate pad; a first substrate ground pattern receiving a ground voltage; and a second electrostatic discharge protection circuit connected between the first substrate power supply pattern and the first substrate ground pattern.

[0020] In some embodiments, the electronic device further comprises: a first conductive pattern facing the first base power pattern; and a first conductive adhesive member connecting the first conductive pattern and the first base power pattern. One end of the circuit board is placed on the upper surface of the display panel, and the other end of the circuit board is placed on the rear surface of the display panel.

[0021] In some embodiments, the electronic device further includes: a second conductive pattern facing the first base ground pattern; and a second conductive adhesive member connecting the second conductive pattern and the first base ground pattern.

[0022] In some embodiments, the electronic device further includes a buffer member on the rear surface of the display panel, and the first conductive pattern and the second conductive pattern are placed on the rear surface of the buffer member.

[0023] In some embodiments, the bracket includes a bottom portion and a first sidewall bent from the bottom portion toward the display panel, the bottom portion including a bracket power pattern facing the first substrate power pattern, a bracket ground pattern facing the first substrate ground pattern, and an insulating pattern between the bracket power pattern and the bracket ground pattern.

[0024] In some embodiments, the circuit board further includes: a second substrate power pattern connected to the first substrate power pattern via a through electrode in a first contact hole passing through the circuit board; and a second substrate ground pattern connected to the first substrate ground pattern via a through electrode in a second contact hole passing through the circuit board.

[0025] In some embodiments, the electronic device further includes: a third conductive adhesive member connecting the second base power pattern and the bracket power pattern; and a fourth conductive adhesive member connecting the second base ground pattern and the bracket ground pattern.

[0026] In some embodiments, the bracket includes a second sidewall, a bracket power supply sidewall bent from the bracket power supply pattern to the display panel, and a bracket insulating sidewall between the second sidewall and the bracket power supply sidewall.

[0027] In some embodiments, the first power supply voltage has a negative voltage level lower than a ground voltage.

[0028] In some embodiments, the display panel includes: a display area in which the multiple pixels are arranged and a non-display area in which the first power line pattern, the second power line pattern, the first panel pad and the second panel pad are arranged, and the non-display area is adjacent to the display area.

[0029] In some embodiments, the non-display area of the display panel further includes: an edge area in which the first power line pattern is positioned, the edge area being adjacent to the display area; a sealing area in which a sealing member is positioned, the sealing area being adjacent to the edge area; and a power line area, the second power line pattern being positioned in the power line area, the power line area being adjacent to the sealing area. The sealing area surrounds the edge area and the display area, and the edge area and the power line area are spaced apart from each other, with the sealing area being interposed between the edge area and the power line area.

[0030] In some embodiments, the first electrostatic discharge protection circuit includes a transient voltage suppressor diode including a first terminal connected to the first substrate pad and a second terminal connected to the second substrate pad.

[0031] In some embodiments, the second electrostatic discharge protection circuit includes a transient voltage suppressor diode including a first terminal connected to the first substrate power pattern and a second terminal connected to the first substrate ground pattern.

[0032] According to the above, the display device includes a path through which the static electricity is discharged to a power supply voltage having a voltage level lower than the ground voltage. Therefore, although static electricity is introduced through the signal line or the pad to which the ground voltage is transmitted, the static electricity can be discharged. In addition, the power supply pattern of the power supply voltage is expanded, and the dispersion effect of the static electricity energy passing through the power supply pattern can be improved. Therefore, compared with the devices of the prior art, the electrostatic discharge protection function of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0034] Figure 1A is a perspective view illustrating an electronic device according to an exemplary embodiment of the present disclosure;

[0035] Figure 1B is a diagram showing an exemplary embodiment according to the present disclosure Figure 1A An exploded perspective view of an electronic device;

[0036] Figure 2 is an exploded perspective view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0037] Figure 3 It shows Figure 2 A perspective view of the display panel shown in ;

[0038] Figure 4 is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0039] Figure 5 It shows Figure 4 A cross-sectional view of the region XX shown in FIG.

[0040] Figure 6 is a circuit diagram showing an electrostatic protection element of a circuit board;

[0041] Figure 7 is a first side view illustrating an electronic device according to an exemplary embodiment of the present disclosure; and

[0042] Figure 8 is a second side view illustrating the electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In the present disclosure, it will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0044] Throughout this disclosure, like reference numerals refer to like elements.In the drawings, the thicknesses of layers, films, and regions may be exaggerated for clarity.

[0045] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It will be understood that, although the terms first, second etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts may not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present disclosure, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part. As used herein, unless the context clearly indicates otherwise, the singular "one", "a kind of" and "described (the)" are also intended to include plural forms.

[0047] For ease of description, spatially relative terms such as "below," "beneath," "down," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the accompanying drawings.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms such as those defined in general dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant art and not as an idealized or overly formalized meaning.

[0049] It will also be understood that when used in this specification, the terms “comprises” and / or “comprising” specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0050] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0051] Figure 1A is a perspective view illustrating an electronic device ED according to an exemplary embodiment of the present disclosure. Figure 1B is an exploded perspective view illustrating an electronic device ED according to an exemplary embodiment of the present disclosure. Figure 2 is an exploded perspective view illustrating a display device DD according to an exemplary embodiment of the present disclosure. Figure 3 It shows Figure 2 2 is a perspective view of the display panel 210 shown in FIG.

[0052] Figure 1A to Figure 1B Typical examples of portable terminals for which the display device is used are shown. Portable terminals may include tablet computers, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), game units, and wristwatch-type electronic devices, but the portable terminals may not be limited thereto or may not be limited thereto.

[0053] The display device DD according to the present disclosure can be applied to large electronic items such as televisions or outdoor billboards, as well as small and medium-sized electronic items such as personal computers, notebook computers, car navigation units, and cameras. These are merely examples and are not limiting. The display device DD according to the present disclosure can be applied to other electronic devices as long as the other electronic devices do not deviate from the concepts of the present disclosure.

[0054] Reference Figure 1A , the display surface through which the image IM is displayed is substantially parallel to the surface defined by the first direction DR1 and the second direction DR2. For example, the image IM displayed in the display surface of the display area DA is substantially parallel to the surface extending in the first direction DR1 and the second direction DR2. The electronic device ED includes a plurality of areas distinguished from each other on the display surface. The display surface includes a display area DA through which the image IM is displayed and a non-display area NDA adjacent to the display area DA. For example, the non-display area NDA may not display any image. The non-display area NDA may be referred to as a bezel area. As an example, the display area DA may have a quadrilateral shape. The non-display area NDA surrounds the display area DA. In addition, although not shown in the drawings, as an example, the electronic device ED may have a partially curved shape. Therefore, a portion of the display area DA may have a curved shape.

[0055] The third direction DR3 represents the normal direction of the display surface, that is, the thickness direction of the electronic device ED. The front (or upper, or first) surface and the rear (or lower, or second) surface of each component of the electronic device ED are defined relative to the direction in which the image IM is displayed. For example, the displayed image IM can serve as a reference point for defining the front (or upper, or first) surface and the rear (or lower, or second) surface of each component of the electronic device ED. However, the directions represented by the first direction DR1, the second direction DR2 and the third direction DR3 may be relative to each other and may be changed to other directions. Hereinafter, the first direction DR1, the second direction DR2 and the third direction DR3 correspond to the directions represented by the first direction axis DR1, the second direction axis DR2 and the third direction axis DR3, respectively, and are assigned the same figure marks as the first direction DR1, the second direction DR2 and the third direction DR3.

[0056] Reference Figure 1B The electronic device ED includes a display device DD, an electronic module EM, a power module PM, a bracket BRK and a housing EDC. Figure 1B It is schematically shown in FIG.

[0057] The display device DD includes a window member WM and a display module DM. The window member WM provides the front surface of the electronic device ED. The window member WM may include a glass substrate, a sapphire substrate, or a plastic substrate. In addition, the window member WM may include functional layers such as an anti-fingerprint layer, an anti-reflection layer, and a hard coating layer. In this exemplary embodiment, the window member WM has a flat shape in the display area DA, however, the shape of the window member WM may be appropriately modified. For example, the shape of the window member WM may be defined based on the application of the electronic device ED. The edges of the window member WM facing each other in the first direction DR1 may be curved. In other embodiments, the edges of the window member WM may be customized to have different shapes based on the application of the electronic device ED.

[0058] The display module DM is located on the rear surface of the window member WM to generate an image. Furthermore, the display module DM can sense user input, such as a user's touch and / or a user's pressure. For example, the display module DM can detect external input from the user, such as a touch and / or a pressure. The display module DM can be electrically connected to the electronics module EM via a flexible circuit board or an electronics component connector.

[0059] In this exemplary embodiment, a display module DM providing a flat display surface is shown as a typical example. However, the shape of the display module DM can be modified as appropriate. For example, the display module DM can be customized to have different shapes based on the application of the electronic device ED. The edges of the display module DM that face (or are opposite to) each other in the first direction DR1 can be curved to provide a curved surface. However, in other embodiments, the edges of the display module may not be curved.

[0060] The power module PM supplies power for the overall operation of the electronic device ED. The power module PM may include a conventional battery module.

[0061] The bracket BRK is coupled to the display device DD and / or the housing EDC to divide the internal space of the electronic device ED. The bracket BRK provides a space in which other components are arranged. In addition, the bracket BRK can support the display device DD so that the display device DD is fixed without shaking. For example, the bracket BRK can provide stability to the structure of the display device DD. The bracket BRK can be provided with a coupling groove defined in the bracket BRK and corresponding to the shape of the electronic module EM so that the electronic module EM is fixed to the bracket BRK. The bracket BRK includes a metal component and / or a plastic component. In this exemplary embodiment, one bracket BRK is shown as a typical example, however, the electronic device ED may include a plurality of brackets BRK.

[0062] The housing EDC can be coupled to the bracket BRK and / or the display device DD. The housing EDC serves as the outer surface of the electronic device ED. For example, the housing EDC can protect the electronic device ED from external interference. In this exemplary embodiment, a housing EDC having a single body is shown as a typical example, however, the housing EDC may include a plurality of bodies assembled to each other. For example, the housing EDC may include a plurality of bodies functionally connected to each other. The housing EDC may include a plurality of frames and / or a plurality of plates made of glass, plastic, or metal materials.

[0063] The electronic module EM includes a motherboard and various functional modules mounted on the motherboard to operate the electronic device ED. The motherboard can be electrically connected to the display device DD via a conventional electronic component connector. In this exemplary embodiment, the motherboard may include a rigid circuit board. However, in some embodiments, the motherboard may include a flexible circuit board.

[0064] Reference Figure 2 , the display module DM includes a display panel 210, a packaging member 220 and a driving control module DCM.

[0065] The display panel 210 may include various display elements. For example, the display element may be a liquid crystal capacitor, an organic light-emitting element, an electrophoretic element, or an electrowetting element. In this exemplary embodiment, a plurality of organic light-emitting diodes will be described as display elements. That is, the display panel 210 according to this exemplary embodiment may be a flexible display panel, such as an organic light-emitting display panel. The display device DD will be described as an organic light-emitting display device including an organic light-emitting display panel. For example, the organic light-emitting display panel may include an organic light-emitting diode (OLED).

[0066] The encapsulation member 220 is located on the display panel 210. The encapsulation member 220 encapsulates the display panel 210 to protect the display element from moisture and oxygen. For example, the encapsulation member 220 can completely cover the display panel 210 to protect the display panel 210 from external interference. The encapsulation member 220 may include a transparent insulating material. The encapsulation member 220 may include at least one of an organic material and an inorganic material. The encapsulation member 220 may be provided in various shapes. For example, the shape of the encapsulation member 220 may be appropriately modified based on the application of the electronic device ED.

[0067] In other embodiments, the display module DM may further include an input sensing unit on the packaging member 220, and may obtain coordinate information about an external input (e.g., a user's touch) or an anti-reflection unit (e.g., a color filter). Furthermore, the display module DM may further include a protective film (not shown) on the rear surface of the display panel 210.

[0068] The drive control module DCM may include a first circuit board MCB, a second circuit board FCB, and a driver chip F-IC mounted on the second circuit board FCB. Depending on various embodiments, some components of the drive control module DCM may be omitted. The driver chip F-IC may be mounted on the display panel 210.

[0069] In some embodiments, a plurality of passive components and a plurality of active components may be mounted on the first circuit board MCB. In other embodiments, the first circuit board MCB may be electrically connected to a motherboard of the electronic module EM via an electronic component connector (see Figure 1B ).

[0070] The second circuit board FCB is electrically connected to the display panel 210. One end of the second circuit board FCB is bonded to a pad arranged in a region of the display panel 210 and is electrically connected to the display panel 210.

[0071] According to an embodiment, the driver chip F-IC may be mounted on the second circuit board FCB in a chip-on-film (COF) manner. The driver chip F-IC may apply electrical signals to the pixels via signal lines. The second circuit board FCB may be implemented as a flexible printed circuit board.

[0072] Reference Figure 3 Because the second circuit board FCB is flexible, it can have a shape that is bent along the side surface of the display panel 210. That is, one end of the second circuit board FCB can be located on the upper surface of the display panel 210, and the other end of the second circuit board FCB can be located on the rear surface of the display panel 210. As described above, because the second circuit board FCB is bent along the side surface of the display panel 210, the first circuit board MCB connected to the other end of the second circuit board FCB can be located on the rear surface of the display panel 210. That is, based on the structure in which the first circuit board MCB is placed on the rear surface of the display panel 210, the display module DM can be located inside the housing EDC. For example, the position of the display module DM inside the housing EDC can vary depending on the position of the first circuit board MCB on the rear surface of the display panel 210.

[0073] Figure 4 is a plan view illustrating a display panel 210 according to an exemplary embodiment of the present disclosure. Figure 5 It shows Figure 4 A cross-sectional view of the region XX shown in FIG.

[0074] Reference Figure 4 and Figure 5 The display panel 210 may include a display area DA and a non-display area NDA. An image is displayed by the display panel 210. For example, an image may be displayed in the display area DA of the display panel 210. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround an edge of the display area DA. However, this is merely an example, and according to some other embodiments, the non-display area NDA may be adjacent to only a portion of the edge of the display area DA, or may be omitted. That is, the non-display area NDA may not be limited to any specific embodiment.

[0075] The display panel 210 can generate an image and display the image through the display area DA. The display panel 210 may include a base substrate BS and at least one pixel PX. For example, the display panel 210 may include a plurality of pixels PX. The display area DA and the non-display area NDA may be areas provided by the base substrate BS. The base substrate BS may include an insulating substrate. For example, the base substrate BS may include a glass substrate, a plastic substrate, or a combination thereof.

[0076] Pixels PX are arranged in the display area DA. For example, the pixels PX are arranged in a matrix in the display area DA. The pixels PX are arranged along a first direction DR1 and a second direction DR2 and are spaced apart from each other in a matrix. Each pixel PX receives an electrical signal and emits light to display an image.

[0077] Each pixel PX is connected to a plurality of signal lines, including a scan line SL, a data line DL, a power line PL, and a sub-power line SPL.

[0078] The scan lines SL extend in the first direction DR1 and are arranged along the second direction DR2 to be spaced apart from each other. The scan lines SL transmit scan signals to the pixels PX.

[0079] The data lines DL are electrically insulated from the scan lines SL while crossing them. For example, the data lines DL are electrically insulated from the scan lines SL at their intersections. In this exemplary embodiment, the data lines DL extend in the second direction DR2 and are spaced apart from each other along the first direction DR1. The data lines DL transmit data signals to the pixels PX.

[0080] The power lines PL may be insulated from the scan lines SL and the data lines DL. In this exemplary embodiment, the power lines PL extend in the first direction DR1 and are arranged to be spaced apart from each other along the second direction DR2. The power lines PL transmit the second power signal to the pixels PX.

[0081] The sub power lines SPL may be insulated from the scan lines SL and the data lines DL. In this exemplary embodiment, the sub power lines SPL extend in the first direction DR1 and are arranged to be spaced apart from each other along the second direction DR2. The sub power lines SPL transmit the first power signal to the pixels PX.

[0082] Each pixel PX may include a first transistor TR1, a second transistor TR2, a capacitor CP, and a light-emitting element OLD. For example, the light-emitting element OLD may be an organic light-emitting diode (OLED). The first transistor TR1 is turned on in response to a scan signal applied thereto via a corresponding scan line SL among the scan lines SL, and applies a data signal applied thereto via a corresponding data line DL among the data lines DL to the capacitor CP.

[0083] The capacitor CP is charged with a voltage corresponding to the potential difference between the second power voltage ELVDD supplied from the third power line pattern PL3 and the data signal. The second transistor TR2 is turned on by the voltage charged in the capacitor CP to supply the second power voltage ELVDD applied thereto to the light emitting element OLD through the power line PL.

[0084] The light emitting element OLD may generate light and control the amount of light in response to an electrical signal. For example, the light emitting element OLD may include an organic light emitting element, a quantum dot light emitting element, an electrophoretic element, or an electrowetting element.

[0085] The light emitting element OLD is connected to the sub power line SPL to receive a first power voltage ELVSS different from the second power voltage ELVDD. A driving current corresponding to the difference between the electrical signal provided by the second transistor TR2 and the first power voltage ELVSS flows through the light emitting element OLD, and the light emitting element OLD can generate light corresponding to the driving current.

[0086] However, this is merely an example. The pixel PX according to an embodiment of the present disclosure may include electronic components having various configurations and arrangements, and the pixel PX may not be particularly limited.

[0087] The signal lines SL, DL, PL, and SPL are positioned on the base substrate BS. The scan lines SL, the data lines DL, the power lines PL, and the sub-power lines SPL may transmit different electrical signals from one another.

[0088] The scan line SL extends in the first direction DR1. A plurality of scan lines SL are provided, and the scan lines SL are arranged along the second direction DR2 to be spaced apart from each other. For convenience of description, the scan line SL is shown as a typical example.

[0089] According to some embodiments, the display panel 210 includes a scan driving circuit SD on a base substrate BS to apply electrical signals to the scan lines SL.

[0090] The scan drive circuit SD may include at least one drive transistor TR-D and a plurality of conductive lines CL and VIN. The drive transistor TR-D has a structure substantially the same as the second transistor TR2. However, the drive transistor TR-D may or may not be limited to this structure. In other words, the drive transistor TR-D may have a different structure than the second transistor TR2. The conductive lines CL and VIN are connected to the drive transistor TR-D to form an electronic circuit. The scan drive circuit SD may be connected to the scan lines SL.

[0091] The first power line pattern PL1, the second power line pattern PL2 and the third power line pattern PL3 are located in the non-display area NDA. The first power line pattern PL1 may include a first long side and a second long side extending in the second direction DR2 and a short side extending in the first direction DR1. The second power line pattern PL2 may include a first long side and a second long side extending in the second direction DR2 and a short side extending in the first direction DR1. When viewed in a plan view, the first power line pattern PL1 and the second power line pattern PL2 may be spaced apart from each other, wherein the plan view is a view viewed from a direction orthogonal to a plane defined by the first direction DR1 and the second direction DR2. The third power line pattern PL3 may be spaced apart from the first power line pattern PL1 and the second power line pattern PL2. The shapes and arrangements of the first power line pattern PL1, the second power line pattern PL2 and the third power line pattern PL3 may be changed in various appropriate ways, without limitation. Figure 4 For example, the shapes and positions of the first power line pattern PL1, the second power line pattern PL2, and the third power line pattern PL3 may be different based on design choice.

[0092] The sealing member SM is positioned in the non-display area NDA to surround the first and third power line patterns PL1 and PL3. In an exemplary embodiment, the sealing member SM is positioned between the first and second power line patterns PL1 and PL2.

[0093] The sealing member SM is positioned between the base substrate BS and the cover substrate 223 to support a cell gap between the base substrate BS and the cover substrate 223 and to couple the base substrate BS and the cover substrate 223 .

[0094] A plurality of panel pads PP1 to PP6 are located in the non-display area NDA. The area in the non-display area NDA where the panel pads PP1 to PP6 are located may be referred to as a "panel pad area PA1." The panel pads PP1 to PP6 may include power pads PP1 to PP4 and a power pad PP6, as well as a data pad PP5. In some embodiments, there may be different numbers of power pads or data pads.

[0095] The second circuit board FCB may be coupled to the panel pad area PA1 to drive the pixels PX. The second circuit board FCB is electrically connected to the display panel 210 via first to fourth substrate pads FP1 to FP4 located in the substrate pad area PA2.

[0096] Of the power supply pads PP1 to PP4 and the power supply pad PP6, the power supply pads PP2 and PP4 are connected to the first power supply line pattern PL1. The first power supply line pattern PL1 can receive a first power supply voltage ELVSS supplied externally through the power supply pads PP2 and PP4. The power supply pads PP1 and PP3 are connected to the second power supply line pattern PL2. The second power supply line pattern PL2 can receive a first power supply voltage ELVSS supplied externally through the power supply pads PP1 and PP3.

[0097] The power pad PP6 is connected to the third power line pattern PL3. The third power line pattern PL3 may receive a second power voltage ELVDD from the outside through the power pad PP6.

[0098] The data pad PP5 is connected to the conductive pattern CP1. The conductive pattern CP1 connects the data line DL and the data pad PP5. The conductive pattern CP1 includes a plurality of line patterns extending in the second direction DR2 and arranged in the first direction DR1 to be spaced apart from each other.

[0099] In this exemplary embodiment, the conductive pattern CP1 can be placed on a different layer from the data line DL. For example, the conductive pattern CP1 can be located on the same layer as the scan line SL. That is, the conductive pattern CP1 can be formed (or placed) integrally with the data line DL and serve as a part of the data line DL, or can be connected to each data line DL via a separate bridge pattern. The conductive pattern CP1 according to the exemplary embodiment of the present disclosure can have various suitable shapes, as long as the conductive pattern CP1 is connected to the data line DL, and there is no specific limitation.

[0100] Reference Figure 4 and Figure 5 The base substrate BS may be an insulating substrate. For example, the base substrate BS may include a plastic substrate or a glass substrate. An auxiliary layer BL is placed on the base substrate BS to cover the entire surface of the base substrate BS. The auxiliary layer BL includes an inorganic material. The auxiliary layer BL includes a barrier layer and / or a buffer layer. Therefore, the auxiliary layer BL prevents oxygen or moisture from penetrating into the pixel PX through the base substrate BS and reduces the surface energy of the base substrate BS, allowing the pixel PX to be stably formed on the base substrate BS. For example, the auxiliary layer BL can protect the pixel PX from external interference and also provide structural stability for the pixel PX.

[0101] The pixels PX may be arranged in the display area DA. In this exemplary embodiment, Figure 2The second transistor TR2 and the light emitting element OLD in the components of the equivalent circuit of the pixel PX shown in FIG are shown as typical examples. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may include an organic material and / or an inorganic material and may have a single-layer or multi-layer structure.

[0102] The second transistor TR2 is located on the base substrate BS and includes a control electrode CE, an input electrode IE, an output electrode OE, and a semiconductor pattern SP. The control electrode CE is spaced apart from the semiconductor pattern SP, with the first insulating layer 10 interposed therebetween. The control electrode CE is connected to one electrode of the capacitor CP. Each of the input electrode IE and the output electrode OE is located on the second insulating layer 20 and is connected to the semiconductor pattern SP after penetrating the first and second insulating layers 10 and 20. The input electrode IE is connected to the other electrode of the capacitor CP, and the output electrode OE is connected to the light-emitting element OLD.

[0103] The light-emitting element OLD is connected to the second transistor TR2 and the sub-power line SPL. The light-emitting element OLD includes a first electrode E1, a light-emitting layer EL, and a second electrode E2. The first electrode E1 is disposed on the third insulating layer 30 and is connected to the second transistor TR2 after penetrating the third insulating layer 30. The light-emitting layer EL covers the first electrode E1 exposed by the fourth insulating layer 40. The light-emitting layer EL may include a light-emitting material that generates light in response to a potential difference. For example, the light-emitting layer EL may include an organic light-emitting material or quantum dots.

[0104] The second electrode E2 is located on the light-emitting layer EL. The second electrode E2 is located on the entire surface of the display area DA. For example, the second electrode E2 may cover the entire surface of the display area DA. The second electrode E2 extends from the display area DA to the non-display area NDA and is connected to a connection pattern E-CNT. The connection pattern E-CNT may correspond to the sub-power line SPL.

[0105] The sub-power line SPL applies a first power supply voltage ELVSS to the light-emitting element OLD. The first power supply voltage ELVSS may have a different potential from the second power supply voltage ELVDD. The light-emitting element OLD generates light corresponding to the potential difference between the data signal from the second transistor TR2 and the first power supply voltage ELVSS from the sub-power line SPL, and emits the light. For example, the light-emitting element OLD emits light having a brightness corresponding to the potential difference between the data signal from the second transistor TR2 and the first power supply voltage ELVSS from the sub-power line SPL.

[0106] The scan drive circuit SD may include at least one drive transistor TR-D, as well as conductors CL and VIN. The drive transistor TR-D has a structure substantially the same as the second transistor TR2. However, the drive transistor TR-D may or may not be limited thereto. In other words, the drive transistor TR-D may have a different structure than the second transistor TR2. The conductors CL and VIN are connected to the drive transistor TR-D to form an electronic circuit. The scan drive circuit SD may be connected to the scan line SL.

[0107] The scan lines SL extend from the display area DA and are connected to a scan driving circuit SD located in the non-display area NDA. The scan driving circuit SD applies an electrical signal, such as a scan signal, to the pixels PX via the scan lines SL.

[0108] In this exemplary embodiment, a single scan drive circuit SD is shown; however, a plurality of scan drive circuits SD may be provided. In this case, the scan drive circuits SD may be spaced apart from one another along the first direction DR1, with the display area DA interposed between the scan drive circuits SD. Furthermore, in this exemplary embodiment, the scan drive circuit SD may be directly on the base substrate BS; however, the scan drive circuit SD may not be limited to this. That is, the scan drive circuit SD may be provided after being mounted on a separate circuit board. In this case, the scan drive circuit SD may be connected to the display panel 210 via a conductive adhesive member. The scan drive circuit SD according to the exemplary embodiment of the present disclosure may be provided in various suitable manners; however, the scan drive circuit SD may not be particularly limited.

[0109] The first power line pattern PL1 is placed in the non-display area NDA to apply the first power voltage ELVSS of the same potential to each pixel PX.

[0110] The first and second power line patterns PL1 and PL2 are placed in the non-display area NDA to be spaced apart from each other along the first direction DR1.

[0111] The encapsulation member 220 is positioned on the fourth insulating layer 40 to encapsulate the light emitting element OLD. The encapsulation member 220 may include an organic layer 221, an encapsulation layer 222, a cover substrate 223, and a sealing member SM.

[0112] The non-display area NDA includes an edge area EA, a seal area SA, and a power line area PLA. The edge area EA is located adjacent to the display area DA, and the scan drive circuit SD and the first power line pattern PL1 are located in the edge area EA. The seal area SA is located adjacent to the edge area EA, and the seal member SM is located in the seal area SA. The power line area PLA is located adjacent to the seal area SA, and the second power line pattern PL2 is located in the power line area PLA. The seal area SA may have a shape surrounding the edge area EA and the display area DA. The edge area EA and the power line area PLA may be spaced apart from each other, with the seal area SA interposed between the edge area EA and the power line area PLA.

[0113] The encapsulation layer 222 may include an inactive material. The cover substrate 223 is placed on the base substrate BS. The cover substrate 223 covers the display area DA and the non-display area NDA. The cover substrate 223 may be spaced apart from the pixel PX, with the encapsulation layer 222 interposed between the cover substrate 223 and the pixel PX.

[0114] The sealing member SM is located between the base substrate BS and the cover substrate 223 to support a cell gap therebetween and to bond the base substrate BS and the cover substrate 223. The sealing member SM prevents the external environment from affecting the edge area EA and the display area DA, thereby protecting the pixels PX. For example, the sealing member SM can protect the edge area EA and the display area DA from external interference, thereby providing protection for the pixels PX.

[0115] Furthermore, the sealing member SM reduces or minimizes the exposure of the first power line pattern PL1 to the outside to prevent external environments such as static electricity from affecting the first power line pattern PL1. For example, the sealing member SM protects the first power line pattern PL1 from being damaged by external interference such as static electricity.

[0116] Refer again Figure 4 , the second circuit board FCB is electrically connected to the display panel 210 through the first to fourth substrate pads FP1 to FP4 located in the substrate pad area PA2. The first to fourth substrate pads FP1 to FP4 can be connected to the panel pads PP1 to PP4, respectively. Although not shown in the drawings, the substrate pad area PA2 may further include substrate pads connected to the panel pads PP5 and PP6.

[0117] The second circuit board FCB receives the first power voltage ELVSS, the second power voltage ELVDD, and the ground voltage GND from the voltage generator 300. In an exemplary embodiment, the voltage generator 300 may be included in Figure 1B According to another embodiment, the voltage generator 300 may be included in the second circuit board FCB.

[0118] The second circuit board FCB transmits the first power voltage ELVSS and the second power voltage ELVDD from the voltage generator 300 to the display panel 210. In an exemplary embodiment, the second circuit board FCB may transmit the first power voltage ELVSS to the panel pads PP1 to PP4 of the display panel 210 through the first to fourth substrate pads FP1 to FP4. In addition, the second circuit board FCB may transmit the second power voltage ELVDD to the panel pad PP6 of the display panel 210 through a substrate pad (not shown).

[0119] The second circuit board FCB further includes a first base power pattern FPL1 , a first base ground pattern FGL1 , and first, second, and third electrostatic discharge protection circuits (ESD) 251 , 252 , and 253 .

[0120] The first substrate power pattern FPL1 electrically connects the first substrate pad FP1 and the third substrate pad FP3. The first substrate ground pattern FGL1 receives a ground voltage GND.

[0121] The first electrostatic discharge protection circuit 251 is connected to the first and second substrate pads FP1 and FP2. The second electrostatic discharge protection circuit 252 is connected to the first substrate power pattern FPL1 and the first substrate ground pattern FGL1. The third electrostatic discharge protection circuit 253 is connected to the third and fourth substrate pads FP3 and FP4.

[0122] Figure 6 is a circuit diagram showing an electrostatic protection element of the second circuit board FCB.

[0123] Reference Figure 6 , the first electrostatic discharge protection circuit 251 may include a transient voltage suppressor (TVS) diode TVS1. Figure 6 In the embodiment shown in FIG, the TVS diode TVS1 is connected between the first substrate pad FP1 and the second substrate pad FP2.

[0124] The second electrostatic discharge protection circuit 252 may include a TVS diode TVS3 connected between the first substrate power pattern FPL1 and the first substrate ground pattern FGL1.

[0125] The third electrostatic discharge protection circuit 253 may include a TVS diode TVS2 connected between the third substrate pad FP3 and the fourth substrate pad FP4.

[0126] Reference Figure 4 and Figure 6, when static electricity is introduced through the first substrate ground pattern FGL1 to which the ground voltage GND is transmitted, the second electrostatic discharge protection circuit 252 may sense the static electricity to be discharged to the first power voltage ELVSS having a voltage level lower than the ground voltage GND.

[0127] When the first to fourth substrate pads FP1 to FP4 of the second circuit board FCB are connected to the panel pads PP2 and PP4 of the display panel 210, static electricity can be introduced through the second power line pattern PL2 and / or the first substrate power pattern FPL1. In this case, the first and third electrostatic discharge protection circuits 251 and 253 suppress (clip) any transient overvoltage, thereby preventing static electricity from being introduced into the first substrate power pattern FPL1 through the second and fourth substrate pads FP2 and FP4. Therefore, the first substrate power pattern FPL1, which is directly connected to the pixel PX, can be protected from static electricity.

[0128] In an exemplary embodiment, the first electrostatic discharge protection circuit 251, the second electrostatic discharge protection circuit 252 and the third electrostatic discharge protection circuit 253 include TVS diodes TVS1, TVS3 and TVS2, respectively; however, the first electrostatic discharge protection circuit 251, the second electrostatic discharge protection circuit 252 and the third electrostatic discharge protection circuit 253 may include high-frequency cutoff elements such as ferrite beads instead of TVS diodes.

[0129] Bracket BRK for electronic device ED (refer to Figure 1A and Figure 1B ) can be implemented by a conductive metal material. For example, the bracket BRK of the electronic device ED can be made of a highly conductive metal such as silver, gold, or copper. Since the bracket BRK is connected to the ground voltage GND, when static electricity is introduced, the static electricity can be dispersed through the bracket BRK.

[0130] According to an exemplary embodiment, although static electricity is introduced through the first substrate ground pattern FGL1, the static electricity can be discharged to the first power voltage ELVSS having a voltage level lower than the ground voltage GND. In addition, a method of extending the power pattern of the first power voltage ELVSS to disperse the electrostatic energy through the first power voltage ELVSS is also desired.

[0131] Figure 7 is a first side view illustrating an electronic device according to an exemplary embodiment of the present disclosure. Figure 8 is a second side view illustrating the electronic device according to an exemplary embodiment of the present disclosure.

[0132] Figure 7 shows a first side in which the second circuit board FCB is bent along a side surface of the display panel 210, and Figure 8 The second side is shown facing the first side in the second direction DR2.

[0133] Reference Figure 7 , the display device DD includes a window member WM and a display module DM. The display device DD and the bracket BRK may be coupled to each other through a window adhesive member WAM.

[0134] The display module DM may further include a buffer tape 205 positioned between the display panel 210 and the second circuit board FCB. The buffer tape 205 prevents the second circuit board FCB from direct contact with the display panel 210, thereby reducing the chance of damage to the second circuit board FCB. For example, the buffer tape 205 provides isolation between the second circuit board FCB and the display panel 210, thereby providing protection for the second circuit board FCB.

[0135] The second circuit board FCB may further include a second base power pattern FPL2, a second base ground pattern FGL2, a first contact hole CH1, and a second contact hole CH2. The second base power pattern FPL2 may be electrically connected to the first base power pattern FPL1 via a through electrode located in the first contact hole CH1. Furthermore, the second base ground pattern FGL2 may be electrically connected to the first base ground pattern FGL1 via a through electrode located in the second contact hole CH2.

[0136] In this exemplary embodiment, the first substrate power pattern FPL1 and the first substrate ground pattern FGL1 are located on the upper surface of the second circuit board FCB, and the second substrate power pattern FPL2 and the second substrate ground pattern FGL2 are located on the lower surface of the second circuit board FCB. However, the present disclosure may or may not be limited to this. For example, the second circuit board FCB may include multiple insulating layers, and the first substrate power pattern FPL1, the second substrate power pattern FPL2, the first substrate ground pattern FGL1, and the second substrate ground pattern FGL2 may be located between the insulating layers. In this case, it is desirable that contact holes expose the first substrate power pattern FPL1, the second substrate power pattern FPL2, the first substrate ground pattern FGL1, and the second substrate ground pattern FGL2 to the outside. For example, the contact holes CH1 and CH2 expose the first substrate power pattern FPL1, the second substrate power pattern FPL2, the first substrate ground pattern FGL1, and the second substrate ground pattern FGL2 to the outside.

[0137] The first conductive pattern MP1 is placed on the lower surface of the buffer tape 205 to face the first base power pattern FPL1. The second conductive pattern MP2 is located on the lower surface of the buffer tape 205 to face the first base ground pattern FGL1. The first conductive pattern MP1 and the second conductive pattern MP2 may be spaced apart from each other in the second direction DR2.

[0138] The first conductive pattern MP1 and the first substrate power pattern FPL1 can be connected to each other via a first conductive adhesive member AM1. Thus, a first power supply voltage ELVSS can be applied to the first conductive pattern MP1. The second conductive pattern MP2 and the first substrate ground pattern FGL1 can be connected to each other via a second conductive adhesive member AM2. Thus, a ground voltage GND can be applied to the second conductive pattern MP2. The first and second conductive adhesive members AM1 and AM2 may include an anisotropic conductive film (ACF) having a strong adhesive force. In exemplary embodiments of the present disclosure, the first and second conductive adhesive members AM1 and AM2 may include solder paste, solder beads, or solder bumps.

[0139] The housing EDC may be coupled to the display device DD and / or the bracket BRK.

[0140] The bracket BRK includes a bottom portion 410 and a first sidewall 420 bent from the bottom portion 410 to the display panel 210 .

[0141] The bottom portion 410 includes a support insulating pattern 411, a support power pattern 412, and a support ground pattern 413. The bottom portion 410 adjacent to the first sidewall 420 may be the support ground pattern 413.

[0142] The bracket insulating pattern 411 is placed between the bracket power pattern 412 and the bracket ground pattern 413 to insulate the bracket power pattern 412 from the bracket ground pattern 413 .

[0143] The bracket power pattern 412 may face the second base power pattern FPL2. The bracket power pattern 412 and the second base power pattern FPL2 may be connected to each other via a third conductive adhesive member AM3. The bracket ground pattern 413 may face the second base ground pattern FGL2. The bracket ground pattern 413 and the second base ground pattern FGL2 may be connected to each other via a fourth conductive adhesive member AM4. The third and fourth conductive adhesive members AM3 and AM4 may include an anisotropic conductive film (ACF) having strong adhesive force. In exemplary embodiments of the present disclosure, the third and fourth conductive adhesive members AM3 and AM4 may include solder paste, solder beads, or solder bumps.

[0144] As described above, even if static electricity is introduced through the first substrate ground pattern FGL1, the second substrate ground pattern FGL2, the second conductive pattern MP2, and / or the first sidewall 420, which receive the ground voltage GND, the static electricity can be discharged to the first power voltage ELVSS, which has a voltage level lower than the ground voltage GND. Furthermore, the power pattern of the first power voltage ELVSS extends to the first substrate power pattern FPL1, the second substrate power pattern FPL2, and the first conductive pattern MP1, thereby improving the dispersion effect of static electricity energy passing through the power pattern. For example, to improve the dispersion of static electricity energy passing through the power pattern, the power pattern of the first power voltage ELVSS can extend to the first substrate power pattern FPL1, the second substrate power pattern FPL2, and the first conductive pattern MP1.

[0145] Reference Figure 8 Other components may be arranged in the space 330 between the housing EDC and the bracket BRK. For example, a power module PM (see Figure 1B ) and the electronic module EM can be arranged in the space 330.

[0146] The electronic module EM may be arranged in a space 330 between the bracket BRK and the housing EDC. Although not shown in the drawings, the electronic module EM may include Figure 4 The voltage generator 300 shown in FIG.

[0147] The electronic module EM may have a structure in which a first insulating layer IL1, a conductive layer ML, and a second insulating layer IL2 are sequentially stacked on each other. The conductive layer ML may be a power pattern transmitting a first power voltage ELVSS.

[0148] The electronic module EM and the bracket BRK can be electrically connected to each other in a third direction DR3, which is the thickness direction of the display device DD, via a first conductive member CAM1 and a second conductive member CAM2 located between the electronic module EM and the bracket BRK. The first and second conductive members CAM1 and CAM2 not only electrically connect the electronic module EM and the bracket BRK, but also physically connect the electronic module EM and the bracket BRK. For example, the first and second conductive members CAM1 and CAM2 provide both a physical and an electrical connection between the electronic module EM and the bracket BRK. In an exemplary embodiment, the first and second conductive members CAM1 and CAM2 may include conductive screws.

[0149] The conductive layer ML of the electronic module EM may be electrically connected to the bracket power pattern 412 of the bracket BRK through the first and second conductive members CAM1 and CAM2 .

[0150] The bracket BRK includes a second sidewall 430, a bracket insulating sidewall 440, and a bracket power supply sidewall 450. The second sidewall 430 is adjacent to the outer housing EDC. The bracket power supply sidewall 450 bends from the bracket power supply pattern 412 of the bottom 410 to the display panel 210. The bracket insulating sidewall 440 is located between the second sidewall 430 and the bracket power supply sidewall 450 to insulate the second sidewall 430 from the bracket power supply sidewall 450. For example, the bracket insulating sidewall 440 provides electrical insulation between the second sidewall 430 and the bracket power supply sidewall 450. A ground voltage GND may be applied to the second sidewall 430.

[0151] The third conductive pattern MP3 is located on the lower surface of the buffer tape 205 and faces the bracket power pattern 412. The third conductive pattern MP3 and the bracket power pattern 412 can be connected to each other via a fifth conductive adhesive member AM5. Thus, the first power supply voltage ELVSS can be applied to the third conductive pattern MP3. The fifth conductive adhesive member AM5 may include an anisotropic conductive film (ACF) having a strong adhesive force. In exemplary embodiments of the present disclosure, the fifth conductive adhesive member AM5 may include solder paste, solder beads, or solder bumps.

[0152] Although static electricity is introduced through the second sidewall 430 receiving the ground voltage GND and the bracket ground pattern 413, the static electricity can be discharged to the first power voltage ELVSS having a voltage level lower than the ground voltage GND. In addition, the power pattern of the first power voltage ELVSS is extended to the bracket power sidewall 450, the bracket power pattern 412, and the third conductive pattern MP3, which can improve the dispersion effect of the static electricity energy passing through the first power voltage ELVSS.

[0153] Although exemplary embodiments of the present disclosure have been described, it will be understood that the present disclosure may not be limited to these exemplary embodiments, but rather that various changes and modifications may be made by those skilled in the art within the spirit and scope of the present disclosure as hereinafter claimed. Therefore, the disclosed subject matter may not be limited to any single embodiment described herein, and the scope of the inventive concept will be determined in light of the present disclosure.

Claims

1. A display device, wherein: The display device includes: A display panel comprising a plurality of pixels, a first panel pad and a second panel pad; and a circuit board comprising a first substrate pad and a second substrate pad, the first substrate pad and the second substrate pad being connected to the first panel pad and the second panel pad, respectively, to apply a first power supply voltage to the first panel pad and the second panel pad, The display panel further includes a first power line pattern and a second power line pattern, the first power line pattern being connected to the second substrate pad to apply the first power voltage to the plurality of pixels, the second power line pattern being connected to the first substrate pad, and Wherein, the circuit board further includes: a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad, wherein the first substrate pad and the second substrate pad are electrically connected in parallel to each other, wherein the first substrate pad is connected between the second power line pattern and the first electrostatic discharge protection circuit, and the second substrate pad is connected between the first power line pattern and the first electrostatic discharge protection circuit; a substrate power pattern electrically connected to the first substrate pad; a ground pattern configured to receive a ground voltage; and The second electrostatic discharge protection circuit is connected between the base power pattern and the ground pattern.

2. The display device according to claim 1, wherein The first power supply voltage has a negative voltage level lower than the ground voltage.

3. The display device according to claim 1, wherein: The display panel includes a display area in which the plurality of pixels are arranged and a non-display area in which the first power line pattern, the second power line pattern, the first panel pad, and the second panel pad are arranged, and The non-display area is adjacent to the display area.

4. The display device according to claim 3, wherein The non-display area of the display panel further includes: an edge region, wherein the first power line pattern is located in the edge region, and the edge region is adjacent to the display region; a sealing region in which a sealing member is located, the sealing region being adjacent to the edge region; and A power line area, the second power line pattern is located in the power line area, the power line area is adjacent to the sealing area, the sealing area surrounds the edge area and the display area, and the edge area and the power line area are spaced apart from each other, and the sealing area is between the edge area and the power line area.

5. The display device according to claim 1, wherein The first electrostatic discharge protection circuit includes a transient voltage suppressor diode including a first terminal connected to the first substrate pad and a second terminal connected to the second substrate pad. The display device according to claim 1 , wherein: The second electrostatic discharge protection circuit includes a transient voltage suppressor diode including a first terminal connected to the substrate power pattern and a second terminal connected to the ground pattern.

7. The display device according to claim 1, wherein The circuit board includes a flexible circuit board.

8. An electronic device, wherein: The electronic device comprises: A display panel comprising a plurality of pixels, a first panel pad and a second panel pad; a circuit board comprising a first substrate pad and a second substrate pad, the first substrate pad and the second substrate pad being connected to the first panel pad and the second panel pad, respectively, to apply a first power supply voltage to the first panel pad and the second panel pad; and a bracket coupled to the display panel, The display panel further includes a first power line pattern and a second power line pattern, the first power line pattern being connected to the second substrate pad to apply the first power voltage to the plurality of pixels, the second power line pattern being connected to the first substrate pad, and Wherein, the circuit board further includes: a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad, wherein the first substrate pad and the second substrate pad are electrically connected in parallel to each other, wherein the first substrate pad is connected between the second power line pattern and the first electrostatic discharge protection circuit, and the second substrate pad is connected between the first power line pattern and the first electrostatic discharge protection circuit; a first substrate power pattern electrically connected to the first substrate pad; a first substrate ground pattern configured to receive a ground voltage; and The second electrostatic discharge protection circuit is connected between the first substrate power pattern and the first substrate ground pattern.

9. The electronic device according to claim 8, wherein: The electronic device further comprises: a first conductive pattern facing the first base power pattern; and A first conductive adhesive member connects the first conductive pattern and the first base power pattern, wherein one end of the circuit board is placed on the upper surface of the display panel and the other end of the circuit board is placed on the rear surface of the display panel.

10. The electronic device according to claim 9, wherein: The electronic device further comprises: a second conductive pattern facing the first base ground pattern; and A second conductive adhesive member connects the second conductive pattern and the first base ground pattern.

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