Positive logic switch with optional DC blocking circuit

Abstract

A positive logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch losses, and can withstand high RF voltages. Embodiments include a FET stack that includes series-coupled positive logic FETs (i.e., FETs that do not require a negative voltage supply to turn off) that are connected at least at one end by a positive logic FET at its V GS The "end cap" FETs of the type that are off at zero volts are coupled in series. One or more end cap FETs provide an optional capacitive DC blocking function or a resistive signal path. Embodiments include zero V only GS type of FET stack, or positive logic and zero V GS Type of FET with zero V GS Some embodiments withstand high RF voltages by combining a resistor ladder including a FET gate resistor, a drain-source resistor, a body charge control resistor, coupled in series or in parallel, with one or more AC coupling modules.

Description

[0001] Cross-references and priority claims to related applications

[0002] This application claims the benefit of priority from the following patent applications, all of which are assigned to the assignee of the present invention, and all of which are incorporated by reference in their entirety:

[0003] U.S. Patent Application No. 15 / 939,128, filed on March 28, 2018, entitled “Positive Logic Switch with Selectable DCBlocking Circuit”;

[0004] U.S. Patent Application No. 15 / 939,132, filed on March 28, 2018, entitled “Stacked FET Switch Bias Ladders”; and

[0005] U.S. patent application Ser. No. 15 / 939,144, filed on Mar. 28, 2018, and entitled “AC Coupling Modules for Bias Ladders.”

[0006] This application may be related to the following patents and patent applications, the entire contents of which are incorporated herein by reference in their entirety:

[0007] U.S. Patent No. 8,669,804, issued on March 11, 2014, and entitled “Device and Methods for Improving Voltage Handling and / or Bi-directionality of Stacks of Elements when Connected Between Terminals”;

[0008] U.S. patent application Ser. No. 15 / 256,453, filed Sept. 2, 2016, entitled “Positive Logic Digitally Tunable Capacitor”;

[0009] U.S. Patent Application No. 15 / 289,768, filed on October 10, 2016 (now abandoned), entitled “Reduced Dissipation Switch FET Gate Biasing,” which claims priority to U.S. Provisional Application No. 62 / 241,498, filed on October 14, 2015;

[0010] U.S. Patent Application No. 15 / 939,128, filed on March 28, 2018, entitled “Positive Logic Switch with Selectable DCBlocking Circuit”;

[0011] U.S. patent application Ser. No. 15 / 939,132, filed on Mar. 28, 2018, and entitled “Stacked FET Switch Bias Ladders.” Technical Field

[0012] The present invention relates to electronic circuits and, more particularly, to radio frequency electronic switching circuits and related methods. Background Art

[0013] In radio frequency (RF) systems such as cellular phones and WiFi networks, electronic switching circuits are often used in series with RF signal lines to selectively block or conduct RF signals, such as between an antenna and a transceiver circuit. Electronic switching circuits are also often used in a shunt configuration between an RF signal line and a reference potential (e.g., circuit ground), for example, to selectively isolate a node of the RF signal line from having a significant effect on other circuits. As an example, Figure 1 FIG. 1 is a simplified schematic circuit diagram of a general prior art series-shunt switch circuit configuration 100. In the configuration shown, the series switch circuit 102 is connected to the RF IN Ports and RF OUT The ports are coupled in series with the RF signal line 104, and the shunt switch circuit 106 is connected to the RF OUT The ports are coupled to the RF signal line 104 between the ports and the circuit ground. As shown, the series switch circuit 102 and the shunt switch circuit 104 are modeled as single-pole single-throw (SPST) switches. In use, the series switch circuit 102 and the shunt switch circuit 106 generally operate in a complementary manner: if the series switch circuit 102 is open, the shunt switch circuit 106 is closed, and if the series switch circuit 102 is closed, the shunt switch circuit 106 is open.

[0014] Ideally, such as Figure 1 The switching circuit shown should not significantly modify or affect the RF signal. However, in integrated circuits, RF switching circuits are often implemented with transistors, especially field effect transistors (FETs), and more especially MOSFETs. A FET in the ON state presents a certain resistance R to the signal being conducted. ON , and in the blocking (OFF) state, it presents a certain capacitance C OFF, which can be connected in series, in shunt, or in parallel with the RF signal line. Therefore, FET-based switching circuits usually do not perform well in RF circuits.

[0015] Another problem with FETs is that the voltage between the drain and source that a single FET can withstand without breaking down is usually limited to a few volts. In electronic systems, some parts of the system may have to withstand voltages far exceeding the voltage handling capabilities of a single FET. A common solution is to stack FETs in series so that the drain-source voltage across any one FET is less than its drain-source breakdown voltage.

[0016] For example, Figure 2 FIG. 2 is a schematic circuit diagram of a prior art series-shunt RF switch circuit 200 using a FET stack. In this example, the RF signal from the antenna ANT is transmitted from the RF IN Coupled to RF via series stack 202 OUT The shunt stack 204 is coupled to the RF OUT and circuit ground. Each of the stacks 202, 204 includes a plurality of FETs M1 to Mn coupled in series (although "n" may be different for the two stacks 202, 204). In this example, each FET includes a dedicated gate resistor Rg.

[0017] A standard biasing scheme is typically used in this type of circuit 200 when configured with FET switches having a common threshold voltage and channel structure. A positive voltage is applied to the gate of each FET M1 to Mn of the stack 202, 204 to turn the stack on (conducting), and a negative voltage is applied to the gate of each FET M1 to Mn of the stack 202, 204 to turn the stack off (blocking). As an example, a positive DC voltage of +3 volts may be applied to the gate of each FET M1 to Mn of the stack 202, 204 (through a resistor Rg) to turn the stack on, and a negative DC voltage of -3 volts may be applied to the gate of each M1 to Mn of the stack 202, 204 (again through a resistor Rg) to turn the stack off. For good performance, it is desirable to use a sufficiently large negative voltage to turn each FET switch M1 to Mn completely off. Turning the FET switch to a fully off state results in advantages such as improved RF linearity in terms of harmonics and intermodulation distortion (IMD), better RF power handling, higher isolation, and lower leakage current.

[0018] In use Figure 2 In most applications of an integrated circuit (IC) implementation of the circuit shown, the positive supply voltage is readily available from an external source. A negative supply voltage is typically generated on-chip using a bias generator 206, such as Figure 2As shown, the bias generator 206 is coupled to the gate resistor Rg. The bias generator 206 may typically use one or more negative voltage charge pumps and a voltage regulator that converts an externally supplied positive supply voltage into a negative voltage.

[0019] Figure 2 The configuration shown works well in many applications. However, in some applications, generating a negative supply voltage is not desirable or practical due to design constraints; in some applications, a negative charge pump cannot even be used. These are typically applications with stringent requirements (e.g., very low current and power consumption, very low noise sensitivity, and / or very small IC die area). In addition, in biasing schemes where a charge pump is used to generate negative supply power, the switching speed is limited by the current source capability of the charge pump. In addition, the voltage swing from full on to full off on the FET gate is significant - from +3V to -3V or 6V in the above example, which further limits the switching speed. In addition, the charge swing must pass through the series gate resistor of the FET, which inhibits and slows down the switching process.

[0020] In co-pending U.S. Patent Application No. 15 / 256,453, filed on September 2, 2016 (now U.S. Patent No. 9,948,281), entitled “Positive Logic Digitally Tunable Capacitor,” a solution utilizing a stack of FET switches without using a negative supply voltage is taught. Figure 3 is a schematic circuit diagram of a series shunt RF switch circuit 300 using a "positive logic" FET stack. According to one embodiment of the referenced patent application, the RF signal from the antenna ANT is transmitted from the RF IN Coupled to RF via series stack 302 OUT The shunt stack 304 is coupled to the RF OUT Each stack 302, 304 includes a plurality of FETs M1 to Mn coupled in series (but "n" may be different for the two stacks 302, 304), which have the following characteristics: when V GS Each FET is fully turned off at ≈0 V. In this example, each FET includes a dedicated gate resistor Rg. Each stack 302, 304 also includes two surrounding DC blocking capacitors C connected in series with the FETs M1 to Mn; each of the blocking capacitors C can have different values ​​for a specific application.

[0021] Each of the stacks 302, 304 is configured to be coupled to two non-negative supply voltages Vgate and Vdrain, which are used to control the switch state ON or OFF of the associated FETs M1 to Mn. The Vgate supply voltage is coupled to the gates of the FETs M1 to Mn of each stack 302, 304 through corresponding parallel gate resistors Rg. The Vdrain supply voltage is coupled to a network of parallel resistors Rds, which are coupled to the respective drain or source of each of the FETs M1 to Mn as shown, including the shared drain-source node between the FETs M1 to Mn.

[0022] In the example shown, FETs M1 to Mn are turned on by applying a positive Vgate voltage (e.g., +3V) to the FET gates through their respective gate resistors Rg, while a Vdrain voltage of 0V is applied to the FET drains and sources through their respective Rds resistors. This configuration effectively creates a positive DC gate-source voltage V for each FET M1 to Mn. GS (That is, if Vgate = +3V, then relative to the source voltage of 0V, V GS = +3V). The FET stack is turned off by applying a Vgate voltage of 0V to the FET gates via their respective gate resistors Rg, while applying a positive Vdrain voltage (e.g., +3V) to the FET drain and source via their respective Rds resistors. This effectively creates a negative V for each FET M1 to Mn, relatively speaking. GS (That is, if Vgate = 0V, then relative to the source voltage of +3V, V GS =-3V).

[0023] Negative V for the off state is achieved with the help of DC blocking capacitors C across each stack 302, 304. GS to achieve the desired gate-source voltage levels in both the ON and OFF states. Without the blocking capacitor C, the "end" FETs (i.e., M1, Mn) would have their drain or source DC coupled to some potential (e.g., circuit ground), which would not allow the desired V GS The voltage is applied to the FETs M1 to Mn. With a DC blocking capacitor C, when a positive Vdrain voltage is applied, a positive voltage may be established on the drain and source nodes of the FETs M1 to Mn as the capacitor C charges. Other variations and modes of operation are also disclosed in U.S. Patent Application No. 15 / 256,453 (now U.S. Patent No. 9,948,281).

[0024] Figure 3Circuits of the type shown avoid the use of negative voltages, and therefore do not require a negative voltage charge pump. Since the discharge of the FET gate does not have to go through a charge pump, switching speed is increased. Thus, operating without a charge pump enables a zero current standby mode with very fast switching and settling times and an effective RF state in standby mode, as well as other advantages, as disclosed in U.S. Patent Application No. 15 / 256,453 (now U.S. Patent No. 9,948,281). However, there is still room for improvement.

[0025] In particular, the DC blocking capacitors C must be large to obtain high isolation and low insertion loss and low mismatch loss (i.e., their impedance at the required operating frequency needs to be low), thus consuming IC die area and increasing cost. The constant presence of the DC blocking capacitors C of the series stack 302 in both the on-state and the off-state affects the transmitted RF signal, while their constant presence and size affect the isolation. In addition, the constantly present DC blocking capacitors C must be charged through the Rds resistor network, which affects the switching time and the setting time (this is in addition to the usual Rg*Cgs time constant on the gate terminal side). In addition, the DC blocking capacitors C are typically formed as a metal insulator metal (MIM) capacitor structure, which is sensitive to electrostatic discharge (ESD) and therefore requires that the RF ports (e.g., RF IN ) for ESD protection.

[0026] Furthermore, in practical applications, the series stack 302 typically requires an integrated shunt tuning inductor L coupled near each DC blocking capacitor C to perform both impedance matching (i.e., resonating the capacitance of the DC blocking capacitor C) and ESD protection for the port connection (by providing a DC path to a reference potential). Such added shunt tuning inductors L, combined with the adjacent blocking capacitors C, give the series stack 302 a high-pass filter response, thereby affecting the RF performance of the switch. The shunt tuning inductors L also consume IC area, thus increasing cost.

[0027] Another area that needs improvement is handling high voltages. Figure 3 Embodiments of the type shown may break down when subjected to a high voltage RF signal due to the RF voltage coupling to the gate resistor causing the breakdown.

[0028] Therefore, there is a need for an improved FET switch stack that does not require a negative bias voltage, but also avoids or mitigates the disadvantages of the positive logic FET stack as described above, and in some embodiments can withstand the application of high voltage RF signals. The present invention addresses these and other needs. Summary of the invention

[0029] The present invention includes an improved positive logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion loss and mismatch loss characteristics, requires less integrated circuit (IC) area, and in some embodiments, can withstand the application of high voltage RF signals.

[0030] Embodiments include a FET stack including one or more positive logic FETs M1 to Mn coupled in series (ie, requiring a negative V GS The one or more series-coupled positive logic FETs M1 to Mn are coupled in series at at least one end to an "end cap" FET M. 0 , where “M 0 ” indicates a high Vt type FET, which has a V GS It is off at essentially zero volts. 0 The FET can selectively provide a capacitive DC blocking function or a resistive signal path. Some embodiments may include only M 0 FET stack or positive logic FET with M 0 FET mix, as long as at least one end cap FET is M 0 FET. An optional end cap capacitor may be included to prevent the corresponding end cap M 0 FET breaks down early.

[0031] Some embodiments are configured to provide a plurality of FETs (ie, M1 to Mn, M2 to M3) in a stack by including a plurality of FETs (ie, M1 to Mn, M3 to M4 to M5) in a stack. 0 ) of the gate, a series connected bias resistor ladder of Rds drain-source resistor ladder, and a series or parallel connected Rb body charge control resistor ladder to withstand high applied RF voltages. Some embodiments may combine the series connected Rb body charge control resistor ladder with the parallel connected bias resistor ladder for the gate. Some embodiments may combine the series connected bias resistor ladder (in a "track" configuration) with the parallel connected bias resistor ladder for the gate (in a "rung" configuration).

[0032] Some embodiments are configured with one or more AC coupling modules, each AC coupling module coupled to at least one end of a corresponding gate bias resistor ladder and / or body charge control resistor ladder and configured to be coupled to a radio frequency voltage source.

[0033] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a simplified schematic circuit diagram of a general prior art series shunt switch circuit configuration.

[0035] Figure 2 is a schematic circuit diagram of a prior art series shunt RF switch circuit using a FET stack.

[0036] Figure 3 is a schematic circuit diagram of a series shunt RF switch circuit using a "positive logic" FET stack.

[0037] Figure 4 is a schematic circuit of a modified positive logic FET stack.

[0038] Figure 5A is shown with Figure 4 1 is a table of example voltages for Vgate and Vdrain corresponding to the on-state and off-state of a FET stack.

[0039] Figure 5B yes Figure 4 A simplified schematic circuit diagram of a FET stack showing the inner FET Mn and the end cap FET M when in the on state. 0 Example drain voltage and example source voltage of .

[0040] Figure 5C yes Figure 4 A simplified schematic circuit of a FET stack showing the internal FET Mn and the end cap FET M when in the off state. 0 Example drain voltage and example source voltage of .

[0041] Figure 6 is used Figure 4 Schematic diagram of the improved positive logic FET stacked series shunt RF switch circuit.

[0042] Figure 7 A schematic equivalent circuit of a portion of a prior art FET stack is depicted, showing parasitic capacitances.

[0043] Fig. 8A is a schematic equivalent circuit of a FET stack with a series connected resistor ladder gate biasing scheme showing parasitic capacitances according to one aspect of the present invention.

[0044] Figure 8B is a schematic diagram of a positive logic FET stack having a series connected gate bias resistor ladder and a series connected drain-source resistor ladder in accordance with the present invention.

[0045] Figure 8Cis a schematic diagram of a positive logic FET stack with an additional series-connected resistor ladder for controlling body charge.

[0046] Fig.8D is a schematic diagram of a conventional FET stack having a gate bias resistor ladder, a series connected drain-source resistor ladder, and a body charge control resistor ladder.

[0047] Fig. 8E is a schematic diagram of a conventional FET stack having a series-connected gate bias resistor ladder, a series-connected drain-source resistor ladder, and a parallel-connected body charge control resistor ladder.

[0048] Fig.8F is a schematic diagram of a conventional FET stack with a series connected gate bias resistor ladder and AC coupled gate modules.

[0049] Figure 8G is a schematic diagram of a conventional FET stack with a series connected gate bias resistor ladder and dual AC coupled gate modules.

[0050] Figure 8H is a simplified schematic diagram of a SOI MOSFET including an ACS structure and conventional drain D, source S and gate G terminals and a gate resistor Rg.

[0051] Fig. 9 is a process flow diagram illustrating one method for providing a FET switch stack.

[0052] Fig.10 is a process flow diagram illustrating one method for providing a series shunt switch circuit.

[0053] Fig.11 is a process flow diagram illustrating one method for biasing a FET switch stack.

[0054] Fig.12 is a process flow diagram illustrating a method for providing a FET switch stack.

[0055] Fig.13 is a process flow diagram illustrating another method for biasing a FET switch stack.

[0056] Throughout the various drawings, like reference numbers and designations refer to like elements. DETAILED DESCRIPTION

[0057] The present invention includes an improved positive logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion loss and mismatch loss characteristics, requires less integrated circuit (IC) area, and in some embodiments, can withstand the application of high voltage RF signals.

[0058] Embodiments include a FET stack including one or more positive logic FETs M1 to Mn coupled in series (ie, requiring a negative V GS The one or more series-coupled positive logic FETs M1 to Mn are coupled in series at at least one end to an "end cap" FET M1. 0 , where “M 0 ” indicates a high Vt type FET, which has a V GS It is off at essentially zero volts. 0 The FET can selectively provide a capacitive DC blocking function or a resistive signal path. Some embodiments may include only M 0 FET stack or positive logic FET with M 0 FET mix, as long as at least one end cap FET is M 0 FET. An optional end cap capacitor may be included to prevent the corresponding end cap M 0 FET breaks down early.

[0059] Some embodiments are configured to withstand applied high RF voltages by including: FETs for the FETs in the stack (i.e., M1 to Mn, M 0 ) of the gate, a series connected bias resistor ladder of Rds drain-source resistor ladder, and a series or parallel connected Rb body charge control resistor ladder. Some embodiments may combine the series connected Rb body charge control resistor ladder with the parallel connected bias resistor ladder for the gate. Some embodiments may combine the series connected bias resistor ladder (in a "track" configuration) with the parallel connected bias resistor ladder for the gate (in a "rung" configuration).

[0060] Some embodiments are configured with one or more AC coupling modules, each AC coupling module coupled to at least one end of a corresponding gate bias resistor ladder and / or body charge control resistor ladder and configured to be coupled to a radio frequency voltage source.

[0061] Embodiments of the present invention may be used in any circuit configuration where FET stacks may be necessary or useful, such as RF switching circuits and digital tuning capacitors (e.g., of the type taught in U.S. patent application Ser. No. 15 / 256,453 (now U.S. Pat. No. 9,948,281, issued Apr. 17, 2018)).

[0062] Optional DC blocking implementation

[0063] Figure 44 is a schematic circuit diagram of an improved positive logic FET stack 400. The stack 400 includes one or more FETs M1 to Mn coupled in series. As taught in co-pending U.S. Patent Application No. 15 / 256,453 (now U.S. Patent No. 9,948,281 issued on April 17, 2018), each of the FETs M1 to Mn is of the following type: GS to shut down (e.g. -3V), but are configured to not require a negative power supply. Such an example of a FET M1 to Mn may have a V T ≈0V and low R ON (For example, much smaller than Z 0 Ohm, where Z 0 is the system characteristic impedance).

[0064] In some embodiments, the FETs M1 to Mn in the “interior” of the stack 400 are “end capped” by M 0 The FETs M1 to Mn may be zero-Vt, low-Vt, or high-Vt FETs. In other embodiments, only one end of one or more series-coupled positive logic FETs M1 to Mn is coupled in series to the M 0 FET; therefore, for example, in some applications the end cap M in the dashed box 402 may be omitted 0 FET or end cap M in dashed box 404 0 FET. Zero-Vt, low-Vt, or high-Vt FETs are available from many different IC commercial foundries. Such end caps M 0 An example of a FET could have a V T ≈0.7V and can have a ratio of FET M1 to M n High R ON .

[0065] Each FET M1 to Mn, M 0 An associated gate resistor Rg is included; in the example shown, the gate resistors Rg are dedicated to each FET and are connected in parallel with each other (for other configurations, see below).

[0066] Two non-negative supply voltages Vgate and Vdrain are used to control the associated FETs M1 to Mn, M 0 The switching state of the FETs M1 to Mn is turned on or off. The Vgate supply voltage is coupled to the gates of the FETs of the stack 400 through corresponding dedicated parallel gate resistors Rg. The Vdrain supply voltage is coupled to a network of parallel resistors Rds, which are coupled to the respective source or drain of each of the FETs M1 to Mn as shown, including the shared drain-source node between the FETs M1 to Mn. Figure 4 In the embodiment of FIG. 5 , the gate resistor Rg and the network resistor Rds may have equal sizes, but those skilled in the art will appreciate that other embodiments may include resistors of different sizes.

[0067] exist Figure 4 In the embodiment shown, each end cap M 0 The drain and source of the FET are coupled in parallel with the capacitor Cd. As disclosed in more detail below, due to the end cap M 0 FET at V GS = 0V and therefore cannot normally handle the full drain-source voltage Vds applied across it, so across each end cap M 0 The Vds of the FETs are stepped down (eg, to 2V) by their respective capacitors Cd.

[0068] Figure 5A is shown with Figure 4 1 is a table of example voltages for Vgate and Vdrain corresponding to the on-state and off-state of a FET stack. Figure 5B yes Figure 4 A simplified schematic circuit diagram of a FET stack showing the internal FET Mn and the end cap M when in the on state. 0 Example drain voltage and example source voltage for a FET. Figure 5C yes Figure 4 A simplified schematic circuit diagram of a FET stack showing the internal FET Mn and the end cap M when in the off state. 0 Example drain voltage and example source voltage for a FET.

[0069] exist Figure 4 and Figure 5B In the example shown, FETs M1 to Mn, M0 are turned on by applying a positive Vgate voltage (e.g., +3V) to the FET gates through their respective gate resistors Rg, while a Vdrain voltage of 0V is applied to the drains and sources of FETs M1 to Mn through their respective Rds resistors. (Note that technically, the “top” FET 0 The source of the FET will be coupled to the antenna or other RF signal source, and therefore its drain is at the "bottom" end of the FET. Similarly, the "bottom" M 0 The source of the FET will be circuit ground, so its drain is at the "top" end of the FET. Therefore, the Vdrain voltage is coupled to the "top" M 0 FET and the "bottom" M 0 The drains of the two FETs. It should be clear that "top" and "bottom" are relative to Figure 4The FET stack in FIG. 1 is oriented as shown and is for convenience only). Figure 5B As shown, this configuration effectively creates a positive DC gate-source voltage V for each FET M1 to Mn, M0. GS (That is, if Vgate = +3V, then relative to the source voltage of 0V, V GS = +3V). In the on state, the end cap M 0 FETs each present R ON The series resistance of the terminal cap M 0 FETs present essentially no series capacitance, so the shunt tuning inductor L for impedance matching can be omitted, thereby improving broadband performance and reducing IC area consumption.

[0070] exist Figure 4 and Figure 5C In the example shown, a 0V Vgate voltage is applied to the FET gates through their respective gate resistors Rg, while a 0V Vgate voltage is applied to the drains and sources of the FETs M1 to Mn (and therefore to the “top” FET M2) through their respective Rds resistors. 0 FET and to the "bottom" M 0 FET) applies a positive Vdrain voltage (e.g., +3V), and FETs M1 to Mn and M0 are turned off. Figure 5C This effectively creates a negative V for each FET M1 to Mn as shown GS (That is, if Vgate = 0V, then relative to the source voltage of +3V, V GS =-3V). End cap M 0 FET has -3V (for the "top" M 0 FET) or 0V (for the “bottom” M 0 FET) V GS , according to its V GS characteristics, both values ​​are sufficient to make the end cap M 0 FET is off (although the current blocking capability of the end cap M0 FET increases with V GS In the off state, the end cap M 0 FETs all show C OFF series capacitor and thus performs a DC blocking function.

[0071] As an alternative embodiment, when the "bottom" M 0 When the FET is turned on, the Figure 4 The terminal marked Vdrain in the figure is left open circuit because all FETs coupled to the Rds resistor network will pass through the “bottom” M 0 The FET is coupled to circuit ground. For the off state, Figure 4The terminal marked Vdrain in the figure will be coupled to a suitable voltage (e.g., +3V).

[0072] exist Figure 4 In the example embodiment of , Vdrain varies between 0V and 3V depending on the on or off state of the FET stack 400. In other embodiments, Vdrain can be set to a fixed voltage, such as a constant mid-rail voltage (e.g., +1.5V). Thus, similar to FIG. 5A to FIG. 5C In the example shown in FIG. 1 , when Vgate is high (eg, +3V), a positive voltage of +1.5V will appear on each FET M1 to Mn, M 0 Conversely, when Vgate is low (e.g., 0V), a negative voltage of -1.5V will appear between the gate-source of each internal FET M1 to Mn and turn these FETs off; similarly, the "top" end cap M 0 FET V GS will be -1.5V, while the "bottom" end cap M 0 FET V GS will be 0V, therefore, the two end caps M 0 FETs will be off. In a constant Vdrain bias scheme, a lower or higher voltage (e.g. +0.5V) can also be used for Vdrain. In other embodiments, the FET threshold voltage V T The fixed mid-rail voltage is selected to provide a beneficial (potentially optimal) level of gate overdrive (V GS -V T ) to balance performance parameters in the on-state and off-state. More generally, the voltages of Vgate and Vdrain can be selected (and potentially optimized) to provide a balanced amount of gate overdrive. If Vdrain is biased to a non-zero DC voltage, then it may be necessary to add a properly sized shunt capacitor (or RC filter) to adequately filter out the RF voltage swing.

[0073] therefore, Figure 4 The circuit configuration of the FET stack 400 is Figure 3 The circuit configurations of the stacks 302 and 304 are similar, except that: the end caps M 0 FETs are used for DC blocking rather than using explicit DC blocking capacitors C. In operation, the end caps M 0 The FETs can be switched to an off state, in which they act as a OFF Capacitors are DC blocking capacitors. It is important that the end caps M 0The FET can also be turned to an on state, which forms a true resistive DC path rather than a capacitive one, causing little or no insertion loss, mismatch loss, or frequency-dependent penalty compared to the constant presence of the DC blocking capacitor C, and also reducing switching time and settling time. 0 FET R ON Typically can be larger than the R ON , while the number of internal FETs M1 to Mn is greater (i.e., higher stack height), the R ON will dominate the series resistance.

[0074] Use one or more end caps M 0 Another benefit of FETs as DC blocking capacitors is that they provide automatic ESD protection because the FET stack is self-protected against drain-source breakdown and there are no additional series components between the FET drain-source terminals and the external port across which the ESD pulse is applied. Therefore, the shunt tuning inductor L for ESD protection of the MIM capacitors in the FET stack coupled to the port can be omitted, thereby reducing the consumption of IC area. In addition, the use of one or more end caps M 0 FETs for those in which the system voltage supply V CC Applications that benefit from some isolation when equal to 0V provide a reasonable "unpowered off" state.

[0075] In some embodiments, all of the FETs in stack 400 may be M 0 In other embodiments, some (but not all) of the internal FETs in stack 400 may be M 0 Type, as long as at least one end cap M is provided 0 For example, the stack 400 may include a plurality of FETs, such as M 0 -M1-M 0 -M2-M 0 A mix of sequential FETs, where M1 and M2 are positive logic FETs. 0 FET R ON higher, so such a mixed configuration may be Figure 4 The embodiment shown has a higher series resistance than that shown, but is comparable to the embodiment including all M 0 FET stacks have lower R ON A mix of FET types and sequences can be used to help optimize R ON , off isolation, peak voltage (Vpk) handling, DC operation, and total stack-up performance parameters for unpowered circuit behavior.

[0076] Return to reference Figure 4 As shown by the dashed connecting line, an optional capacitor Cd can be connected from drain to source and end cap M 0 FETs are coupled in parallel. When the end cap M 0 When the FET is in the on state, the optional capacitor Cd is effectively bypassed and therefore acts outside the RF signal path. 0 When the FET is in the off state, the optional capacitor Cd and the end cap M 0 FETs (each presented as C OFF The capacitor Cd is coupled in parallel to the RF signal path. One advantage of the optional capacitors Cd is that they reduce the cross-cap M 0 The RF voltage swing of the FETs is reduced (e.g., to 2V instead of the full 3V), thus helping to prevent early breakdown of these FETs. It may be desirable for the optional capacitor Cd to have a terminal cap M 0 FET's C OFF In some embodiments, only the "bottom" M 0 FET (i.e. Figure 4 closest to circuit ground) includes capacitor Cd.

[0077] Further reference Figure 4 , those skilled in the art will appreciate that regardless of the switching state of the FET stack 400, and other than leakage current, the FET stack 400 and the generation of the bias voltages Vgate and Vdrain do not consume any significant DC power, unlike the case of a FET stack that requires a charge pump. This is very beneficial for integrated circuits with strict power or current consumption requirements. Implementations can use existing system voltage supply rails to provide Vgate and Vdrain; however, those skilled in the art will appreciate that other design options for providing Vgate and Vdrain are contemplated.

[0078] In some other embodiments, the end cap M 0 The gate of one or both of the FETs can be biased separately from the internal FETs M1 to Mn. For example, with a negative gate voltage (and thus a negative V GS )Offset end cap M 0 The gates of both FETs will more completely turn off both FETs and improve the linear and harmonic performance of these FETs, but will not require significant current draw since such FETs inherently draw low body current and are only two in number. Negative biasing will also allow the optional capacitor Cd to be much smaller than otherwise, or omitted entirely. Thus, a simple negative voltage generator can be used to supply only one capacitor to the terminal cap M. 0 The FET generates a negative gate voltage bias.

[0079] Figure 6 is used Figure 4 Schematic diagram of an improved positive logic FET stacked series shunt RF switch circuit 600. In the example shown, the RF signal from the antenna ANT is transmitted from the RF IN Coupled to RF via series stack 602 OUT In RF OUT A shunt stack 604 is coupled between 602 and a reference potential (circuit ground in this case). Each of the stacks 602, 604 is similar to Figure 4 FET stack 400, but "n" may be different for the two stacks 602, 604. (To avoid confusion, the coupling to FETs M1 to M2 is omitted. n , M0, and the network of resistors Rds and gate resistors Rg of the source or drain of each of M0). Figure 4 As shown, each of the stacks 602, 604 is configured to be coupled to two non-negative supply voltages Vgate and Vdrain. An optional capacitor Cd is shown with the end cap M 0 FETs are coupled in parallel. Note that there is no Figure 3 The fixed connected DC blocking capacitors or shunt tuning and ESD protection inductors L are shown.

[0080] exist Figure 6 In a variation of the series-shunt RF switch circuit 600, only one end of the series stack 602 and / or the shunt stack 604 includes an end cap M. 0 FET.

[0081] Stacked FET Switch Bias Ladder

[0082] In the embodiments of the present invention disclosed above, in a conventional biasing scheme, each FET M1 to Mn, M2 is biased by an associated gate resistor Rg. 0 Vgate is applied, which provides excellent performance in many applications including low power RF switching circuits and many series and / or shunt circuit configurations. However, for high RF voltage applications such as RF tuning switches, the innovative biasing scheme provides an enhanced ability to withstand such voltages.

[0083] To better understand the problems caused by applying high RF voltages to a FET stack, Figure 7 A schematic equivalent circuit of a portion of a prior art FET stack 700 is depicted, showing parasitic capacitances. The “top” FET Mtop of the FET stack 700 is coupled to an RF input voltage V RF, and is coupled to the next sequential FET Mnext. It should be understood that additional FETs may be similarly coupled in sequence to Mnext.

[0084] A conventional parallel gate bias resistor ladder 702 is shown, where a variable DC gate bias voltage Vgate is coupled to the gate of each FET Mtop, Mnext through a corresponding gate resistor Rg. Since the FETs and gate resistors are integrated devices formed on an IC substrate, there are inherent associated parasitic capacitances. In particular, each gate resistor Rg has a parallel parasitic capacitance Cp R , and each FET includes a parasitic capacitance Cp between its gate and drain and between its gate and source M . Therefore, the gate of each FET is not perfectly isolated from the gate and source with respect to the RF signal.

[0085] use Figure 7 For example, if V RF The RF voltage is 100V, and the stack 700 is in the off state (i.e., all FETs are biased to prevent drain-source current from flowing), and if each FET Mtop, Mnext, etc. can safely withstand a voltage of 3V from drain to source (further assuming that there are enough other FETs to drop the applied RF voltage so that no FET experiences a voltage greater than 3V), then the source voltage of Mtop (and therefore the drain voltage of Mnext) will be 97V and the source voltage of Mnext will be 94V; additional FETs in the sequence will similarly drop 3V from drain to source. Parasitic capacitance Cp M This will cause an RF voltage of about 98.5V (i.e., about half the difference between 100V and 97V) to be applied to the gate of Mtop; for Mnext, the applied gate voltage will be about 95.5V. More specifically, the gate resistor Rg of Mtop will have essentially AC ground (0V) on its Vgate side, and a very high RF voltage (~98.5V) on its other side. This causes excessive power dissipation in the gate resistor Rg for Mtop. The parallel parasitic capacitor Cp across the gate resistor Rg R Making the effective resistance smaller increases the RF power dissipation in the gate resistor Rg, which may cause device failure. For each of the successive FETs Mnext in the stack 700, a similar problem occurs, but the RF voltage becomes progressively lower.

[0086] Fig. 8A 8 is a schematic equivalent circuit of a FET stack 800 with a series connected resistor ladder gate biasing scheme according to one aspect of the present invention, showing parasitic capacitances. The “top” FET Mtop of the FET stack 800 is coupled to an RF input voltage VRF , and coupled to the next sequential FET Mnext; additional FETs may be similarly coupled to Mnext in sequence. A variable DC gate bias voltage Vgate may be coupled to the gate of each FET Mtop, Mnext at nodes A, B located after a corresponding one of a plurality of series-coupled gate resistors Rg, thereby forming a series-connected gate bias resistor ladder 802. In other words, each gate resistor Rg is coupled to the gates of two adjacent FETs, and the series-connected gate bias resistor ladder 802 is configured to be connected to the gate bias voltage Vgate. Thus, in the example shown, for n FETs, there are n-1 gate resistors Rg (see also Figure 8B ); however, if desired, an additional gate resistor Rg may be coupled between Vgate and the gate of the “bottom” FET in the FET stack 800 (see, for example, Figure 8B The resistor R BF ). Each FET gate will see a DC bias voltage of Vgate applied through the series connection of gate resistors Rg of resistor ladder 802; that is, Vgate essentially charges or discharges each FET gate only through the corresponding gate resistor Rg.

[0087] Using the example values ​​stated above, if V RF If the RF voltage is 100V and each FET Mtop, Mnext, etc. can safely withstand a voltage of 3V from drain to source, then the source voltage of Mtop (and therefore the drain voltage of Mnext) will be 97V, and the source voltage of Mnext will be 94V. When the stack 800 is in the off state, the parasitic capacitance Cp M will result in an RF voltage of about 98.5 V being applied to the gate of Mtop; for Mnext, the applied gate voltage will be about 95.5 V. Importantly, due to the altered configuration of the series-connected gate resistors Rg of the resistor ladder 802, each gate resistor Rg and its corresponding parasitic capacitance Cp is R will experience an RF voltage of only 3V, representing the difference between the RF voltages applied to the gates of adjacent FETs (e.g., 98.5V for the gate of Mtop and 95.5V for the gate of Mnext). Figure 7 The topmost gate resistor of FET stack 700 of FIG. 8 is subjected to an RF voltage of 98.5 V across its terminals, but all gate resistors of FET stack 800 of FIG. 8 are subjected to an RF voltage of only 3 V and are therefore protected from breakdown due to excessive RF voltage capacitively coupled to the gates of the associated FETs.

[0088] Figure 8Bis a schematic diagram of a positive logic FET stack 820 having a series connected gate bias resistor ladder 802 and a series connected drain-source resistor ladder according to the present invention. The example shown is similar to Figure 4 FET stack 400 (with optional capacitor Cd), but with gate resistor Rg as Fig. 8A 802, and in addition, the resistors Rds of the drain-source resistor network are also arranged in a series connected resistor ladder 804, which is configured to be connected to the drain-source bias voltage Vdrain. More specifically, each resistor Rds is connected across the drain and source of the corresponding internal FET M1 to Mn (but not across the end cap M 0 FET connection, which will make the end cap M 0 Like the series-connected gate bias resistor ladder 802, the series-connected drain-source resistor ladder 804 prevents either the Rds resistor or the FET device from experiencing the high RF voltage V RF . Note that, as described below Figure 8C As depicted, a DC blocking capacitor (not shown) may be coupled to Vgate and / or Vdrain.

[0089] exist Figure 8B In the example shown, the bias voltage Vgate is shown as being supplied through a “bottom feed” resistor R at one end of a series of resistors comprising a gate bias resistor ladder 802. BF is coupled to the "bottom" FET in FET stack 820 at a "bottom feed" node BF. However, alternative connection points may be used if desired; for example, Vgate may optionally be coupled to the "bottom" FET in FET stack 820 through a "mid feed" resistor R MF The FET stack 820 is coupled to the series connected gate bias resistor ladder 802 at a "mid-feed" node MF. It should be clear that the "mid-feed" node MF does not have to be in the exact middle of the gate bias resistor ladder 802, but can be located anywhere between the ends of the series of resistors that include the gate bias resistor ladder 802. When the FET stack 820 may experience a "top" or "bottom" (relative to the top) of the stack 820, the FET stack 820 may be coupled to the series connected gate bias resistor ladder 802 at a "mid-feed" node MF. It should be clear that the "mid-feed" node MF does not have to be in the exact middle of the gate bias resistor ladder 802, but can be located anywhere between the ends of the series of resistors that include the gate bias resistor ladder 802. Figure 8B ) is applied to the FET at a “mid-feed” configuration, such as might be the case if the FET stack 820 is designed for a bipolar series application (i.e., the RF signal can be applied to either end of the stack) rather than a shunt configuration (see also below). Fig.8F) situation. In particular, the "mid-feed" configuration can provide a reduction in power dissipation in the gate resistor Rg, regardless of whether the RF voltage amplitude is applied at either end of the transistor stack. Other benefits of the "mid-feed" configuration are described in U.S. Patent Application No. 15 / 289,768 cited above.

[0090] In an optional configuration, an additional parallel-connected gate resistor ladder 805 may be included. The parallel-connected gate resistor ladder 805 includes corresponding resistors Rg' (indicated by block symbols) coupled to the gates of the FETs in the FET stack 820. In some embodiments, the combination of the series-connected gate bias resistor ladder 802 and the parallel-connected gate resistor ladder 805 can provide reduced RF power consumption while maintaining a low switching time constant (and therefore high switching speed). Additional benefits of the "series plus parallel" gate bias ladder configuration are described in the above-referenced U.S. Patent Application No. 15 / 289,768.

[0091] Figure 8C 8 is a schematic diagram of a positive logic FET stack 830 having an increased series connected resistor ladder for controlling body charge and thus the "back gate" characteristic in the FET. In this example, each FET (any type M1-Mn, M 0 ) is considered as an explicit four-terminal transistor, and the body of each of the stacked four-terminal FETs is configured to be connected to the body bias voltage Vbody directly or through a corresponding resistor Rb of the body charge control resistor ladder 806. Figure 8B As is the case with the series-connected gate bias resistor ladder 802, the series-connected body charge control resistor ladder 806 prevents any resistor Rb from being subjected to the high RF voltage V RF The series connected body charge control resistor ladder 806 is also useful for FET stacks that draw large amounts of body current to mitigate or eliminate disturbances to the gate voltage when high peak RF voltages are applied across the FET stack.

[0092] In an optional configuration, an additional parallel connected gate resistor ladder may be included (not shown, but similar to Figure 8B The parallel gate resistor ladder 805 is basically the same).

[0093] exist Figure 8C In the circuit configuration of FIG. 1 , a separate Vbody terminal is shown in the schematic for flexibility, but in many applications, Vbody can be connected directly to circuit ground. When Vbody is connected directly to circuit ground, FETs M1 to Mn, M 0 All bulk current in the circuit is derived from circuit ground (for example, V GS =Vbody=0V). In contrast, Figure 2 In a conventional FET stack of the type shown, the body current needs to be sourced from a negative power supply (e.g., V GS =Vbody=-3V). Such a negative power supply is usually provided by a negative charge pump, whose output Vss will drop and induce significant body current when a high peak RF voltage is applied across the FET stack.

[0094] In some embodiments, capacitors Cgate, Cdrain, and / or Cbody can be coupled to Vgate, Vdrain, and Vbody terminals, respectively, as shown, and to a reference potential, such as circuit ground. The Cgate, Cdrain, and / or Cbody capacitors (when present) are used to filter RF voltage from a DC bias voltage applied to these terminals (i.e., to AC-ground Vgate, Vdrain, and / or Vbody).

[0095] Fig. 8A The series connected gate bias resistor ladder 802 is configured, Figure 8B The series connected drain-source resistor ladder 804 and Figure 8C The series connected bulk charge control resistor ladder 806 is suitable for conventional FET stacks (e.g., Figure 2 or FET stack of the type shown in 3) and having one or more end caps M 0 FET (that is, when its V GS For example, Fig.8D is a schematic diagram of a conventional FET stack 840 having a series-connected gate bias resistor ladder 802, a series-connected drain-source resistor ladder 804, and a series-connected body charge control resistor ladder 806. Figure 8C Compared to the embodiment of the present invention, the "end cap" FETs M1 and Mn are conventional FETs, and an additional drain-source resistor Rds' is added to the drain-source resistor ladder 804 to span the drain and source of each of M1 and Mn, removing the Figure 8C The optional capacitor Cd is provided, and there is no Vdrain bias voltage. This configuration has the advantages of the series-connected gate bias resistor ladder 802 for each of the series-connected resistor ladders 802, 804, 806 described above, especially the advantage of preventing breakdown due to RF voltage coupled by excessive capacitance.

[0096] In some embodiments, in a conventional FET stack or in a stack with one or more end caps M 0 In a FET stack of FETs, the series connected body charge control resistor ladder 806 may be replaced by a parallel connected body charge control resistor ladder. For example, Fig. 8E808. FIG. 809 is a schematic diagram of a conventional FET stack 850 having a series-connected gate bias resistor ladder 802, a series-connected drain-source resistor ladder 804, and a parallel-connected body charge control resistor ladder 808. Fig.8D This parallel connection approach may prove advantageous if the lower body current (as shown) will be high enough that the accumulated IR drop will cause the voltage on the body of the "top" FET Mn (i.e., the FET farthest from the input node of the bias voltage Vbody) to become undesirably high. The parallel connected body charge control resistor ladder 808 configuration produces a consistent voltage drop across the body resistor Rb so that there is no additional voltage increase.

[0097] In an optional configuration, an additional parallel connected gate resistor ladder may be included (not shown, but similar to Figure 8B In some embodiments, the configuration of the bulk charge control resistor ladder can be a series connection (e.g., Fig.8D ), while the gate bias resistor ladder configuration can be connected in parallel (as shown Figure 4 as shown) or a combination of series connection and parallel connection (as shown Figure 8B As shown, with an increased parallel connected gate resistor ladder 805), the benefits are similar to those described above for Fig. 8E Describe the benefits.

[0098] It should be understood that any combination of series connected resistor ladders 802, 804, 806 may be used in conjunction with the FET stack, with or without the addition of a parallel connected gate resistor ladder 805 or with or without a parallel connected body charge control resistor ladder 808 in place of the series connected resistor ladder 806. Examples include: a gate bias resistor ladder plus a body charge control resistor ladder; a gate bias resistor ladder plus a drain-source resistor ladder; a body charge control resistor ladder plus a drain-source resistor ladder; and a gate bias resistor ladder plus a body charge control resistor ladder plus a drain-source resistor ladder.

[0099] If the end cap M is included 0 If more than one resistor ladder is used in a FET stack of a FET, it may be necessary or useful to provide non-overlapping sequencing of the state changes of the Vgate, Vdrain, and Vbody voltages to help prevent end cap M 0 The “breakdown” DC current in a FET. Due to the essentially zero V GS M 0 FETs, positive logic FETs (e.g. Figure 4 FETs M1 to Mn in the embodiment have different on-to-off and off-to-on switching characteristics and timing, so such current may occur. Figure 8C , when switching the FET stack from the off state to the on state, it may be preferred to change Vdrain (e.g., from 3V to 0V) before changing Vgate (e.g., from 0V to 3V). Conversely, when switching the FET stack from the on state to the off state, it may be preferred to change Vgate (e.g., from 3V to 0V) before changing Vdrain (e.g., from 0V to 3V).

[0100] Bias ladder with AC coupling module

[0101] The series-connected or series / parallel-connected gate resistor ladders described above allow the gate of each FET in the switch stack to track the common-mode voltage of its associated FET. Typically, such gate resistor ladders must provide a high impedance relative to the impedance (capacitance) between the gate of the FET in the switch stack and the source / drain of the FET. Although the series-connected gate bias resistor ladder 802 described so far (e.g., as Fig. 8A ) or a combination of a series-connected gate bias resistor ladder 802 and a parallel-connected gate bias resistor ladder 805 (e.g., as shown Figure 8B ) has the benefit that in some applications the FET closest to the applied RF signal (e.g. FIG. 8B to FIG. 8E The coupling to V RF The “top” FET of the “top” FET still has an effective RF load, which may prevent the gate of the FET from completely tracking the transistor common-mode voltage during RF operation. The RF load on the gate of the “top” FET acts as a parasitic capacitor in creating a non-ideal voltage division and, if not compensated, can reduce the peak breakdown voltage (BV) capability of that FET by several percentage points.

[0102] However, by coupling the AC coupled gate module 822 between the RF input terminal and the gate of the FET in the stack closest to the RF input terminal (at least through a gate resistor), the load seen by that “top” FET can be greatly reduced or even completely eliminated. FIG. 8B to FIG. 8E In the embodiment, the AC coupling gate module 822 is coupled to receive V RF The signal terminal is connected to the "top" FET (Mn or M as appropriate). 0 ) between the gates of the AC coupled gate module 822, therefore, the AC coupled gate module 822 is also coupled to the “top” of the series connected gate bias resistor ladder 802.

[0103] As another example, Fig.8F8 is a schematic diagram of a conventional FET stack 860 having a series connected gate bias resistor ladder 802 and an AC coupled gate module 822. The FET stack 860 is configured to be coupled in a shunt configuration or a series configuration. In the shunt configuration, the RF- terminal is typically circuit grounded, the RF input signal is applied at the RF+ terminal, and Vgate is connected via a resistor R BF applied at the "bottom" of the FET stack 860. In a series configuration, one or both of the RF+ and RF- terminals can be the source of an RF signal (e.g., RF+ can be coupled between an RF antenna and an amplifier), and Vgate is typically connected through a resistor R MF is applied in the “middle” of the FET stack 860. As described above, the “mid-feed” configuration can provide a reduction in power consumption of the gate resistor Rg, regardless of whether the RF voltage amplitude is applied at either end of the FET stack 860. It should be clear that Fig.8F The FETs M1 to Mn of the conventional FET stack 860 may be composed of Figure 8B Positive logic stack replacement of the type shown.

[0104] In some embodiments, the AC coupling gate module 822 may include a DC blocking capacitor C1, while in other embodiments, the AC coupling gate module 822 may include a DC blocking capacitor C1 connected in series with a resistor R1 (the order of connection of C1 and R1 is not important, and for a shunt stack configuration, Cgate and R1 at the “bottom” of the stack are connected in series with each other). BF The order of connection is important). The AC coupled gate module 822 improves the voltage division along the gate bias resistor ladder 802 and allows the gate of the "top" FET to more completely track the transistor common mode voltage during RF operation. Another benefit of the AC coupled gate module 822 in a series configuration is that it enables the coupled antenna to be loaded directly, rather than through the stacked FETs.

[0105] As mentioned above, in a series configuration, one or both of the RF+ and RF- terminals can be the source of the RF signal, and Vgate will typically be connected through a resistor R MF is applied in the "middle" of the FET stack 860. In this case, it may be beneficial to couple the coupling gate module between the series-connected gate bias resistor ladder 802 and both the RF+ and RF- terminals. For example, Figure 8G is a schematic diagram of a conventional FET stack 870 having a series connected gate bias resistor ladder 802 and dual AC coupled gate modules. Figure 8G The FET stack 870 is similar to Fig.8F822', the FET stack 860 is shown, but with a "mid-fed" configuration of Vgate, a first AC-coupled gate module 822 at the "top" of the stack closest to FET Mn, and a second AC-coupled gate module 822' at the "bottom" of the stack closest to FET M1. The second AC-coupled gate module 822' may include a DC blocking capacitor C2, while in other embodiments, the second AC-coupled gate module 822' may include a DC blocking capacitor C2 connected in series with a resistor R2. With the illustrated configuration of the AC-coupled gate modules 822, 822', the loading seen by the FETs closest to the RF+ and RF- terminals may be greatly reduced or even completely eliminated.

[0106] Return to reference Fig.8F , if a series-connected body charge control resistor ladder 806 is included in the FET stack 860, a similar AC-coupled body module 823 will provide the same benefits to the body (or "back gate") of the "top" FET (in this example, the FET Mn closest to the RF+ terminal). In the illustrated embodiment, the AC-coupled body module 823 is coupled between the RF+ terminal and the series-connected body charge control resistor ladder 806 connected to the "top" FET Mn closest to the RF+ terminal. In some embodiments, the AC-coupled body module 823 may include a DC blocking capacitor C2, while in other embodiments, the AC-coupled body module 823 may include a DC blocking capacitor C2 connected in series with resistor R2 (again, the order of connection is not important). Additionally, in a series configuration, a second AC-coupled body module (not shown) may be coupled between the RF- terminal and the series-connected body charge control resistor ladder 806 connected to the "bottom" FET M1 closest to the RF- terminal to provide similar benefits.

[0107] The AC coupled gate modules and the AC coupled body modules can be used independently of each other, or can be used together. In general, when using a series connected gate bias resistor ladder 802 and / or a series connected body charge control resistor ladder 806, there is a significant benefit in using an AC coupled gate and / or body module between each ladder 802, 806 and any RF terminal that presents an RF load to reduce or even completely eliminate the RF load across the FET coupled to that RF terminal.

[0108] In some embodiments, a parallel-connected gate bias ladder 805 may be included, wherein the value of the resistor Rg' is selected to isolate the component FETs M1 to Mn of the FET stack 860 for different voltage divisions in the gate bias resistor ladder. More specifically, if the voltage division across the FET stack 860 is uniform, the constant Rg value of the series-connected gate bias resistor ladder 802 (i.e., a "track-only" configuration) combined with the AC-coupled gate module 822 completely eliminates the RF loading on the FETs because the voltage division across the gate bias resistor ladder is uniform. On the other hand, if there is an undesirable voltage division across the FET stack 860, a mismatch may occur between the voltage division across the FETs and the voltage division across the track-only gate bias resistor ladder. This can be remedied by including a parallel-connected gate bias ladder 805 (i.e., adding "rungs" to the "tracks" of the series-connected gate bias resistor ladder 802). Adding the ladder resistor Rg' helps reduce the RF loading due to the non-ideal voltage division across the FET stack 860 with minimal switching time constant penalty.

[0109] In some gate bias ladder embodiments having a gate bias resistor ladder 802 connected in series (a "track" configuration) and a gate bias ladder 805 connected in parallel (a "ladder" configuration), it is beneficial to have variable values ​​(rather than constant resistance values) for the resistors of either or both of the "track" bias resistor ladder 802 and the "ladder" bias resistor ladder 805. Generally, the variation should taper from the top to the bottom of the FET stack; that is, the resistor value of one or both of the bias resistor ladders 802, 805 should be higher near the top, taper off, and lower at the bottom. For example, when the track resistance is variable and the ladder resistance is constant, there is a significant improvement in the peak breakdown voltage (BV) for the topmost transistor (closest to the RF signal input) compared to constant value track resistors and ladder resistors, while maintaining similar switching time and power consumption characteristics. In addition, the "variable track / constant ladder" gate bias resistor ladder configuration allows the ladder resistors to be much smaller in size than other configurations, thereby achieving greater flexibility in designing IC layouts. Similar benefits can be seen in embodiments using a "variable rail / variable rung" gate bias resistor ladder configuration. Note that the variable rail resistor values ​​can be adjusted to achieve the desired relationship of (1) RF loading on the FET gate and (2) peak BV of the topmost transistor. However, there is a tradeoff with the switching time constant.

[0110] Note that when the FET stack 860 is coupled to an antenna, etc., then the resistance of R1 is preferably set to half the resistance of the series connected resistor Rg (i.e., R1 = 1 / 2Rg) because the gate of the "top" FET only sees half the voltage below the antenna compared to the voltage across each of the other FETs.

[0111] Notably, the inclusion of the AC-coupled gate module 822 and / or the AC-coupled body module 823 has substantially no adverse effect on the performance characteristics of the FET stack 860 (e.g., in terms of switching time constants, resistor power dissipation, resistive voltage drop through the body resistor caused by body current, etc.). On the other hand, the inclusion of one or more of such modules 822, 823 substantially eliminates the reduction in peak breakdown voltage (BV) withstand capability of the "top" FET of the FET stack that would otherwise occur. As a specific example, using a modeling circuit to compare (1) a FET stack configuration using a series-connected gate bias resistor ladder 802 but without an AC-coupled gate module 822 to (2) a FET stack configuration using a series-connected gate bias resistor ladder 802 and an AC-coupled gate module 822, the former configuration shows a reduction in the BV withstand capability of the "top" FET by approximately 0.714, while the latter configuration shows a reduction in the BV withstand capability of the "top" FET by approximately 0.001 - an improvement of more than 700 times due to the AC-coupled gate module 822.

[0112] Note that in a series configuration of the FET stack 860 where one or both of the RF+ and RF- terminals may be the source of an RF signal, the AC-coupled gate module 822 may be coupled between the terminals RF+, RF-, and the respective ends of the series-connected gate bias resistor ladder 802 for the FET stack 860. In this case, a "mid-feed" configuration is typically used to apply Vgate to the FET stack 860. Similarly, an AC-coupled body module 823 may be coupled to each end of the body charge control resistor ladder 806 of the FET stack 860.

[0113] Accumulated charge absorption (sink) structure

[0114] Embodiments of the present invention including the above-described embodiments fabricated using silicon-on-insulator (SOI) MOSFETs, including silicon-on-sapphire (SOS) MOSFETs, may be implemented by providing one or more constituent FETs (i.e., M1 to Mn and / or M 0) can benefit from the addition of an Accumulated Charge Sink (ACS) structure. In particular, the linearity of SOI MOSFETs can be improved by providing a means for scavenging accumulated charge trapped beneath the gate oxide layer of the MOSFET, such as by using the "HaRP" Accumulated Charge Sink (ACS) technique taught in U.S. Patent No. 7,910,993, issued on March 22, 2011, entitled "Method and Apparatus for use in Improving Linearity of MOSFETs Using an Accumulated Charge SinK," which is incorporated herein by reference. "Accumulated charge," as defined in more detail in U.S. Patent No. 7,910,993 and as used herein, refers to gate bias induced carriers that can accumulate in the body of the off-state MOSFET, even when the majority of carriers in the body do not have the same polarity as the accumulated charge.

[0115] More specifically, as described in more detail in U.S. Patent No. 7,910,993, when the MOSFET is operated in the off state (i.e., the gate voltage does not exceed V th ) and when sufficient non-zero gate bias voltage is applied to the MOSFET source and drain, no matter what operating mode the SOI MOSFET adopts (i.e., whether it is enhancement mode or depletion mode), "accumulated charge" may appear under the MOSFET gate, which adversely affects the linearity and other performance aspects of the MOSFET. In order to mitigate the effects of such accumulated charge, the SOI MOSFET may include an ACS structure that allows the accumulated charge to be released when the MOSFET is in the non-conducting (off) mode, while allowing normal operation when the MOSFET is in the conducting (on) mode.

[0116] Figure 8H810 is a simplified schematic diagram of an SOI MOSFET 810 including an ACS structure and conventional drain D terminal, source S terminal and gate G terminal and gate resistor Rg. In this particularly illustrated example, the ACS structure includes a diode 812 coupled from the body of the MOSFET 810 to the gate G of the MOSFET 810. When the MOSFET 810 is in a non-conducting (off) mode, the diode 812 releases the accumulated charge from the body of the MOSFET 810 through the gate G, while allowing normal operation when the MOSFET 810 is in a conducting (on) mode. Alternative ACS structure circuits and methods for reducing accumulated charge in floating body semiconductor devices are described in more detail in U.S. Patent No. 7,910,993 cited above. The MOSFET 810 together with the ACS structure (e.g., the body-to-gate diode 812) may also be referred to as an "ACS FET". It should be clear that in the embodiment including a "end cap" M coupled to one or more series coupled 0 In an SOI MOSFET stack of one or more series-coupled positive logic MOSFETs M1 to Mn (ie, FETs that do not require a negative voltage supply to turn off), one or more of the MOSFETs may be ACS FETs.

[0117] method

[0118] Note that, in specifying a particular circuit implementation having the architecture and characteristics of the example circuits described above, the principle of "superposition" can be used as a method for independently optimizing the DC bias and the optimal AC voltage handling configurations and then combining the results. That is, the optimal circuit configuration can first be independently defined for the AC behavior and the DC behavior, and then the two solutions can be superimposed and combined. Mathematically, superposition can be expressed as f(DC+AC)=f(DC)+f(AC), where "DC" is the DC behavior of the circuit and "AC" is the AC behavior of the circuit.

[0119] Another aspect of the present invention includes a method for providing a FET switch stack. For example, Fig. 9 900 is a process flow diagram illustrating a method for providing a FET switch stack. The method includes: providing one or more positive logic FETs coupled in series (step 902); and providing a first end cap FET of a type that is energized at a V of such end cap FET. GS The first end cap FET is coupled in series to a first end of one or more series coupled positive logic FETs (step 904) when turned off at substantially zero volts.

[0120] Fig. 9Additional aspects of the method may include one or more of the following: providing a second end cap FET of the following type, the second end cap FET of the type having a V GS The second end cap FET is coupled in series to the second end of the one or more series coupled positive logic FETs; and further comprising coupling in series at least one additional FET of the type to the FET switch stack, the at least one additional FET of the type being turned off at the V of such FETs GS The invention further comprises a method for providing a gate bias resistor ladder comprising a plurality of resistors coupled in series and configured to be coupled to a gate bias voltage, wherein each resistor is coupled to a respective gate of a corresponding adjacent FET; further comprising coupling a capacitor between the gate bias resistor ladder and a reference potential; further comprising coupling an AC-coupled gate module to at least one end of the gate bias resistor ladder and configuring the AC-coupled gate module to be coupled to an RF voltage source; wherein the AC-coupled gate module comprises one of a capacitor or a capacitor coupled in series to a resistor; further comprising providing a body charge control resistor ladder comprising a plurality of resistors coupled in series to a gate bias voltage, wherein each resistor is coupled to a respective gate of a corresponding adjacent FET; further comprising coupling a capacitor between the gate bias resistor ladder and a reference potential; further comprising coupling an AC-coupled gate module to at least one end of the gate bias resistor ladder and configuring the AC-coupled gate module to be coupled to an RF voltage source; wherein the AC-coupled gate module comprises one of a capacitor or a capacitor coupled in series to a resistor; further comprising providing a body charge control resistor ladder comprising a plurality of resistors coupled in series to a resistor; coupled or parallel coupled resistors, the body charge controlled resistor ladder is configured to be coupled to a body bias voltage, wherein each resistor is coupled to the body of at least one corresponding FET; also includes a capacitor coupled between the body charge controlled resistor ladder and a reference potential; also includes coupling an AC coupling body module to at least one end of the body charge controlled resistor ladder, the AC coupling body module is configured to be coupled to an RF voltage source; wherein the AC coupling body module includes a capacitor or one of a capacitor coupled in series to the resistor; also includes providing a drain-source resistor ladder, the drain-source resistor ladder including a plurality of resistors coupled in series, the drain-source resistor ladder is configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drain and source of a corresponding adjacent positive logic FET; also includes coupling a negative gate bias voltage supply to the gate of the end cap FET; and wherein at least one FET is an ACS FET.

[0121] As another example, Fig.101000 is a process flow diagram illustrating a method for providing a series shunt switch circuit. The method includes: providing a series FET switch stack having an input port configured to be coupled in series with an RF signal line and an output port (step 1002); coupling the shunt FET switch stack to the output port of the series FET switch stack (step 1004); configuring the shunt FET switch stack to be coupled to a reference potential (step 1006); wherein the series FET switch stack and the shunt FET switch stack have at least one end cap FET, the at least one end cap FET being at a V of such end cap FET. GS The series FET switch stack and the shunt FET switch stack include at least one series-coupled positive logic FET, the at least one series-coupled positive logic FET being series-coupled to at least one end cap FET of a type that is energized at V of such end cap FET. GS Turn off at substantially zero volts (step 1010).

[0122] As yet another method example, Fig.11 1100 is a process flow diagram illustrating a method for biasing a FET switch stack. The method includes: providing a plurality of FETs coupled in series (step 1102); providing a gate bias resistor ladder comprising a plurality of resistors, the gate bias resistor ladder being configured to be coupled to a gate bias voltage and to a gate of at least one corresponding FET (step 1104); providing a body charge control resistor ladder comprising a plurality of resistors, the charge control resistor ladder being configured to be coupled to a body bias voltage and to a body of at least one corresponding FET (step 1106); and providing a drain-source resistor ladder comprising a plurality of resistors coupled in series. A gate bias resistor ladder is provided, the drain-source resistor ladder being configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drain and source of at least one corresponding adjacent FET (step 1108); and wherein the resistors in the gate bias resistor ladder are connected in series and the resistors in the body charge control resistor ladder are connected in parallel (step 1110), or alternatively, wherein the resistors in the gate bias resistor ladder are connected in parallel and the resistors in the body charge control resistor ladder are connected in series (step 1112).

[0123] Fig.11 Additional aspects of the method may include one or more of the following: wherein the plurality of series-coupled FETs include one or more series-coupled positive logic FETs, the one or more series-coupled positive logic FETs being serially coupled at at least one end to an end cap FET of a type that is operative at a V GSis substantially zero volts; and further comprising a second end cap FET of the type that is turned off when the V GS The invention relates to a method of controlling a positive logic FET to be turned off when the voltage is substantially zero volts, the second end cap FET being coupled in series to the second end of one or more series coupled positive logic FETs; coupling a capacitor between the gate bias resistor ladder and a reference potential; coupling an AC coupled gate module to at least one end of the gate bias resistor ladder and configuring the AC coupled gate module to be coupled to an RF voltage source; wherein the AC coupled gate module includes one of a capacitor or a capacitor coupled in series to a resistor; further comprising coupling an AC coupled body module to at least one end of a body charge control resistor ladder and configuring the AC coupled gate module to be coupled to an RF voltage source; wherein the AC coupled body module includes one of a capacitor or a capacitor coupled in series to a resistor; coupling a capacitor between the body charge control resistor ladder and a reference potential; configuring the gate bias resistor ladder to be coupled to a bias voltage at a node at a first end of the gate bias resistor ladder; configuring the gate bias resistor ladder to be coupled to a bias voltage at a node between the first end and the second end of the gate bias resistor ladder; wherein at least one FET is an ACS FET; further comprising coupling a parallel-connected gate resistor ladder comprising a plurality of resistors between the gate bias resistor ladder and a gate of a corresponding FET; wherein the plurality of series-coupled FETs comprises at least one series-coupled positive logic FET surrounded by series-coupled end cap FETs of the type having a Vdc of such end cap FETs GS is substantially zero volts; and wherein the plurality of series coupled FETs include: a first end cap FET of the type GS is essentially off at zero volts; the following type of second end cap FET, which is turned off at the V GS being off at substantially zero volts; and one or more series-coupled positive logic FETs, which are coupled in series between the first end cap FET and the second end cap FET.

[0124] As yet another method example, Fig.121200 is a process flow diagram illustrating a method for providing a FET switch stack. The method includes providing a plurality of FETs coupled in series (step 1202); coupling a gate bias resistor ladder to gates of the series coupled FETs (step 1204); coupling an AC coupled gate module to at least one end of the gate bias resistor ladder and configuring the AC coupled gate module to couple to a corresponding RF voltage source (step 1206); optionally, coupling a body charge control resistor ladder to the bodies of the series coupled FETs (step 1208); and, optionally, coupling an AC coupled body module to at least one end of the body charge control resistor ladder and configuring the AC coupled body module to couple to a corresponding RF voltage source (step 1210).

[0125] Fig.12 Additional aspects of the method may include one or more of the following: wherein the plurality of series-coupled FETs include one or more series-coupled positive logic FETs, the one or more series-coupled positive logic FETs being serially coupled at at least one end to an end cap FET of a type that is operative at a V GS is substantially zero volts; and further comprising providing a second end cap FET of the type that is turned off when the V GS wherein the AC coupled gate module comprises one of a capacitor or a capacitor coupled in series to a resistor; wherein the AC coupled body module comprises one of a capacitor or a capacitor coupled in series to a resistor; wherein the gate bias resistor ladder is configured to be coupled to the bias voltage at a node of a first end of the gate bias resistor ladder; wherein the gate bias resistor ladder is configured to be coupled to the bias voltage at a node between the first end and the second end of the gate bias resistor ladder; and wherein at least one FET is an AC coupled gate module. FET.

[0126] As yet another method example, Fig.131300 is a process flow diagram illustrating another method for biasing a FET switch stack. The method includes providing a plurality of FETs coupled in series (step 1302); providing a first gate resistor ladder comprising a plurality of constant value (or optionally, variable value) resistors connected in parallel, each resistor coupled to the gate of a corresponding FET (step 1304); and providing a second gate bias resistor ladder comprising a plurality of variable value resistors connected in series, each of the variable value resistors connected in series coupled to a corresponding constant value resistor in the first gate resistor ladder (step 1306).

[0127] Manufacturing Techniques and Options

[0128] As used in the present disclosure, the term "MOSFET" refers to any field effect transistor (FET) having an insulated gate and including metal or metalloid, insulator, and semiconductor structures. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0129] As should be apparent to those of ordinary skill in the art, various embodiments of the present invention can be implemented to meet a variety of specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice, and various embodiments of the present invention can be implemented in any suitable IC technology (including but not limited to MOSFET structures) or in the form of hybrid or discrete circuits. Integrated circuit implementations can be manufactured using any suitable substrate and process, including but not limited to standard bulk silicon, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, the present invention can be implemented in other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technologies. However, the above-mentioned inventive concept is particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes with similar characteristics. Manufacturing with CMOS processes on SOI or SOS enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., up to and exceeding 50GHz radio frequency). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can usually be kept low (or kept to a minimum and uniform across all cells, allowing them to be compensated for).

[0130] Voltage levels may be adjusted or voltage and / or logic signal polarity may be reversed according to specific specifications and / or implementation techniques (e.g., NMOS, PMOS, or CMOS, and enhancement or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device size, "stacking" components in sequence to withstand larger voltages as described above, and / or using multiple components in parallel to handle larger currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0131] in conclusion

[0132] A number of embodiments of the present invention have been described. It should be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order independent and therefore may be performed in an order different from that described. In addition, some of the above steps may be optional. The various actions described with respect to the methods identified above may be performed in a repetitive, serial, or parallel manner.

[0133] It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims, and that other implementations are within the scope of the claims. (Note that parenthetical labels of claim elements are for convenience in referencing such elements and do not in themselves indicate a particular required order or enumeration of the elements; furthermore, such labels may be reused in dependent claims as references to other elements without being considered to cause a conflicting label sequence).

Claims

1. A FET switch stack circuit, comprising: (a) a plurality of FETs coupled in series, having a first FET configured to be coupled to a radio frequency (RF) signal input; (b) a first gate resistor ladder (805) comprising a plurality of constant value resistors (Rg') connected in parallel, each constant value resistor being coupled at a first end to the gate of a corresponding FET; as well as (c) a second gate bias resistor ladder (802) comprising a plurality of variable value resistors (Rg) connected in series, each variable value resistor being coupled between a second end of a corresponding constant value resistor in the first gate resistor ladder and a gate bias voltage source and having a resistance value gradually decreasing from a higher resistance value to a lower resistance value, wherein the higher resistance value is located near an RF signal input of the first FET.

2. A FET switch stack circuit, comprising: (a) a plurality of FETs coupled in series, having a first FET configured to be coupled to a radio frequency (RF) signal input; (b) a first gate resistor ladder comprising a plurality of variable value resistors connected in parallel, each variable value resistor coupled at a first end to the gate of a corresponding FET; as well as (c) a second gate bias resistor ladder comprising a plurality of variable value resistors connected in series, each of the variable value resistors connected in series is coupled between the second end of a corresponding variable value resistor in the first gate resistor ladder and a gate bias voltage source and has a resistance value gradually decreasing from a higher resistance value to a lower resistance value, wherein the higher resistance value is located near the RF signal input of the first FET.

3. A method of biasing a FET switch stack, comprising: (a) providing a plurality of FETs coupled in series, the plurality of FETs coupled in series having a first FET configured to be coupled to a radio frequency (RF) signal input; (b) providing a first gate resistor ladder, the first gate resistor ladder comprising a plurality of constant value resistors connected in parallel, each constant value resistor coupled at a first end to the gate of a corresponding FET; as well as (c) providing a second gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of variable value resistors connected in series, each variable value resistor being coupled between the second end of a corresponding constant value resistor in the first gate resistor ladder and a gate bias voltage source and having a resistance value gradually decreasing from a higher resistance value to a lower resistance value, wherein the higher resistance value is located near the RF signal input of the first FET.

4. A method of biasing a FET switch stack, comprising: (a) providing a plurality of FETs coupled in series, the plurality of FETs coupled in series having a first FET configured to be coupled to a radio frequency (RF) signal input; (b) providing a first gate resistor ladder, the first gate resistor ladder comprising a plurality of variable value resistors connected in parallel, each of the variable value resistors connected in parallel being coupled at a first end to the gate of a corresponding FET; as well as (c) providing a second gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of variable value resistors connected in series, each of the variable value resistors connected in series is coupled between the second end of a corresponding variable value resistor in the first gate resistor ladder and a gate bias voltage source and has a resistance value that gradually decreases from a higher resistance value to a lower resistance value, wherein the higher resistance value is located near the RF signal input of the first FET.

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