Micro-electromechanical system and method for manufacturing the same

Abstract

Some aspects of the present invention provide a micro-electromechanical system, which includes a semiconductor substrate having a first recess. The semiconductor substrate forms a base adjacent to the first recess. A device overlies the base and is bonded to the semiconductor substrate through metal in the first recess. A plurality of second recesses are formed in the surface of the base below the device, wherein the second recesses are smaller than the first recesses. In some teachings, the second recesses are voids. In some teachings, the metal in the first recess includes a eutectic mixture. This structure relates to a method for manufacturing a micro-electromechanical system, wherein a layer providing a mask to etch the first recess is segmented so that the mask providing layer can be easily removed from an area above the base.

Description

Technical Field

[0001] Some teachings of the present invention relate to a micro-electromechanical system and a method for manufacturing the same. Background Art

[0002] In many cases of semiconductor manufacturing, especially the manufacturing of micro-electromechanical systems (MEMS), it is desirable to bond separately manufactured devices to a semiconductor substrate. The range of applications for MEMS is wide. For example, MEMS appear in handheld devices (e.g., accelerometers, gyroscopes, digital compasses), pressure sensors (e.g., collision sensors), microfluidic elements (e.g., valves, pumps), optical switches (e.g., mirrors), and light detection and ranging (LiDAR). Summary of the invention

[0003] Some aspects of the present teachings relate to a micro-electromechanical system, the system including a semiconductor substrate having a first cavity. The semiconductor substrate forms a base adjacent to the first cavity. A device overlies the base and is bonded to the semiconductor substrate by metal in the first cavity. A plurality of second cavities are formed in a surface of the base below the device, wherein the second cavities are smaller than the first cavities.

[0004] Some aspects of the present teachings relate to a micro-electromechanical system. The system includes: a semiconductor substrate and a device, the device being bonded to the semiconductor substrate via a metal bonding structure in a bonding region. The device is contacted above the semiconductor substrate in a support region adjacent to the bonding region. The semiconductor substrate has a base structure in the support region. A first device abuts against an upper surface of the scored base structure.

[0005] Some aspects of the present teachings relate to a method for manufacturing a micro-electromechanical system, the method comprising: forming a dielectric matrix over a semiconductor substrate. A first device structure is contained within the dielectric matrix. The dielectric matrix is ​​patterned to have an opening and a plurality of slits in an area of ​​the dielectric matrix adjacent to the opening. The opening is wider than the slits. The dielectric matrix is ​​used as a mask to etch the semiconductor substrate to form a recess below the opening and a base adjacent to the opening, wherein the base is etched with grooves produced by etching through the slits. The dielectric matrix is ​​then removed from the base by etching. A second device is placed on the semiconductor substrate over the recess and the base, and the second device is bonded to the semiconductor substrate using metal in the recess to produce a structure in which the second device abuts the base. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description read in conjunction with the accompanying drawings. According to standard practice in the industry, the various features are not drawn to scale. In addition, for ease of illustration or emphasis, the size of the various features within the individual drawings may be arbitrarily increased or reduced relative to each other.

[0007] Figure 1 A cross-sectional view of a microelectromechanical system (MEMS) is shown in accordance with some aspects of the present disclosure.

[0008] Figures 2 to 10 Cross-sectional views of various stages during the fabrication process of a MEMS are shown according to some aspects of the present disclosure.

[0009] Fig.11 A flow chart of a method of manufacturing a MEMS device is shown according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0010] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0011] Spatial relative terms such as "beneath", "below", "lower", "above", "upper" may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. In addition to the orientation depicted in the figure, these spatial relative terms are intended to cover different orientations of the device or equipment when in use or operation. The device or equipment can be oriented in addition (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article can therefore be interpreted accordingly. The terms "first", "second", "third", "fourth", etc. are merely general identifiers and can therefore be interchanged in various embodiments. For example, although an element (such as an opening) may be referred to as a "first" element in some embodiments, the element may be referred to as a "second" element in other embodiments.

[0012] The present disclosure relates to a microelectromechanical system (MEMS) comprising: a device attached to a semiconductor substrate using a bonding process (e.g., compression bonding, solid-liquid inter-diffusion bonding (SLiD) etc.). The device and substrate can be configured together in a lock and key arrangement, wherein a recess on the substrate provides the lock and a metal bump on the device provides the key. The device can be placed on a mount formed by a portion of the substrate adjacent to the recess.

[0013] According to some aspects of the present teachings, the base is engraved with closely adjacent openings. When etching the cavity in the substrate, these openings correspond to the openings formed in the layer as a mask. The openings reduce the critical dimensions of the mask providing layer related to the etching process at the positions where the mask providing layer overlies the base. Reducing the critical dimensions of the mask providing layer at those positions enables the mask providing layer to be removed from the base area with a simplified etching process. Simplifying the etching process for removing the mask providing layer from the base can avoid incidental damage to other structures during the removal process.

[0014] As used in the present disclosure, the critical dimension associated with an etching process characterizes the approximation of the time it takes to remove a structure by etching, and this time taken is proportional to the maximum depth of any part of the structure from the nearest exposed surface. The critical dimension of a cube will be one-half the length of the side. The critical dimension of a sphere will be its radius. The critical dimension of a solid film with only one side exposed will be the thickness of the film. The critical dimension of a solid film can be reduced by patterning the film into a pattern with a critical dimension that is smaller than the film thickness. For example, if the film is segmented into periodically spaced trenches with a trench-to-trench spacing that is smaller than the film thickness, the critical dimension is reduced to one-half the trench-to-trench spacing.

[0015] Some aspects of the present teachings relate to a method of bonding a second device to a substrate on which a first device is formed. In some teachings, the first device is formed in a dielectric matrix on the substrate. The dielectric matrix can be an oxide. The process includes: forming a mask above the dielectric matrix, wherein the mask includes an opening for forming a cavity and a plurality of smaller openings in a base area adjacent to the cavity opening. The mask is used to etch a corresponding pattern in the dielectric matrix. Subsequently, the patterned dielectric matrix is ​​etched through to form the cavity in the substrate. The smaller opening can produce a base with a notched surface, and the base is adjacent to the cavity. After the cavity is formed, the dielectric matrix is ​​removed from the base area. The smaller opening reduces the time required for the following stage: the stage of processing by reducing the critical dimension of the portion of the dielectric matrix to be removed. The reduction in processing time is related to the reduction in lateral etching of the dielectric matrix adjacent to the base area, which can improve the function of the resulting device. In some embodiments, the first device is a waveguide that extends from the dielectric matrix to the opening in the dielectric matrix formed above the base area. Reducing lateral etching may reduce overhang of the waveguide within the opening, which in turn may facilitate maintaining proper orientation of the waveguide.

[0016] The second device may be bonded to the substrate after the dielectric matrix is ​​removed from the base area. In some teachings, the second device includes a metal bump that is inserted into the cavity when the second device is placed on the substrate. In some teachings, the metal is diffused or flowed when the second device is pressed against the substrate. Before completing the bonding process, the second device will be against the base, so that the second device is vertically aligned with the first device by the base height. In some teachings, the second device is a laser device, the first device is a waveguide, and the vertical positioning aligns the laser device with the waveguide. In the resulting structure, the second device is bonded to the substrate by a metal bonding structure contained in the cavity. In some teachings, the bonding process includes SLiD bonding.

[0017] Figure 1 A MEMS 100 is shown in accordance with some aspects of the present teachings. MEMS 100 includes a substrate 115. A dielectric matrix 119 is formed over substrate 115. A waveguide 117 or other device may be formed within dielectric matrix 119. A second device (device 109) is bonded to semiconductor substrate 115 within opening 101 in dielectric matrix 119. Device 109 is bonded to substrate 115 by a metal bonding structure 107 within cavity 105, which has been formed in substrate 115 within bonding region 123. In some teachings, device 109 is a laser device. In some teachings, metal bonding structure 107 includes a eutectic mixture of two metals.

[0018] Device 109 rests against base 103 within support region 125 of substrate 115 adjacent to engagement region 123. Base 103 is the region of substrate 115 adjacent to recess 105. With device 109 placed on base 103, output device 111 of device 109 is aligned with waveguide 117. Waveguide 117 protrudes a distance 112 from dielectric matrix 119. According to some teachings, distance 112 is less than a thickness 114 of dielectric matrix 119. In some teachings, thickness 114 is in a range of 1 micron to 40 microns. In some teachings, thickness 114 is in a range of 2 microns to 20 microns (e.g., 5 microns). In some teachings, distance 112 is one-half or less than one-half of thickness 114. In some teachings, distance 112 is one-quarter or less than one-quarter of thickness 114. In some teachings, distance 112 is one-tenth or less than one-tenth of thickness 114. Shortening distance 112 will minimize any possibility of the overhanging portion of waveguide 117 sag and affect the alignment of waveguide 117 with output device 111.

[0019] Base 103 is engraved with openings 102. The engraving is periodic, whereby the critical dimension of the pattern reflected in the upper surface of base 103 is approximately one-half of the distance 126 between adjacent openings 102. In some teachings, distance 126 is in the range of 0.1 microns to 10 microns.

[0020] Recess 105 has dimensions suitable for accommodating metal bonding structure 107 that bonds device 109 to substrate 115. In some teachings, recess 105 has a width 108 in a range of 10 microns to 2000 microns. In some teachings, recess 105 has a depth 110 in a range of 0.5 microns to 20 microns. Opening 102 may have a depth 128 that is less than depth 110. In some teachings, depth 128 is 75% or less than 75% of depth 110. Opening 102 has a width 124 that is much smaller than width 108 of recess 105. In some teachings, width 124 is in a range of 0.1 microns to 10 microns. Base 103 has a width 122 suitable for supporting device 109. Base 103 may have additional width so that base 103 may have some flexibility to support portions of device 109 on either side of recess 105 when device 109 is positioned over recess 105. In some teachings, base 103 has width 122 in a range of 5 microns to 2000 microns. In some teachings, base 103 has width 122 in a range of 10 microns to 200 microns, such as 50 microns.

[0021] A hard mask 121 may be present over the dielectric substrate 119. The hard mask 121 may protect the dielectric substrate 119 and the devices within the dielectric substrate 119 during the process of forming the cavity 105 and the base 103. The devices formed within the dielectric substrate 119 may include a waveguide 117. In some teachings, the waveguide 117 is silicon nitride (SiN). In some teachings, a heater that can be operated to change the refractive index within the waveguide 117 is formed with the dielectric substrate 119. This heater can be used for phase tuning or phase scanning. The dielectric substrate 119 may also include devices such as an optical delection device, a diffraction grating, a beam transmitter, a phase tuner, an optical phased array, a photodetector, etc. Although MEMS 100 can be any type of MEMS device, in some teachings, MEMS 100 is a light detection and ranging system (LiDAR) or a time-of-flight (TOF) depth camera. In some teachings, MEMS 100 is a wireless communication device. In some teachings, MEMS 100 includes an optical switch. In some teachings, MEMS 100 includes circuits for processing data generated by a light detector.

[0022] In some teachings, substrate 115 is a bulk silicon substrate. Substrate 115 may also be a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), a more complex semiconductor substrate, or even a sapphire substrate. In some teachings, substrate 115 is a semiconductor-on-insulator (SOI) substrate (e.g., a silicon-on-insulator substrate).

[0023] Device 109 can be any type of device that can be suitably bonded to substrate 115. In some teachings, device 109 is a device that is vertically aligned relative to other devices on substrate 115 to enhance the functionality of MEMS 100. In some teachings, device 109 includes a semiconductor substrate. In some teachings, device 109 is a laser device. In some teachings, device 109 is a laser diode.

[0024] In some teachings, the metal bonding structure 107 includes one or more of copper (Cu), tin (Sn), gold (Au), indium (In), titanium (Ti), alloys thereof, combinations thereof, and the like. In some teachings, the metal bonding structure 107 includes two or more of the foregoing substances. For example, the metal bonding structure 107 may include CuSn, AuSn, or Au11n. In some teachings, the metal bonding structure 107 includes a CuSn-Cu bond, a CuSn-CuSn bond, an AuSn-Au bond, an Au11n-Au bond, and the like. In some teachings, the metal bonding structure 107 includes one or more materials having a melting point temperature of 300° C. or less. The low melting point enables a lower temperature bonding process.

[0025] Figures 2 to 10 A series of cross-sectional views (cross-sectional view 200 to cross-sectional view 1000) at various stages of fabrication of a MEMS device are shown according to some aspects of the present disclosure. Although described with reference to a series of actions, Figures 2 to 10 , but it should be understood that the order of these actions may be changed in certain situations, and this series of actions may be applicable to structures other than the structure shown. In some embodiments, some of these actions may be omitted in whole or in part. In addition, it should be understood that Figures 2 to 10 The structures shown are not limited to the manufacturing method, but can stand alone as structures independent of the method.

[0026] like Figure 2 As shown in cross-sectional view 200 of FIG. 1 , a process according to the present disclosure may begin with a substrate 115 over which a waveguide 117 or other device has been formed within a dielectric matrix 119. In some embodiments, the substrate 115 is in wafer form at this stage of processing and is not singulated prior to being bonded to the device 109. When in wafer form, the substrate 115 may have a diameter of, for example, 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm); or 125 mm (4.9 inches); 150 mm (5.9 inches, often referred to as "6 inches"); 200 mm (7.9 inches, often referred to as "8 inches"); 300 mm (11.8 inches, often referred to as "12 inches"); or 450 mm (17.7 inches, often referred to as "18 inches").

[0027] The dielectric matrix 119 may include one or more layers of different dielectrics. In some teachings, the dielectric matrix 119 includes an oxide, such as silicon dioxide. The dielectric matrix 119 may be a low dielectric constant (low κ) dielectric. As used herein, a low κ dielectric is a dielectric material having a dielectric constant κ of less than about 3.9. The dielectric 119 may be an extremely low K dielectric, which may be a low κ dielectric with pores that reduce the overall dielectric constant. In addition to or in lieu of the waveguide 117, the dielectric matrix 119 may include any number of devices of any suitable type. In some teachings, a back-end-of-line (BEOL) metal interconnect structure is formed within the dielectric matrix 119.

[0028] like Figure 3 , a hard mask 121 may be formed and patterned over the dielectric substrate 119. The hard mask 121 may be formed of any suitable material. A suitable material may be SiN. The hard mask 121 may be patterned by photolithography or any other method so that the hard mask 121 includes an opening 301 that defines a device attachment area. The opening 301 may have a width in a range of 100 microns to 10,000 microns. The opening 301 may be positioned to have an edge 303 at or slightly beyond a position 302 aligned with the outer edge of the waveguide 117.

[0029] like Figure 4 As shown in cross-sectional view 400, a mask layer 401 is formed over dielectric substrate 119 and hard mask 121. Mask layer 401 may be a photoresist or another type of mask that may be patterned using a photoresist.

[0030] like Figure 5 As shown in the cross-sectional view 500 of FIG. 4 , the mask layer 401 is patterned to have a cavity opening 501 and a segmented opening 503. The cavity opening 501 has a width in the range of 10 microns to 2000 microns. The segmented openings 503 are formed in the base area 505 on either side of the cavity opening 501. The base area 505 may have a width in the range of 5 microns to 2000 microns. The segmented openings 503 may have a width in the range of 0.1 microns to 10 microns. The segmented openings 503 may be in the form of grooves or other shapes. The segmented openings 503 may be distributed throughout the base area 505 to pattern the mask layer 401 in the base area 505, thereby obtaining a critical dimension in the range of 0.05 microns to 5 microns.

[0031] like Figure 6As shown in the cross-sectional view 600 of , etching is performed to transfer the pattern of the mask layer 401 into the dielectric matrix 119. In some teachings, the etching process is an anisotropic etching process. In some teachings, the etching process used for this pattern transfer is a dry etching process, such as plasma etching. Etching chemicals (etch chemistry) can be used to selectively remove oxides while leaving nitrides. In some teachings, the etching process is a process for self-aligned contact oxide etching. The etching process can expose the ends of the waveguide 117. The mask 401 can be stripped after this etching process. The mask 401 can be stripped by ashing or any other suitable process.

[0032] like Figure 7 As shown in the cross-sectional view 700 of , another etching process is performed in which the dielectric matrix 119 acts as a mask to etch the substrate 115. In some teachings, the etching process for etching the substrate 115 is a dry etching process. In some teachings, the etching process is an anisotropic etching process. The etching chemistry can be used to selectively remove silicon while leaving oxides and nitrides. This etching process creates a cavity 105 in the substrate 115 and creates an opening 102 in the base area (base 103) on the side of the cavity 105. Due to the smaller aspect ratio of the opening in the base area 103, the opening 102 has a depth 128 that is less than the depth 110 of the cavity 105. The etching process may include plasma etching using a fluorine chemistry. The plasma may be generated using carbon tetrafluoride (CF4), chloroform (CHF3), difluoromethane (e.g., CH2F2), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), hexafluoropropylene (C3F6), octafluorocyclobutane (C4F8), octafluorocyclopentane (C5F8), another suitable fluorine compound(s), any combination of the foregoing, and the like. Argon, oxygen, and other suitable gases may also be included in the etching chemistry. In some teachings, the etching process is a plasma etching process for forming a high aspect ratio, such as a Bosch etching process. The Bosch etching process is a cyclic process comprising alternating steps of etching the substrate 115 with sulfur hexafluoride (SF6) or the like and generating a protective layer on the dielectric substrate 119 for providing a mask with octafluorocyclobutane (C4F8) or the like.

[0033] like Figure 8 As shown in the cross-sectional view 800 of FIG. 1 , an etching process is performed to remove the dielectric matrix 119 from the area above the base 103. This etching increases the size of the opening 101 and the distance 112 that the waveguide 117 overhangs the opening 101. The increase in distance 112 may be limited to the critical dimension of the dielectric matrix 119 within the opening 101, which may be limited to one-half of the spacing between the openings 102 (see FIG. 1 ). Figure 7). In some teachings, the etching process is an isotropic etching process. In some teachings, the etching process is a wet etching process. In some teachings, the wet etching process includes etching with hydrofluoric acid (HF).

[0034] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , the bonding process may begin by introducing metal 901 into the cavity 105. The metal 901 may be all or part of the metal bonding structure 107 used to bond the device 109 to the substrate 115 (see FIG. 1 ). Figure 1 ). In some teachings, metal 901 is a seed layer. In some teachings, metal 901 is copper (Cu). Depositing metal 901 may include one or more of physical vapor deposition, chemical vapor deposition, electroplating, or any other suitable process. Other metals that may be deposited into recess 105 include, but are not limited to, tin (Sn), gold (Au), indium (In), titanium (Ti), alloys thereof, and the like.

[0035] like Fig.10 1000, the device 109 is then placed over the cavity 105. In some teachings, a metal bump 1001 is formed on the device 109 before the device 109 is placed over the cavity 105. In some teachings, the metal bump 1001 fits within the cavity 105 and helps to properly position the device 109 on the substrate 115. In some teachings, the metal bump 1001 includes forming a metal bonding structure 107 (see Figure 1 ) except for metal 901 introduced into cavity 105 before device 109 is placed over cavity 105. Device 109 may be part of a wafer, wafer chip, or another device structure that is subsequently singulated during the processing stage. Device 109 may be placed on base 103, but in some teachings, metal bumps 1001 prevent device 109 from being placed on base 103 prior to the bonding process.

[0036] Figure 1 Shows the application of the bonding process to Fig.10 The result is a structure shown in the cross-sectional view 1000 of FIG. The bonding process may cause the metal 901 and the metal bump 1001 to combine by flowing, mixing and / or inter-diffusing. Figure 1, at the end of the bonding process, the device 109 is against the base 103, resulting in a desired vertical alignment of the device 109. The bonding process may include pressing the device 109 against the substrate 115. Examples of suitable processes for such bonding include compression bonding, solid liquid diffusion bonding (SLiD), etc. The bonding process may include heating. In some teachings, heating includes heating at a temperature above the eutectic point of the two metals used to form some portions of the metal bonding structure 107. In some teachings, the temperature is limited to be below the melting point of one of the metals forming the eutectic mixture.

[0037] Fig.11 A flow chart of a process 1100 according to some aspects of the present disclosure is provided, which process can be used to manufacture a MEMS device according to the present disclosure. Although process 1100 is shown and described as a series of actions or events in this article, it should be understood that the shown ordering of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described in this article, some actions may occur in different orders and / or at the same time as other actions or events. In addition, not all of the shown actions may be required to implement one or more aspects or embodiments described in this article. In addition, one or more of the actions depicted in this article can be performed in one or more separate actions and / or stages.

[0038] Process 1100 begins with action 1101, where a dielectric layer having an embedded device is formed on a substrate 115 to produce a structure, such as Figure 2 1101 may include front-end-of-line (FEOL) processing and BEOL processing. FEOL processing may include doping regions in or on substrate 115 and forming transistors and similar devices. BEOL processing may include forming multi-level metal interconnect structures within dielectric matrix 119. The embedded device may include waveguide 117.

[0039] The process 1100 continues with act 1103: forming a hard mask 121 and patterning the hard mask (eg, Figure 3 The hard mask 121 limits the opening 101 in the dielectric substrate 119 to the area open to attach the device 109. The hard mask 121 is selectively provided in the process according to the present disclosure. Figure 5 and Figure 6As shown in FIG. 1 , mask 401 can protect areas outside of opening 101 of dielectric substrate 119 during segmentation of dielectric substrate 119 over pedestal 103. Segmentation of dielectric substrate 119 over pedestal 103 allows portions of dielectric substrate 119 to be removed using an etching process that is too short in duration to etch through dielectric substrate 119. Figure 7 and Figure 8 If the hard mask 121 is not present, segmented portions of the dielectric matrix 119 may be removed while only removing a thinner layer from the top of the dielectric matrix 119 at other locations above the substrate 115 .

[0040] Process 1100 continues with act 1105: forming Figure 4 and action 1107: the mask 401 is patterned to have an opening 501 for forming a cavity 105 and an opening 503 for segmenting the dielectric substrate 119 above the base 103 (eg Figure 5 ). Mask 401 may be a photoresist mask and mask 401 may be patterned using photolithography or any other method.

[0041] Process 1100 continues with act 1107: using mask 401 to pattern dielectric substrate 119 (eg, Figure 6 600 of the cross-sectional view of FIG. 600). The patterning may be an etching process. The etching process may be an anisotropic dry etching process, such as anisotropic plasma etching. This patterning forms openings at the desired locations of the recesses 105 of the dielectric matrix 119 and may segment the dielectric matrix 119 above the desired locations of the base 103. The mask 401 may be stripped at the end of this step.

[0042] The process 1100 continues with act 1109 by etching the substrate 115 (eg, Figure 7 The etching process may be an anisotropic dry etching process, such as anisotropic plasma etching. The etching forms a notched base region 103 in the cavity 105 using the opening 102.

[0043] The process 1100 continues with act 1109 by etching to remove the segmented portion of the dielectric matrix 119 from the base 103 (eg, Figure 8 800 of the cross-sectional view of FIG. 1 ). The etching process can be an isotropic wet etching process. The previous processing of the segmented dielectric substrate 11 significantly speeds up this etching process. In some embodiments, this etching process exposes the waveguide 117. If the waveguide 117 is exposed, then this etching can increase the extent to which the waveguide 117 overhangs the opening 101. In some teachings, this etching is completed in one hour or less.

[0044] Process 1100 continues with a series of acts 1113, 1115, 1117, and 1119 by which device 109 is placed on base 103 and bonded to substrate 115 via metal bonding structure 107 in cavity 105. Different acts in different orders may provide the same function. In some teachings, these acts provide a lock-and-key process, where a portion of metal bonding structure 107 attached to device 109 provides the key and cavity 105 provides the lock. In some teachings, a portion of metal bonding structure 107 is introduced into cavity 105 before device 109 is placed over substrate 115. Act 1113 provides an example. Act 1113 is to form a seed layer (e.g., a layer of metal 901) in cavity 105. Fig. 9 The seed layer (metal 901) may be copper (Cu) or any other metal. The seed layer (metal 901) may be formed by sputtering or any other suitable process. A portion of the metal bonding structure 107 may also be provided by a metal bump 1001 formed on the device 109 before placing the device 109 on the substrate 115. Action 1117 is to place the device 109 and the metal bump 1001 on the substrate 115 (e.g., Fig.10 Between the metal bump 1001 and the seed layer (metal 901 ), all metal bonding structures 107 for bonding the device 109 to the substrate 115 may be introduced into the cavity 105 by the end of action 1117 .

[0045] Action 1119 is to apply heat and pressure while placing the device 109 on the base 103 to soften, mix and diffuse the metal bump 1001 and the seed layer (metal 901) to form a metal bonding structure 107, thereby manufacturing the device 109 on the base 103. Figure 1 The device 100 shown is similar to the product. In some teachings, this bonding process is a low temperature thermal compression bonding process. The low temperature is 300°C or below 300°C. Any suitable process can be used. In some teachings, action 119 includes metal diffusion bonding. Metal diffusion bonding can include similar metals, examples include aluminum gold (Al-Au), copper (Cu-Cu), etc. In some teachings, the process used includes eutectic bonding. Eutectic bonding can be produced between copper and tin (Cu-Sn), gold and tin (Au-Sn), tin and lead (Sn-Pd), etc. Alloys and three metal layer structures of these metals can also be used. The resulting metal bonding structure 107 may include different layers with different compositions, and the layers include at least one layer of eutectic mixture and at least another layer of pure metal or a mixture with a mixing ratio different from the eutectic mixture.

[0046] Some aspects of the present teachings relate to a micro-electromechanical system, the system including a semiconductor substrate having a first recess. The semiconductor substrate forms a base adjacent to the first recess. A device overlies the base and is bonded to the semiconductor substrate by metal within the first recess. A plurality of second recesses are formed in a surface of the base below the device, wherein the second recesses are smaller than the first recesses. In some teachings, the second recesses are voids. In some teachings, the metal in the first recess comprises a eutectic mixture. This structure relates to a method of manufacturing a micro-electromechanical system, wherein a layer providing a mask to etch the first recess is segmented so that the mask providing layer can be easily removed from an area above the base.

[0047] Some aspects of the present teachings relate to a micro-electromechanical system. The system includes: a semiconductor substrate and a device, the device being bonded to the semiconductor substrate via a metal bonding structure in a bonding area. The device contacts above the semiconductor substrate in a support area adjacent to the bonding area. The semiconductor substrate has a base structure in the support area. A first device abuts against an upper surface of the scored base structure. In some teachings, the metal bonding structure is formed in a recess in the semiconductor structure, the recess having a width, and the upper surface of the base structure is engraved with a groove having a width less than the width of the recess. In some teachings, the recess has a depth, and the groove has a depth less than the depth of the recess.

[0048] In some teachings, the metal bonding structure is below the height of the upper surface of the base structure. In some teachings, the upper surface of the base structure is aligned with the top of the metal bonding structure. In some teachings, the metal bonding structure is a product of solid-liquid diffusion bonding. In some teachings, the second device is formed in or on the semiconductor substrate, and the function of the micro-electromechanical system depends on the vertical alignment between the first device and the second device. In some teachings, the waveguide is formed in a dielectric matrix formed above the semiconductor substrate, and the first device is a laser device. In some teachings, the dielectric matrix has a thickness, the waveguide extends from the dielectric matrix into an opening in the dielectric matrix, the laser device is located in the opening, and the waveguide extends into the opening at a distance less than the thickness of the dielectric matrix.

[0049] Some aspects of the present teachings relate to a method for manufacturing a micro-electromechanical system, the method comprising: forming a dielectric matrix over a semiconductor substrate. A first device structure is contained within the dielectric matrix. The dielectric matrix is ​​patterned to have an opening and a plurality of slits in an area of ​​the dielectric matrix adjacent to the opening. The opening is wider than the slits. The dielectric matrix is ​​used as a mask to etch the semiconductor substrate to form a recess below the opening and a base adjacent to the opening, wherein the base is etched with grooves produced by etching through the slits. The dielectric matrix is ​​then removed from the base by etching. A second device is placed on the semiconductor substrate over the recess and the base, and the second device is bonded to the semiconductor substrate using metal in the recess to produce a structure in which the second device abuts the base.

[0050] In some teachings, the method includes: pressing the second device and the semiconductor substrate together during the bonding process at least until after the second device abuts the base. In some teachings, the gap reduces the critical dimension of the dielectric substrate above the base to less than the thickness of the dielectric substrate. In some teachings, the method includes: forming a metal bump on the second device, and bonding the second device to the semiconductor substrate includes: using metal from the metal bump for bonding. In some teachings, bonding the second device to the semiconductor substrate includes solid-liquid inter-diffusion al bonding. In some teachings, the gap reduces the time required for etching to be completed to remove the dielectric substrate from the base. In some teachings, the gap is periodically formed on the dielectric substrate above the base at a spacing less than the thickness of the dielectric substrate. In some of these teachings, the dielectric substrate is an oxide.

[0051] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other methods and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A micro-electromechanical system, comprising: A semiconductor substrate having a first cavity; a base formed by the semiconductor substrate in a region adjacent to the first cavity; a device overlying the base and bonded to the semiconductor substrate through metal in the first cavity; as well as A plurality of second recesses are formed in the upper surface of the base below the device, wherein the depth and width of the second recesses are smaller than the depth and width of the first recesses, wherein the device abuts against the upper surface of the base. The micro-electromechanical system according to claim 1 , wherein the second cavity is a void. 3 . The micro-electromechanical system of claim 1 , wherein the metal in the first cavity comprises a eutectic mixture. The micro-electromechanical system according to claim 1 , wherein the second recess is shallower than the first recess. 5 . The micro-electromechanical system of claim 1 , wherein the second recesses are periodically spaced apart from each other throughout the surface of the base.

6. A micro-electromechanical system, comprising: A semiconductor substrate having a cavity; a first device bonded to the semiconductor substrate via a metal bonding structure in a bonding region and within the cavity, wherein the first device contacts over the semiconductor substrate in a support region adjacent to the bonding region; The semiconductor substrate has a base structure in the support region, and a groove is engraved on the upper surface of the base structure; as well as The first device abuts against the upper surface of the base structure.

7. The micro-electromechanical system according to claim 6, wherein: The recess has a width; and The groove has a width that is smaller than the width of the recess.

8. The micro-electromechanical system according to claim 7, wherein: The recess has a depth; and The groove has a depth that is less than the depth of the recess. 9 . The micro-electromechanical system of claim 6 , wherein the metal bonding structure is lower than the height of the upper surface of the base structure.

10. The micro-electromechanical system according to claim 6, wherein the metal bonding structure is a product of solid-liquid diffusion bonding.

11. The micro-electromechanical system according to claim 6, further comprising: a second device formed in or on the semiconductor substrate, wherein functionality of the micro-electromechanical system depends on vertical alignment between the first device and the second device.

12. The micro-electromechanical system according to claim 6, further comprising: a waveguide in a dielectric matrix formed above the semiconductor substrate; Wherein the first device is a laser device.

13. The micro-electromechanical system according to claim 12, wherein: The dielectric matrix has a thickness; The waveguide extends from the dielectric substrate into an opening in the dielectric substrate, and the laser device is located in the opening; as well as The waveguide protrudes into the opening by a distance that is less than the thickness of the dielectric substrate.

14. The micro-electromechanical system of claim 6, wherein the upper surface of the base structure is aligned with a top of the metal bonding structure.

15. A method for manufacturing a micro-electromechanical system, comprising: forming a dielectric matrix over a semiconductor substrate, wherein a first device structure is housed within the dielectric matrix; patterning the dielectric substrate to have an opening and a plurality of slits in a region of the dielectric substrate adjacent to the opening, wherein the opening is wider than the slits; etching the semiconductor substrate through the dielectric matrix to form a recess below the opening and a pedestal adjacent to the opening, wherein the pedestal is etched with a trench produced by etching through the gap; etching to remove the dielectric matrix from the base; placing a second device on the semiconductor substrate above the cavity and the base; as well as The second device is bonded to the semiconductor substrate using the metal in the cavity so that the second device rests against an upper surface of the base.

16. The method for manufacturing a micro-electromechanical system according to claim 15, wherein: Also includes: The second device and the semiconductor substrate are pressed together during the bonding process at least until after the second device abuts against the base. 17 . The method for manufacturing a micro-electromechanical system according to claim 15 , wherein the gap reduces a critical dimension of the dielectric substrate above the base to be smaller than a thickness of the dielectric substrate.

18. The method for manufacturing a micro-electromechanical system according to claim 15, further comprising: forming a metal bump on the second device; Wherein bonding the second device to the semiconductor substrate comprises: using metal from the metal bump for bonding. 19 . The method for manufacturing a micro-electromechanical system according to claim 15 , wherein bonding the second device to the semiconductor substrate comprises solid-liquid diffusion bonding. 20 . The method for manufacturing a micro-electromechanical system according to claim 15 , wherein the gap reduces the time required for the etching to remove the dielectric substrate from the completed base. 21 . The method for manufacturing a micro-electromechanical system according to claim 15 , wherein the slits are periodically formed on the dielectric substrate above the base at a pitch smaller than a thickness of the dielectric substrate.

22. The method for manufacturing a micro-electromechanical system according to claim 15, wherein the dielectric matrix is ​​an oxide.

23. A micro-electromechanical system, comprising: A semiconductor substrate including a cavity and one or more pedestals adjacent to the cavity; as well as device, bonded to the semiconductor substrate by metal in the cavity and supported by the one or more pedestals, The one or more bases are engraved with a plurality of grooves, wherein the device rests against an upper surface of the one or more bases.

24. The microelectromechanical system of claim 23, wherein the grooves have a periodic spacing throughout each of the one or more mounts.

25. The micro-electromechanical system according to claim 23, wherein: The recess is formed below the one or more pedestals of the semiconductor substrate. The micro-electromechanical system according to claim 25 , wherein a depth of the trench is smaller than a depth of the cavity.

27. The micro-electromechanical system according to claim 23, further comprising: A waveguide is formed in a dielectric substrate, wherein the waveguide extends from the dielectric substrate.

28. The microelectromechanical system of claim 27, wherein the waveguide extends toward the device.

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