Stream address generation

Abstract

The present application is entitled "Stream Address Generation". A digital signal processor (300) has at least one stream address generator (380, 381, 382, 383), each having dedicated hardware for generating addresses for writing multi-dimensional stream data comprising a plurality of elements. Each of the at least one stream address generator (380, 381, 382, 383) is configured to generate a plurality of offsets for addressing the stream data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. An address for each of the plurality of elements is a respective one of the plurality of offsets combined with a base address.

Description

BACKGROUND

[0001] Modern digital signal processors (DSPs) face multiple challenges. Workloads continue to increase, requiring increased bandwidth. System on a chip (SOC) sizes and complexity continue to grow. Memory system latency severely impacts certain classes of algorithms. As transistors get smaller, memory and register reliability decreases. As software stacks get larger, the number of potential interactions and bugs also grows. Even conductive traces on circuit boards and conductive paths on semiconductor dies become increasingly challenging. Wide buses are difficult to route. Signal propagation through conductors continues to lag behind transistor speed. Routing congestion is a persistent challenge.

[0002] In many DSP algorithms, such as sorting, fast Fourier transforms (FFTs), video compression, and computer vision, data is processed in blocks. Thus, the ability to generate read and write access patterns in multiple dimensions helps to accelerate these algorithms. However, multi-dimensional address computation is complex and often requires several instructions and execution units to perform. SUMMARY

[0003] One example implementation described herein includes a digital signal processor. The digital signal processor includes a stream address generator having specialized hardware configured to generate a plurality of offsets to address stream data including a plurality of elements. Each of the plurality of offsets corresponds to a respective one of the plurality of elements. An address for each of the plurality of elements is a respective one of the plurality of offsets combined with a base address. Another example implementation described herein includes a digital signal processor system. The digital signal processor system includes a buffer and a digital signal processor. The digital signal processor includes a central processing unit (CPU). The CPU includes a stream address generator having specialized hardware configured to generate a plurality of offsets to address stream data for writing to the buffer or reading from the buffer. The stream data includes a plurality of elements, and each of the plurality of offsets corresponds to a respective one of the plurality of elements.

[0004] Another example implementation described herein includes a method of operating a digital signal processor system configured for addressing stream data having a plurality of elements. The method includes receiving and processing the stream data using a first set of execution units. The method further includes generating a plurality of offsets corresponding to the plurality of elements by using execution units that are not available for the steps of processing the stream data. The method further includes determining an address by combining each of the plurality of offsets with a base address. BRIEF DESCRIPTION OF DRAWINGS

[0005] To describe various examples in greater detail, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 A single-core DSP is shown;

[0007] Figure 2 More details of the single-core DSP are shown; Figure 1

[0008] Figure 3 A DSP with a stream address generator is shown;

[0009] Figure 4 Example logic used by the stream address generator is shown;

[0010] Figure 5 An example 4-dimensional memory pattern is shown;

[0011] Figure 6 An example stream address configuration register is shown;

[0012] Figure 7 Example subfield definitions for the flags field of the stream address configuration register are shown; Figure 7

[0013] An example stream address count register is shown; Figure 8

[0014] An example hardware implementation of the stream address generator and related circuitry is shown; and Figure 9

[0015] An example hardware implementation of the stream address logic is shown. Figure 10A DETAILED DESCRIPTION Figure 10B The expression "based on" means "based, at least in part, on." Thus, if X is based on Y, X can be a function of Y and any number of other factors.

[0016] DSPs typically have 64-bit buses. Recently, some DSPs have 512-bit buses, such as the Texas Instruments C7x family of DSPs. An example 512-bit DSP is the C6713.

[0017] Figure 1 ​​​A single-core DSP 100 is shown and described in detail in U.S. Patent No. 9,606,803, which is incorporated herein by reference in its entirety. DSP 100 includes a vector CPU 110 coupled to a separate level 1 instruction cache (L1I) 111 and a level 1 data cache (L1D) 112. The DSP further includes a level 2 cache (L2) 114, which may be a random access memory (RAM). Vector CPU 110, level 1 instruction cache (L1I) 111, level 1 data cache (L1D) 112, and a level 2 combined instruction / data cache (L2) 114 may be formed on a single integrated circuit.

[0018] The single integrated circuit may also include auxiliary circuits such as power control circuitry 121, emulation / trace circuitry 122, design-for-test (DFT) programmable built-in self-test (PBIST) circuitry 123, and clock circuitry 124. External to CPU 110 and possibly integrated into single integrated circuit 100 is a memory controller 131.

[0019] Figure 2 1 shows a block diagram of at least a portion of a DSP 100 having a vector CPU 110. Figure 2 As shown, vector CPU 110 includes an instruction fetch unit 141, an instruction dispatch unit 142, an instruction decode unit 143, and a control register 144. Vector CPU 110 further includes a 64-bit register file 150 and a 64-bit functional unit 151 for receiving and processing 64-bit scalar data from the first level data cache (L1D) 112. Vector CPU 110 also includes a 512-bit register file 160 and a 512-bit functional unit 161 for receiving and processing 512-bit vector data from the first level data cache (L1D) 112 and / or from the stream engine 113. DSP 100 also includes a second level combined instruction / data cache (L2) 114, which sends and receives data from the first level data cache (L1D) 112 and sends the data to the stream engine 113. Vector CPU 110 may also include a debug unit 171 and an interrupt logic unit 172.

[0020] As described in U.S. Patent No. 9,606,803 (which is incorporated by reference herein in its entirety), a streaming engine such as streaming engine 113 can increase the available bandwidth of a CPU, reduce the number of cache misses, reduce scalar operations, and allow multi-dimensional memory accesses. While vector CPU 110 has a significantly increased bandwidth for consuming data, and can accommodate multi-dimensional memory accesses at least in part due to streaming engine 113, vector CPU 110 lacks a similar increase in bandwidth for writing streaming data from the CPU, resulting in a bottleneck for streaming operations. Furthermore, the number of address calculations required to write streaming data consumes a large number of execution units required for other operations. Indeed, address generation for multi-dimensional data can require one functional unit per dimension, which can be more functional units than the CPU has.

[0021] The examples described below at least partially address at least some of these issues by having specialized hardware that automatically generates streaming addresses as offsets and allows multi-dimensional load or store accesses to be fully pipelined.

[0022] Figure 3 A block diagram showing at least a portion of DSP 300 and its interaction with a level two combined instruction / data cache (L2) 314. As Figure 3 shown, vector CPU 310 includes an instruction fetch unit 341, an instruction dispatch unit 342, an instruction decode unit 343, and control registers 344. Vector CPU 310 further includes a 64-bit register file 350 and 64-bit functional units 351 for receiving and processing 64-bit scalar data from a level one data cache (LID) 312. Vector CPU 310 also includes a 512-bit register file 360 and 512-bit functional units 361 for receiving and processing 512-bit vector data from level one data cache (LID) 312 and / or from streaming engine 313. DSP 300 also includes a level two combined instruction / data cache (L2) 314 that sends and receives data from level one data cache (LID) 312 and sends data to streaming engine 313. Vector CPU 310 can also include a debug unit 371 and interrupt logic unit 372.

[0023] The main difference between DSP 300 Figure 1 and Figure 2 is that CPU 310 of DSP 300 includes streaming address generators SAG0 380, SAG1 381, SAG2 382, SAG3 383. While Figure 3The CPU 310 is shown as having four stream address generators (stream address generators SAG0 380, SAG1 381, SAG2 382, SAG3 383), but the CPU 310 can include one, two, three, or four stream address generators, and in some other examples can include more than four stream address generators. While the address computation logic of the stream engine 313 performs multi-dimensional address computation to provide stream data into the CPU 310, the stream address generators SAG0 380, SAG1 381, SAG2 382, SAG3 383 perform multi-dimensional address computation to serve as offsets for addresses used to store instructions in the CPU 310. Alternatively, one or more of the SAG0 380, SAG1 381, SAG2 382, SAG3 383 can be used instead of or in conjunction with the stream engine 313 to generate addresses for loading instructions.

[0024] The offsets generated by the stream address generators 380, 381, 382, 383 are stored in stream address offset registers SA0 390, SA1 391, SA2 392, and SA3 393, respectively. Each stream address generator SAG0 380, SAG1 381, SAG2 382, SAG3 383 includes a respective stream address control register STRACR0 384, STRACR1 385, STRACR2 386, STRACR3 387 and a respective stream address count register STRACNTR0 394, STRACNTR1 395, STRACNTR2 396, STRACNTR3 397. As explained in more detail below, the stream address control registers STRACR0 384, STRACR1 385, STRACR2 386, STRACR3 387 contain configuration information for the respective stream address generator, and the stream address count registers STRACNTR0 394, STRACNTR1 395, STRACNTR2 396, STRACNTR3 397 store run-time information used by the respective stream address generator.

[0025] When using a stream address generator, a full address is computed, for example, by adding a base value to the offset generated by the stream address generator. The stream address generators SAG0-SAG3 support an address computation mode for forward linear streams, and start from an offset of 0. The addressing examples described herein use a multi-level nested loop to iteratively generate offsets for multi-dimensional data using a small number of parameters. The program accesses these offsets through the stream address offset registers SA0 390, SA1 391, SA2 392, and SA3 393.

[0026] Table 1 lists the parameters for a multi-dimensional stream.

[0027] Table 1

[0028]

[0029] Figure 4 Figure 1 shows the logic used by the stream address generator to calculate the offsets for a 6-stage forward loop. VECLEN specifies the number of elements to fetch each time. The iteration counts ICNT0, ICNT1, ICNT2, ICNT3, ICNT4, and ICNT5 for a loop stage indicate the number of times that stage is repeated. The dimensions DIM0, DIM1, DIM2, DIM3, DIM4, and DIM5 indicate the distance between the pointer positions for successive iterations of the corresponding loop stage.

[0030] exist Figure 4 In the example logic of , the innermost loop 40 (referred to as loop 0) calculates the offset of physically adjacent elements from memory. Because the elements are adjacent and there is no space between them, the dimension of loop 0 is always 1 element, so there is no dimension (DIM) parameter defined for loop 0. The pointer itself moves from one element to another in a continuous increasing order. In each level outside the inner loop (41, 42, 43, 44, 45), the loop moves the pointer to a new position based on the size of the loop level dimension (DIM). The innermost loop 40 also includes logic for vector predication, which is described in detail in a U.S. patent application entitled "System and Method for Predication Handling" (hereinafter referred to as the "Predication Application"), which was filed concurrently with the present application and is incorporated herein by reference.

[0031] Figure 5 An example of a 4-dimensional memory address pattern is shown. Figure 5 In the example, the addressing parameters have the following values:

[0032] ICNT0=8

[0033] ICNT1=4

[0034] ICNT2=3

[0035] ICNT3=3

[0036] DIM1=0x080

[0037] DIM2=0x400

[0038] DIM3=0x230

[0039] like Figure 5As shown, the innermost loop (Loop 0) has ICNT0=8 and is shown as having 8 elements per row. Since the implicit dimension is 1 element, the bytes in each row are adjacent. The next loop (Loop 1) has ICNT1=4 and is shown as 4 groups of loop 0 rows, each separated by DIM1. The next loop (Loop 2) has ICNT2=3 and is shown as three groups of 4 rows from loop 0 and loop 1, each separated by DIM2. The last loop (Loop 3) has ICNT3=3 and is shown as 3 groups in loop 0 to loop 2, each separated by DIM3.

[0040] The CPU 310 exposes the stream address generator to the program through a small number of instructions and dedicated registers.

[0041] The stream open instruction SAOPEN begins a new address generation sequence for the specified stream address generator 380, 381, 382, ​​383. As discussed in more detail in the U.S. patent application entitled "System and Method for Addressing Data in Memory," filed concurrently and incorporated herein by reference, once the SAOPEN instruction is executed, any load or store instruction (discussed below) with the correct addressing mode and offset register field value 0-3 will use the offset value calculated by the corresponding stream address generator SAG0, SAG1, SAG2, SAG3.

[0042] The operand of the SAOPEN instruction is, for example, a register value containing configuration template information and a stream identifier. After executing SAOPEN, the register value is copied to the corresponding stream address control register to be used as an addressing template, and the ICNT field of the corresponding STRCNTR register is initialized.

[0043] The stream close instruction SACLOSE explicitly turns off the specified stream address generation operation for a given stream. Executing SACLOSE resets the corresponding STRACR and STRACNTR registers to their default values. After the stream is closed, the stream address generator cannot be used for addressing.

[0044] The stream break instruction SABRK allows for an early exit from a loop nesting level within a stream. Issuing a stream break instruction SABRK causes the stream address generator to skip all remaining elements of the corresponding number of loop levels. "SABRK 5,SAn" ends the stream without closing it, where "5" represents the exit from loop 5 and "SAn" represents the stream address offset register.

[0045] Stream address control registers STRACR0 384, STRACR1 385, STRACR2 386, STRACR3 387 contain parameters such as element count, loop dimension, access length, and other flags to start the stream address computation.

[0046] Figure 6 An exemplary stream address configuration register is shown. Table 2 shows an example of the field definitions for the stream address configuration register.

[0047] Table 2

[0048]

[0049] The fields in Table 2 are described above. DEC_DIM1_WIDTH and DEC_DIM2_WIDTH help define any vertical strip mining, which is described in more detail in the Predication application. Strip mining is also discussed in the following applications, each of which is incorporated by reference in its entirety: Application No. 16 / 420,480 entitled “Inserting Predefined Pad Values into a Stream of Vectors,” Application No. 16 / 420,467 entitled “Inserting Null Vectors into a Stream of Vectors,” Application No. 16 / 420,457 entitled “Two-Dimensional Zero Padding in a Stream of Matrix Elements,” and Application No. 16 / 420,447 entitled “One-Dimensional Zero Padding in a Stream of Matrix Elements,” each of which was filed on May 23, 2019.

[0050] Figure 7 Subfield definitions for the flags field of the stream address configuration register are shown.

[0051] Stream address count registers STRACNTR0 394, STRACNTR1 395, STRACNTR2 396, STRACNTR3 397 contain the intermediate element counts for all loop levels. When the element count CNT for one loop becomes zero, the next loop dimension is used to compute the address of the element for the next loop. Figure 8 An exemplary stream address count register is shown.

[0052] Executing the STRAOPEN instruction sets the CNT field in STRACNTR to the value contained in the ICNT field of STRACR. While a stream is opened, no functional access to the associated STRACR and STRACNTR registers is allowed.

[0053] A streaming load instruction or a streaming store instruction is a regular load instruction or a store instruction that uses an offset generated by a streaming address generator. The address is a combination of the offset and a base address. Similar to regular load and store instructions, the base address can come from a global scalar register or from a .D unit local register. Exemplary addressing modes that can be used with streaming load instructions or streaming store instructions are described in detail in U.S. patent application entitled "System and Method for Addressing Data in Memory," filed concurrently and incorporated herein by reference. By default, reading the streaming address offset registers SA0 390, SA1 391, SA2 392, and SA3 393 does not advance the offset calculation, and the registers can be re-read with the same value as many times as desired. However, for example Figure 4 As shown, encoding schemes can be used that also advance the offset calculation by one element length, thereby enabling the stream address generation logic.

[0054] Figure 9 An exemplary hardware implementation of stream address generators SAG0 380 and SAG1 381 is shown. Although space limitations Figure 9 The stream address generators SAG2 382 and SAG3 383 are not shown, but Figure 9 It is indeed contemplated that these additional stream address generators exist. The stream address generators SAG2 382 and SAG3 383 may be configured similarly to Figure 9 This is implemented in the manner of stream address generators SAG0 380 and SAG1 381 as shown.

[0055] like Figure 9 As shown, the configuration information contained in the SAOPEN instruction is stored in the register file 160 and provided to the corresponding stream address control registers STRACR0 384 and STRACR1 385. The stream address control registers STRACR0 384 and STRACR1 385 provide necessary information to the corresponding stream address generation logic 70 and 71, and provide necessary information to the corresponding stream address count registers STRACNTR0 394 and STRACNTR1 395. The stream address generation logic 70 and 71 are, for example, Figure 4The stream address counter registers STRACNTR0 394, STRACNTR1 395 receive information and provide it to the stream address generation logic 70, 71. The output of each of the stream address generators SAG0 380 and SAG1 381 is an offset that is stored in the stream address offset registers SA0 390 and SA1 391 and then sent to the multiplexer circuitry 64 for routing to the functional unit 351 ( Figure 3 ) in the appropriate functional unit D1, D2. Depending on the determination of the addressing mode blocks 66, 67, these offsets may be stored as operands in the relevant instructions 62, 63.

[0056] As described in more detail in the Predication application, each of stream address generators SAG0 380 and SAG1 381 may also generate a predicate for storage in the corresponding predicate stream address register 60 , 61 , which is then expanded into byte enables in 68 , 69 .

[0057] Figure 10A and Figure 10B Shown from Figure 9 801, the corresponding stream address control registers (e.g., STRACR0 384, STRACR1 385) provide the necessary information to the corresponding stream address generation logic 70 and 71 (at 809), and provide the necessary information to the corresponding stream address count registers (e.g., STRACNTR0 394, STRACNTR1 395) (at 808). Block 802 is an exemplary embodiment of the innermost loop 40. Block 803 iterates the other loops 41, 42, 43, 44, 45 ( Figure 4 ). Block 805 is executed in each loop 41, 42, 43, 44, 45 ( Figure 4 ) The current offset is calculated at the end of the process. The offset is generated at 806 and stored in the stream address offset registers (eg, SA0 390 and SA1 391) in block 807.

[0058] To start the streaming address generation logic, a load instruction or store instruction can indicate that an offset is to be advanced. For example, a load instruction or store instruction can include "[SA0++]" as an operand, which tells the streaming address generator to use the value of the streaming address generator register SA0 as the offset and then advance the offset by one element. Placing "++" within the brackets indicates that only the offset is advanced, not the base address. Therefore, the same base address can be used with an advanced offset to address multi-dimensional data.

[0059] The element size is based on the size of the data in the load instruction or store instruction using the offset. The number of elements accessed is specified by the VECLEN field of the stream address configuration register (STRACR.VECLEN), and is independent of the access size specified by the load instruction or store instruction. The exemplary stream address generator described herein improves the performance and efficiency of address generation by performing address generation of stream data in dedicated hardware. Address generation is separated from data processing. The example of the stream address generator described herein can also use multiple base addresses with the same offset and different element sizes. Although the exemplary stream address generator described herein includes stream address offset registers SA0 390, SA1 391, SA2 392 and SA3 393 for storing the offsets generated by each stream address generator, the offset can be output by the stream address generator.

[0060] The described embodiments may be modified, and other embodiments are possible, within the scope of the claims.

Claims

1. A digital signal processor, comprising: A stream address generator having dedicated hardware configured to generate a plurality of offsets to address stream data comprising a plurality of elements, each of the plurality of offsets corresponding to a respective one of the plurality of elements, wherein the plurality of offsets are configured to define a multi-dimensional space in a memory for the stream data. 2 . The digital signal processor of claim 1 , wherein the stream address generator is configured to generate the plurality of offsets using a nested loop.

3. The digital signal processor of claim 2 , wherein the stream address generator further comprises: a stream address offset register configured to store each of the plurality of offsets; a stream address control register configured to store configuration information; as well as A stream address count register is configured to store runtime information. 4 . The digital signal processor according to claim 3 , wherein the configuration information includes the number of iterations of each loop and the number of elements of the data separated in each loop. 5 . The digital signal processor of claim 4 , wherein the stream address generator is configured to advance the offset by one element length after each iteration of each loop. The digital signal processor of claim 4 , wherein an innermost loop of the nested loops writes data continuously. 7 . The digital signal processor of claim 1 , further comprising a second stream address generator, a third stream address generator, and a fourth stream address generator.

8. The digital signal processor of claim 1, further comprising a central processing unit, the central processing unit comprising the stream address generator.

9. A digital signal processor system comprising: Cache; and A digital signal processor comprising a CPU including a stream address generator having dedicated hardware configured to generate a plurality of offsets to address stream data for writing to or reading from the buffer, the stream data comprising a plurality of elements, and each of the plurality of offsets corresponding to a respective one of the plurality of elements, wherein the plurality of offsets are configured to define a multidimensional space in a memory for the stream data.

10. The digital signal processor system of claim 9, wherein the stream address generator is configured to generate the plurality of offsets using a nested loop.

11. The digital signal processor system of claim 10, wherein the stream address generator further comprises: a stream address offset register configured to store each of the plurality of offsets; a stream address control register configured to store configuration information; as well as A stream address count register is configured to store runtime information. 12 . The digital signal processor system according to claim 11 , wherein the configuration information includes the number of iterations of each loop and the number of elements of the data separated in each loop. 13 . The digital signal processor system of claim 12 , wherein the stream address generator is configured to advance the offset by one element length after each iteration of each loop.

14. A method of operating a digital signal processor system, the digital signal processor system being configured to address streaming data having a plurality of elements, the method comprising: Receive streaming data; Processing the stream data using a first set of execution units; generating, by using an execution unit, a plurality of offsets corresponding to the plurality of elements, wherein the plurality of offsets are configured to define a multi-dimensional space in a memory for the stream data; as well as The address is determined by combining each of the plurality of offsets with a base address. The method of claim 14 , further comprising advancing the offset after each iteration.

16. The method of claim 14, further comprising storing each of the plurality of offsets in a stream address offset register.

17. The method of claim 16, wherein the determining step comprises: successively retrieving each of the plurality of offsets from the stream address offset register; as well as Each of the plurality of offsets is combined with the base address.

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