Input circuit devices for a sense amplifier circuit

Abstract

According to a specific implementation of this disclosure, for operation of the sense amplifier circuitry, the input circuitry provides one or more reference paths and bit paths. In one implementation, the input circuitry includes a reference path, a bit path, and a CMOS resistor. The reference path includes a first MTJ device and a first access device, wherein the reference path is coupled to the sense amplifier via a first input terminal. The bit path includes a second MTJ device and a second access device, wherein the bit path is coupled to the sense amplifier via a second input terminal. In a specific implementation, the CMOS resistor is coupled to one of the reference path or the bit path.

Description

Technical Field

[0001] This disclosure generally relates to input circuit devices for sense amplifier circuits. Background Technology

[0002] Unlike conventional random access memory (RAM) chip technology, in magnetic RAM (MRAM), data is not stored as electrical charge, but rather through the magnetic polarization of the storage element. The storage element is formed by two ferromagnetic layers separated by a tunneling layer. One of the two ferromagnetic layers, called the pinned layer or anchor layer, has a fixed magnetization in a specific direction. The other ferromagnetic layer, called the free layer, has a magnetization direction that can be changed to represent a "1" when the free layer magnetization is antiparallel to the pinned layer magnetization, or to represent a "0" when the free layer magnetization is parallel to the pinned layer magnetization, and vice versa. A device with such a pinned layer, tunneling layer, and free layer is a magnetic tunnel junction (MTJ). The resistance of an MTJ depends on whether the free layer magnetization and the pinned layer magnetization are parallel or antiparallel to each other. Memory devices such as MRAM are composed of arrays of individually addressable MTJs.

[0003] To read data in a conventional MRAM, the read current flows through the MTJ via the same current path used to write data to the MTJ. The resistance presented by the MTJ differs if the magnetizations of the free and fixed layers are parallel to each other, compared to the resistance presented if the magnetizations of the free and fixed layers are in an antiparallel orientation. In a conventional MRAM, two distinct states are defined by the two distinct resistances of the MTJ within the bit cell of the MRAM. These two distinct resistances represent the logic "0" and logic "1" values ​​stored by the MTJ. When comparing the logarithm of the read operation samples with the resistance (kΩ) on a two-dimensional Cartesian plot, the two distinct resistances of the MTJ within the bit cell of the MRAM are shown as a low-resistance state (LRS) and a high-resistance state (HRS) distribution.

[0004] A current sense amplifier is a dedicated amplifier whose output is a voltage proportional to the current flowing in the power rail. Typically, these amplifiers utilize a current-sensing "resistor-like" device to convert the load current in the power rail into a small voltage, which is then amplified by the current sense amplifier. To read the MTJ device in a bit cell of MRAM, conventional sensing circuitry can be used to determine the differential voltage, and a conventional current sense amplifier can be used to amplify the differential voltage into the amplified voltage. Therefore, the output of a conventional current sense amplifier can be used to determine (i.e., read) the logic state of the MRAM bit cell.

[0005] For this process, the current or voltage from the reference memory path (i.e., the reference memory element, the reference path) can be compared with the current or voltage from the bit memory path (i.e., the bit memory element, the bit path) as input to the current or voltage sense amplifier. The reference path can be constructed using pure complementary metal-oxide-semiconductor (CMOS) devices (e.g., the reference device may include transistors and / or polysilicon resistors, etc.) or MTJ-based devices. One disadvantage of using a pure CMOS reference is the potential for global process, voltage, and temperature (PVT) variations on the LRS and HRS. These global PVT variations can prevent accurate tracking capabilities, thus increasing the difficulty of performing read operations under all conditions. Furthermore, on the other hand, a disadvantage of using MTJ-based references is that they may require additional refreshes at high temperatures (i.e., above the application-specific MTJ device qualification temperature (e.g., between 85°C and 125°C)) to prevent instability and functional problems during read operations.

[0006] Therefore, there is a need in the art for economical and stable reference and bit path circuits that can be utilized in the operation of sense amplifier circuits, allowing for accurate tracking capabilities with fewer circuit components and less system complexity. Summary of the Invention

[0007] This disclosure provides an input circuit for a sense amplifier, comprising: a reference path including a first magnetic tunnel junction (MTJ) device and a first access device, wherein the reference path is coupled to the sense amplifier via a first input terminal; a bit path including a second MTJ device and a second access device, wherein the bit path is coupled to the sense amplifier via a second input terminal; and a complementary metal-oxide-semiconductor (CMOS) resistor coupled to one of the reference path and the bit path. Attached Figure Description

[0008] The present technology will be further described by way of example with reference to embodiments shown in the accompanying drawings. However, it should be understood that the drawings only illustrate various implementations described herein and are not intended to limit the scope of the various technologies, systems, circuits, or devices described herein.

[0009] Figures 1A to 1B It is an input circuit for a readout amplifier according to a specific embodiment.

[0010] Figure 2 It is a circuit diagram of a reference path or bit path of an input circuit according to a specific embodiment.

[0011] Figures 3A to 3B This is an input circuit for an example readout amplifier according to a specific embodiment.

[0012] Figures 4A to 4B It is an input circuit for a readout amplifier according to a specific embodiment.

[0013] Figure 5 It is an input circuit for a readout amplifier according to a specific embodiment.

[0014] Figures 6A to 6B It is an input circuit for a readout amplifier according to a specific embodiment.

[0015] Figure 7 It is another input circuit for a readout amplifier according to a specific embodiment.

[0016] Figures 8A to 8B It is an input circuit for a readout amplifier according to a specific embodiment.

[0017] Figures 9A to 9B It is an input circuit for a readout amplifier according to a specific embodiment.

[0018] Figures 10A to 10B It is an input circuit for a readout amplifier according to a specific embodiment.

[0019] Figures 11A to 11B It is an input circuit for a readout amplifier according to a specific embodiment.

[0020] The following detailed description is made with reference to the accompanying drawings, which form part of this document, wherein the same reference numerals may always denote the same parts, which are corresponding and / or similar. It will be understood that the drawings are not necessarily drawn to scale, for example, for simplicity and / or clarity of illustration. For example, the dimensions of some aspects may be enlarged relative to others. Furthermore, it should be understood that other embodiments may be utilized. Additionally, structural and / or other changes may be made without departing from the claimed subject matter. Throughout this specification, reference to “claimed subject matter” means subject matter intended to be covered by one or more claims or any part thereof, and is not necessarily intended to refer to the entire set of claims, a particular combination of claims (e.g., device claims, etc.), or a particular claim. Therefore, the following detailed description is not intended to limit the claimed subject matter and / or equivalents. Detailed Implementation

[0021] According to specific examples of this disclosure, the input circuitry provides one or more reference paths and bit paths for operation of the sense amplifier circuitry. In one implementation, the input circuitry includes a reference path, a bit path, and a CMOS resistor. The reference path includes a first MTJ device and a first access device, wherein the reference path is coupled to the sense amplifier via a first input terminal. The bit path includes a second MTJ device and a second access device, wherein the bit path is coupled to the sense amplifier via a second input terminal. In a particular implementation, the CMOS resistor is coupled to either the reference path or the bit path.

[0022] According to one implementation of this disclosure, a reference memory element calibrates a reference path for operation of a sense amplifier circuit. The reference memory element includes an MTJ device in a low-resistance state, an access device, and a CMOS resistor. The impedance of the reference memory element can be between a low-resistance state and a high-resistance state.

[0023] According to another implementation of this disclosure, the bit memory element calibrates the bit path used for the operation of the readout amplifier circuit. The reference memory element includes an MTJ device in a high-resistance state, an access device, and a CMOS resistor. The impedance of the bit memory element can be either greater than or less than the high-resistance state.

[0024] Specific implementations of this disclosure are described below with reference to the accompanying drawings. In the description, common features are indicated by common reference numerals throughout the drawings.

[0025] refer to Figures 1A to 1B The diagram illustrates input circuitry 100 and 150 (e.g., current or voltage sense amplifier input arrangements) having a single MTJ reference path 160 and bit path 170 for example sense amplifier 110. Each of circuits 100 and 150 illustrates a reference path 160 (i.e., reference, reference element, reference memory element, reference circuitry) (including reference impedance) and a bit path 170 (i.e., bit, bit element, bit memory element, bit circuitry) (including bit impedance) coupled via a first input terminal 112 and a second input terminal 114 (e.g., negative input terminal and positive input terminal, or alternatively, positive input terminal and negative input terminal) of sense amplifier 110. As illustrated herein, for each of the circuit configurations, the first input terminal 112 and the second input terminal 114 may be interchanged as either positive or negative input terminals. Reference path 160 includes a first MTJ device 122 (e.g., LRS MTJ or HRS MTJ) and a first access device 124. Bit path 170 includes a second MTJ device 132 and a second access device 134. Furthermore, each of circuits 100 and 150 includes a reference path 160 (…). Figure 1A ) or bit path 170 ( Figure 1BThe CMOS resistor 140 is coupled (i.e., a CMOS resistor shifter, CMOS resistor element, resistor offset) (e.g., a CMOS-based transistor and / or PDK resistor). In an alternative embodiment, each of circuits 100 and 150 may be coupled with, for example, a reference... Figures 6A to 6B The two or more reference paths (e.g., multiple reference paths 660) and two or more bit paths (e.g., multiple bit paths 670) described are coupled together.

[0026] In one implementation, such as input circuit 100 ( Figure 1A As shown, a single MTJ122 in a low-resistance state (LRS) (i.e., the first MTJ device, LRS resistive memory element) can be used as a reference portion for the sense amplifier 110. For this implementation, reference path 160 is a “hybrid reference scheme” including the first MTJ device 122, CMOS resistor 140, and first access device 124. Bit path 170 includes a second MTJ device 132 (low-resistance / high-resistance resistive memory element 132 (LRS / HRS 132)) and a second access device 134. As shown, CMOS resistor 140 is used as a resistive offset coupled in series with the LRS MTJ122 and the first access device 124, such that the total reference impedance of reference path 160 is between the LRS and HRS. Therefore, the total reference impedance of reference path 160 can be constructed such that it can be distinguished between the LRS and HRS of the corresponding bit path 170. Figure 1A The advantages of the LRS reference scheme are that the reference path is more stable than the HRS state and can withstand higher temperatures. Therefore, less or even zero refreshes will be required at high temperatures (i.e., temperatures above MTJ qualification). This makes high-temperature operation easier to perform.

[0027] In alternative implementations, such as input circuit 150 ( Figure 1BAs shown, a single MTJ in a high-resistance state (HRS) (i.e., the first MTJ device 122, the HRS resistive memory element) can be used as a reference for the sense amplifier 110. For this implementation, bit path 170 is a “hybrid bit scheme” including the second MTJ device 132 (a low-resistance / high-resistance resistive memory element 132 (LRS / HRS 132)), the second access device 134, and a CMOS resistor 140, while reference path 160 includes the first MTJ device 122 (i.e., the HRS MTJ device 122) and the first access device 124. As shown, the CMOS resistor 140 serves as a resistive offset coupled in series with the second MTJ device 132 and the second access device 134, such that the total bit impedance of bit path 170 is below the HRS (e.g., when the second MTJ device 132 is in LRS) or above the HRS (e.g., when the second MTJ device 132 is in HRS). As an advantage of using the HRS reference scheme, the reference path can be used to track MTJ parameters, such as the tunnel magnetoresistance (TMR) variation relative to voltage.

[0028] like Figures 1A to 1B As shown, the first MTJ device 122 and the second MTJ device 132 include resistive memory elements capable of switching between a high-impedance state (i.e., HRS) and a low-impedance state (LRS), thereby allowing the storage of logic values, such as logic "0" and logic "1". As an example, refer to... Figure 1A The first MTJ device 122 can store logic "0" in response to placing the memory element in a low-impedance state, and the second MTJ device 132 can store logic "1" in response to placing the memory element in a high-impedance state. In an alternative example, the first MTJ device 122 can store logic "1", while the second MTJ device can store logic "0".

[0029] exist Figures 1A to 1B In the case where reference path 160 bit line 116 is coupled to reference node (V REF ) and the first input terminal 112, while the bit path 170 and bit line 118 are coupled to the bit node (V BIT When the second input terminal 114 is used, a read operation can be performed on the bit line (BL). For example, in response to a voltage signal at example word line 136 (which allows current to flow from the input voltage V), a read operation can be performed. BL The signal is conducted and flows through the sense amplifier (110 will provide the output logic signal 175). In a particular implementation, in response to the presence of node V... BIT The location includes less than V REF The voltage signal, including the value of the voltage signal at the location, and the output logic signal 175 may include a dual-state output signal, for example, including a signal with a relatively low voltage. In response to the presence of node V...BIT The location includes those greater than V REF The second state of logic signal 175, including the value of the voltage signal at the location, can include a relatively high voltage. In a non-limiting example, the sense amplifier 110 can operate differently such that it responds to the presence of signal node V. BIT The location includes those greater than V BIT The voltage signal at the point provides a relatively high voltage due to the voltage value included in the voltage, and in response to the presence of node V BIT The location includes less than V REF The voltage signal at that location is included in the signal, thus providing a relatively low voltage. (See reference...) Figures 3A to 11B As described above, similar read operations can be performed on the source line and bit line using the implementation of other input circuits, depending on the corresponding input circuit arrangement.

[0030] Use a hybrid reference scheme (e.g., Figure 1A (as shown) or a hybrid bit scheme (e.g., as shown) Figure 1B The advantages (shown) also include a reference that can track global changes in the MTJ, and because a single MTJ is used for the reference path instead of two, the reference path will also optimize the circuit design in terms of performance, power, and area (i.e., optimal PPA). Furthermore, the overall reference variability can be reduced due to the significantly smaller variability of CMOS resistors compared to MTJ devices. Additionally, depending on the specific sense amplifier design, "reference jitter" (i.e., randomization) can be employed to achieve a larger read margin (as shown below). Figures 8A to 8B , Figures 9A to 9B and Figures 11A to 11B (As described). Furthermore, in certain implementations, both the hybrid reference scheme and the hybrid bit scheme can be used with both voltage sense amplifiers and current sense amplifiers.

[0031] refer to Figure 2 The figure illustrates a composite resistance path 200 corresponding to a single MTJ reference path 160 or a single MTJ bit path 170 of the example sense amplifier 110. As shown, the composite resistance path 200, together with the single MTJ (e.g., a reference path MTJ device 122 with a known LRS / HRS value or a bit path MTJ device 132 with an unknown value (HRS or LRS)) and access devices (e.g., a first access device 124 or a second access device 134), also includes a bit line multiplexer 210, a bit line parasitic resistor 220, a source line multiplexer 230, a source line parasitic resistor 240, and a read pull-down device 250.

[0032] refer to Figure 3A and Figure 3BIn input circuits 300 and 350, reference path 160 and bit path 170 are shown, respectively, for performing read operations on the source line (SL) using a single LRSMTJ (i.e., the first MTJ device 122) reference scheme. Figures 3A to 3B As shown, reference path 160 includes a CMOS resistor 140, a first MTJ device 122, and a first access device 124, which are series coupled from ground 102 to the second input terminal 114 of the sense amplifier 110. Furthermore, in Figures 3A to 3B In the input circuit 300, bit path 170 includes a second MTJ device 132 (whose unknown value is HRS or LRS) coupled to ground 102 on bit line (BL) 118, while a second access device 134 is coupled to a first input terminal 112 on SL 128. In a comparison between input circuit 300 and input circuit 350, in input circuit 300, on reference path 160, a CMOS resistor 140 is coupled between the first MTJ device 122 and ground 102 on bit line (BL) 116, while the first access device 124 is coupled to a second input terminal 114 on SL 126. In input circuit 350, on reference path 160, a CMOS resistor 140 is coupled between the first access device 124 and the second input terminal 114 on SL 126, while the first MTJ device 122 is coupled between the first access device 124 and ground 102 on BL 116.

[0033] As an example, return to the reference. Figure 1A The input circuit 100 in the diagram illustrates reference path 160 and bit path 170 for performing read operations on the bit line (BL) using an implementation of a single LRS MTJ (i.e., first MTJ device 122) reference scheme. As described above, on reference path 160, a CMOS resistor 140 is coupled at BL 116 between the first MTJ device 122 and the first input terminal 112, while the first access device 124 is coupled at SL 126 to ground 102. Furthermore, on bit path 170, a second MTJ device 132 is coupled at BL 118 between the second access device 134 and the second input terminal 114, while the second access device 134 is coupled at SL 128 to ground. In another implementation (not shown), on reference path 160, CMOS resistor 140 is coupled between first access device 124 and ground 102 on SL 126, while first MTJ device 122 is coupled between first access device 124 and first input terminal 112 on BL 116. Furthermore, in this implementation, on bit path 170, second MTJ device 132 is coupled between second access device 134 and second input terminal 114 on BL 118, while second access device 134 is coupled to ground on SL 128.

[0034] refer to Figure 4A and Figure 4B In input circuits 400 and 450, example reference path 160 and bit path 170 are shown, respectively, for performing read operations on the source line (SL) using an implementation of a single HRSMTJ (i.e., first MTJ device 122) reference scheme. Figures 4A to 4B As shown, reference path 160 includes a first MTJ device 122 and a first access device 124, both connected in series from ground 102 to the second input terminal 114 of the sense amplifier 110. The first MTJ device 122 is coupled on BL 116 between the first access device 124 and ground 102, while the first access device 124 is coupled to the second input terminal 114 of SL 126. Furthermore, reference... Figure 4A Bit path 170 includes a CMOS resistor 140 coupled between a second MTJ device 132 (whose unknown value is HRS or LRS) and ground 102 on BL 118, while the second access device 134 is coupled to a first input terminal 112 on SL 128. In contrast, in Figure 4B In the middle, bit path 170 includes a CMOS resistor 140 coupled between a first input terminal 112 on the second access device 134 and SL 128, while the second MTJ device (whose unknown value is HRS or LRS) is coupled to ground 102 on BL 118.

[0035] In one implementation, a reference is returned. Figure 1B Reference path 160 and bit path 170 are shown for performing read operations on the bit line (BL) using a single HRS MTJ (i.e., first MTJ device 122) reference scheme. Furthermore, on reference path 160, the first MTJ device 122 is coupled at BL 116 between the first input terminal 112 and the first access device 124, while the first access device 124 is also coupled to ground 102 on SL 126. Furthermore, on bit path 170, a CMOS resistor 140 is coupled at BL 118 between the second MTJ device 132 and the second input terminal 114, while the second access device 134 is coupled to ground 102 on SL 128. In another implementation (not shown), on reference path 160, the first MTJ device 122 is coupled at BL 116 between the first input terminal 112 and the first access device 124, while the first access device 124 is also coupled to ground 102 on SL 126. However, in this implementation, on bit path 170, CMOS resistor 140 is coupled between second access device 134 and second input terminal 114 on BL 118, while second MTJ device 132 (whose unknown value is HRS or LRS) is coupled to ground 102 on SL 128.

[0036] refer to Figure 5 Switch 520 is coupled to CMOS resistor 140 in input circuit 500. As shown, in one implementation, switch 520 is coupled to both the first and second terminals of CMOS resistor 140. Therefore, in operation, when switch (SW1) 520 is closed (i.e., turned on) (executed at the beginning of the example read operation), CMOS resistor 140 is shunt, and the first input terminal 112 of the sense amplifier is directly connected to BL 116. Thus, sense amplifier 110 can directly supply the correct voltage charge to BL 116. When BL 116 is fully charged, the switch can be turned on (i.e., turned off). Advantageously, switch 520 can accelerate the voltage dynamics on example BL 116. Furthermore, in various alternative implementations (e.g., similar to reference...), Figure 1A and Figures 1B to 4A and Figure 4B , Figure 6A and Figures 6B to 11A and Figure 11B In those described herein, switch 520 can be coupled to CMOS resistor 140 as an additional circuit design in each of the implementations described herein. In a particular example, when CMOS resistor 140 can be coupled to reference path 160 or bit path 170, switch 520 can be coupled to both the first and second terminals of CMOS resistor 140. Switch 520 can also be coupled to both the first and second terminals of CMOS resistor 140 when CMOS resistor 140 can be coupled to SL 126, SL 128 or BL 116, BL 118.

[0037] refer to Figures 6A to 6B In each of input circuits 600 and 650, the voltage drop element 620 is coupled to a plurality of reference paths 660 (i.e., a first memory array, a reference memory array) (e.g., two or more reference paths 160) and a plurality of bit paths 670 (i.e., a second memory array, a bit memory array) (e.g., two or more bit paths 170). Therefore, in a particular implementation, the first memory array 660 may include a corresponding plurality of reference paths 660, and the second memory array may include a corresponding plurality of bit paths 670. The corresponding plurality of bit paths 670 and the plurality of reference paths 660 can be implemented using any of the circuit implementations described in the preceding paragraphs.

[0038] As shown in input circuits 600 and 650, voltage drop element 620 is coupled to node 630 and ground 102, which combines multiple reference paths 660 and multiple bit paths 670. In a particular operation, the reference... Figure 6A Bit line voltage (V) used for bit path BL BIT ) and the bit line voltage of the reference path (VBL REF The reference path may have different values ​​(e.g., at high temperatures), resulting in different leakage on each of the reference paths compared to leakage on each of the bit paths 170. In a particular operation, the reference path... Figure 6B Source line voltage (V) used for bit path SL BIT ) and the source line voltage of the reference path (V SL REF The leakage current may have different values ​​(e.g., at high temperatures), resulting in different leakage current on each of the reference paths 160 compared to each of the leakage currents in bit paths 170. This difference in leakage current can cause a voltage shift in the system. Voltage drop element 620 can be configured to mitigate leakage and voltage shift in the system. Figure 6A As shown in the input circuit 600, when a read operation is performed from BL, the voltage drop element 620 is coupled to the source line of each of the reference paths 160 and each of the bit paths 170. Figure 6B As shown in the input circuit 650, when a read operation is performed from SL, the voltage drop element 620 is coupled to the bit line of each of the reference path 160 and the bit path 170.

[0039] In various implementations of input circuits 600 and 650, the voltage drop element 620 can be a resistor, a transistor, or a voltage generator. By including the voltage drop element 620, a series impedance is added to the current path, resulting in a voltage rise. For each of the multiple access devices (i.e., NMOS access devices) (e.g., access device 124, access device 134), the voltage rise is a negative gate-source voltage (Vgs). Furthermore, in operation, the negative Vgs can exponentially reduce leakage of all unaccessed bit cells, making the leakage difference between the multiple bit paths 6700 and the multiple reference paths 660 negligible. In a particular implementation, the series impedance can be "common-mode" so that it does not add an offset to the read operation.

[0040] refer to Figure 7 In input circuit 700, voltage drop element 620 is shown as a circuit element added to an example implementation of input circuit 100. As depicted, Figure 7 A voltage drop element 620 coupled to reference path 160 and bit path 170 is shown. Figure 7 The simplified input circuit diagram in Figure 6 can also be represented, where reference path 160 is a representative reference path 160 among multiple reference paths 660, and bit path 170 is a representative bit path 170 among multiple bit paths 670. In addition to the above references... Figure 1AIn addition to the features described, when a read operation is performed from the BL, the voltage drop element 620 is coupled to the SL of the corresponding reference path 160 and bit path 170, as well as ground 102. In another implementation (not shown), when a read operation is performed from the BL, the voltage drop element 620 is coupled to the BL of the corresponding reference path 160 and bit path 170, as well as ground 102.

[0041] Reference Figures 8A to 8B , Figures 9A to 9B as well as Figures 11A to 11B In the specific implementation described, reference "jittering" (i.e., randomization) can be performed when the reference element is "shared" between two sense amplifiers. That is, by averaging the reference with two different references of the two input circuit arrangements in two different stages (e.g., the sampling stage of the sense amplifier and the amplification stage of the sense amplifier), a better read margin result is achieved.

[0042] refer to Figures 8A to 8B Reference paths (i.e., reference memory paths, reference memory elements) 860, 862 and bit paths (i.e., bit memory paths, bit memory elements) 870, 872 are shown as first input circuitry 830 and second input circuitry 832 coupled to first sense amplifier 810 (SA0) and second sense amplifier 820 (SA1) (i.e., first system and second system). As in sampling phase 800 (e.g., Figure 8A (Or in another circuit implementation,) Figure 8B (depending on the internal operation of the readout amplifier) ​​and amplification stage 850 (e.g., Figure 8B (Or in another circuit implementation,) Figure 8A As described in the two phases (i.e., two periods) of the sense amplifier (depending on its internal operation), sense amplifiers 810 (SA1) and 820 (SA2) can be configured to determine (i.e., read) the logic state (whether HRS or LRS) of the corresponding MTJ in bit paths 870 and 872. Figures 8A to 8B As shown, each of reference paths 860 and 862 includes a first MTJ device 122, a CMOS resistor 140, and a first access device 124. Furthermore, each of bit paths 870 and 872 includes a second MTJ device 132 and a second access device 134.

[0043] In one example operation, outside of example first system 810 and second system 820, for sampling stage 800, the first reference memory element 860 (of the first input circuit 830) may be coupled to the second input terminal 114 (e.g., a positive port). Furthermore, the first bit to be read (the first bit memory element 870 of the first input circuit 830) may be coupled to the first input terminal 112 of system 810 (SA0) (e.g., a negative port). Similarly, the second reference memory element 862 (of the second input circuit 832) may be coupled to the second input terminal 214 (e.g., a positive port), and the second bit to be read (the second bit memory element 872 of the second input circuit 832) may be coupled to the first input terminal 212 of system 820 (SA1) (e.g., a negative port). Conversely, for amplification stage 850, the first bit memory element 870 may be coupled to the second input terminal 114 (e.g., a positive port), and the second reference memory element 862 may be coupled to the first input terminal 112 of system 810 (SA0) (e.g., a negative port). Similarly, the first reference memory element 860 may be coupled to the first input terminal 212 (e.g., a negative port), and the second bit memory element 872 may be coupled to the second input terminal 214 of the system 820 (SA1) (e.g., a positive port). Therefore, during the amplification phase, comparisons can be made between the desired bits to be read (i.e., between each of the first and second bit memory elements 870 and 872 and the reference memory elements 860 and 862). In the various implementations described herein, the first input circuit 830 and the second input circuit 832 can be any of the input circuits described herein, where the first MTJ is in LRS, for example, in Figure 1A , Figure 3A , Figure 3B , Figure 5 , Figures 6A to 6B ,as well as Figure 7 middle.

[0044] refer to Figures 9A to 9B Reference paths (i.e., reference memory paths, reference memory elements) 960, 962 and bit paths (i.e., bit memory paths, bit memory elements) 970, 972 are shown as first input circuitry 930 and second input circuitry 932 coupled to first sense amplifier 910 (SA0) and second sense amplifier 920 (SA1) (i.e., first system and second system). As in sampling phase 900 (e.g., Figure 9A (Or in another circuit implementation,) Figure 9B (depending on the internal operation of the readout amplifier) ​​and amplification stage 950 (e.g., Figure 9B (Or in another circuit implementation,) Figure 9AAs depicted in the two phases (i.e., two periods) of the readout amplifier (depending on the internal operation of the readout amplifier), readout amplifiers 910 (SA1) and 920 (SA2) can be configured to determine (i.e., read) the logic state (whether HRS or LRS) of the corresponding MTJs in bit paths 970 and 972. As shown, each of reference paths 960 and 962 includes a first MTJ device 122 and a first access device 124. Furthermore, each of bit paths 970 and 972 includes a second MTJ device 132, a second access device 134, and a CMOS resistor 140.

[0045] In one example operation, outside of example first system 910 and second system 920, for sampling stage 900, first reference memory element 960 (of first input circuit 930) may be coupled to second input terminal 114 (e.g., positive port). Furthermore, the first bit to be read (first bit memory element 970 of first input circuit 930) may be coupled to first input terminal 112 of system 910 (SA0) (e.g., negative port). Similarly, second reference memory element 962 (of second input circuit 932) may be coupled to second input terminal 214 (e.g., positive port), and second bit to be read (second bit memory element 972 of second input circuit 932) may be coupled to first input terminal 212 of system 920 (SA1) (e.g., negative port). Conversely, for amplification stage 950, first bit memory element 970 may be coupled to second input terminal 114 (e.g., positive port), and second reference memory element 962 may be coupled to first input terminal 112 of system 910 (SA0) (e.g., negative port). Similarly, the first reference memory element 960 may be coupled to the first input terminal 212 (e.g., a negative port), and the second bit memory element 972 may be coupled to the second input terminal 214 of the system 920 (SA1) (e.g., a positive port). Therefore, in the amplification stage 950, comparisons can be made between the desired bits to be read (i.e., between each of the first and second bit memory elements 970 and 972 with the first and second reference memory elements 960 and 962). In the various implementations described herein, the first input circuit 930 and the second input circuit 932 can be any of the input circuits described herein, where the first MTJ is in the HRS, for example, in Figure 1B , Figure 4A and Figure 4B middle.

[0046] refer to Figure 10A and Figure 10BIn input circuits 1000 and 1050, example reference paths 160 and 170 are shown, respectively, for performing read operations on bit lines (BLs) using an implementation of a single LRS MTJ (i.e., first MTJ device 122) reference scheme. Figures 10A to 10B As shown, each of the reference paths 160 includes: a CMOS resistor 140, a first access device 124, and a first MTJ device 122, which are connected in series from ground 102 to the first input terminal 112 of the sense amplifier 110.

[0047] like Figure 10A As shown, the first MTJ device 122 is coupled on BL 116 between the first access device 124 and the first input terminal 112, while the CMOS resistor 140 is coupled between the first access device 124 and ground 102 on SL 126. Figure 10A As shown, when a read operation is performed from BL 116, reference path 160 includes a direct connection between the first MTJ device 122 and the sense amplifier 110. Advantageously, this direct connection allows for interference-free reference path read operations. Furthermore, in Figure 10A In the middle, bit path 170 includes a second MTJ device 132 (whose unknown value is HRS or LRS) coupled between access device 134 and ground 102 on BL 118, while access device 134 is also coupled to a second input terminal 114 on SL 128.

[0048] In another implementation, Figure 10B In the reference path 160, a first access device 124, a first MTJ device 122, and a CMOS resistor 140 are connected in series from ground 102 to the first input terminal 112. As shown, the first MTJ device 122 and the CMOS resistor 140 are coupled on BL 116 between the first access device 124 and the first input terminal 112, and the first access device 124 is also coupled to ground 102 on SL 126. Furthermore, in Figure 10B In the middle, bit path 170 includes a second MTJ device 132 (whose unknown value is HRS or LRS) coupled between access device 134 and ground 102 on BL 118, while access device 134 is also coupled to a second input terminal 114 on SL 128.

[0049] refer to Figures 11A to 11BReference paths (i.e., reference memory paths, reference memory elements) 1160, 1162 and bit paths (i.e., bit memory paths, bit memory elements) 1170, 1172 are shown as first input circuit 1130 and second input circuit 1132 coupled to first sense amplifier 1110 (SA0) and second sense amplifier 1120 (SA1) (i.e., first system and second system). As in sampling phase 1100 (e.g., Figure 11A (Or in another circuit implementation,) Figure 11B (depending on the internal operation of the readout amplifier) ​​and amplification stage 1150 (e.g., Figure 11B (Or in another circuit implementation,) Figure 11A As described in the two phases (i.e., two periods) of the readout amplifier (depending on its internal operation), the first readout amplifier 1110 (SA1) and the second readout amplifier 1120 (SA2) can be configured to determine (i.e., read) the logic state (whether HRS or LRS) of the corresponding MTJ in bit paths 1170 and 1172. Figures 11A to 11B As shown, each of reference paths 1160 and 1162 includes a first MTJ device 122, a first access device 124, and a CMOS resistor 140. Furthermore, each of bit paths 1170 and 1172 includes a second MTJ device 132 and a second access device 134.

[0050] It is worth noting that, similar to Figures 10A to 10B The coupling shown is in Figure 11A In both reference paths 1160 and 1162, a CMOS resistor 140, a first access device 124, and a first MTJ device 122 are connected in series from ground 102 to the respective first input terminals of the sense amplifiers (e.g., to the respective first input terminal 112 of the first sense amplifier 1110 and to the respective first input terminal 212 of the second sense amplifier 1120), and are connected in series. As shown, for each of reference paths 1160 and 1162, the first MTJ device 122 is coupled on BL 116 between the first access device 124 and the first input terminal 112, while the CMOS resistor 140 is coupled between the first access device 124 and ground 102 on SL 126. Furthermore, in Figure 11A In the middle, both bit path 1170 and bit path 1172 include a second MTJ device 132 (whose unknown value is HRS or LRS) coupled between access device 134 and ground 102 on BL118, while access device 134 is coupled to a corresponding second input terminal of a sense amplifier on SL128 (e.g., coupled to a corresponding second input terminal 114 of the first sense amplifier 1110 and a corresponding second input terminal 214 of the second sense amplifier 1120).

[0051] In one example operation, in addition to the example first sense amplifier 1110 and second sense amplifier 1120, for the sampling phase 1100, the first reference memory element 1160 (of the first input circuit 1130) can be coupled to the first input terminal 112 (e.g., the positive port) of the first sense amplifier 1110 (SA0). Furthermore, the first bit to be read (the first memory element 1170 of the first input circuit 1130) can be coupled to the second input terminal 114 (e.g., the negative port) of the first sense amplifier 1110 (SA0). Similarly, the second reference memory element 1162 (of the second input circuit 1132) can be coupled to the first input terminal 212 (e.g., the positive port) of the second sense amplifier 1120 (SA1), and the second bit to be read (the second bit memory element 1172 of the second input circuit 1132) can be coupled to the second input terminal 214 (e.g., the negative port) of the second sense amplifier 1120 (SA1). Conversely, for amplification stage 1150, the first memory element 1170 may be coupled to the first input terminal 112 (e.g., a positive port), and the second reference memory element 1162 may be coupled to the second input terminal 114 (e.g., a negative port) of the first sense amplifier 1110 (SA0). Similarly, the first reference memory element 1160 may be coupled to the second input terminal 214 (e.g., a negative port), and the second bit memory element 1172 may be coupled to the first input terminal 212 (e.g., a positive port) of the second sense amplifier 1120 (SA1). Therefore, in amplification stage 1150, comparisons can be made between the desired bits to be read (i.e., between each of the first memory element 1170 and the second bit memory element 1172 and the first reference memory element 1160 and the second reference memory element 1162). In the various implementations described herein, the first input circuit 1130 and the second input circuit 1132 may be any of the input circuits described herein, where the first MTJ is in LRS, for example, in Figure 10A and Figure 10B middle.

[0052] Advantageously, in one example, such as Figures 10A to 10B and Figures 11A to 11B As shown, by reading the reference path from the BL, read interference on the reference path can be avoided. For example, since the reference MTJ can be in the LRS (e.g., P state) during a read operation and the read operation from the BL will include a write path from the AP state to the P state, the LRS MTJ will not be disturbed.

[0053] For each of the circuit implementations described herein with reference to Figures 1 through 11, the reference path can be coupled to the negative port (negative input terminal) of the sense amplifier, while the bit path can be coupled to the positive port (positive input terminal). Furthermore, in alternative circuit implementations, the reference path can be coupled to the positive port (positive input terminal) of the sense amplifier, while the bit path can be coupled to the negative port (negative input terminal). Accordingly, in each of the circuit implementations described herein, the negative input terminal can be either the first or the second input terminal, while the positive input terminal can be either the second or the first input terminal.

[0054] although Figures 1A to 11B One or more of these may illustrate systems and apparatuses according to the teachings of this disclosure, but this disclosure is not limited to these illustrated systems, apparatuses, or methods. The systems, apparatuses, or methods shown or described herein... Figures 1A to 11B One or more functions or components of any of the accompanying drawings may be related to Figures 1A to 11B The other figures in the diagram are combined with one or more other portions. Therefore, no single implementation described herein should be construed as limiting without departing from the teachings of this disclosure, and implementations of this disclosure may be appropriately combined.

[0055] Those skilled in the art will also recognize that the various illustrative logic blocks, configurations, modules, circuits, and algorithmic steps described in conjunction with the implementations disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or a combination of both. They have been generally described above according to the functionality of the various illustrative components, blocks, configurations, modules, circuits, and steps. Whether this functionality is implemented as hardware or processor-executable instructions depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0056] The steps of the methods or algorithms described in conjunction with the disclosure herein can be implemented directly in hardware, in a software module executed by a processor, or in a combination of both. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, optical disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). The ASIC can reside in a computing device or user terminal. Alternatively, the processor and storage medium can reside as discrete components in a computing device or user terminal.

[0057] The foregoing description is provided to enable those skilled in the art to make or use the disclosed implementations. Various modifications to these implementations will be apparent to those skilled in the art, and the principles defined herein can be applied to other implementations without departing from the scope of this disclosure. Therefore, this disclosure is not intended to limit the implementations shown herein, but should be accorded the widest possible scope consistent with the principles and novel features defined in the appended claims.

Claims

1. An input circuit for a sense amplifier, comprising: a reference path comprising a first magnetic tunnel junction (MTJ) device and a first access device, wherein the reference path is coupled to the sense amplifier via a first input terminal; a bit path comprising a second MTJ device and a second access device, wherein the bit path is coupled to the sense amplifier via a second input terminal; and a complementary metal-oxide-semiconductor (CMOS) resistor coupled to one of the reference path and the bit path, wherein, when the CMOS resistor is coupled to the bit path, the CMOS resistor is configured as a resistance offset of the second MTJ device such that an impedance of the bit path is greater than or less than a high resistance state (HRS).

2. The input circuit of claim 1, wherein, Each of the reference path and the bit path comprises a separate MTJ device.

3. The input circuit of claim 1, wherein, The impedance of the bit path is greater than or less than the impedance of the reference path.

4. The input circuit of claim 1, wherein, When the CMOS resistor is coupled to the reference path, the CMOS resistor is configured as a resistance offset of the first MTJ device such that corresponds to a low resistance state, and wherein the impedance of the reference path is between the low resistance state and the HRS.

5. The input circuit of claim 1, wherein, The first MTJ device corresponds to the HRS, wherein the impedance of the reference path corresponds to the HRS, and wherein the impedance of the bit path is greater than or less than the HRS.

6. The input circuit of claim 1, wherein, The CMOS resistor comprises a transistor or a process design kit (PDK) resistor.

7. The input circuit of claim 1, wherein, The CMOS resistor is coupled with the first access device and the first MTJ device in a series arrangement from the first input terminal to ground, or the CMOS resistor is coupled with the second access device and the second MTJ device in a series arrangement from the second input terminal to ground.

8. The input circuit of claim 1, wherein, Each of the reference path and the bit path further comprises a bit line multiplexer, a bit line parasitic resistance, a source line multiplexer, a source line parasitic resistance, and a read pull-down device.

9. The input circuit of claim 1, further comprising a switch coupled with a first end and a second end of the CMOS resistor.

10. The input circuit of claim 1, wherein, A read operation is configured to be performed from a bit line or a source line.

11. The input circuit of claim 10, wherein, If the read operation is performed on the bit line and the first MTJ device corresponds to a low resistance state, it is determined that the CMOS resistor is coupled on the reference path between the first MTJ device and the first input terminal of the sense amplifier, or the CMOS resistor is coupled between the first access device and ground.

12. The input circuit of claim 10, wherein, If the read operation is performed on the source line and the first MTJ device corresponds to a low resistance state, it is determined that the CMOS resistor is coupled on the reference path between the first MTJ device and ground, or the CMOS resistor is coupled between the first access device and the first input terminal of the sense amplifier.

13. The input circuit of claim 10, wherein, if the read operation is performed on the bit line and the first MTJ device corresponds to a high resistance state, then determining that the CMOS resistor is coupled between the second MTJ device and ground on the bit path, or the CMOS resistor is coupled between the second access device and a second input terminal of the sense amplifier.

14. The input circuit of claim 10, wherein, if the read operation is performed on the bit line and the first MTJ device corresponds to a high resistance state, then determining that the CMOS resistor is coupled between the second MTJ device and ground on the bit path, or the CMOS resistor is coupled between the second MTJ device and a second input terminal of the sense amplifier.

15. An input circuit for a sense amplifier, comprising: a reference path comprising a first magnetic tunnel junction (MTJ) device and a first access device, wherein the reference path is coupled to the sense amplifier via a first input terminal; a bit path comprising a second MTJ device and a second access device, wherein the bit path is coupled to the sense amplifier via a second input terminal; and a complementary metal-oxide-semiconductor (CMOS) resistor coupled to one of the reference path and the bit path; and a voltage drop element configured to mitigate leakage and system voltage offset, wherein the voltage drop element is coupled between a node that combines the reference path and the bit path and ground, and wherein the voltage drop element comprises one of a resistor, a transistor, and a voltage generator.

16. The input circuit of claim 15, further comprising two or more reference paths and two or more bit paths, wherein, the voltage drop element is coupled between a node that combines the two or more reference paths and the two or more bit paths and ground.

17. The input circuit of claim 15, wherein, the input circuit for a sense amplifier is integrated into a memory comprising two or more input circuits.

18. An input circuit for a sense amplifier, comprising: a reference path comprising a first magnetic tunnel junction (MTJ) device and a first access device, wherein the reference path is coupled to the sense amplifier via a first input terminal; a bit path comprising a second MTJ device and a second access device, wherein the bit path is coupled to the sense amplifier via a second input terminal; and a complementary metal-oxide-semiconductor (CMOS) resistor coupled to one of the reference path and the bit path, wherein the input circuit for a sense amplifier is integrated into a memory comprising two or more input circuits, and wherein a first input circuit of the two or more input circuits is coupled to a first sense amplifier and a second input circuit of the two or more input circuits is coupled to a second sense amplifier, and wherein, during a sampling phase, the bit path and the reference path of the first input circuit are coupled to a first input terminal and a second input terminal, respectively, of the first sense amplifier, and the bit path and the reference path of the second input circuit are coupled to a first input terminal and a second input terminal, respectively, of the second sense amplifier, and during a read phase, the bit path and the reference path of the first input circuit are coupled to a second input terminal and a first input terminal, respectively, of the first sense amplifier, and the bit path and the reference path of the second input circuit are coupled to a second input terminal and a first input terminal, respectively, of the second sense amplifier. In the amplification phase, a reference path of the second input circuit and a bit path of the first input circuit are coupled to first and second input terminals, respectively, of the first sense amplifier, and a reference path of the first input circuit and a bit path of the second input circuit are coupled to first and second input terminals, respectively, of the second sense amplifier.

19. An input circuit for a sense amplifier, comprising: a reference element comprising a first magnetic tunnel junction (MTJ) device and a first access device, wherein the reference element is coupled to the sense amplifier via a first input terminal; a bit element comprising a second MTJ device and a second access device, wherein the bit element is coupled to the sense amplifier via a second input terminal; and a complementary metal-oxide-semiconductor (CMOS) resistor coupled to the second access device and the second MTJ device.

20. The input circuit of claim 19, wherein, The CMOS resistor is configured to shift the first MTJ device.

21. The input circuit of claim 19, wherein the reference element further comprises a bit line multiplexer, a bit line parasitic resistance, a source line multiplexer, a source line parasitic resistance, and a read pull-down device.

22. A bit storage element for calibrating a bit storage path of a sense amplifier circuit, comprising: an MTJ device corresponding to a high resistance state, an access device, and a CMOS resistor shifter, wherein the CMOS resistor shifter of the bit storage element is configured to shift an impedance of the bit storage element to be greater than or less than the high resistance state.

23. The bit memory element of claim 22, wherein, The bit element is integrated into the bit storage path of a sense amplifier input circuit.

24. The bit storage element of claim 22, further comprising a bit line multiplexer, a bit line parasitic resistance, a source line multiplexer, a source line parasitic resistance, and a read pull-down device.

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