Package structure

Abstract

The present case provides a packaging structure, wherein a first packaging component includes a first metal layer, a first insulating layer, and a second metal layer, the first insulating layer is formed between the first metal layer and the second metal layer, the second packaging component includes a third metal layer, a semiconductor chip is arranged between the first packaging component and the second packaging component, the semiconductor chip includes a plurality of conductive terminals connected to the first metal layer or the third metal layer, a plurality of metal pins are arranged between the second packaging component and the first packaging component, extending outward from the second packaging component and the first packaging component, a plurality of metal pins are electrically connected to the plurality of conductive terminals, and a second insulating layer is arranged between the first packaging component and the second packaging component to stabilize the first packaging component, the second packaging component, the semiconductor chip and the plurality of metal pins.

Description

Technical Field

[0001] The present invention relates to a packaging structure, and more particularly to a packaging structure with a double-sided cooling mechanism. Background Art

[0002] In recent years, the design of electronic devices has been developing towards a trend of being small, thin and easy to carry. Furthermore, with the increasing advancement of electronic industry technology, the internal circuits of electronic devices have gradually developed towards modularization. In other words, multiple electronic components are integrated into a single electronic module. For example, a power module is one of the widely used electronic modules. The power module may include, for example but not limited to, a DC to DC converter, a DC to AC converter or an AC to DC converter. After multiple electronic components (such as integrated circuit chips, capacitors, resistors, inductors, transformers, diodes and transistors) are integrated into a power module, the power module can be installed on a motherboard or a system circuit board.

[0003] At present, the embedded packaging method without any bonding wires is widely used in the packaging structure of power modules to reduce the package footprint and increase the efficiency at the same time. However, when the semiconductor chip embedded in the insulating layer of the embedded packaging structure works, a large amount of heat is generated, and the generated heat can only be dissipated from one side of the packaging structure, so that the heat dissipation efficiency of the traditional packaging structure cannot be satisfied. In addition, the traditional packaging structure is relatively complex and cannot be applied to flip-chipped semiconductor chips.

[0004] Therefore, it is necessary to provide an improved packaging structure to solve the above problems faced by the prior art. Summary of the invention

[0005] The purpose of this case is to provide a packaging structure, wherein at least one semiconductor chip is disposed between a first packaging component and a second packaging component and has a double-sided cooling mechanism for heat dissipation. Therefore, the heat dissipation efficiency of the packaging structure of this case is improved and has a simpler packaging structure.

[0006] To achieve the above-mentioned purpose, a more general implementation of the present case is to provide a packaging structure, comprising: a first packaging component, a second packaging component, at least one semiconductor chip, a plurality of metal pins and a second insulating layer. The first packaging component comprises a first metal layer, a first insulating layer, and a second metal layer, wherein the first insulating layer is formed between the first metal layer and the second metal layer. The second packaging component comprises a third metal layer. At least one semiconductor chip is disposed between the first packaging component and the second packaging component, and at least one semiconductor chip comprises a plurality of conductive terminals, wherein the plurality of conductive terminals are connected to the first metal layer or the third metal layer. A plurality of metal pins are disposed between the second packaging component and the first packaging component, and extend outward from the second packaging component and the first packaging component, and a plurality of metal pins are electrically connected to the plurality of conductive terminals, respectively. The second insulating layer is disposed between the first packaging component and the second packaging component to stabilize the first packaging component, the second packaging component, the at least one semiconductor chip and the plurality of metal pins.

[0007] Those skilled in the art will have a further understanding of the above contents of the present invention after reading the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A It is a schematic diagram of the cross-sectional structure of the packaging structure of the first embodiment of the present case.

[0009] Figure 1B FIG. 1 is a schematic cross-sectional view of a packaging structure including a heat dissipation device according to a first embodiment of the present invention.

[0010] FIG. 2A to FIG. 2E for Figure 1A A schematic cross-sectional structural diagram of a packaging method for a packaging structure.

[0011] Figure 3 It is a schematic cross-sectional structure diagram of the packaging structure of the second embodiment of the present case.

[0012] Figure 4 It is a schematic cross-sectional structure diagram of the packaging structure of the third embodiment of the present case.

[0013] Figure 5 It is a schematic cross-sectional structure diagram of the packaging structure of the fourth embodiment of the present case.

[0014] Figure 6 It is a schematic cross-sectional structure diagram of the packaging structure of the fifth embodiment of the present case.

[0015] Figure 7 It is a schematic cross-sectional structure diagram of the packaging structure of the sixth embodiment of the present case.

[0016] Figure 8 It is a schematic cross-sectional structure diagram of the packaging structure of the seventh embodiment of the present case.

[0017] Fig. 9 It is a schematic cross-sectional structure diagram of the packaging structure of the eighth embodiment of the present case.

[0018] Fig.10 It is a schematic cross-sectional structure diagram of the packaging structure of the ninth embodiment of the present case.

[0019] Fig.11 FIG. 1 is a schematic cross-sectional structural diagram of a packaging structure of the tenth embodiment of the present invention.

[0020] Fig.12 FIG. 1 is a schematic cross-sectional structural diagram of the packaging structure of the eleventh embodiment of the present invention.

[0021] Fig.13 FIG. 1 is a schematic cross-sectional structural diagram of a packaging structure of the twelfth embodiment of the present invention.

[0022] Fig.14 It is a schematic cross-sectional structural diagram of the packaging structure of the thirteenth embodiment of the present case.

[0023] Fig.15 It is a schematic cross-sectional structural diagram of the packaging structure of the fourteenth embodiment of the present case.

[0024] Fig.16 It is a schematic cross-sectional structural diagram of the packaging structure of the fifteenth embodiment of the present case.

[0025] Fig.17A It is a schematic cross-sectional structural diagram of the packaging structure of the sixteenth embodiment of the present case.

[0026] Fig. 17B for Fig.17A The top view of the package structure is shown.

[0027] Fig.18 It is a schematic cross-sectional structural diagram of the packaging structure of the seventeenth embodiment of the present case.

[0028] Fig.19 It is a schematic diagram of the cross-sectional structure of the packaging structure of the eighteenth embodiment of the present case.

[0029] Fig. 20 It is a schematic cross-sectional structural diagram of the packaging structure of the nineteenth embodiment of the present case.

[0030] FIG. 21A to FIG. 21E for Fig. 20 A schematic cross-sectional structural diagram of a packaging method for a packaging structure.

[0031] Fig. 22 It is a schematic cross-sectional structural diagram of the packaging structure of the twentieth embodiment of the present case.

[0032] Fig.23 This is a schematic diagram of the cross-sectional structure of the packaging structure of the twenty-first embodiment of the present case.

[0033] Fig.24 It is a schematic diagram of the cross-sectional structure of the packaging structure of the twenty-second embodiment of the present case.

[0034] Fig.25 This is a schematic diagram of the cross-sectional structure of the packaging structure of the twenty-third embodiment of the present case.

[0035] Fig.26 It is a schematic diagram of the cross-sectional structure of the packaging structure of the twenty-fourth embodiment of the present case.

[0036] The reference numerals are described as follows:

[0037] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j, 1k, 1l, 1m, 1n, 1o, 1p, 1q, 1r, 1s, 1t, 1u, 1v, 1w: Package structure

[0038] 11: Semiconductor chips

[0039] 111: Side 1

[0040] 112: Side 2

[0041] 113: First conductor terminal

[0042] 114: Second conductor terminal

[0043] 12: Metal pins

[0044] 121: Side 1

[0045] 122: Side 2

[0046] 123: Part 1

[0047] 124: Part 2

[0048] 13: First conductive layer

[0049] 14: Second conductive layer

[0050] 14a: Part 1

[0051] 14b: Part 2

[0052] 14c: Part III

[0053] 15: Second insulation layer

[0054] 15a: Part 1

[0055] 15b: Part 2

[0056] 15c: Part III

[0057] 16: Second packaging component

[0058] 16a: Side 1

[0059] 16b: Side 2

[0060] 161: The third metal layer

[0061] 162: The third insulation layer

[0062] 163: Fourth metal layer

[0063] 164: First protrusion

[0064] 165: Second protrusion

[0065] 166: Fourth groove

[0066] 17: First packaging component

[0067] 171: First metal layer

[0068] 171a: Part 1

[0069] 171b: Part 2

[0070] 172: First insulation layer

[0071] 173: Second metal layer

[0072] 174: First groove

[0073] 175: Second groove

[0074] 176: Concave

[0075] 177: Third groove

[0076] 18: Insulation structure

[0077] 19: Shell

[0078] 191: Accommodation space

[0079] 192: Opening

[0080] h1: first heat sink

[0081] h2: Second heat sink

[0082] 21: First conductive column

[0083] 22: Second conductive column

[0084] 23: Conductive gasket

[0085] 24: The third conductive layer

[0086] 25: Gasket DETAILED DESCRIPTION

[0087] Some embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different aspects without departing from the scope of the present invention, and the descriptions and drawings are essentially for illustrative purposes rather than for limiting the present invention.

[0088] See also Figure 1A and Figure 1B ,in Figure 1A is a schematic cross-sectional view of the packaging structure of the first embodiment of the present invention, Figure 1B FIG. 1 is a schematic diagram of a cross-sectional structure of a packaging structure including a heat dissipation device according to the first embodiment of the present invention. Figure 1A and Figure 1B As shown, the package structure 1 includes at least one semiconductor chip 11 , a plurality of metal pins 12 , a first conductive layer 13 , a second conductive layer 14 , a second insulating layer 15 , a first package component 17 and a second package component 16 .

[0089] The semiconductor chip 11 may be an active component or a passive component. The semiconductor chip 11 may be, for example but not limited to, an integrated circuit (IC) chip, an integrated power device, a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (HEMT), an insulated gate bipolar transistor (IGBT), a diode, a capacitor, a resistor, an inductor or a fuse. The semiconductor chip 11 includes a first surface 111, a second surface 112 and a plurality of conductive terminals, such as at least one first conductive terminal 113 and at least one second conductive terminal 114. The first surface 111 is opposite to the second surface 112. In the present embodiment, the semiconductor chip 11 is a lateral device and is disposed on the first conductive layer 13 in a flip chip manner, wherein at least one first conductive terminal 113 and at least one second conductive terminal 114 are disposed on the second surface 112 of the semiconductor chip 11. In other embodiments, the semiconductor chip 11 is a vertical device and includes other conductive terminals located on the first surface 111. The metal pin 12 includes a first surface 121 and a second surface 122 , and the first surface 121 is opposite to the second surface 122 .

[0090] At least one semiconductor chip 11 is disposed between the first package component 17 and the second package component 16. The first conductive layer 13, the second conductive layer 14 and the second insulating layer 15 are disposed between the first package component 17 and the second package component 16 to stabilize the first package component 17, the second package component 16, the at least one semiconductor chip 11 and the plurality of metal pins 12. The plurality of metal pins 12 are disposed between the first package component 17 and the second package component 16 and extend outward from the first package component 17 and the second package component 16 respectively. The plurality of metal pins 12 are electrically connected to a plurality of conductive terminals, such as at least one first conductive terminal 113 and at least one second conductive terminal 114 respectively. In this embodiment, a portion of the first conductive layer 13 is connected between the second package component 16 and the first surface 111 of the semiconductor chip 11, and another portion of the first conductive layer 13 is connected between the second package component 16 and the first surface 121 of a portion of the metal pins 12, and another portion of the first surface 121 of the metal pins 12 is exposed. In this embodiment, the second conductive layer 14 includes a first portion 14a, a second portion 14b and a third portion 14c which are separated from each other. The first portion 14a is disposed between the first packaging component 17 and a portion of the second surface 112 of the semiconductor chip 11, and the first portion 14a is in contact with at least one first conductive terminal 113 of the semiconductor chip 11. The second portion 14b is disposed between the first packaging component 17 and another portion of the second surface 112 of the semiconductor chip 11, and the second portion 14b is in contact with at least one second conductive terminal 114 of the semiconductor chip 11. The third portion 14c is disposed between the first packaging component 17 and a portion of the second surface 122 of the metal pin 12, and the second surface 122 of the other portion of the metal pin 12 is exposed.

[0091] In this embodiment, the second insulating layer 15 includes a first portion 15a, a second portion 15b and a third portion 15c. The first portion 15a is disposed between the first package component 17, the first portion 14a of the second conductive layer 14, the second portion 14b of the second conductive layer 14 and the semiconductor chip 11, the second portion 15b is disposed between the semiconductor chip 11, the metal pin 12, the first package component 17 and the second package component 16, and the third portion 15c is disposed between the semiconductor chip 11, the first package component 17 and the second package component 16. The second insulating layer 15 can be formed of, for example but not limited to, a suitable insulating material with high thermal conductivity.

[0092] The first package component 17 includes a first metal layer 171, a first insulating layer 172 and a second metal layer 173. The first metal layer 171 is formed on the first insulating layer 172, and the first insulating layer 172 is formed on the second metal layer 173, so the first insulating layer 172 is formed between the first metal layer 171 and the second metal layer 173. In this embodiment, the first metal layer 171 is in contact with the second conductive layer 14 and the second insulating layer 15, and one side of the second metal layer 173 is exposed. In some embodiments, the first package component 17 is an insulating metal substrate, such as but not limited to a direct bonding copper substrate. The first insulating layer 172 can be formed of, for example but not limited to, a suitable insulating material with a high thermal conductivity. In some embodiments, the package structure 1 further includes a first heat dissipation device h1, which is disposed on the exposed side of the second metal layer 173 to dissipate heat from the package structure 1 along a first heat dissipation channel. The first heat dissipation device h1 can be, but not limited to, a heat sink, a liquid cooling device or a heat pipe.

[0093] The second package component 16 includes a third metal layer 161, a third insulating layer 162, and a fourth metal layer 163. The third insulating layer 162 is formed on the third metal layer 161, and the fourth metal layer 163 is formed on the third insulating layer 162. The third metal layer 161 is in contact with the first conductive layer 13 and the second insulating layer 15, and one side of the fourth metal layer 163 is exposed. The second package component 16 includes a first surface 16a and a second surface 16b. The first surface 16a is opposite to the second surface 16b. The first surface 16a of the second package component 16 is in contact with the first conductive layer 13 and the second insulating layer 15, and the second surface 16b of the second package component 16 is exposed. In some embodiments, the second package component 16 is an insulating metal substrate, such as but not limited to a direct bonding copper substrate. In some embodiments, the package structure 1 further includes a second heat dissipation device h2, which is disposed on the second surface 16b of the second package component 16 to dissipate heat from the package structure 1 along a second heat dissipation channel. The second heat dissipation device h2 may be, but is not limited to, a heat sink, a liquid cooling device or a heat pipe.

[0094] As can be seen from the above, since one side of the first packaging component 17 is exposed and connected to the first heat sink h1, and one side of the second packaging component 16 is exposed and connected to the second heat sink h2, the packaging structure 1 of this case uses a double-sided cooling mechanism to dissipate heat energy. Compared with the traditional packaging structure, the heat dissipation efficiency of the packaging structure 1 of this case is improved.

[0095] In the present embodiment, the first metal layer 171 includes a first portion 171a, a second portion 171b and at least one first groove 174. The first portion 171a and the second portion 171b are separated from each other by at least one first groove 174. The first portion 14a of the second conductive layer 14 is disposed in the first groove 174 and connected between the first portion 171a of the first metal layer 171 and at least one first conductive terminal 113 of the semiconductor chip 11. The second portion 14b of the second conductive layer 14 is disposed in the first groove 174 and connected between the second portion 171b of the first metal layer 171 and at least one second conductive terminal 114 of the semiconductor chip 11. In some embodiments, the height of the first groove 174 is determined according to the thickness of the semiconductor chip 11, and the first surface 111 of the semiconductor chip 11 is maintained coplanar with the upper surface of the first metal layer 171, so as to facilitate the combination of the first package component 17 and the second package component 16. The third metal layer 161 includes at least one first protrusion 164 disposed at a corresponding position of the first groove 174. In addition, the first metal layer 171 further includes a second groove 175, which is disposed in the first groove 174. The first portion 15a of the second insulating layer 15 is disposed in the second groove 175 and is disposed between the first insulating layer 172 of the first package element 17, the first portion 171a of the first metal layer 171, the second portion 171b of the first metal layer 171, the first portion 14a of the second conductive layer 14, the second portion 14b of the second conductive layer 14, and a portion of the second surface 112 of the semiconductor chip 11. Therefore, the first portion 171a and the second portion 171b of the first metal layer 171 are separated from each other. The semiconductor chip 11 is accommodated in the first groove 174, and the first surface 111 of the semiconductor chip 11 is coplanar with a surface of the first metal layer 171. Since the first metal layer 171 includes at least one first groove 174, the semiconductor chip 11 is accommodated in the first groove 174 and connected to the metal pin 12 via the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171 and the third portion 14c of the second conductive layer 14, the package structure 1 can have a thinner thickness and make the embedded flip-chip semiconductor chip 11 have better pressure resistance. In addition, the line width / line spaceratio of the conductive line of the package structure 1 is also better.

[0096] In some embodiments, the package structure 1 further includes at least one insulating structure 18, which is disposed on the sides of the first package component 17 and the second package component 16 and surrounds a portion of the metal pins 12. A portion of the metal pins 12 is disposed between the first conductive layer 13 and the third portion 14c of the second conductive layer 14, another portion of the metal pins 12 is embedded in the insulating structure 18, and another portion of the metal pins 12 is exposed. The metal pins 12 are connected to at least one first conductive terminal 113 of the semiconductor chip 11 through the third portion 14c of the second conductive layer 14, the first portion 171a of the first metal layer 171, and the first portion 14a of the second conductive layer 14, so that the metal pins 12 can be regarded as the lead-out terminal of the package structure 1. In some embodiments, the material type of the insulating structure 18 is the same as the material type of the second insulating layer 15. In other embodiments, the material type of the insulating structure 18 is different from the material type of the second insulating layer 15.

[0097] In this embodiment, the number of at least one semiconductor chip 11 is two, and the two semiconductor chips 11 are horizontally arranged between the first package component 17 and the second package component 16. It should be noted that the number of at least one semiconductor chip 11 is not limited to the above two, and can be changed according to actual needs.

[0098] See also FIG. 2A to FIG. 2E ,in FIG. 2A to FIG. 2E for Figure 1A The cross-sectional structure diagram of the packaging method of the packaging structure is shown in FIG. Figure 2A As shown, a first package component 17 and a second package component 16 are provided. In the present embodiment, the first package component 17 includes a first metal layer 171, a first insulating layer 172 and a second metal layer 173, wherein the first metal layer 171 is formed on the first insulating layer 172, and the first insulating layer 172 is formed on the second metal layer 173, so the first insulating layer 172 is formed between the first metal layer 171 and the second metal layer 173. The second package component 16 includes a third metal layer 161, a third insulating layer 162 and a fourth metal layer 163, wherein the fourth metal layer 163 is formed on the third insulating layer 162, and the third insulating layer 162 is formed on the third metal layer 161.

[0099] Then, if Figure 2BAs shown, the first package component 17 and the second package component 16 are respectively formed by a patterning process. In this embodiment, the patterning process may include a stage etching process. In addition, the patterning process may also include an etching process and a metal plating process. In this embodiment, at least one first groove 174 and at least one second groove 175 are formed on the first metal layer 171 of the first package component 17, and at least one first protrusion 164 is formed on the third metal layer 161 of the second package component 16 and is disposed at a corresponding position of the first groove 174. The second groove 175 is located in the first groove 174, and a portion of the first insulating layer 172 is exposed through the first groove 174 and the second groove 175. The first metal layer 171 includes a first portion 171a and a second portion 171b separated from each other by the first groove 174 and the second groove 175.

[0100] Then, if Figure 2C As shown, at least one semiconductor chip 11, at least one metal pin 12, a first conductive layer 13 and a second conductive layer 14 are provided, and the at least one semiconductor chip 11, at least one metal pin 12, the first conductive layer 13 and the second conductive layer 14 are disposed between a first package component 17 and a second package component 16. In this embodiment, a portion of the first conductive layer 13 is disposed between the third metal layer 161 of the second package component 16 and the first surface 111 of the semiconductor chip 11, and another portion of the first conductive layer 13 is disposed between the third metal layer 161 of the second package component 16 and the first surface 121 of a portion of the metal pin 12. The second conductive layer 14 includes a first portion 14a, a second portion 14b, and a third portion 14c that are separated from each other. The first portion 14a is disposed between the first portion 171a of the first metal layer 171 and at least one first conductive terminal 113 of the semiconductor chip 11, the second portion 14b is disposed between the second portion 171b of the first metal layer 171 and at least one second conductive terminal 114 of the semiconductor chip 11, and the third portion 14c is disposed between the first portion 171a of the first metal layer 171 and a portion of the second surface 122 of the metal pin 12. The semiconductor chip 11 is disposed at the positions corresponding to the first protrusion 164 and the first groove 174. In this embodiment, the first conductive layer 13 and the second conductive layer 14 can be, but are not limited to, conductive liquid or conductive film.

[0101] Then, if Figure 2DAs shown, a pressing process and a curing process are performed to combine at least one semiconductor chip 11, at least one metal pin 12, a first conductive layer 13, a second conductive layer 14, a first package component 17, and a second package component 16. In this embodiment, a portion of the first conductive layer 13 is connected to the first protrusion 164 of the third metal layer 161 and the first surface 111 of the semiconductor chip 11, another portion of the first conductive layer 13 is connected to the third metal layer 161 and the first surface 121 of the metal pin 12, a first portion 14a of the second conductive layer 14 is connected between the first portion 171a of the first metal layer 171 and at least one first conductive terminal 113 of the semiconductor chip 11, a second portion 14b of the second conductive layer 14 is connected between the second portion 171b of the first metal layer 171 and at least one second conductive terminal 114 of the semiconductor chip 11, and a third portion 14c of the second conductive layer 14 is connected between the first portion 171a of the first metal layer 171 and the second surface 122 of the metal pin 12. The semiconductor chip 11 is accommodated in the first cavity 174 , and the first surface 111 of the semiconductor chip 11 is coplanar with a surface of the first metal layer 171 .

[0102] Then, if Figure 2EAs shown, a filling process is performed so that the second insulating layer 15 is disposed between the first package component 17 and the second package component 16. Then, at least one insulating structure 18 is formed on the side of the first package component 17 and the second package component 16 and surrounds a portion of the metal pins 12 so that a portion of the metal pins 12 is exposed to form a package structure 1. In this embodiment, the second insulating layer 15 includes a first portion 15a, a second portion 15b and a third portion 15c. The first portion 15a is disposed between the first portion 171a of the first metal layer 171, the second portion 171b of the first metal layer 171, a portion of the first insulating layer 172, the first portion 14a of the second conductive layer 14, the second portion 14b of the second conductive layer 14 and a portion of the second surface 112 of the semiconductor chip 11; the second portion 15b is disposed between the semiconductor chip 11, the metal pin 12, the first conductive layer 13, the third metal layer 161, the first portion 171a of the first metal layer 171, the first portion 14a of the second conductive layer 14 and the third portion 14c of the second conductive layer 14; and the third portion 15c is disposed between the semiconductor chip 11, the third metal layer 161, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14 and the first conductive layer 13. In this embodiment, part of the metal pin 12 is disposed between the first conductive layer 13 and the third portion 14c of the second conductive layer 14, another part of the metal pin 12 is embedded in the insulating structure 18, and another part of the metal pin 12 is exposed. The metal pin 12 is connected to at least one first conductive terminal 113 of the semiconductor chip 11 via the third portion 14c of the second conductive layer 14, the first portion 171a of the first metal layer 171, and the first portion 14a of the second conductive layer 14, so that the metal pin 12 can be regarded as the lead-out end of the package structure 1 to form the package structure 1. As can be seen from the above, the insulating structure 18 is formed after the second insulating layer 15 is formed. In some embodiments, the second insulating layer 15 and the insulating structure 18 are formed simultaneously and in the same step.

[0103] See also Figure 3 ,in Figure 3 FIG. 2 is a schematic diagram of a cross-sectional structure of a packaging structure of a second embodiment of the present invention. In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Figure 3As shown, compared with the package structure 1 of FIG. 1 , the package structure 1a of the present embodiment further includes at least one first conductive pillar 21 and a plurality of second conductive pillars 22. The semiconductor chip 11 includes at least one first conductive terminal 113 and a plurality of second conductive terminals 114, the first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11, and the first protrusion 164 of the third metal layer 16 of FIG. 1 is omitted and does not need to be provided. In the present embodiment, at least one first conductive pillar 21 is disposed in the first groove 174 and connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14, and each second conductive pillar 22 is disposed in the first groove 174 and connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. In addition, the first surface 111 of the semiconductor chip 11 and the first surface 121 of the metal pin 12 are coplanar. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1a is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1a, so that the problem of chip adhesive material short circuit can be prevented.

[0104] In some embodiments, a surface treatment is performed between the first conductive terminal 113 of the semiconductor chip 11 and the first conductive pillar 21 to connect the first conductive terminal 113 of the semiconductor chip 11 and the first conductive pillar 21. A surface treatment is also performed between the second conductive terminal 114 of the semiconductor chip 11 and the second conductive pillar 22 to connect the second conductive terminal 114 of the semiconductor chip 11 and the second conductive pillar 22. In some embodiments, a solder ball is disposed between the first conductive pillar 21 and the first portion 14a of the second conductive layer 14 to connect the first conductive pillar 21 and the first portion 14a of the second conductive layer 14. A solder ball is also disposed between the second conductive pillar 22 and the second portion 14b of the second conductive layer 14 to connect the second conductive pillar 22 and the second portion 14b of the second conductive layer 14. In some embodiments, the first metal layer 171 is designed as multiple components. The pad 25 is formed between the first metal layer 171 and the third metal layer 161 to be electrically connected to a portion of the first metal layer 171 and the third metal layer 161 according to the circuit design.

[0105] See also Figure 4 ,in Figure 4 FIG. 2 is a schematic diagram of a cross-sectional structure of a package structure of a third embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Figure 4 As shown, compared to Figure 3 The package structure 1a of the present embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminals 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0106] See also Figure 5 ,in Figure 5 FIG. 4 is a schematic diagram of a cross-sectional structure of a packaging structure of a fourth embodiment of the present invention. In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Figure 5 As shown, compared with the packaging structure 1 of Figure 1, the first metal layer 171 of the packaging structure 1c of this embodiment further includes at least one recess 176, which is arranged around the first packaging element 17, and the third metal layer 161 further includes at least one second protrusion 165, which corresponds to the setting position of the recess 176 of the first metal layer 171. A portion of the metal pin 12 is arranged in the recess 176, and the semiconductor chip 11 is arranged in the first groove 174. The first surface 111 of the semiconductor chip 11 is coplanar with the first surface 121 of the metal pin 12.

[0107] See also Figure 6 ,in Figure 6 FIG. 5 is a schematic diagram of a cross-sectional structure of a packaging structure of the fifth embodiment of the present invention. In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Figure 6 As shown, compared to Figure 5 The package structure 1c of the present embodiment further comprises at least one first conductive pillar 21 and a plurality of second conductive pillars 22. The semiconductor chip 11 comprises at least one first conductive terminal 113 and a plurality of second conductive terminals 114. The first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, and the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11. In the present embodiment, at least one conductive pillar 21 is disposed in the first groove 174 and connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14. Each second conductive pillar 22 is disposed in the first groove 174 and connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. The first surface 111 of the semiconductor chip 11 is coplanar with the first surface 121 of the metal pin 12. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1d is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1d, so that the problem of chip adhesive material short circuit can be prevented.

[0108] See also Figure 7 ,in Figure 7 FIG. 6 is a schematic diagram of a cross-sectional structure of a package structure of a sixth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Figure 7 As shown, compared to Figure 6The package structure 1e of this embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0109] See also Figure 8 ,in Figure 8 FIG. 2 is a schematic diagram of a cross-sectional structure of a packaging structure of the seventh embodiment of the present invention. In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Figure 8 As shown, compared with the package structure 1 of FIG. 1 , the package structure 1f of the present embodiment further includes a conductive pad 23 and a third conductive layer 24, and the first protrusion 164 of the third metal layer 16 of FIG. 1 is omitted and does not need to be provided. The conductive pad 23 is provided between the semiconductor chip 11 and the third metal layer 161 of the second package component 16, the first conductive layer 13 is connected between the semiconductor chip 11 and the conductive pad 23, the third conductive layer 24 is connected between the conductive pad 23 and the third metal layer 161, and a surface of the conductive pad 23 is coplanar with the first surface 121 of the metal pin 12.

[0110] See also Fig. 9 ,in Fig. 9 FIG. 8 is a schematic diagram of a cross-sectional structure of a package structure of an eighth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig. 9 As shown, compared to Figure 8The package structure 1f of the present embodiment further comprises at least one first conductive pillar 21 and a plurality of second conductive pillars 22, and the semiconductor chip 11 comprises at least one first conductive terminal 113 and a plurality of second conductive terminals 114. The first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, and the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11. In the present embodiment, at least one first conductive pillar 21 is disposed in the first groove 174 and connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14, and each second conductive pillar 22 is disposed in the first groove 174 and connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1g is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1g, so that the problem of chip adhesive material short circuit can be prevented.

[0111] See also Fig.10 ,in Fig.10 FIG. 9 is a schematic diagram of a cross-sectional structure of a ninth embodiment of the present invention. In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.10 As shown, compared to Fig. 9 The package structure 1g of the present embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminals 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0112] See also Fig.11 ,in Fig.11FIG. 1 is a schematic diagram of a cross-sectional structure of a package structure of the tenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.11 As shown, compared to Figure 5 The second package component 16 of the package structure 1i of this embodiment only includes the third metal layer 161, and Figure 5 The third insulating layer 162 and the fourth metal layer 163 are omitted and do not need to be set. One side of the third metal layer 161 is in contact with the first conductive layer 13 and the second insulating layer 15, and the other side of the third metal layer 161 is exposed. The second portion 15b of the second insulating layer 15 is further disposed between the first surface 121 of the metal pin 12 and the third metal layer 161. The semiconductor chip 11 is disposed in the first groove 174, and part of the metal pin 12 is disposed in the recess 176. The first surface 111 of the semiconductor chip 11 is coplanar with the first surface 121 of the metal pin 12. Since the second packaging element 16 of the packaging structure 1i only includes the third metal layer 161, the heat dissipation efficiency of the packaging structure 1i is better.

[0113] See also Fig.12 ,in Fig.12 FIG. 1 is a schematic diagram of a cross-sectional structure of the package structure of the eleventh embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.12 As shown, compared to Fig.11The package structure 1i of the present embodiment further comprises at least one first conductive pillar 21 and a plurality of second conductive pillars 22, and the semiconductor chip 11 comprises at least one first conductive terminal 113 and a plurality of second conductive terminals 114. The first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, and the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11. In the present embodiment, at least one first conductive pillar 21 is disposed in the first groove 174 and connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14, and each second conductive pillar 22 is disposed in the first groove 174 and connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1j is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1j, so that the problem of chip adhesive material short circuit can be prevented.

[0114] See also Fig.13 ,in Fig.13 FIG. 1 is a schematic diagram of a cross-sectional structure of a package structure of the twelfth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.13 As shown, compared to Fig.12 The package structure 1j of the present embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminals 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0115] See also Fig.14 ,in Fig.14FIG. 1 is a schematic diagram of a cross-sectional structure of a package structure of the thirteenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.14 As shown, compared with the package structure 1 of FIG. 1 , the metal pin 12 of the package structure 11 of the present embodiment includes a first portion 123 and a second portion 124. Part of the first portion 123 is disposed between the first conductive layer 13 and the third portion 14c of the second conductive layer 14, another part of the first portion 123 is embedded in the insulating structure 18, and another part of the first portion 123 is exposed. The second portion 124 is vertically connected to one end of the first portion 123 and extends outward, so that the first portion 123 and the second portion 124 form an L shape. In the present embodiment, the second portion 124 of the metal pin 12 can be inserted into a corresponding hole on a circuit board (not shown).

[0116] See also Fig.15 ,in Fig.15 FIG. 1 is a schematic cross-sectional view of the package structure of the fourteenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.15 As shown, compared to Fig.14The package structure 11 of the present embodiment further comprises at least one first conductive pillar 21 and a plurality of second conductive pillars 22, and the semiconductor chip 11 comprises at least one first conductive terminal 113 and a plurality of second conductive terminals 114. The first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, and the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11. In the present embodiment, at least one first conductive pillar 21 is disposed in the first groove 174 and connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14, and each second conductive pillar 22 is disposed in the first groove 174 and connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1m is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1m, so that the problem of chip adhesive material short circuit can be prevented.

[0117] See also Fig.16 ,in Fig.16 FIG. 1 is a schematic diagram of a cross-sectional structure of a package structure of the fifteenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.16 As shown, compared to Fig.15 The package structure 1m of the present embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminals 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0118] See also Fig.17A and Fig. 17B , Fig.17A is a schematic cross-sectional structural diagram of the packaging structure of the sixteenth embodiment of the present invention, Fig. 17B for Fig.17A In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.17A and Fig. 17B As shown, compared with the package structure 1 of FIG. 1 , the package structure 1o of the present embodiment further includes a housing 19, and the housing 19 includes a housing space 191 and an opening 192. The opening 192 is connected to the housing space 191, and the housing 19 covers the second package component 16, the insulating structure 18, and a portion of the metal pins 12, so that the second package component 16 and the insulating structure 18 are connected to the housing space 191 of the housing 19. A portion of the second package component 16 is exposed through the opening 192 to dissipate heat along the second heat dissipation channel, so that the heat dissipation efficiency of the package structure 1o can be improved, and the package structure 1o can use the housing 19 to reduce collisions.

[0119] See also Fig.18 ,in Fig.18 FIG. 1 is a schematic diagram of a cross-sectional structure of a package structure of the seventeenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.18 As shown, compared to Fig.17AThe package structure 1o of the present embodiment further comprises at least one first conductive pillar 21 and a plurality of second conductive pillars 22, and the semiconductor chip 11 comprises at least one first conductive terminal 113 and a plurality of second conductive terminals 114. The first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, and the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11. In the present embodiment, at least one first conductive pillar 21 is disposed in the first groove 174 and connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14, and each second conductive pillar 22 is disposed in the first groove 174 and connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1p is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1p, so that the problem of chip adhesive material short circuit can be prevented.

[0120] See also Fig.19 ,in Fig.19 FIG. 1 is a schematic diagram of a cross-sectional structure of the package structure of the eighteenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.19 As shown, compared to Fig.18 The package structure 1p of the present embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminals 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0121] See also Fig. 20 ,in Fig. 20FIG. 1 is a schematic diagram of a cross-sectional structure of a package structure of the nineteenth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig. 20 As shown, compared with the package structure 1 of FIG. 1 , the first metal layer 171 of the package structure 1r of the present embodiment includes at least one second groove 175 and at least one third groove 177, and at least one first groove 174 is omitted and does not need to be provided. A portion of the first insulating layer 172 is exposed through the at least one second groove 175 and the at least one third groove 177. The third metal layer 161 includes at least one fourth groove 166, and the first protrusion 164 is omitted and does not need to be provided. A portion of the third insulating layer 162 is exposed through the at least one fourth groove 166, and the at least one third groove 177 corresponds to the setting position of the at least one fourth groove 166. The third portion 15c of the second insulating layer 15 is disposed in the third groove 177 and the fourth groove 166, that is, the third portion 15c of the second insulating layer 15 is disposed on the first insulating layer 172, the third insulating layer 162, the first conductive layer 13, the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. In this embodiment, the first surface 111 of the semiconductor chip 11 and the first surface 121 of the metal pin 12 are coplanar.

[0122] See also FIG. 21A to FIG. 21E ,in FIG. 21A to FIG. 21E for Fig. 20 The cross-sectional structure diagram of the packaging method of the packaging structure is shown in FIG. Fig.21A As shown, a first package 17 and a second package component 16 are provided. In the present embodiment, the first package component 17 includes a first metal layer 171, a first insulating layer 172 and a second metal layer 173, wherein the first metal layer 171 is formed on the first insulating layer 172, and the first insulating layer 172 is formed on the second metal layer 173, so the first insulating layer 172 is formed between the first metal layer 171 and the second metal layer 173. The second package component 16 includes a third metal layer 161, a third insulating layer 162 and a fourth metal layer 163, wherein the fourth metal layer 163 is formed on the third insulating layer 162, and the third insulating layer 162 is formed on the third metal layer 161.

[0123] Then, if Fig. 21BAs shown, the first package component 17 and the second package component 16 are formed by a patterning process. In this embodiment, the patterning process may include a stage etching process. In this embodiment, at least one second groove 175 and at least one third groove 177 are formed in the first metal layer 171 of the first package component 17, and at least one fourth groove 166 is formed in the third metal layer 161 of the second package component 16. The at least one fourth groove 166 corresponds to the location of the at least one third groove 177. A portion of the first insulating layer 172 is exposed through the second groove 175 and the third groove 177, and a portion of the third insulating layer 162 is exposed through the fourth groove 166. The first metal layer 171 includes a first portion 171a and a second portion 171b. The first portion 171a and the second portion 171b are separated from each other by the second groove 175.

[0124] Then, if Fig. 21C As shown, at least one semiconductor chip 11, at least one metal pin 12, a first conductive layer 13 and a second conductive layer 14 are provided, and the at least one semiconductor chip 11, at least one metal pin 12, the first conductive layer 13 and the second conductive layer 14 are disposed between a first package component 17 and a second package component 16. In this embodiment, a portion of the first conductive layer 13 is disposed between the third metal layer 161 of the second package component 16 and the first surface 111 of the semiconductor chip 11, and another portion of the first conductive layer 13 is disposed between the third metal layer 161 of the second package component 16 and the first surface 121 of the metal pin 12. The second conductive layer 14 includes a first portion 14a, a second portion 14b, and a third portion 14c that are separated from each other. The first portion 14a is disposed between the first portion 171a of the first metal layer 171 and at least one first conductive terminal 113 of the semiconductor chip 11, the second portion 14b is disposed between the second portion 171b of the first metal layer 171 and at least one second conductive terminal 114 of the semiconductor chip 11, and the third portion 14c is disposed between the first portion 171a of the first metal layer 171 and the second surface 122 of the metal pin 12. The semiconductor chip 11 is disposed between the first metal layer 171 and the third metal layer 161. In this embodiment, the first conductive layer 13 and the second conductive layer 14 may be, but are not limited to, conductive liquid or conductive film.

[0125] Then, if Fig.21DAs shown, a pressing process and a curing process are performed to combine at least one semiconductor chip 11, at least one metal pin 12, a first conductive layer 13, a second conductive layer 14, a first package component 17, and a second package component 16. In this embodiment, a portion of the first conductive layer 13 is connected between the third metal layer 161 of the second package component 16 and the first surface 111 of the semiconductor chip 11, and another portion of the first conductive layer 13 is connected between the third metal layer 161 of the second package component 16 and the first surface 121 of the metal pin 12. The first portion 14a is connected between the first portion 171a of the first metal layer 171 and at least one first conductive terminal 113 of the semiconductor chip 11, the second portion 14b is connected between the second portion 171b of the first metal layer 171 and at least one second conductive terminal 114 of the semiconductor chip 11, and the third portion 14c is connected between the first portion 171a of the first metal layer 171 and the second surface 122 of the metal pin 12, and the first surface 111 of the semiconductor chip 11 is coplanar with the first surface 121 of the metal pin 12.

[0126] Then, if Fig.21EAs shown, a filling process is performed so that the second insulating layer 15 is disposed between the first package component 17 and the second package component 16. Then, at least one insulating structure 18 is formed on the side of the first package component 17 and the second package component 16 and surrounds a portion of the metal pins 12, so that a portion of the metal pins 12 are exposed to form a package structure 1r. In this embodiment, the second insulating layer 15 includes a first portion 15a, a second portion 15b and a third portion 15c. The first portion 15a is disposed between the first portion 171a of the first metal layer 171, the second portion 171b of the first metal layer 171, a portion of the first insulating layer 172, the first portion 14a of the second conductive layer 14, the second portion 14b of the second conductive layer 14 and a portion of the second surface 112 of the semiconductor chip 11. The second portion 15b is disposed between the semiconductor chip 11, the metal pins 12, the first conductive layer 13, the third portion 15c of the second package component 16, and the third portion 15c. The third portion 15c is disposed between the metal layer 161, the first portion 171a of the first metal layer 171, the first portion 14a of the second conductive layer 14, and the third portion 14c of the second conductive layer 14, and the third portion 15c is disposed between the third groove 177 and the fourth groove 166, and the third portion 15c is disposed between the semiconductor chip 11, the third metal layer 161 of the second package component 16, the third insulating layer 162 of the second package component 16, the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the first conductive layer 13. In this embodiment, a portion of the metal pin 12 is disposed between the first conductive layer 13 and the third portion 14c of the second conductive layer 14, another portion of the metal pin 12 is embedded in the insulating structure 18, and another portion of the metal pin 12 is exposed. The metal pin 12 is connected to at least one first conductive terminal 113 of the semiconductor chip 11 through the third portion 14c of the second conductive layer 14, the first portion 171a of the first metal layer 171 and the first portion 14a of the second conductive layer 14, so that the metal pin 12 can be regarded as the lead-out terminal of the package structure 1r to form the package structure 1r.

[0127] See also Fig. 22 ,in Fig. 22 FIG. 2 is a schematic diagram of a cross-sectional structure of a package structure of the twentieth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig. 22 As shown, compared to Fig. 20The package structure 1r of the present embodiment further comprises at least one first conductive pillar 21 and a plurality of second conductive pillars 22. The semiconductor chip 11 comprises at least one first conductive terminal 113 and a plurality of second conductive terminals 114. The first conductive pillar 21 is connected to the first conductive terminal 113 of the semiconductor chip 11, and the plurality of second conductive pillars 22 are connected to the plurality of second conductive terminals 114 of the semiconductor chip 11. In the present embodiment, at least one first conductive pillar 21 is connected between the first conductive terminal 113 of the semiconductor chip 11 and the first portion 14a of the second conductive layer 14, and each second conductive pillar 22 is connected between the corresponding second conductive terminal 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14. In addition, the first surface 111 of the semiconductor chip 11 and the first surface 121 of the metal pin 12 are coplanar. The first portion 15a of the second insulating layer 15 is disposed between the semiconductor chip 11, the first conductive pillar 21, the first portion 14a of the second conductive layer 14, the first portion 171a of the first metal layer 171, a portion of the first insulating layer 172, the second portion 171b of the first metal layer 171, the second portion 14b of the second conductive layer 14, and the second conductive pillar 22. In one embodiment, the first conductive pillar 21 is a copper pillar, and the second conductive pillar 22 is a copper pillar. Since the first conductive terminal 113 of the semiconductor chip 11 is connected to the first portion 14a of the second conductive layer 14 via the first conductive pillar 21, and the second conductive terminal 114 of the semiconductor chip 11 is connected to the second portion 14b of the second conductive layer 14 via a plurality of second conductive pillars 22, the semiconductor chip 11 is not directly connected to the second conductive layer 14, and thus the line width / line space ratio of the conductive circuit of the package structure 1s is also better. In addition, at least one ultra-thin flip chip IC is embedded in the package structure 1s, so that the problem of chip adhesive material short circuit can be prevented.

[0128] See also Fig.23 ,in Fig.23 FIG. 2 is a schematic diagram of a cross-sectional structure of a package structure of the twenty-first embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.23 As shown, compared to Fig. 22 The package structure 1s of the present embodiment includes a single first conductive pillar 21 and a single second conductive pillar 22. The second conductive pillar 22 is connected between the second conductive terminals 114 of the semiconductor chip 11 and the second portion 14b of the second conductive layer 14.

[0129] See also Fig.24 ,in Fig.24FIG. 2 is a schematic diagram of a cross-sectional structure of a packaging structure of the twenty-second embodiment of the present invention. In this embodiment, the components and elements of the packaging structure are similar to those of the packaging structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.24 As shown, compared to Fig. 20 The package structure 1r of the present embodiment further comprises a conductive pad 23 and a third conductive layer 24, and the second package component 16 comprises only a third metal layer 161. Fig. 20 The third insulating layer 162 and the fourth metal layer 163 are omitted and do not need to be set. One side of the third metal layer 161 is in contact with the third conductive layer 24 and the second insulating layer 15, and the other side of the third metal layer 161 is exposed. Since the second package component 16 of the package structure 1u only includes the third metal layer 161, the heat dissipation efficiency of the package structure 1u is better. The conductive gasket 23 is arranged between the semiconductor chip 11 and the third metal layer 161 of the second package component 16, the first conductive layer 13 is connected between the semiconductor chip 11 and the conductive gasket 23, and the third conductive layer 24 is connected between the conductive gasket 23 and the third metal layer 161.

[0130] See also Fig.25 ,in Fig.25 FIG. 2 is a schematic diagram of a cross-sectional structure of a package structure of the twenty-third embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.25 As shown, compared to Fig. 20 The metal pin 12 of the package structure 1v of the present embodiment includes a first portion 123 and a second portion 124. A portion of the first portion 123 is disposed between the first conductive layer 13 and the third portion 14c of the second conductive layer 14, another portion of the first portion 123 is embedded in the insulating structure 18, and another portion of the first portion 123 is exposed. The second portion 124 is vertically connected to one end of the first portion 123 and extends outward, so that the first portion 123 and the second portion 124 form an L shape. In the present embodiment, the second portion 124 of the metal pin 12 can be inserted into a corresponding hole on a circuit board (not shown).

[0131] See also Fig.26 ,in Fig.26 FIG. 2 is a schematic diagram of a cross-sectional structure of a package structure of the twenty-fourth embodiment of the present invention. In this embodiment, the components and elements of the package structure are similar to those of the package structure of the first embodiment, wherein the same component symbols represent the same components and are not described in detail herein. Fig.26 As shown, compared to Fig. 20The package structure 1r of the present embodiment further includes a housing 19, and the housing 19 includes a housing space 191 and an opening 192. The opening 192 is connected to the housing space 191, and the housing 19 covers the second package component 16, the insulating structure 18 and part of the metal pin 12, so that the second package component 16 and the insulating structure 18 are connected to the housing space 191 of the housing 19. Part of the second package component 16 is exposed through the opening 192 to dissipate heat along the second heat dissipation channel, so the heat dissipation efficiency of the package structure 1w can be improved, and the package structure 1w can use the housing 19 to reduce collision.

[0132] In summary, the embodiments of the present invention provide a packaging structure, in which at least one semiconductor chip is disposed between a first packaging component and a second packaging component, and a double-sided cooling mechanism is used to dissipate heat energy. Therefore, the packaging structure of the present invention has better heat dissipation efficiency, and the structure is simpler, and can be applied to flip-chip semiconductor chips. In addition, the first conductive terminal of the semiconductor chip is connected to the first part of the second conductive layer via a first conductive column, and the second conductive terminal of the semiconductor chip is connected to the second part of the second conductive layer via at least one second conductive column, so that the semiconductor chip is not directly connected to the second conductive layer, so the line width / line space ratio of the conductive line of the packaging structure is also better. In addition, at least one ultra-thin flip-chip IC is embedded in the packaging structure, so that the problem of chip adhesive material short circuit can be prevented.

Claims

1. A packaging structure, comprising: A first packaging component comprises a first metal layer, a first insulating layer, and a second metal layer, wherein the first insulating layer is formed between the first metal layer and the second metal layer, and the first metal layer comprises at least one first groove; A second packaging component includes a third metal layer, wherein the third metal layer includes at least one first protrusion and is disposed at a corresponding position of the at least one first groove; At least one semiconductor chip is disposed between the first packaging component and the second packaging component, and the at least one semiconductor chip includes a plurality of conductive terminals, and the plurality of conductive terminals are connected to the first metal layer or the third metal layer; A plurality of metal pins are disposed between the second packaging component and the first packaging component and extend outward from the second packaging component and the first packaging component, and the plurality of metal pins are electrically connected to the plurality of conductive terminals respectively; as well as A second insulating layer is disposed between the first packaging component and the second packaging component to stabilize the first packaging component, the second packaging component, the at least one semiconductor chip and the plurality of metal pins.

2. The packaging structure as claimed in claim 1, wherein the first metal layer is formed on the first insulating layer and includes a first portion and a second portion separated from each other, wherein the semiconductor chip includes a first surface, a second surface corresponding to the first surface, at least one first conductive terminal and at least one second conductive terminal, wherein the at least one first conductive terminal and the at least one second conductive terminal are arranged on the second surface, the at least one first conductive terminal is connected to the first portion of the first metal layer, and the at least one second conductive terminal is connected to the second portion of the first metal layer, wherein the second insulating layer includes a first portion, a second portion and a third portion, the first portion of the second insulating layer is arranged between the semiconductor chip, the first portion of the first metal layer, the second portion of the first metal layer and the first insulating layer, the second portion of the second insulating layer is arranged between the semiconductor chip, the metal pin, the first portion of the first metal layer and the third metal layer, and the third portion of the second insulating layer is arranged between the semiconductor chip, the second portion of the first metal layer and the third metal layer.

3. The packaging structure as described in claim 2 further includes a first conductive layer, which is arranged between the first packaging element and the second packaging element, wherein a portion of the first conductive layer is connected between the first surface of the semiconductor chip and the third metal layer, and another portion of the first conductive layer is connected between a first surface of the metal pin and the third metal layer.

4. The packaging structure as described in claim 2 further includes a second conductive layer, which is arranged between the first packaging element and the second packaging element, and the second conductive layer further includes a first part, a second part and a third part, wherein the first part of the second conductive layer is connected between the at least one first conductive terminal and the first part of the first metal layer, the second part of the second conductive layer is connected between the at least one second conductive terminal and the second part of the first metal layer, and the third part of the second conductive layer is connected between a second surface of the metal pin and the first metal layer.

5. The packaging structure as described in claim 2, wherein the first metal layer includes at least one second groove, the at least one first groove and the at least one second groove are located between the first portion of the first metal layer and the second portion of the first metal layer, wherein the second groove is arranged on the first groove, a portion of the second insulation layer is exposed through the first groove and the second groove, and wherein the semiconductor chip is accommodated in the first groove.

6. The package structure as claimed in claim 5, wherein the second package component further comprises: a third insulating layer formed on the third metal layer; and A fourth metal layer is formed on the third insulating layer.

7. The packaging structure as described in claim 6, wherein the first metal layer includes at least one third groove, and the third metal layer includes at least one fourth groove, wherein a portion of the first insulating layer is exposed through the third groove, and a portion of the third insulating layer is exposed through the fourth groove, and the at least one third groove corresponds to the setting position of the at least one fourth groove, wherein the third portion of the second insulating layer is set in the third groove and the fourth groove, and the third portion of the second insulating layer is set between the second portion of the first metal layer, the first insulating layer, the semiconductor chip, the third metal layer and the third insulating layer.

8. The package structure as claimed in claim 4, wherein the at least one second conductive terminal of the semiconductor chip comprises a plurality of second conductive terminals, wherein the package structure further comprises: At least one first conductive pillar connected between the at least one first conductive terminal of the semiconductor chip and the first portion of the second conductive layer; and A plurality of second conductive pillars are connected between the plurality of second conductive terminals of the semiconductor chip and the second portion of the second conductive layer.

9. The package structure as claimed in claim 4, wherein the at least one second conductive terminal of the semiconductor chip comprises a plurality of second conductive terminals, wherein the package structure further comprises: a first conductive column connected between the first conductive terminal of the semiconductor chip and the first portion of the second conductive layer; and A second conductive column is connected between the second conductive terminal of the semiconductor chip and the second portion of the second conductive layer. 10 . The package structure as claimed in claim 2 , wherein the first surface of the semiconductor chip is coplanar with a surface of the metal pin.

11. The packaging structure as described in claim 2 further comprises a first conductive layer connected between the first surface of the semiconductor chip and the third metal layer, wherein the second portion of the second insulating layer is disposed between the first portion of the first metal layer, the metal pin, the third metal layer and the semiconductor chip.

12. The packaging structure as described in claim 2, wherein the metal pin includes a first portion and a second portion, the first portion of the metal pin is partially disposed between a first conductive layer and a third portion of a second conductive layer, and the second portion of the metal pin is vertically connected to one end of the first portion of the metal pin. 13 . The package structure as claimed in claim 1 , further comprising an insulating structure disposed on sides of the first package component and the second package component, wherein the metal pin is partially embedded in the insulating structure. 14 . The package structure as claimed in claim 1 , wherein the first metal layer comprises at least one concave portion, wherein a portion of the metal pin is disposed in the concave portion. 15 . The package structure as claimed in claim 1 , further comprising a gasket disposed between the first metal layer and the third metal layer to electrically connect the first metal layer and the third metal layer. 16 . The package structure as claimed in claim 15 , wherein an upper surface of the pad is coplanar with a first surface of the semiconductor chip.

17. The packaging structure as described in claim 1 further comprises a shell covering the second packaging element, and the shell comprises a accommodating space and an opening, the opening is connected to the accommodating space, wherein the second packaging element is accommodated in the accommodating space, and a portion of the second packaging element is exposed through the opening. 18 . The package structure as claimed in claim 1 , further comprising at least one heat dissipation device disposed on a surface of the first package component or on a surface of the second package component.

19. The package structure as claimed in claim 1, wherein the semiconductor chip is a flip chip integrated circuit chip.

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