Semiconductor packaging structure and forming method thereof

Abstract

The invention discloses a semiconductor packaging structure and a forming method thereof, and the method comprises the steps: providing a glass substrate which is provided with a plurality of discrete glass through hole interconnection structures, and is also provided with a groove located in the upper surface; a semiconductor chip without internal wiring is provided, the semiconductor chip comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, and a semiconductor device is arranged in the device layer; mounting a semiconductor chip without internal wiring into the groove; an inorganic dielectric layer and a first interconnection structure and a second interconnection structure which are located in the inorganic dielectric layer are formed on the upper surface of the glass substrate, the first interconnection structure is electrically connected with the upper end surface of the glass through hole interconnection structure, and the second interconnection structure is electrically connected with the semiconductor device. The semiconductor chip without internal wiring, the second interconnection structure and a part of the inorganic dielectric layer form a first semiconductor chip; and forming an organic passivation layer and a third interconnection structure located in the organic passivation layer on the lower surface of the glass substrate. And the performance of the packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] The most common packaging substrate is an organic material substrate. Organic material substrates are easy to process and can transmit signals at high speed. They have always been regarded as leaders in the chip field. However, organic material substrates also have some disadvantages. For example, the thermal expansion coefficient of organic material substrates and chips is too different. At high temperatures, the connection point between the chip and the organic material substrate is easy to disconnect, making the chip easy to burn. In addition, the size of the organic substrate is greatly limited, and it cannot accommodate too many chips within the limited size.

[0003] In this context, glass substrates came into being. Glass substrates have ultra-low flatness (extremely flat), better thermal stability and mechanical stability. Because the glass material is very flat, it can improve the focus depth of lithography. Under the same area, the number of openings is much more than that on the organic material substrate, so that the spacing between the formed through-glass vias (Through Glass Via) can be less than 100 microns, which can directly increase the interconnection density between chips by 10 times. In addition, the thermal expansion coefficient of the glass substrate is closer to that of the chip, and the higher temperature tolerance can reduce deformation by 50%, which can reduce the risk of fracture at the connection point and increase the reliability of the chip. In addition, compared with traditional organic material substrates, glass substrates not only have lower power consumption, but also faster signal transmission speed, and the thickness of the glass substrate can be reduced by about half. These advantages make glass substrates an ideal choice for the next generation of high-density packaging, capable of building higher-performance multi-chip packaging structures. However, the performance of existing packaging structures based on glass substrates still needs to be improved. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a semiconductor packaging structure and a method for forming the same, so as to improve the performance of the packaging structure based on a glass substrate.

[0005] To this end, the present application first provides a method for forming a semiconductor packaging structure, comprising: Providing a glass substrate, wherein the glass substrate has a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate respectively expose the upper end surface and the lower end surface of the through-glass interconnect structures, and wherein the glass substrate further has a groove, wherein the groove is located on the upper surface of the glass substrate; Providing a semiconductor chip without internal wiring, the semiconductor chip without internal wiring comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, wherein the device layer has a semiconductor device; Mounting the semiconductor chip without internal wiring into the groove, wherein the upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate; An inorganic dielectric layer and a first interconnection structure and a second interconnection structure located in the inorganic dielectric layer are formed on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, the first interconnection structure is electrically connected to the upper end surface of the through-glass via interconnection structure, the second interconnection structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring, and a part of the second interconnection structure is also electrically connected to a part of the first interconnection structure, and the semiconductor chip without internal wiring, the second interconnection structure and a part of the inorganic dielectric layer constitute a first semiconductor chip; forming an organic passivation layer and a third interconnection structure located in the organic passivation layer on the lower surface of the glass substrate, wherein the third interconnection structure is electrically connected to the lower end surface of the through-glass via interconnection structure; At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnection structure.

[0006] In an optional embodiment, the forming method further includes: forming a plurality of discrete first welding protrusions on the lower surface of the inorganic passivation layer, wherein the first welding protrusions are electrically connected to the third interconnect structure.

[0007] In an optional embodiment, the inorganic dielectric layer, the first interconnect structure and the second interconnect structure are manufactured using the BEOL process in the semiconductor front-end process, and the organic passivation layer and the third interconnect structure are manufactured using the RDL process in the semiconductor back-end process; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

[0008] In an optional embodiment, the characteristic size of the first interconnect structure and the second interconnect structure is 0.2-0.8 microns, and the characteristic size of the third interconnect structure is 1.5-2.5 microns.

[0009] In an optional embodiment, the first interconnect structure and the second interconnect structure include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the third interconnect structure is a rewiring layer.

[0010] In an optional embodiment, the inorganic dielectric layer is a multi-layer stacked structure, and the first interconnect structure and the second interconnect structure are multi-layer stacked structures.

[0011] In an optional embodiment, the material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure, the second interconnection structure and the third interconnection structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0012] In an optional embodiment, the device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, and the conductive connection structure is electrically connected to the second interconnection structure.

[0013] In an optional embodiment, the semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

[0014] In an optional embodiment, the semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

[0015] In an optional embodiment, the formation method further includes: providing a passive device, mounting the passive device on the lower surface of the glass substrate or embedding the passive device into the glass substrate from the lower surface direction of the glass substrate, and the passive device is electrically connected to the third interconnection structure.

[0016] The present application also provides a semiconductor packaging structure, comprising: A glass substrate having a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass interconnect structures respectively, and wherein the glass substrate further has a groove, wherein the groove is located on the upper surface of the glass substrate; A semiconductor chip without internal wiring located in the groove, wherein the semiconductor chip without internal wiring comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, wherein the device layer has semiconductor devices, and the upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate; an inorganic dielectric layer located on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, and a first interconnection structure and a second interconnection structure located in the inorganic dielectric layer, wherein the first interconnection structure is electrically connected to the upper end surface of the through-glass via interconnection structure, the second interconnection structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring, and a part of the second interconnection structure is also electrically connected to a part of the first interconnection structure, and the semiconductor chip without internal wiring, the second interconnection structure and a part of the inorganic dielectric layer constitute a first semiconductor chip; an organic passivation layer located on the lower surface of the glass substrate and a third interconnection structure located in the organic passivation layer, wherein the third interconnection structure is electrically connected to the lower end surface of the through-glass via interconnection structure; At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnection structure.

[0017] In an optional embodiment, the packaging structure further includes: a plurality of discrete first welding protrusions located on the lower surface of the inorganic passivation layer, the first welding protrusions being electrically connected to the third interconnect structure.

[0018] In an optional embodiment, the inorganic dielectric layer, the first interconnect structure and the second interconnect structure are formed by the BEOL process in the semiconductor front-end process; the organic passivation layer and the third interconnect structure are formed by the RDL process in the semiconductor back-end process; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

[0019] In an optional embodiment, the characteristic size of the first interconnect structure and the second interconnect structure is 0.2-0.8 microns, and the characteristic size of the third interconnect structure is 1.5-2.5 microns.

[0020] In an optional embodiment, the first interconnect structure and the second interconnect structure include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the third interconnect structure is a rewiring layer.

[0021] In an optional embodiment, the inorganic dielectric layer is a multi-layer stacked structure, and the first interconnection structure and the second interconnection structure are multi-layer stacked structures; the material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure, the second interconnection structure and the third interconnection structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0022] In an optional embodiment, the device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, and the conductive connection structure is electrically connected to the second interconnection structure.

[0023] In an optional embodiment, the semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

[0024] In an optional embodiment, the semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

[0025] In an optional embodiment, the packaging structure further includes: a passive device, which is mounted on the lower surface of the glass substrate or embedded in the glass substrate from the lower surface of the glass substrate, and the passive device is electrically connected to the third interconnection structure.

[0026] Compared with the prior art, the advantages of the technical solution of this application are: In the present application, when the semiconductor chip without internal wiring is manufactured, only the front-end process (FEOL, Front End Of Line) of the semiconductor front-end process is performed to form a semiconductor device, and the back-end process (BEOL, Back End Of Line) of the semiconductor front-end process is not performed, that is, the internal wiring for interconnecting the semiconductor device is not formed. After the semiconductor chip without internal wiring is mounted on or buried in the groove of the glass substrate, an inorganic dielectric layer and a first interconnection structure and a second interconnection structure located in the inorganic dielectric layer are formed on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring through the back-end process (BEOL, Back End Of Line) of the semiconductor front-end process. The semiconductor chip without internal wiring, the second interconnection structure and part of the inorganic dielectric layer constitute a first semiconductor chip, so that the first semiconductor chip has corresponding functions (such as logic control and / or data storage, etc.). The first semiconductor chip formed by the aforementioned specific steps can increase the function of the packaging structure and improve the performance of the packaging structure. Moreover, since the semiconductor chip without internal wiring is only made to the device layer without internal wiring, it can not only greatly simplify the manufacturing process of the semiconductor chip without internal wiring, but also make the thickness of the semiconductor chip without internal wiring thinner, so the depth of the groove in the glass substrate can be shallower, so that the glass substrate can maintain a thinner thickness, and the semiconductor chip without internal wiring is buried in the glass substrate, which will not increase the thickness of the packaging structure. In addition, the second interconnection structure (or internal wiring) used for interconnecting the semiconductor devices on the semiconductor chip without internal wiring is synchronized with the step of forming the first interconnection structure on the upper surface of the glass substrate, which can fully realize the structure and function of the first semiconductor chip, and make the formation process of the internal wiring of the semiconductor chip without internal wiring compatible with the formation process of the first interconnection structure on the glass substrate. In addition, semiconductor devices (thin film transistor package) can be made on the upper surface of the glass substrate later, and the semiconductor devices are integrated and made on the semiconductor chip without internal wiring, which simplifies the process and reduces the thermal effect on the one hand, and optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate on the other hand. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1-Figure 7 This is a structural schematic diagram of a formation process of a semiconductor packaging structure in one embodiment of the present application; Figure 8 A structural schematic diagram of a formation process of a semiconductor packaging structure in another embodiment of the present application; Fig. 9 It is a structural schematic diagram of the formation process of a semiconductor packaging structure in another embodiment of the present application. DETAILED DESCRIPTION

[0028] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0029] An embodiment of the present application first provides a method for forming a semiconductor packaging structure, and the specific process of the forming method is described in detail below with reference to the accompanying drawings.

[0030] refer to Figure 1 A glass substrate 100 is provided, wherein the glass substrate 100 has a plurality of discrete through-glass interconnect structures 103, wherein the upper surface and the lower surface of the glass substrate 100 respectively expose the upper end surface and the lower end surface of the through-glass interconnect structures 103, and the glass substrate 100 also has a groove 110, wherein the groove 110 is located on the upper surface of the glass substrate 100.

[0031] The glass substrate 100 serves as a support carrier and a wiring carrier of the packaging structure. Compared with an organic material substrate, the glass substrate 100 has ultra-low flatness (extremely flat), better thermal stability and mechanical stability. In one embodiment, the material of the glass substrate 100 is glass, crystal and the like, and the thermal expansion coefficient of the glass substrate 100 is less than or equal to 9 ppm / °C, specifically 3 ppm / °C-4 ppm / °C, 6 ppm / °C-9 ppm / °C.

[0032] The glass substrate 100 may have a thinner thickness and a larger size. In one embodiment, the thickness of the glass substrate 100 is less than 800 microns. In a specific embodiment, the thickness of the glass substrate 100 may be 300 microns-500 microns. In another specific embodiment, the thickness of the glass substrate 100 may be 30 microns-200 microns. In one embodiment, the shape of the glass substrate 100 is a cuboid, and the size of the glass substrate 100 is greater than 100mmX100mm. Specifically, the size of the glass substrate 100 may be 110mmX110mm, 300mmx300mm, 515mmx510mm, 600mmx600mm, 620mmx750mm.

[0033] A plurality of discrete through glass via (TGV, Through Glass Via) interconnect structures 103 are formed in the glass substrate 100. In one embodiment, the material of the through glass via interconnect structure 103 is one material selected from copper, tungsten, aluminum, nickel, gold, gallium, silver, and titanium, or a combination of two or more thereof. In one embodiment, the formation process of the through glass via interconnect structure 103 includes: forming a through glass via (TGV, Through Glass Via) in the glass substrate 103, wherein the through glass via may be formed by a photosensitive glass method, a focused power generation method, a plasma etching method, a laser ablation method, an electrochemical discharge machining method, or a laser induced etching method; filling a metal conductive material in the through glass via and planarizing the metal conductive material to form the through glass via interconnect structure 103, wherein the filling of the metal conductive material may be performed by electroplating or physical vapor deposition (such as sputtering), and the planarization of the metal conductive material may be performed by a chemical mechanical polishing process.

[0034] The groove 110 is used to mount a semiconductor chip without internal wiring later. The shape of the groove 110 is the same as the shape of the semiconductor chip without internal wiring to be mounted later. The depth of the groove 110 is equal to or slightly greater than the thickness of the semiconductor chip without internal wiring. The size of the groove 110 is equal to or slightly greater than the size of the semiconductor chip without internal wiring. In one embodiment, the groove 110 is formed after the glass through hole interconnection structure 103 is formed. The groove 110 can be formed by a photosensitive glass method, a focused power generation method, a plasma etching method, a laser ablation method, an electrochemical discharge machining method, or a laser induced etching method.

[0035] refer to Figure 2 , a semiconductor chip 300 without internal wiring is provided, wherein the semiconductor chip 300 without internal wiring includes a semiconductor substrate 302 and a device layer located on the upper surface of the semiconductor substrate 302, wherein the device layer has a semiconductor device 304.

[0036] When the semiconductor chip 300 without internal wiring is manufactured, only the front-end process (FEOL) of the semiconductor front-end process is performed to form the semiconductor device 304, and the back-end process (BEOL) of the semiconductor front-end process is not performed, that is, the internal wiring for interconnecting the semiconductor device 304 is not formed. The semiconductor chip 300 without internal wiring will be mounted on or embedded in the groove 110 of the glass substrate (refer to Figure 3), then an inorganic dielectric layer 104 and a first interconnect structure 101 and a second interconnect structure 305 (reference Figure 4 ), the first interconnect structure 101 is electrically connected to the upper end surface of the through glass via interconnect structure 103, the second interconnect structure 305 is electrically connected to the semiconductor device 304 in the semiconductor chip 300 without internal wiring, and part of the second interconnect structure 305 is also electrically connected to part of the first interconnect structure 101, the semiconductor chip 300 without internal wiring, the second interconnect structure 305 and part of the inorganic dielectric layer 104 constitute a first semiconductor chip (reference Figure 4 ), the first semiconductor chip 301 may have corresponding functions (such as logic control and / or data storage, etc.), and the first semiconductor chip 301 may be connected to the second semiconductor chip 201 (refer to FIG. 2 ) subsequently mounted on the upper surface of the inorganic dielectric layer 104 through part of the first interconnect structure 101. Figure 6 ) interconnection, that is, the first semiconductor chip 301 formed by the aforementioned specific steps can increase the function of the packaging structure and improve the performance of the packaging structure. In addition, since the semiconductor chip 300 without internal wiring is only made to the device layer without internal wiring, it can not only greatly simplify the manufacturing process of the semiconductor chip 300 without internal wiring, but also make the thickness of the semiconductor chip 300 without internal wiring thinner, so that the depth of the groove 110 in the glass substrate 100 can be shallower, so that the glass substrate 100 can maintain a thinner thickness, and the semiconductor chip 300 without internal wiring is buried in the glass substrate 100, and the thickness of the packaging structure will not be increased. In addition, the second interconnection structure 305 (or internal wiring) for interconnecting the semiconductor devices on the semiconductor chip 300 without internal wiring is synchronized with the step of forming the first interconnection structure 101 on the upper surface of the glass substrate 100, which can fully realize the structure and function of the first semiconductor chip 301, while making the formation process of the internal wiring of the semiconductor chip 300 without internal wiring compatible with the formation process of the first interconnection structure 101 on the glass substrate 100. In addition, semiconductor devices (thin film transistor packages) do not need to be manufactured on the upper surface of the glass substrate 101 subsequently. The semiconductor devices are integrated and manufactured on the semiconductor chip 300 without internal wiring. On the one hand, this simplifies the process and reduces thermal effects. On the other hand, it optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate 100.

[0037] In one embodiment, the device layer further includes a bottom inorganic dielectric layer 303 located on the upper surface of the semiconductor substrate 302, the bottom inorganic dielectric layer 303 covers the semiconductor device 304, and the device layer further includes a conductive connection structure 307 located in the bottom inorganic dielectric layer 303 and electrically connected to the active area of ​​the semiconductor device 304, the conductive connection structure 307 is electrically connected to the second interconnect structure 305, the bottom inorganic dielectric layer 303 directly exposes part or all of the active area of ​​the semiconductor device 302, and the bottom inorganic dielectric layer 303 exposes the upper end surface of the conductive connection structure 307. In one embodiment, the semiconductor substrate 302 can be a wafer. In one embodiment, the material of the semiconductor substrate 302 is silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V compounds such as gallium arsenide. The semiconductor substrate 300 can also be implanted with certain doping ions according to design requirements to change electrical parameters. In one embodiment, a shallow trench isolation structure 306 is further formed in the semiconductor substrate 300, and the shallow trench isolation structure is used to isolate different semiconductor devices 304 to prevent electrical connection between different semiconductor devices 304. The material of the bottom inorganic dielectric layer 303 and the shallow trench isolation structure 306 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0038] In one embodiment, the semiconductor device 304 includes one or a combination of bipolar transistors, field effect transistors, and insulated gate bipolar transistors. In another embodiment, the semiconductor device 304 also includes one or a combination of diodes, resistors, capacitors, and inductors. It should be noted that: Figure 2 The semiconductor device 304 is described by taking two field effect transistors as an example. In other embodiments, the semiconductor device 304 may be other semiconductor devices, other quantities, or other layout structures.

[0039] The bipolar transistor (full name bipolar junction transistor (BJT)), commonly known as triode, is an electronic device with three terminals, made of three parts of semiconductors with different doping levels in a semiconductor substrate, including an emitter, a base and a collector. The base has different doping types from the emitter and the collector. For example, for an NPN triode, the base is doped with a P-type, and the emitter and collector are doped with an N-type. For details, please refer to the Field Effect Transistor (FET). Figure 2 , including a gate 304a located on the upper surface of a semiconductor substrate 302 and a source 304b and a drain 304c in the semiconductor substrate 302 located on both sides of the gate 304a, and the field effect transistor also includes a sidewall 304d located on the sidewall surface of the gate 304a. The field effect transistor may include a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) or a fin field effect transistor (Fin Field-Effect Transistor, FinFET), and the metal oxide semiconductor field effect transistor includes a PMOS transistor and an NMOS transistor. The insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor—IGBT) includes a gate, a collector and an emitter with different doping levels, and the gate has different doping types from the emitter and the collector. For example, in an N-type IGBT, when the gate is doped with a P-type, the emitter and the collector are doped with an N-type.

[0040] refer to Figure 3 , the semiconductor chip 300 without internal wiring is mounted into the groove 110 , and the upper surface of the device layer of the semiconductor chip 300 without internal wiring is flush with the upper surface of the glass substrate 100 .

[0041] In one embodiment, before mounting the semiconductor chip 300 without internal wiring into the groove 110 , an adhesive is applied to the lower surface (and side surfaces) of the semiconductor chip 300 without internal wiring.

[0042] refer to Figure 4An inorganic dielectric layer 104 and a first interconnect structure 101 and a second interconnect structure 305 located in the inorganic dielectric layer 104 are formed on the upper surface of the glass substrate 100 and the upper surface of the device layer of the semiconductor chip 300 without internal wiring, the first interconnect structure 101 is electrically connected to the upper end surface of the through-glass hole interconnect structure 103, the second interconnect structure 305 is electrically connected to the semiconductor device 304 in the semiconductor chip 300 without internal wiring, and part of the second interconnect structure 305 is also electrically connected to part of the first interconnect structure 101, the semiconductor chip 300 without internal wiring, the second interconnect structure 305 and part of the inorganic dielectric layer 104 constitute the first semiconductor chip 301.

[0043] The inorganic dielectric layer 104 is used for isolating adjacent first interconnect structures 101 , adjacent second interconnect structures 305 , and adjacent first interconnect structures 101 and second interconnect structures 305 .

[0044] The first interconnection structure 101 is used for interconnection between different chips. In one embodiment, part of the first interconnection structure 101 can be used to interconnect the second semiconductor chip 201 (refer to FIG. 5 ) subsequently mounted on the inorganic dielectric layer 104 with the glass through hole interconnection structure 103 in the glass substrate 100. In another embodiment, part of the first interconnection structure 101 can also be used for interconnection between multiple second semiconductor chips 201 subsequently mounted. In another embodiment, part of the first interconnection structure 101 can also be used to interconnect with part of the second interconnection structure 305.

[0045] The second interconnection structure 305 is used for interconnection between semiconductor devices 304 in the device layer of the unwired semiconductor chip 300. Part of the second interconnection structure 305 is also used for interconnection with part of the first interconnection structure 101, so that the first semiconductor chip 301 can be interconnected with the second semiconductor chip 201 to be subsequently mounted through part of the second interconnection structure 305 and part of the first interconnection structure 101, or can also be interconnected with the glass through hole interconnection structure 103 in the glass substrate 100.

[0046] The inorganic dielectric layer 104 is a multi-layer (multi-layer means ≥ two layers) stacked structure, the first interconnect structure 101 and the second interconnect structure 305 can be a multi-layer stacked structure, the number of layers of the first interconnect structure 101 is the same as the number of layers of the inorganic dielectric layer 104, and the number of layers of the second interconnect structure 305 can be equal to or less than the number of layers of the inorganic dielectric layer 104. In one embodiment, when the inorganic dielectric layer 104 is an N-layer stacking structure (N may be 2, 3, 4, 5, 6 or greater than 6), the corresponding first interconnection structure 101 is also an N-layer stacking structure, and the second interconnection structure 305 is an N-layer or NM-layer stacking structure (M is less than N and greater than 0, and M may be 1, 2 or greater than 2), that is, each layer of the inorganic dielectric layer 104 may have a corresponding layer of the first interconnection structure 101, and for the second interconnection structure 305, each layer of the inorganic dielectric layer 104 may have a corresponding layer of the second interconnection structure 305, or the L-layer (L is less than N) inorganic dielectric layer 104 close to the upper surface of the glass substrate 101 may have the corresponding L-layer second interconnection structure 305, while the NL-layer inorganic dielectric layer 104 far from the upper surface of the glass substrate 101 does not have the second interconnection structure 305, and only has the first interconnection structure 101. Figure 4 In the example, the inorganic dielectric layer 104 has three layers, the corresponding first interconnect structure 101 also has three layers, and the second interconnect structure 305 has two layers. The number of layers of the inorganic dielectric layer 104, the first interconnect structure 101, and the second interconnect structure 305 should not limit the protection scope of the present application, and Figure 4 The specific structures of the inorganic dielectric layer 104, the first interconnect structure 101 and the second interconnect structure 305 are only used as an illustration, and their specific structures should not limit the protection scope of the present application. In other embodiments, the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 can have other numbers of layers, and the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 can have other specific structures.

[0047] In one embodiment, the first interconnect structure 101 and the second interconnect structure 305 may include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; the material of the inorganic dielectric layer 104 is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material, and the material of the first interconnect structure 101 and the second interconnect structure 305 is one or a combination of more than two (two or more) of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0048] As we all know, the current semiconductor manufacturing process includes semiconductor front-end process and semiconductor back-end process. The semiconductor front-end process will make transistors, resistors, capacitors and other devices on the wafer, as well as the internal wiring that connects these devices to each other. The semiconductor front-end process is also subdivided into front-end process (FEOL, Front End Of Line) and back-end process (BEOL, Back End Of Line). The front-end process (FEOL, Front End Of Line) is used to make transistors, resistors, capacitors and other devices, and the back-end process (BEOL, Back End Of Line) is used to make internal wiring that connects transistors, resistors, capacitors and other devices to each other. The semiconductor back-end process generally includes wafer testing, thinning, mounting, redistribution layer (RDL), packaging and other processes. When semiconductor chips are currently packaged, the redistribution layer is usually produced using the redistribution layer (RDL) process in the semiconductor back-end process, such as forming a resin material layer (such as an ABF resin layer) on the surface of a substrate (such as an inorganic material substrate, a PCB substrate, or a glass substrate); exposing and developing the resin material layer to form a groove; forming a redistribution layer in the groove and on the upper surface of the resin material. The density of the redistribution layer formed in this way is relatively low. Based on the different requirements of the process and various considerations such as yield, in the current semiconductor manufacturing process, the back-end process (BEOL) in the semiconductor front-end process will not be applied to the back-end process.

[0049] The inventors have found through research that the glass substrate has ultra-low flatness (extremely flat), better thermal stability and mechanical stability, which are similar to the characteristics of silicon wafers, and even some characteristics are better than those of silicon wafers. This makes it very suitable for the BEOL process in the semiconductor front-end process when wiring on the glass substrate. Therefore, in one embodiment, the inventors unconventionally use the BEOL process in the semiconductor front-end process for the production of part of the rewiring layer (the inorganic dielectric layer 104 and the first interconnect structure 101 and the second interconnect structure 305) in the back-end process. Since the BEOL process in the semiconductor front-end process is relatively advanced, the density of the formed first interconnect structure 101 is greater than that of the third interconnect structure 102 (reference 305) formed subsequently on the lower surface of the glass substrate 101. Figure 5), the characteristic size of the first interconnect structure 101 is smaller than the characteristic size of the third interconnect structure 102 formed subsequently, that is, in the present application, the density of the redistribution layer (first interconnect structure 101) formed on the upper surface of the glass substrate 100 can be higher and the characteristic size can be smaller (more first interconnect structures 101 can be arranged and more connection ports can be reserved under the same area), so that when the second semiconductor chip is subsequently mounted on the upper surface of the inorganic dielectric layer 104, the second semiconductor chip can reserve more external ports to be electrically connected to the corresponding connection ports in the first interconnect structure 101, thereby improving the performance of the packaging structure.

[0050] In one embodiment, the density of the second interconnect structure 305 may be greater than or equal to the density of the first interconnect structure 101 .

[0051] In one embodiment, the first interconnect structure 101 and the second interconnect structure 305 have a characteristic size of 0.2-0.8 micrometers, and the third interconnect structure 102 formed subsequently has a characteristic size of 1.5-2.5 micrometers.

[0052] In one embodiment, before forming the inorganic dielectric layer 104, the first interconnect structure 101 and the second interconnect structure 305, an upper pad is formed on the upper surface of the glass substrate 100, and the upper pad is electrically connected to the upper end surface of the through glass hole interconnect structure 103, and the upper pad is also correspondingly used as a part of the first interconnect structure 101 and the second interconnect structure 305.

[0053] refer to Figure 5 An organic passivation layer 105 and a third interconnect structure 102 located in the organic passivation layer 105 are formed on the lower surface of the glass substrate 100 , and the third interconnect structure 102 is electrically connected to the lower end surface of the through glass via interconnect structure 103 .

[0054] In one embodiment, the third interconnect structure 102 is a redistribution layer (RDL). The organic passivation layer 105 is a single-layer or multi-layer stacked structure, and the third interconnect structure 102 is a single-layer or multi-layer stacked structure accordingly. The material of the organic passivation layer 105 is a resin material, such as ABF resin or other resins, and the material of the third interconnect structure 102 is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0055] In one embodiment, before forming the organic passivation layer 105 and the third interconnect structure 102 , a lower pad is formed on the lower surface of the glass substrate 100 , and the lower pad is electrically connected to the lower end surface of the through glass via interconnect structure 103 , and the lower pad is also used as a part of the third interconnect structure 102 .

[0056] In one embodiment, the organic passivation layer 105 and the third interconnect structure 102 are manufactured by using the RDL process in the semiconductor back-end process. In one embodiment, the process of manufacturing the organic passivation layer 105 and the third interconnect structure 102 by using the RDL process in the semiconductor back-end process includes: forming the organic passivation layer 105 on the lower surface of the glass substrate 100, and the process of forming the organic passivation layer 105 includes spin coating; exposing and developing the organic passivation layer 105 to form a groove, and the groove exposes the lower end surface of the through-glass interconnect structure 103 or the upper pad formed on the lower end surface of the through-glass interconnect structure 103; forming the third interconnect structure 102 in the groove and on a portion of the upper surface of the organic passivation layer 105, and the process of forming the third interconnect structure 102 includes electroplating.

[0057] In one embodiment, the density of the formed third interconnect structure 102 is smaller than that of the first interconnect structure 101, the characteristic size of the third interconnect structure 102 is larger than the characteristic size of the first interconnect structure 101, and the organic passivation layer 105 and the third interconnect structure 102 are formed after the inorganic dielectric layer 104 and the first interconnect structure 101 are formed, so that when the inorganic dielectric layer 104 and the first interconnect structure 101 are formed on the upper surface of the glass substrate 100, the lower surface of the glass substrate 100 can maintain a relatively high flatness, which is conducive to performing a more advanced BEOL process in a semiconductor front-end process on the upper surface of the glass substrate 100 to manufacture a first interconnect structure with a higher density and a smaller characteristic size.

[0058] refer to Figure 6 At least one second semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104 , and the second semiconductor chip 201 is electrically connected to the first interconnect structure 101 .

[0059] The second semiconductor chip 201 includes a relative back surface and an active surface, an integrated circuit (not shown in the figure) (having a specific function) is formed in the second semiconductor chip, and the active surface has a plurality of external protrusions 202 (the plurality of external protrusions 202 correspond to a plurality of external ports of the second semiconductor chip), and the plurality of external protrusions 202 are electrically connected to the integrated circuit. The external protrusions 202 are microbumps, and the material of the external protrusions 202 is one or a combination of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0060] In one embodiment, the second semiconductor chip 201 is mounted by flip-chip mounting. Specifically, the active surface of the second semiconductor chip 201 is mounted downward on the upper surface of the inorganic dielectric layer 104 , and the external protrusions 202 on the active surface of the second semiconductor chip 201 are welded together with the corresponding first interconnect structure 101 .

[0061] The number of the mounted second semiconductor chips 201 is one or more (greater than or equal to 2). Figure 4 The mounting of two second semiconductor chips 201 is taken as an example for description.

[0062] In one embodiment, when there are multiple mounted second semiconductor chips 201 , the multiple second semiconductor chips 201 may be semiconductor chips with the same function or different functions.

[0063] In one embodiment, the plurality of second semiconductor chips 201 may include logic chips and / or memory chips. In some embodiments, the logic chip may include but is not limited to a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip or a complementary metal oxide semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include but is not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), a phase change memory (PRAM), a resistive random access memory (RRAM) or a non-volatile memory chip (such as a flash memory).

[0064] In one embodiment, reference Figure 7 , further comprising: forming a plurality of discrete first welding protrusions 106 on the lower surface of the organic passivation layer 105 , wherein the first welding protrusions 106 are electrically connected to the third interconnect structure 102 .

[0065] The first welding protrusion 106 is used as a port for connecting the packaging structure to other substrates, other packaging structures and devices. In one embodiment, the material of the first welding protrusion 106 is one or a combination of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.

[0066] In one embodiment, before forming the first welding protrusion 106 , a second inorganic passivation layer (not shown) may be formed on the lower surface of the organic passivation layer 105 , and the second inorganic passivation layer partially exposes the lower surface of the third interconnect structure 102 .

[0067] Another embodiment of the present application further provides a method for forming a semiconductor packaging structure, referring to Figure 8The main difference between this embodiment and the previous embodiment is that: a passive device 401 is provided, and the passive device 401 is embedded in the glass substrate 100 from the lower surface direction of the glass substrate 100, and the passive device 401 is electrically connected to the third interconnect structure 102 to further improve the function and performance of the packaging structure, and when the passive device 401 is embedded in the glass substrate 100, it will not occupy the wiring space on the lower surface of the glass substrate 100, and will not increase the thickness of the packaging structure. In a specific embodiment, a second groove (not shown in the figure) is pre-formed in the glass substrate 100, and the second groove is located on the lower surface of the glass substrate 100. The passive device 401 is mounted in the second groove, so that the passive device 401 is embedded in the glass substrate 100. The embedding position of the passive device 401 is located below the embedding position of the semiconductor chip 300 without internal wiring.

[0068] In one embodiment, the passive component 401 is one or more of a resistor, a capacitor or an inductor.

[0069] Another embodiment of the present application further provides a method for forming a semiconductor packaging structure, referring to Fig. 9 The main difference between this embodiment and the previous embodiment is that: a passive device 401 is provided, and the passive device is mounted on the lower surface of the glass substrate 100, and the passive device 401 is electrically connected to the third interconnection structure 102 to further improve the function and performance of the packaging structure. Another embodiment of the present application also provides a semiconductor packaging structure, referring to Figure 7 ,include: A glass substrate 100 is provided with a plurality of discrete through-glass interconnect structures 103. The upper surface and the lower surface of the glass substrate 100 expose the upper end surface and the lower end surface of the through-glass interconnect structures 103, respectively. The glass substrate also has a groove 110 (see FIG. Figure 1 or Figure 3 ), the groove 110 is located on the upper surface of the glass substrate 100; A semiconductor chip 300 without internal wiring located in the groove 110, wherein the semiconductor chip 300 without internal wiring comprises a semiconductor substrate 302 and a device layer located on the upper surface of the semiconductor substrate 302, wherein the device layer has a semiconductor device 304, and the upper surface of the device layer of the semiconductor chip 300 without internal wiring is flush with the upper surface of the glass substrate 100; An inorganic dielectric layer 104 located on the upper surface of the glass substrate 100 and the upper surface of the device layer of the semiconductor chip 300 without internal wiring, and a first interconnection structure 101 and a second interconnection structure 305 located in the inorganic dielectric layer 104, wherein the first interconnection structure 101 is electrically connected to the upper end surface of the through-glass via interconnection structure 103, the second interconnection structure 305 is electrically connected to the semiconductor device 304 in the semiconductor chip 300 without internal wiring, and a part of the second interconnection structure 305 is also electrically connected to a part of the first interconnection structure 101, and the semiconductor chip 300 without internal wiring, the second interconnection structure 305 and a part of the inorganic dielectric layer 104 constitute a first semiconductor chip 301; an organic passivation layer 105 located on the lower surface of the glass substrate 100 and a third interconnection structure 102 located in the organic passivation layer 105, wherein the third interconnection structure 102 is electrically connected to the lower end surface of the through-glass via interconnection structure 103, and the density of the first interconnection structure 101 is greater than that of the third interconnection structure 102, and the characteristic size of the first interconnection structure 101 is smaller than that of the third interconnection structure 102; At least one second semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104 , and the second semiconductor chip 201 is electrically connected to the first interconnect structure 101 .

[0070] In one embodiment, the present invention further comprises: a plurality of discrete first welding protrusions 106 located on the lower surface of the organic passivation layer 105 , wherein the first welding protrusions 106 are electrically connected to the third interconnect structure 102 .

[0071] In one embodiment, the first interconnect structure 101 and the second interconnect structure 305 include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the third interconnect structure 102 is a rewiring layer.

[0072] In one embodiment, the inorganic dielectric layer 104 is a multi-layer stacked structure, and the first interconnect structure 101 and the second interconnect structure 305 are multi-layer stacked structures; the material of the inorganic dielectric layer 104 is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer 105 is a resin material, and the material of the first interconnect structure 101, the second interconnect structure 305 and the third interconnect structure 102 is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0073] In one embodiment, the inorganic dielectric layer 104, the first interconnect structure 101 and the second interconnect structure 305 are formed by the BEOL process in the semiconductor front-end process; the organic passivation layer 105 and the third interconnect structure 102 are formed by the RDL process in the semiconductor back-end process; the density of the first interconnect structure 101 is greater than the density of the third interconnect structure 102, and the characteristic size of the first interconnect structure 101 is smaller than the characteristic size of the third interconnect structure 102; the density of the second interconnect structure 305 is greater than or equal to the density of the first interconnect structure 101. In one embodiment, the characteristic sizes of the first interconnect structure 101 and the second interconnect structure 305 are 0.2-0.8 microns, and the characteristic size of the third interconnect structure 102 is 1.5-2.5 microns.

[0074] In one embodiment, reference Figure 2 The device layer also includes a bottom inorganic dielectric layer 303 located on the upper surface of the semiconductor substrate 302, and the bottom inorganic dielectric layer 303 covers the semiconductor device 304. The device layer also includes a conductive connection structure 307 located in the bottom inorganic dielectric layer 303 and electrically connected to the active area of ​​the semiconductor device 304, and the conductive connection structure 307 is electrically connected to the second interconnection structure 305.

[0075] In one embodiment, the semiconductor device 304 includes a bipolar transistor, a field effect transistor (refer to Fig. 9 ) and insulated gate bipolar transistor or a combination of these.

[0076] In another embodiment, the semiconductor device 304 may further include one or a combination of a diode, a resistor, a capacitor and an inductor.

[0077] In one embodiment, the packaging structure further includes: a passive component 401, wherein the passive component 401 is mounted on the lower surface of the glass substrate (refer to Fig. 9 ) or embedded in the glass substrate 101 from the bottom surface direction of the glass substrate 101 (reference Figure 8 ), the passive device 401 is electrically connected to the third interconnect structure 102.

[0078] It should be noted that the parts in the embodiment of the aforementioned semiconductor packaging structure that are the same or similar to those in the embodiment of the aforementioned method for forming the semiconductor packaging structure will not be repeated in the embodiment of the semiconductor packaging structure. Please refer to the limitations or descriptions of the corresponding parts in the embodiment of the method for forming the aforementioned semiconductor packaging structure for details.

[0079] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a semiconductor packaging structure, characterized in that: include: Providing a glass substrate, wherein the glass substrate has a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate respectively expose the upper end surface and the lower end surface of the through-glass interconnect structures, and wherein the glass substrate further has a groove, wherein the groove is located on the upper surface of the glass substrate; Providing a semiconductor chip without internal wiring, the semiconductor chip without internal wiring comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, wherein the device layer has a semiconductor device; Mounting the semiconductor chip without internal wiring into the groove, wherein the upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate; An inorganic dielectric layer and a first interconnection structure and a second interconnection structure located in the inorganic dielectric layer are formed on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, the first interconnection structure is electrically connected to the upper end surface of the through-glass via interconnection structure, the second interconnection structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring, and a part of the second interconnection structure is also electrically connected to a part of the first interconnection structure, and the semiconductor chip without internal wiring, the second interconnection structure and a part of the inorganic dielectric layer constitute a first semiconductor chip; forming an organic passivation layer and a third interconnection structure located in the organic passivation layer on the lower surface of the glass substrate, wherein the third interconnection structure is electrically connected to the lower end surface of the through-glass via interconnection structure; At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnection structure.

2. The method for forming a semiconductor package structure according to claim 1, wherein: The forming method further includes: forming a plurality of discrete first welding protrusions on the lower surface of the organic passivation layer, wherein the first welding protrusions are electrically connected to the third interconnection structure.

3. The method for forming a semiconductor package structure according to claim 1 or 2, wherein: The inorganic dielectric layer, the first interconnect structure and the second interconnect structure are manufactured by the BEOL process in the semiconductor front-end process, and the organic passivation layer and the third interconnect structure are manufactured by the RDL process in the semiconductor back-end process; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

4. The method for forming a semiconductor package structure according to claim 3, wherein: The first interconnect structure and the second interconnect structure have characteristic sizes of 0.2-0.8 micrometers, and the third interconnect structure has a characteristic size of 1.5-2.5 micrometers.

5. The method for forming a semiconductor package structure according to claim 3, wherein: The first interconnect structure and the second interconnect structure include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the third interconnect structure is a rewiring layer.

6. The method for forming a semiconductor package structure according to claim 6, wherein: The inorganic dielectric layer is a multi-layer stacked structure, and the first interconnection structure and the second interconnection structure are multi-layer stacked structures.

7. The method for forming a semiconductor package structure according to claim 7, wherein: The material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure, the second interconnection structure and the third interconnection structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

8. The method for forming a semiconductor package structure according to claim 1, wherein: The device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, the conductive connection structure is electrically connected to the second interconnection structure.

9. The method for forming a semiconductor package structure according to claim 8, wherein: The semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

10. The method for forming a semiconductor package structure according to claim 9, wherein: The semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

11. The method for forming a semiconductor package structure according to claim 1, wherein: The forming method further includes: providing a passive device, mounting the passive device on the lower surface of the glass substrate or embedding the passive device into the glass substrate from the lower surface of the glass substrate, wherein the passive device is electrically connected to the third interconnection structure.

12. A semiconductor packaging structure, characterized in that: include: A glass substrate having a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass interconnect structures respectively, and the glass substrate further has a groove, wherein the groove is located on the upper surface of the glass substrate; A semiconductor chip without internal wiring located in the groove, wherein the semiconductor chip without internal wiring comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, wherein the device layer has semiconductor devices, and the upper surface of the device layer of the semiconductor chip without internal wiring is flush with the upper surface of the glass substrate; an inorganic dielectric layer located on the upper surface of the glass substrate and the upper surface of the device layer of the semiconductor chip without internal wiring, and a first interconnection structure and a second interconnection structure located in the inorganic dielectric layer, wherein the first interconnection structure is electrically connected to the upper end surface of the through-glass via interconnection structure, the second interconnection structure is electrically connected to the semiconductor device in the semiconductor chip without internal wiring, and a part of the second interconnection structure is also electrically connected to a part of the first interconnection structure, and the semiconductor chip without internal wiring, the second interconnection structure and a part of the inorganic dielectric layer constitute a first semiconductor chip; an organic passivation layer located on the lower surface of the glass substrate and a third interconnection structure located in the organic passivation layer, wherein the third interconnection structure is electrically connected to the lower end surface of the through-glass via interconnection structure; At least one second semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the second semiconductor chip is electrically connected to the first interconnection structure.

13. The semiconductor package structure according to claim 12, wherein: The packaging structure further includes: a plurality of discrete first welding protrusions located on the lower surface of the organic passivation layer, wherein the first welding protrusions are electrically connected to the third interconnection structure.

14. The semiconductor package structure according to claim 12 or 13, characterized in that: The inorganic dielectric layer, the first interconnect structure and the second interconnect structure are formed by the BEOL process in the semiconductor front-end process; the organic passivation layer and the third interconnect structure are formed by the RDL process in the semiconductor back-end process; the density of the first interconnect structure is greater than the density of the third interconnect structure, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the third interconnect structure; the density of the second interconnect structure is greater than or equal to the density of the first interconnect structure.

15. The semiconductor package structure according to claim 14, wherein: The first interconnect structure and the second interconnect structure have characteristic sizes of 0.2-0.8 micrometers, and the third interconnect structure has a characteristic size of 1.5-2.5 micrometers.

16. The semiconductor package structure according to claim 14, wherein: The first interconnect structure and the second interconnect structure include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the third interconnect structure is a rewiring layer.

17. The semiconductor package structure according to claim 16, wherein: The inorganic dielectric layer is a multi-layer stacked structure, and the first interconnection structure and the second interconnection structure are multi-layer stacked structures; the material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure, the second interconnection structure and the third interconnection structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

18. The semiconductor package structure according to claim 12, wherein: The device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, the conductive connection structure is electrically connected to the second interconnection structure.

19. The semiconductor package structure according to claim 18, wherein: The semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

20. The semiconductor package structure according to claim 19, wherein: The semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

21. The semiconductor package structure according to claim 12, wherein: The packaging structure further includes: a passive device, which is mounted on the lower surface of the glass substrate or embedded in the glass substrate from the lower surface of the glass substrate, and is electrically connected to the third interconnection structure.

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