Semiconductor test method and device

Abstract

The invention relates to the technical field of semiconductor testing, and provides a semiconductor testing method and device.The method comprises the steps that electric signal parameters, temperature data and optical image information of a semiconductor device are collected and processed, and a standardized electric signal sequence, a continuous temperature distribution curve and device surface topography features are obtained; analyzing the standardized electric signal sequence and the continuous temperature distribution curve to generate a dynamic working condition mapping matrix; and performing mode matching on the dynamic working condition mapping matrix by using a preset fault mode library, identifying potential defect types and position coordinates, inputting the device surface topography features and the potential defect types and position coordinates into a composite scoring model, generating a comprehensive quality score, and then performing grading to obtain a semiconductor test result. By generating the comprehensive quality score and then grading, the semiconductor test result is obtained, so that the accuracy of defect identification is improved, and the problems that the multi-dimensional correlation analysis is lacked and the dynamic working condition of the device is difficult to comprehensively evaluate in the semiconductor test are solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a semiconductor testing method and device. Background Art

[0002] In the modern electronics industry, semiconductor devices are the core components of various electronic devices. The development of semiconductor technology has promoted the rapid progress of various fields such as information technology, communication technology, and consumer electronics. Therefore, the quality of semiconductor devices directly affects the performance and reliability of products. In order to ensure the high quality and high reliability of semiconductor devices, comprehensive testing and analysis are very necessary.

[0003] Among the related technical means, semiconductor testing is mainly carried out in the following ways: electrical parameter testing, temperature measurement and optical imaging. Electrical parameter testing usually uses parameter analysis instruments to measure the current, voltage and other parameters of the device. Temperature measurement uses devices such as thermocouples or infrared thermal imagers to obtain the temperature distribution of the device under different working conditions. Optical imaging technology uses high-resolution microscopes and image processing software to analyze the morphological characteristics and defects of the device surface. Through these testing methods, the quality and performance of semiconductor devices can be preliminarily evaluated.

[0004] Regarding the above technical solutions, although multi-faceted testing and analysis of semiconductor devices can be achieved through electrical parameter testing, temperature measurement and optical imaging, in actual applications, the information of electrical parameters, temperature and optical images is obtained independently, lacking multi-dimensional correlation analysis, making it difficult to comprehensively evaluate the dynamic working conditions of the device. Summary of the invention

[0005] In order to improve the problem that in practical applications, the information of electrical parameters, temperature and optical images is obtained independently, lacks multi-dimensional correlation analysis, and is difficult to comprehensively evaluate the dynamic working conditions of the device, the present application provides a semiconductor testing method and device.

[0006] The present invention provides a semiconductor testing method, comprising: collecting electrical signal parameters, temperature data and optical image information of a semiconductor device; normalizing the electrical signal parameters to obtain a standardized electrical signal sequence, performing time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, performing edge enhancement and feature segmentation on the optical image information, and extracting device surface morphology characteristics; performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic operating condition mapping matrix; performing pattern matching on the dynamic operating condition mapping matrix using a preset fault mode library to identify potential defect types and position coordinates, inputting the device surface morphology characteristics and the potential defect types and position coordinates into a composite scoring model to generate a comprehensive quality score; and grading the comprehensive quality score using a preset rating standard to obtain a semiconductor test result.

[0007] As a preferred solution, the step of collecting electrical signal parameters, temperature data and optical image information of semiconductor devices includes: synchronously acquiring the current, voltage and frequency signals of the device through a multi-channel electrical signal acquisition module to obtain original electrical signal data, and performing signal filtering and denoising on the original electrical signal data to obtain electrical signal parameters; collecting device data at preset time intervals through a distributed temperature sensor array to obtain a temperature discrete point set, and performing density compensation on the temperature discrete point set through a spatial interpolation algorithm to obtain temperature data; and capturing an optical image of the surface area of ​​the device using a high-resolution optical imaging device to form an optical image sequence, and performing frame alignment and distortion correction on the optical image sequence to obtain optical image information.

[0008] As a preferred scheme, the steps of normalizing the electrical signal parameters to obtain a standardized electrical signal sequence, performing time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, performing edge enhancement and feature segmentation on the optical image information, and extracting device surface morphology features include: performing multi-scale normalization on the electrical signal parameters through a normalization algorithm based on the signal amplitude range to obtain a standardized electrical signal sequence; performing time series fitting on the temperature data using a time series regression model to generate a continuous temperature distribution curve; performing edge enhancement processing on the optical image information using a multi-directional gradient operator to generate an enhanced edge map, and applying a region growing algorithm to extract and partition the surface features of the enhanced edge map to obtain device surface morphology features.

[0009] As a preferred scheme, the step of performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic operating condition mapping matrix includes: performing multi-scale signal decomposition on the standardized electrical signal sequence through wavelet transform, extracting low-frequency trend signals and high-frequency transient signals, and obtaining multi-scale signal features; analyzing the continuous temperature distribution curve through a curvature analysis method to extract key change point features of the curve; aligning the signal multi-scale features with the key change point features on the time axis according to a dynamic time warping algorithm to obtain a standardized electrical signal sequence and a continuous temperature distribution curve aligned on the time axis, and jointly modeling the standardized electrical signal sequence and the continuous temperature distribution curve aligned on the time axis using a multi-dimensional matrix correlation algorithm to generate a correlation matrix; applying kernel principal component analysis to perform feature dimensionality reduction on the correlation matrix, extracting the main correlation dimensions and forming a simplified matrix, and performing spatial smoothing constraints on the simplified matrix through a spatial smoothing algorithm to obtain a dynamic operating condition mapping matrix.

[0010] As a preferred scheme, the step of jointly modeling the standardized electrical signal sequence after time axis alignment and the continuous temperature distribution curve after time axis alignment by using a multidimensional matrix association algorithm to generate an association matrix includes: performing time-frequency analysis on the standardized electrical signal sequence after time axis alignment based on short-time Fourier transform, extracting time-varying spectrum features, and obtaining an electrical signal spectrum matrix; smoothing the continuous temperature distribution curve after time axis alignment by cubic spline interpolation to remove high-frequency noise components and obtain a smooth temperature curve; calculating the dynamic correlation coefficient between the electrical signal spectrum matrix and the smooth temperature curve by dynamic correlation analysis to form a signal-temperature correlation matrix, extracting features from the signal-temperature correlation matrix by principal component analysis to obtain a principal component feature matrix; applying a weighted graph embedding algorithm to topologically model the principal component feature matrix to construct a multidimensional topological feature matrix, performing feature clustering on the multidimensional topological feature matrix by non-negative matrix decomposition, extracting main correlation features, and generating an association matrix.

[0011] As a preferred scheme, the steps of using a preset fault mode library to perform pattern matching on the dynamic operating condition mapping matrix, identifying potential defect types and location coordinates, inputting the device surface morphology characteristics and the potential defect types and location coordinates into a composite scoring model, and generating a comprehensive quality score include: using a K-nearest neighbor classification method to classify the dynamic operating condition mapping matrix to generate a preliminary classification result of potential defects, performing weighted matching on the preliminary classification result of potential defects with templates in a preset fault mode library to generate potential defect types and location coordinates; combining the potential defect types and the location coordinates with the device surface morphology characteristics to generate a defect-morphology joint feature set, and inputting the defect-morphology joint feature set into a preset Gaussian mixture model to obtain a comprehensive quality score.

[0012] As a preferred embodiment, the step of weighted matching the preliminary classification result of the potential defect with the template in the preset fault mode library to generate the potential defect type and location coordinates includes: using Euclidean distance measurement to match the preliminary classification result of the potential defect with the template in the preset fault mode library, calculating the weighted distance between each template in the fault mode library and the preliminary classification result of the potential defect, and obtaining a weighted matching score; according to the sorting of the weighted matching scores, selecting the template with the highest score for matching, and generating the potential defect type and location coordinates based on the matching results.

[0013] As a preferred scheme, the step of inputting the defect-morphology joint feature set into a preset Gaussian mixture model to obtain a comprehensive quality score includes: performing density estimation on the defect-morphology joint feature set through a Gaussian mixture model to obtain a defect distribution probability, performing regression calculation on the defect distribution probability and the structural parameters of the semiconductor device using principal component regression analysis to generate preliminary quality influencing factors; using a random forest decision tree to perform hierarchical screening on the preliminary quality influencing factors to obtain a main influencing feature set, performing time series derivation on the main influencing feature set based on a dynamic Bayesian network to obtain a device quality change trend; applying a hierarchical fuzzy reasoning method to perform quality assessment on the device quality change trend to obtain a quality score matrix, and performing confidence calculation on the quality score matrix based on maximum a posteriori estimation to obtain a comprehensive quality score.

[0014] As a preferred embodiment, the step of grading the comprehensive quality score using a preset rating standard to obtain a semiconductor test result includes: grading the comprehensive quality score using a preset rating standard to generate a type grading result, combining the type grading result with the potential defect type and the position coordinates to perform a spatial distribution analysis to generate a spatial distribution grading result; and cross-validating the spatial distribution grading result with the comprehensive quality score to obtain a semiconductor test result.

[0015] The present application also provides a semiconductor testing device, including: an acquisition module, used to acquire electrical signal parameters, temperature data and optical image information of semiconductor devices; a processing module, used to normalize the electrical signal parameters to obtain a standardized electrical signal sequence, perform time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, perform edge enhancement and feature segmentation on the optical image information, and extract device surface morphology characteristics; an analysis module, used to perform multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic operating condition mapping matrix; a matching module, used to perform pattern matching on the dynamic operating condition mapping matrix using a preset fault mode library, identify potential defect types and location coordinates, input the device surface morphology characteristics and the potential defect types and location coordinates into a composite scoring model, and generate a comprehensive quality score; a grading module, used to grade the comprehensive quality score using a preset rating standard to obtain a semiconductor test result.

[0016] Compared with the prior art, the present application has the following beneficial effects: accurate testing and comprehensive analysis. By collecting the electrical signal parameters, temperature data and optical image information of semiconductor devices, and performing normalization, time series interpolation fitting, edge enhancement and feature segmentation on these data, a detailed analysis of various aspects of the device is achieved, and a multi-dimensional correlation analysis is performed using a standardized electrical signal sequence and a continuous temperature distribution curve to generate a dynamic working condition mapping matrix, which can fully reflect the working state of the device, and identify the potential defect type and position coordinates by pattern matching with a preset fault mode library, and input a composite scoring model in combination with the surface morphology characteristics of the device to generate a comprehensive quality score, and further use the rating standard for grading to obtain semiconductor test results, improve the accuracy of defect identification, and achieve a comprehensive quality assessment of semiconductor devices, effectively improve the reliability and quality control level of the test, and improve the problem that in practical applications, the information of electrical parameters, temperature and optical images is independently obtained, lacks multi-dimensional correlation analysis, and is difficult to fully evaluate the dynamic working conditions of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0019] Figure 1 is a flow chart of a semiconductor testing method provided by an embodiment of the present invention; Figure 2 It is a schematic block diagram of the structure of a semiconductor testing device provided by an embodiment of the present invention.

[0020] Description of reference numerals: 10. Semiconductor testing device; 11. Acquisition module; 12. Processing module; 13. Analysis module; 14. Matching module; 15. Classification module. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0023] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0024] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0025] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0026] Embodiment 1: like Figure 1 As shown, the present application provides a semiconductor testing method, including steps S100 to S500.

[0027] Step S100: collecting electrical signal parameters, temperature data and optical image information of semiconductor devices.

[0028] In this step, the test equipment is used to measure the electrical signal parameters of the semiconductor device, and the current, voltage and other data of the device under different working conditions are recorded. At the same time, the surface temperature data of the semiconductor device is obtained by thermocouples or infrared thermal imagers, and the temperature changes at different time points are recorded. In addition, the device surface is optically imaged using a high-resolution microscope to obtain detailed image information of the device surface. Specifically, the on-resistance and threshold voltage of the device are measured by the current-voltage characteristic curve, the heat flux density distribution of the device is measured using a thermocouple, and the surface defects and morphological characteristics of the device are analyzed using an optical microscope.

[0029] For example, in the acquisition of electrical signal parameters, a source measurement unit is used to measure the current-voltage characteristics of MOSFET; in temperature data acquisition, an infrared thermal imager is used to record the temperature changes of the device during heating and cooling; in optical image information acquisition, a high-power microscope is used to capture the device surface image, and image processing software is used for edge enhancement and feature extraction.

[0030] Step S200, normalize the electrical signal parameters to obtain a standardized electrical signal sequence, perform time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, perform edge enhancement and feature segmentation on the optical image information, and extract the surface morphology characteristics of the device.

[0031] In this step, the collected electrical signal parameters are first normalized to eliminate the influence of different test conditions and obtain a standardized electrical signal sequence. Then, the temperature data is time-series interpolation fitting is performed to generate a continuous temperature distribution curve, which is convenient for observing the temperature change trend over time. At the same time, the optical image information is edge enhanced to highlight the surface features of the device, and feature segmentation is performed to extract representative morphological features. Specifically, the least squares method is used to normalize the electrical signal parameters, the polynomial interpolation method is used to perform time-series fitting on the temperature data, and the Sobel operator is used to detect and enhance the edges of the optical image.

[0032] For example, when normalizing electrical signal parameters, the current-voltage curves under different test environments are standardized; when performing time series interpolation fitting of temperature data, the cubic spline interpolation method is used to generate the temperature change curve; when processing optical image information, the Canny edge detection operator is used to extract device surface defects.

[0033] Step S300: Perform multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic working condition mapping matrix.

[0034] In this step, a mapping matrix that can reflect the dynamic working conditions of semiconductor devices is generated by performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve. This mapping matrix can comprehensively reflect the working state of the device under different electrical signal and temperature conditions, facilitating comprehensive performance evaluation. Specifically, the Pearson correlation coefficient is used to calculate the correlation between the electrical signal sequence and the temperature curve, and the principal component analysis (PCA) is used to reduce the dimension to generate the dynamic working condition mapping matrix.

[0035] For example, the current variation curves under different working voltages are correlated with the corresponding temperature distribution to obtain a voltage-temperature dynamic operating condition mapping matrix.

[0036] Step S400: Use a preset fault mode library to perform pattern matching on the dynamic operating condition mapping matrix, identify potential defect types and location coordinates, input device surface morphology characteristics and potential defect types and location coordinates into a composite scoring model, and generate a comprehensive quality score.

[0037] In this step, the generated dynamic condition mapping matrix is ​​pattern matched with the preset fault mode library to identify the potential defect types and specific locations of the device. Then, the morphological features of the device surface are input into the composite scoring model together with the identified potential defect types and location coordinates to generate a comprehensive quality score for the device. Specifically, the KNN algorithm is used to pattern match the dynamic condition mapping matrix, and the device surface defect features are extracted through morphological analysis, and these features are input into the machine learning model for comprehensive quality scoring.

[0038] For example, the support vector machine (SVM) model is used to classify the mapping results of electrical signal parameters and temperature data, identify typical failure modes, and locate defect locations; the identified potential defect types are combined with the defect morphology features in the optical image to perform a comprehensive quality score.

[0039] Step S500: grade the comprehensive quality score using a preset rating standard to obtain a semiconductor test result.

[0040] In this step, the generated comprehensive quality score is graded according to the preset rating standard to obtain the final semiconductor device test result. The test result can be used as a basis for device quality assessment and fault diagnosis. Specifically, the comprehensive quality score is graded according to four levels: A, B, C, and D, corresponding to different quality and reliability levels.

[0041] For example, devices with an overall quality score of 90 or above are classified as Grade A, devices with a score between 80 and 90 are classified as Grade B, devices with a score between 70 and 80 are classified as Grade C, and devices with a score below 70 are classified as Grade D.

[0042] In this embodiment, the electrical signal parameters, temperature data and optical image information of the semiconductor device are collected. Then the electrical signal parameters are normalized to obtain a standardized electrical signal sequence. Then the temperature data is interpolated and fitted in a time series to generate a continuous temperature distribution curve. At the same time, the optical image information is edge enhanced and feature segmented to extract the surface morphology characteristics of the device. The standardized electrical signal sequence and the continuous temperature distribution curve are multi-dimensionally correlated and analyzed to generate a dynamic working condition mapping matrix. Finally, the dynamic working condition mapping matrix is ​​pattern matched using a preset fault mode library to identify the potential defect type and position coordinates, and the device surface morphology characteristics and the potential defect type and position coordinates are input into a composite scoring model to generate a comprehensive quality score, and finally the comprehensive quality score is graded using a preset rating standard to obtain a semiconductor test result. Through the multi-dimensional correlation analysis of electrical signal parameters, temperature data and optical image information, the dynamic working condition of the semiconductor device can be evaluated more comprehensively and accurately. The composite scoring model is used to perform pattern matching and quality scoring on the potential defect type and its location, which not only improves the accuracy of defect identification, but also realizes the comprehensive quality evaluation of semiconductor devices. Improve the problem that in practical applications, the information of electrical parameters, temperature and optical images is obtained independently, lacking multi-dimensional correlation analysis, and it is difficult to comprehensively evaluate the dynamic working conditions of the device.

[0043] Embodiment 2: In step S100, the current, voltage and frequency signals of the device are synchronously acquired through a multi-channel electrical signal acquisition module to obtain raw electrical signal data, and signal filtering and denoising are performed on the raw electrical signal data to obtain electrical signal parameters.

[0044] The current, voltage and frequency signals of the device are synchronously collected through the multi-channel electrical signal acquisition module. During the acquisition process, the original electrical signal data is filtered using anti-aliasing filters and high-order bandpass filters to remove noise signals. The filtered signal is digitally denoised, and the adaptive noise reduction algorithm is used to eliminate the remaining noise to obtain the purified electrical signal parameters. Specifically, various types of signals are synchronously acquired through the high-precision current sensor, voltage sensor and frequency meter in the multi-channel acquisition module. After the electrical signal parameters are subjected to data filtering, the wavelet denoising algorithm is used to purify the signal to obtain more accurate electrical signal parameters.

[0045] For example, in current signal acquisition, the instantaneous current value of the device is recorded by a high-precision current sensor, and high-frequency noise is removed by an anti-aliasing filter; in voltage signal acquisition, a high-precision voltage sensor is used to synchronously obtain the change curve under different working voltages, and a high-order bandpass filter is used to remove low-frequency interference; in frequency signal acquisition, a frequency meter is used to measure the frequency changes of the device under different working conditions, and an adaptive noise reduction algorithm is used to eliminate interference.

[0046] The distributed temperature sensor array collects device data at preset time intervals to obtain a discrete temperature point set, and the density of the discrete temperature point set is compensated by a spatial interpolation algorithm to obtain temperature data.

[0047] Multiple sensors are arranged on the device surface through a distributed temperature sensor array, and temperature data is synchronously collected at preset time intervals to form a temperature discrete point set. The spatial interpolation algorithm is used to perform density compensation on the temperature discrete point set to generate a continuous temperature distribution curve to better reflect the temperature changes on the device surface. Specifically, a uniformly distributed temperature sensor array is used to ensure uniform temperature data collection in different areas, and the Kriging interpolation method is used to interpolate the temperature discrete point set to improve the density and accuracy of the temperature data.

[0048] For example, by placing 9 temperature sensors on the surface of a semiconductor device, the temperature changes every second are recorded and a discrete temperature point set is formed. Then, the Kriging interpolation method is used to perform density compensation on these points to generate a detailed temperature distribution curve that reflects the temperature changes of the device under different working conditions.

[0049] The optical image of the device surface area is captured by a high-resolution optical imaging device to form an optical image sequence, and the optical image sequence is subjected to inter-frame alignment and distortion correction to obtain optical image information.

[0050] The device surface is scanned and imaged by high-resolution optical imaging equipment to obtain optical image sequences at different time points. These images are aligned between frames to eliminate displacement errors caused by the movement or vibration of the imaging equipment. Distortion correction algorithms are used to correct image distortion to obtain clear and accurate optical image information. Specifically, digital image processing technology is used to perform sub-pixel frame alignment on the optical image sequence, and radial distortion correction algorithms and Chebyshev polynomials are used to correct image distortion to ensure image consistency and accuracy.

[0051] For example, in image acquisition, the device surface is imaged multiple times by a high-resolution microscope to obtain an optical image sequence. Each frame of the image is aligned using sub-pixel alignment technology to eliminate tiny displacement errors, and lens distortion is corrected using a radial distortion correction algorithm to ultimately obtain clear optical image information.

[0052] In step S200, the electrical signal parameters are normalized at multiple scales by using a normalization algorithm based on the signal amplitude range to obtain a standardized electrical signal sequence.

[0053] The collected electrical signal parameters are normalized by a normalization algorithm based on the signal amplitude range, eliminating the influence of different measurement conditions and environment, and obtaining a standardized electrical signal sequence. Specifically, for different voltage and current signals, the minimum-maximum normalization method is used to normalize each signal parameter to the same range, so as to facilitate subsequent analysis and processing. Specifically, for each signal sample, its amplitude range is calculated, and linear scaling is performed according to the maximum and minimum values ​​so that it falls into the predetermined standardized range.

[0054] For example, when normalizing the current signal, the current values ​​under different measurement conditions are converted to the range of 0 to 1 through the minimum-maximum normalization method to ensure data consistency; when normalizing the voltage signal, the voltage value is normalized using the same method to make it comparable under different environments.

[0055] The time series regression model is used to perform time series fitting on the temperature data to generate a continuous temperature distribution curve.

[0056] The collected temperature data is fitted in time series through the time series regression model to generate a continuous temperature distribution curve to accurately describe the temperature change over time. Specifically, the temperature data is modeled using the autoregressive integrated moving average model (ARIMA), and the temperature change trend is predicted through the fitting process to generate a continuous temperature distribution curve. Specifically, the time series characteristics of the temperature data are used to construct the ARIMA model, perform parameter estimation and model verification, and finally generate a suitable data fitting model.

[0057] For example, in the process of fitting temperature data, the ARIMA model is trained using past temperature data, and the model is used to predict future temperature changes. The temperature data is fitted with the ARIMA model to generate a continuous temperature distribution curve from the initial to the current time point, accurately reflecting the temperature changes of the device.

[0058] A multi-directional gradient operator is used to perform edge enhancement on optical image information to generate an enhanced edge map. A region growing algorithm is used to extract and partition the surface features of the enhanced edge map to obtain the surface morphology of the device.

[0059] The optical image information is edge enhanced by a multi-directional gradient operator to generate an enhanced edge map to highlight the subtle features of the device surface. Then, the enhanced edge map is subjected to surface feature extraction and partitioning by a region growing algorithm to obtain accurate device surface morphological features. Specifically, the Sobel operator is used to perform multi-directional edge detection and enhancement on the optical image to generate an enhanced image containing significant edge features. Then, the enhanced image is subjected to feature extraction by a region growing algorithm to segment representative morphological feature regions.

[0060] For example, when performing edge enhancement on an optical image, the Sobel operator is used to detect image edges from multiple directions to generate an enhanced image containing rich edge information. When performing region segmentation on the enhanced image, the region growing algorithm is used to extract and partition edge regions with distinct features to obtain complete device surface morphology features.

[0061] In step S300, the standardized electrical signal sequence is subjected to multi-scale signal decomposition by wavelet transform, low-frequency trend signals and high-frequency transient signals are extracted, and multi-scale signal features are obtained.

[0062] The standardized electrical signal sequence is decomposed into multi-scale signals by wavelet transform, and the low-frequency trend signal and high-frequency transient signal are extracted to obtain the multi-scale characteristics of the signal. Specifically, the standardized electrical signal sequence is decomposed by discrete wavelet transform (DWT) to extract detail coefficients and approximation coefficients at different scales. Specifically, for each signal sequence, multi-level wavelet decomposition is performed to obtain signal features of different resolutions, and low-frequency and high-frequency components are extracted from them.

[0063] For example, when performing wavelet decomposition on electrical signals, a suitable wavelet basis function (such as Daubechies wavelet) is selected to perform multi-level decomposition of the electrical signal sequence to obtain details and approximation coefficients at multiple scales, and extract low-frequency trend signals and high-frequency transient signals as multi-scale features.

[0064] The continuous temperature distribution curve is analyzed by curvature analysis method to extract the key change point features of the curve.

[0065] The generated continuous temperature distribution curve is analyzed by curvature analysis method to extract the key change point characteristics of the curve to reflect the significant position and trend of temperature change. Specifically, the second-order derivative of the temperature distribution curve is calculated by high-order differential method to identify the local extreme value and inflection point of the curve, thereby determining the key change point.

[0066] For example, in the curvature analysis of temperature data, the second-order derivative of the temperature distribution curve is calculated to determine the inflection points of the temperature change. These inflection points represent significant areas of temperature change, such as the heating and cooling stages of the device.

[0067] According to the dynamic time warping algorithm, the multi-scale features of the signal and the key change point features are aligned on the time axis to obtain the standardized electrical signal sequence after time axis alignment and the continuous temperature distribution curve after time axis alignment. The standardized electrical signal sequence after time axis alignment and the continuous temperature distribution curve after time axis alignment are jointly modeled using the multidimensional matrix association algorithm to generate a correlation matrix.

[0068] The dynamic time warping (DTW) algorithm is used to align the extracted signal multi-scale features with the key change point features in time axis, and the standardized electrical signal sequence and the continuous temperature distribution curve after time axis alignment are obtained. Then, the multi-dimensional matrix association algorithm is used to jointly model these aligned data to generate a correlation matrix that can reflect the dynamic working conditions of the device. Specifically, the DTW algorithm is used to align the time series of signal and temperature data to ensure that the time points between different signals match. Subsequently, the multi-dimensional matrix association algorithm is used to jointly model the electrical signal and temperature data to generate a comprehensive correlation matrix that reflects the correlation between different parameters.

[0069] For example, when aligning the time axis of electrical signals and temperature data, the DTW algorithm is used to match the voltage change and temperature change points at different times to ensure data consistency. Then, the matched data is modeled through a multi-dimensional matrix association algorithm to generate an association matrix that reflects the relationship between voltage, temperature, and time.

[0070] Kernel principal component analysis is used to reduce the dimension of the correlation matrix, extract the main correlation dimensions and form a simplified matrix. The simplified matrix is ​​spatially smoothed by a spatial smoothing algorithm to obtain a dynamic working condition mapping matrix.

[0071] The generated correlation matrix is ​​subjected to feature dimensionality reduction by applying kernel principal component analysis (KPCA), the main correlation dimensions are extracted, and a simplified matrix is ​​formed. Then, the simplified matrix is ​​subjected to spatial smoothing constraints by a spatial smoothing algorithm, and a dynamic operating condition mapping matrix is ​​obtained to reflect the comprehensive working state of the device. Specifically, the KPCA method is used to reduce the dimensionality of the features in the correlation matrix, select the main feature dimensions, and generate a simplified feature matrix. Next, the bilinear interpolation algorithm is used to perform spatial smoothing on the simplified matrix to remove noise and outliers in the data.

[0072] For example, when performing feature dimensionality reduction on the correlation matrix, the KPCA algorithm is used to extract the first few dimensions with the highest correlation to generate a simplified matrix. When performing spatial smoothing constraints on the simplified matrix, the bilinear interpolation method is used to smooth the matrix, and finally a mapping matrix reflecting the dynamic working conditions is obtained.

[0073] Among them, the standardized electrical signal sequence after time axis alignment and the continuous temperature distribution curve after time axis alignment are jointly modeled using a multidimensional matrix association algorithm to generate a correlation matrix, including: performing time-frequency analysis on the standardized electrical signal sequence after time axis alignment based on short-time Fourier transform, extracting time-varying spectrum features, and obtaining an electrical signal spectrum matrix.

[0074] By performing time-frequency analysis on the standardized electrical signal sequence after time axis alignment based on short-time Fourier transform (STFT), its time-varying spectrum features are extracted to obtain the electrical signal spectrum matrix, which is further used to generate the correlation matrix. Specifically, the STFT method is used to perform time-frequency transformation on the aligned electrical signal to generate a spectrum diagram, and the time-varying spectrum features are extracted from it to construct the electrical signal spectrum matrix.

[0075] For example, when performing time-frequency analysis on the aligned electrical signal, the STFT algorithm is used to generate a spectrum diagram of the electrical signal, from which the spectrum features at different time points are extracted to construct a spectrum matrix representing the characteristics of the electrical signal.

[0076] The continuous temperature distribution curve after time axis alignment is smoothed by cubic spline interpolation method to remove high-frequency noise components and obtain a smooth temperature curve.

[0077] The continuous temperature distribution curve after time axis alignment is smoothed by cubic spline interpolation to remove high-frequency noise components and obtain a smoother temperature change curve. This helps to improve the accuracy and stability of the data. Specifically, the cubic spline interpolation algorithm is used to smooth the temperature data, eliminate noise interference, and generate a smooth temperature distribution curve.

[0078] For example, when smoothing temperature data, the unsmoothed temperature curve is interpolated using the cubic spline interpolation method to remove high-frequency noise and ultimately obtain a more accurate temperature change curve.

[0079] The dynamic correlation coefficient between the electrical signal spectrum matrix and the smooth temperature curve is calculated using dynamic correlation analysis to form a signal-temperature correlation matrix. The principal component analysis is used to extract features from the signal-temperature correlation matrix to obtain a principal component feature matrix.

[0080] The dynamic correlation coefficient between the electrical signal spectrum matrix and the smooth temperature curve is calculated through dynamic correlation analysis to form a signal-temperature correlation matrix that reflects the relationship between the signal and temperature. Then, the signal-temperature correlation matrix is ​​feature extracted through principal component analysis (PCA) to obtain the principal component feature matrix, which reflects the main correlation features. Specifically, the dynamic correlation analysis method is used to calculate the correlation coefficient matrix between the electrical signal spectrum and the temperature data, and the PCA algorithm is used to extract the main feature dimensions to generate the principal component feature matrix.

[0081] For example, when calculating the dynamic correlation coefficient between the signal and temperature, a correlation matrix containing the relationship between the two is generated through the dynamic correlation analysis method. Then, the PCA algorithm is used to reduce the dimension of the correlation matrix and obtain the main feature matrix, which reflects the correlation characteristics between the signal and temperature.

[0082] The weighted graph embedding algorithm is applied to perform topological modeling on the principal component feature matrix, and a multi-dimensional topological feature matrix is ​​constructed. The multi-dimensional topological feature matrix is ​​clustered through non-negative matrix decomposition, and the main correlation features are extracted to generate a correlation matrix.

[0083] The weighted graph embedding algorithm is applied to topologically model the principal component feature matrix, and a topological feature matrix that reflects the multidimensional feature relationship is constructed. Subsequently, the non-negative matrix factorization (NMF) method is used to perform feature clustering on the topological feature matrix, extract the main correlation features, and generate the final correlation matrix. Specifically, the weighted graph embedding method is used to topologically model the principal component feature matrix, forming a topological matrix that represents the feature relationship. Then, the NMF method is used to decompose and cluster the topological matrix to extract the representative main features.

[0084] For example, when topologically modeling the principal component feature matrix, a weighted graph embedding algorithm is used to construct a topological relationship graph between features. Subsequently, the NMF algorithm is used to perform cluster analysis on the topological relationship graph, extract the main correlation features, and generate the final correlation matrix.

[0085] In step S400, the dynamic operating condition mapping matrix is ​​classified using the K nearest neighbor classification method to generate a preliminary classification result of potential defects, and the preliminary classification result of potential defects is weightedly matched with the template in the preset fault mode library to generate the potential defect type and location coordinates.

[0086] The K-nearest neighbor classification method is used to classify the data of the dynamic working condition mapping matrix to generate preliminary classification results of potential defects. Specifically, the K-nearest neighbor classification method is used to classify the data into different defect categories according to the characteristics in the dynamic working condition mapping matrix, and the location and type of potential defects are preliminarily identified.

[0087] For example, in the dynamic working condition mapping matrix, according to the distance relationship between each sample point, the K nearest neighbor algorithm is used to classify them into several known types of defects to generate preliminary classification results.

[0088] The potential defect type and position coordinates are combined with the device surface morphology characteristics to generate a defect-morphology joint feature set, which is then input into a preset Gaussian mixture model to obtain a comprehensive quality score.

[0089] By combining the identified potential defect types with their location coordinates and the morphological features of the device surface, a defect-morphology joint feature set is generated. Specifically, the location information of the potential defects is fused with the morphological features extracted from the device surface to form a comprehensive feature set.

[0090] For example, the morphological features in the optical image information and the potential defect types and position coordinates in the preliminary classification results are combined to form a complete defect-morphology joint feature set.

[0091] Among them, the step of weighted matching the preliminary classification results of potential defects with the templates in the preset fault mode library to generate the potential defect type and location coordinates includes: using Euclidean distance measurement to match the preliminary classification results of potential defects with the templates in the preset fault mode library, calculating the weighted distance between each template in the fault mode library and the preliminary classification results of potential defects to obtain a weighted matching score, selecting the template with the highest score for matching according to the sorting of the weighted matching scores, and generating the potential defect type and location coordinates based on the matching results.

[0092] By using the Euclidean distance metric, the preliminary classification results of potential defects are matched with the templates in the fault mode library, and the weighted distance between each template and the classification result is calculated to determine the matching score. According to the matching score, the type of potential defect and its specific location coordinates are determined. Specifically, the Euclidean distance formula is used to calculate the distance between each classification result and the template, and weighted according to the weight coefficient to obtain the matching score.

[0093] For example, in the matching process, the Euclidean distance between the classification result and each template in the fault mode library is calculated, combined with the preset weight coefficient, to obtain a weighted matching score. The template with the highest score is selected as the final matching result to determine the type and location coordinates of the potential defect.

[0094] Among them, the step of inputting the defect-morphology joint feature set into a preset Gaussian mixture model to obtain a comprehensive quality score includes: performing density estimation on the defect-morphology joint feature set through a Gaussian mixture model to obtain the defect distribution probability, and using principal component regression analysis to regress the defect distribution probability and the structural parameters of the semiconductor device to generate preliminary quality influencing factors.

[0095] By inputting the defect-morphology joint feature set into the preset Gaussian mixture model, density estimation is performed to obtain the defect distribution probability. Specifically, the Gaussian mixture model is used to estimate the probability density of each joint feature and calculate its probability of occurrence. Then, the principal component regression analysis method is used to regress the defect distribution probability and the structural parameters of the semiconductor device to generate preliminary quality influencing factors.

[0096] For example, when analyzing the defect-morphology joint feature set, the distribution probability of each feature is calculated through the Gaussian mixture model, and these probabilities are regressed with the electrical performance parameters of the device through principal component regression analysis to generate preliminary quality influencing factors.

[0097] The random forest decision tree is used to perform hierarchical screening of preliminary quality influencing factors to obtain the main influencing feature set. The time series of the main influencing feature set is derived based on the dynamic Bayesian network to obtain the device quality change trend.

[0098] The random forest decision tree algorithm is used to perform hierarchical screening on the initially generated quality influencing factors and select the main influencing feature set. Specifically, the random forest algorithm is used to screen out the features that have a significant impact on quality assessment from the initial quality influencing factors. Then, the dynamic Bayesian network is used to derive the time series of these main influencing feature sets to predict the quality change trend of the device.

[0099] For example, when screening the initial quality influencing factors, the random forest algorithm is used to evaluate the contribution of each factor and select the main influencing feature set. Then, these features are analyzed in time series through the dynamic Bayesian network to generate a quality change trend chart of the device.

[0100] The hierarchical fuzzy reasoning method is used to evaluate the quality trend of device quality and obtain the quality score matrix. The confidence of the quality score matrix is ​​calculated based on the maximum a posteriori estimation to obtain the comprehensive quality score.

[0101] By applying the hierarchical fuzzy reasoning method, the quality change trend of the generated device is evaluated to obtain the quality score matrix. Specifically, the hierarchical fuzzy reasoning method is used to convert the quality change trend data into score values ​​and construct the quality score matrix. Then, based on the maximum a posteriori estimation method, the confidence of the quality score matrix is ​​calculated to finally obtain the comprehensive quality score of the device.

[0102] For example, in the quality assessment process, the quality change trend derived from the time series is converted into a specific score through the hierarchical fuzzy reasoning method, and a quality score matrix is ​​generated. Subsequently, the confidence of the score is calculated through the maximum a posteriori estimation to determine the final comprehensive quality score.

[0103] In step S500, the comprehensive quality score is graded using a preset rating standard to generate a type grading result, and the type grading result is combined with the potential defect type and location coordinates to perform spatial distribution analysis to generate a spatial distribution grading result.

[0104] By using the preset rating standards, the comprehensive quality score is graded to generate the type classification result of the device. Specifically, according to the preset rating standards, the comprehensive quality score is divided into different levels, and the spatial distribution analysis is performed in combination with the potential defect type and location coordinates to generate the final spatial distribution classification result.

[0105] For example, when grading the comprehensive quality score, the score is divided into four levels: A, B, C, and D. Then, these grading results are combined with the potential defect type and location coordinates to perform spatial distribution analysis and generate the spatial distribution grading results of the device.

[0106] The semiconductor test results are obtained by cross-validating the spatial distribution classification results with the comprehensive quality score.

[0107] The final semiconductor test result is obtained by cross-validating the spatial distribution classification result and the comprehensive quality score. Specifically, the spatial distribution classification result is compared with the comprehensive quality score by a cross-validation method to verify the consistency of the result and obtain a reliable semiconductor test result.

[0108] For example, during the verification process, the spatial distribution grading results are compared with the comprehensive quality score to ensure the consistency of the results and ultimately confirm the accuracy and reliability of the semiconductor test results.

[0109] In this embodiment, the current, voltage and frequency signals of the device are synchronously acquired through a multi-channel electrical signal acquisition module, and the original electrical signal data is subjected to signal filtering and denoising to obtain the purified electrical signal parameters. The temperature data of the device is collected by a distributed temperature sensor array, and density compensation is performed by a spatial interpolation algorithm to form a continuous temperature distribution curve. A high-resolution optical imaging device is used to capture the surface image of the device, and inter-frame alignment and distortion correction are performed to obtain accurate optical image information. The electrical signal parameters are subjected to multi-scale normalization processing to obtain a standardized electrical signal sequence, and a continuous temperature distribution curve is generated using a time series regression model. The optical image edge is enhanced by a multi-directional gradient operator to extract the surface morphology features of the device. In the data analysis stage, the multi-scale features of the signal are extracted by wavelet transform, and the key change points of the temperature curve are extracted by the curvature analysis method. The data is aligned on the time axis by a dynamic time warping algorithm, the correlation matrix is ​​generated by a multi-dimensional matrix correlation algorithm, and the dynamic working condition mapping matrix is ​​obtained by applying the kernel principal component analysis and the spatial smoothing algorithm. Subsequently, the K nearest neighbor classification method is used to classify the dynamic working condition mapping matrix to generate preliminary classification results of potential defects, and the Euclidean distance metric is used to perform weighted matching with the fault mode library template to determine the potential defect type and location coordinates. The potential defect type and location coordinates are combined with the surface morphology characteristics of the device to generate a defect-morphology joint feature set, and the Gaussian mixture model is used to perform density estimation and principal component regression analysis to generate preliminary quality influencing factors. Finally, the random forest decision tree and dynamic Bayesian network are used to analyze the quality influencing factors, and the hierarchical fuzzy reasoning method and maximum a posteriori estimation are used to perform comprehensive quality scoring, and the scoring results are verified using spatial distribution analysis to obtain reliable semiconductor test results. This embodiment achieves more accurate defect identification and quality assessment through multi-dimensional data fusion and comprehensive analysis, effectively improving the test reliability and quality control level of semiconductor devices.

[0110] Embodiment 3: like Figure 2 As shown, the present application also provides a semiconductor testing device 10 , including a collection module 11 , a processing module 12 , an analysis module 13 , a matching module 14 and a grading module 15 .

[0111] The acquisition module 11 is mainly used to acquire electrical signal parameters, temperature data and optical image information of semiconductor devices.

[0112] The processing module 12 is mainly used to normalize the electrical signal parameters to obtain a standardized electrical signal sequence, perform time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, perform edge enhancement and feature segmentation on the optical image information, and extract the surface morphology characteristics of the device.

[0113] The analysis module 13 is mainly used to perform multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic working condition mapping matrix.

[0114] The matching module 14 is mainly used to use the preset fault mode library to perform pattern matching on the dynamic working condition mapping matrix, identify the potential defect type and location coordinates, input the device surface morphology characteristics and the potential defect type and location coordinates into the composite scoring model, and generate a comprehensive quality score.

[0115] The grading module 15 is mainly used to grade the comprehensive quality scores using a preset grading standard to obtain semiconductor test results.

[0116] In this embodiment, by setting up the collaborative work of the acquisition module 11, the processing module 12, the analysis module 13, the matching module 14 and the grading module 15, a comprehensive test and evaluation of semiconductor devices is achieved. The acquisition module 11 collects the electrical signal parameters, temperature data and optical image information of the semiconductor device through a multi-channel electrical signal acquisition device, a distributed temperature sensor array and a high-resolution optical imaging device. The processing module 12 normalizes the electrical signal parameters to obtain a standardized electrical signal sequence; performs time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve; performs edge enhancement and feature segmentation on the optical image information to extract the surface morphology characteristics of the device. The analysis module 13 generates a dynamic working condition mapping matrix by performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve. The matching module 14 uses a preset fault mode library to perform pattern matching on the dynamic working condition mapping matrix, identifies the potential defect type and position coordinates, and inputs the device surface morphology characteristics and the potential defect type and position coordinates into a composite scoring model to generate a comprehensive quality score. The grading module 15 grades the comprehensive quality score according to the preset rating standard to obtain the semiconductor test result. Through modular design, efficient and accurate semiconductor device quality assessment is achieved, which is highly operable and scalable. It not only improves the reliability of test results, but also provides effective support for subsequent fault diagnosis and quality control.

[0117] It should be noted that technicians in the relevant technical field can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described device and each module can refer to the corresponding process in the aforementioned semiconductor testing method embodiment, and will not be repeated here.

[0118] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0119] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor testing method, characterized in that: include: Collect electrical signal parameters, temperature data and optical image information of semiconductor devices; Normalizing the electrical signal parameters to obtain a standardized electrical signal sequence, performing time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, performing edge enhancement and feature segmentation on the optical image information to extract device surface morphology features; Performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic working condition mapping matrix; Using a preset fault mode library to perform pattern matching on the dynamic working condition mapping matrix, identifying potential defect types and location coordinates, inputting the device surface morphology characteristics and the potential defect types and location coordinates into a composite scoring model to generate a comprehensive quality score; The comprehensive quality score is graded using a preset rating standard to obtain a semiconductor test result.

2. The semiconductor testing method according to claim 1, characterized in that: The step of collecting electrical signal parameters, temperature data and optical image information of semiconductor devices includes: The current, voltage and frequency signals of the device are synchronously acquired through a multi-channel electrical signal acquisition module to obtain raw electrical signal data, and the raw electrical signal data is subjected to signal filtering and denoising to obtain electrical signal parameters; The distributed temperature sensor array is used to collect device data at preset time intervals to obtain a temperature discrete point set, and the temperature discrete point set is density compensated by a spatial interpolation algorithm to obtain temperature data; An optical image of the device surface area is captured using a high-resolution optical imaging device to form an optical image sequence, and the optical image sequence is subjected to frame alignment and distortion correction to obtain optical image information.

3. The semiconductor testing method according to claim 1, characterized in that: The steps of normalizing the electrical signal parameters to obtain a standardized electrical signal sequence, performing time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, performing edge enhancement and feature segmentation on the optical image information, and extracting device surface morphology features include: Performing multi-scale normalization on the electrical signal parameters by a normalization algorithm based on the signal amplitude range to obtain a standardized electrical signal sequence; Performing time series fitting on the temperature data using a time series regression model to generate a continuous temperature distribution curve; The optical image information is subjected to edge enhancement processing by using a multi-directional gradient operator to generate an enhanced edge map, and the surface features of the enhanced edge map are extracted and partitioned by using a region growing algorithm to obtain device surface morphology features.

4. The semiconductor testing method according to claim 1, characterized in that: The step of performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic operating condition mapping matrix includes: Performing multi-scale signal decomposition on the standardized electrical signal sequence by wavelet transform, extracting low-frequency trend signals and high-frequency transient signals, and obtaining multi-scale signal features; The continuous temperature distribution curve is analyzed by curvature analysis method to extract the key change point characteristics of the curve; The multi-scale features of the signal are aligned with the key change point features on the time axis according to a dynamic time warping algorithm to obtain a standardized electrical signal sequence after the time axis alignment and a continuous temperature distribution curve after the time axis alignment, and the standardized electrical signal sequence after the time axis alignment and the continuous temperature distribution curve after the time axis alignment are jointly modeled using a multi-dimensional matrix association algorithm to generate an association matrix; The kernel principal component analysis is applied to perform feature dimension reduction on the correlation matrix, the main correlation dimensions are extracted and a simplified matrix is ​​formed, and the simplified matrix is ​​spatially smoothed by a spatial smoothing algorithm to obtain a dynamic working condition mapping matrix.

5. The semiconductor testing method according to claim 4, characterized in that: The step of jointly modeling the standardized electrical signal sequence after time axis alignment and the continuous temperature distribution curve after time axis alignment by using a multidimensional matrix association algorithm to generate an association matrix includes: Based on short-time Fourier transform, time-frequency analysis is performed on the standardized electrical signal sequence after time axis alignment, time-varying spectrum features are extracted, and an electrical signal spectrum matrix is ​​obtained; The continuous temperature distribution curve after the time axis alignment is smoothed by a cubic spline interpolation method to remove high-frequency noise components and obtain a smooth temperature curve; The dynamic correlation coefficient between the electric signal spectrum matrix and the smooth temperature curve is calculated by dynamic correlation analysis to form a signal-temperature correlation matrix, and the feature extraction of the signal-temperature correlation matrix is ​​performed by principal component analysis to obtain a principal component feature matrix; A weighted graph embedding algorithm is applied to perform topological modeling on the principal component feature matrix, a multi-dimensional topological feature matrix is ​​constructed, and feature clustering is performed on the multi-dimensional topological feature matrix through non-negative matrix decomposition, and main correlation features are extracted to generate a correlation matrix.

6. The semiconductor testing method according to claim 1, characterized in that: The step of using a preset fault mode library to perform pattern matching on the dynamic working condition mapping matrix, identifying potential defect types and location coordinates, inputting the device surface morphology characteristics and the potential defect types and location coordinates into a composite scoring model, and generating a comprehensive quality score includes: The dynamic working condition mapping matrix is ​​classified by using a K-nearest neighbor classification method to generate a preliminary classification result of potential defects, and the preliminary classification result of potential defects is weightedly matched with a template in a preset fault mode library to generate a potential defect type and location coordinates; The potential defect type and the position coordinates are combined with the device surface morphology characteristics to generate a defect-morphology joint feature set, and the defect-morphology joint feature set is input into a preset Gaussian mixture model to obtain a comprehensive quality score.

7. The semiconductor testing method according to claim 6, characterized in that: The step of weighted matching the preliminary classification result of the potential defect with the template in the preset fault mode library to generate the potential defect type and location coordinates includes: Using the Euclidean distance metric to match the preliminary classification result of the potential defect with the templates in the preset fault mode library, calculating the weighted distance between each template in the fault mode library and the preliminary classification result of the potential defect, and obtaining a weighted matching score; According to the ranking of the weighted matching scores, the template with the highest score is selected for matching, and the potential defect type and location coordinates are generated based on the matching result.

8. The semiconductor testing method according to claim 6, characterized in that: The step of inputting the defect-morphology joint feature set into a preset Gaussian mixture model to obtain a comprehensive quality score includes: Density estimation is performed on the defect-morphology joint feature set by using a Gaussian mixture model to obtain a defect distribution probability, and principal component regression analysis is used to regress the defect distribution probability and the structural parameters of the semiconductor device to generate a preliminary quality influencing factor; The preliminary quality influencing factors are screened in layers using a random forest decision tree to obtain a main influencing feature set, and the main influencing feature set is deduced in time series based on a dynamic Bayesian network to obtain a device quality change trend; A hierarchical fuzzy reasoning method is applied to perform quality assessment on the quality change trend of the device to obtain a quality score matrix, and a confidence calculation is performed on the quality score matrix based on maximum a posteriori estimation to obtain a comprehensive quality score.

9. The semiconductor testing method according to claim 1, characterized in that: The step of grading the comprehensive quality score using a preset grading standard to obtain a semiconductor test result includes: The comprehensive quality score is graded using a preset rating standard to generate a type grading result, and the type grading result is combined with the potential defect type and the location coordinates to perform spatial distribution analysis to generate a spatial distribution grading result; The spatial distribution classification result is cross-validated with the comprehensive quality score to obtain a semiconductor test result.

10. A semiconductor testing device, characterized in that: include: An acquisition module, used to acquire electrical signal parameters, temperature data and optical image information of semiconductor devices; A processing module, used to normalize the electrical signal parameters to obtain a standardized electrical signal sequence, perform time series interpolation fitting on the temperature data to generate a continuous temperature distribution curve, perform edge enhancement and feature segmentation on the optical image information, and extract device surface morphology features; An analysis module, used for performing multi-dimensional correlation analysis on the standardized electrical signal sequence and the continuous temperature distribution curve to generate a dynamic operating condition mapping matrix; A matching module, used to perform pattern matching on the dynamic working condition mapping matrix using a preset fault mode library, identify potential defect types and location coordinates, input the device surface morphology characteristics and the potential defect types and location coordinates into a composite scoring model, and generate a comprehensive quality score; The grading module is used to grade the comprehensive quality score using a preset grading standard to obtain a semiconductor test result.

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