Semiconductor device

Abstract

A semiconductor device is described, including: a substrate; an active region protruding from the substrate and extending in a first direction; a plurality of channel layers disposed on the active region and spaced apart from each other in a direction perpendicular to an upper surface of the substrate; an isolation film disposed between a lowermost channel layer of the plurality of channel layers and the active region; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; and a source / drain region disposed at least one side of the gate electrode and connected to each of the plurality of channel layers. The isolation film is disposed at a level higher than a bottom surface of the source / drain region.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0061196, filed on May 24, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] Many people use mobile electronic devices such as tablets and mobile phones. Semiconductor devices are commonly used in mobile electronic devices. As the demand for mobile electronic devices increases, semiconductor manufacturing processes must keep pace.

[0005] The increasingly smaller designs of semiconductor devices offer packaging benefits. However, smaller designs can also introduce performance constraints, for example, due to the reduction in semiconductor size. Therefore, improvements to semiconductor design preferably result in size reduction while achieving minimal, no, or improved performance.

[0006] In some cases, performance problems in semiconductor devices can be attributed to current leakage. Furthermore, optimal performance typically requires a stable power supply. Therefore, there is a need in the art to improve the performance of semiconductor devices by reducing current leakage. Summary of the Invention

[0007] This disclosure describes semiconductor devices capable of reducing current leakage through the substrate between adjacent transistors. For example, aspects of the inventive concept include three-dimensional channels with improved electrical properties.

[0008] According to an example embodiment, a semiconductor device is described, the semiconductor device comprising: a substrate; an active region protruding from the substrate in a first direction; channel layers disposed on the active region and spaced apart from each other in a direction perpendicular to an upper surface of the substrate; an isolation film disposed between the lowermost of the plurality of channel layers and the active region; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; and a source / drain region disposed on at least one side of the gate electrode and connected to each of the plurality of channel layers. In some cases, the isolation film is disposed at a horizontal height higher than the bottom surface of the source / drain region.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a substrate; an active region protruding from the substrate and extending in a first direction; a plurality of channel layers disposed on the active region and spaced apart from each other in a direction perpendicular to an upper surface of the substrate; an isolation film disposed between the lowermost of the plurality of channel layers and the active region; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; internal spacers disposed between the plurality of channel layers and on both sides of the gate electrode in the first direction; and a plurality of source / drain regions disposed on both sides of the gate electrode in the first direction and connected to the plurality of channel layers, wherein the edge regions of the internal spacers and the isolation film on both sides in the first direction comprise the same material, and the isolation film is disposed at a horizontal height higher than the bottom surface of the source / drain regions.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a substrate; an active region protruding from the substrate and extending in a first direction; a plurality of channel layers disposed on the active region and spaced apart from each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; internal spacers disposed between the plurality of channel layers and on both sides of the gate electrode in the first direction; an isolation film disposed between the lowermost channel layer of the plurality of channel layers and the active region, wherein the isolation film and the internal spacers have the same material; and source / drain regions disposed on each of the two sides of the gate electrode in the first direction, the bottom surface of the source / drain regions being disposed at a horizontal height below the isolation film, and the source / drain regions being connected to each of the plurality of channel layers. Attached Figure Description

[0011] The above and other aspects, features, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a top view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0013] Figure 2 It is along Figure 1 Cross-sectional views taken from lines I-I' and II-II' in the diagram;

[0014] Figures 3A to 3FThis is a perspective view illustrating a portion of the process of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

[0015] Figures 4A to 4C This is a cross-sectional view illustrating a portion of the process (formation of source / drain regions) of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0016] Figures 5A to 5C This is a cross-sectional view illustrating a portion of the process (forming a gate electrode) of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention; and

[0017] Figures 6 to 8 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Detailed Implementation

[0018] Semiconductor devices can be scaled down to reduce overall size and packaging. Optimizing transistor structure can result in improved performance. For example, an optimized structure can provide high speed and high precision. According to an example embodiment of this disclosure, the transistor may include a three-dimensional channel with active fins formed on a substrate. Active fins can be used to form the gate.

[0019] In an example embodiment, the channel structure of the multi-bridge channel field-effect transistor (MBCFET) is formed using a Si / SiGe multi-nanosheet structure. In the MBCFET, a SiGe layer (with a higher Ge content than that contained in the first semiconductor pattern) can be added below the bottommost channel layer as a semiconductor pattern for isolation (i.e., a sacrificial layer).

[0020] When forming the internal spacers, the semiconductor pattern used for isolation can be etched deeper than the first semiconductor pattern, and a self-aligned internal spacer with a thickness greater than the thickness of the internal spacer can be formed in the space where the semiconductor pattern used for isolation has been removed. Therefore, electrical isolation from the substrate can be enhanced. The structure and material of the isolation film used in the example embodiment can be varied.

[0021] In some example embodiments, the area surrounding the internal spacers and the isolation film can be formed of the same material. In some cases, the material for the semiconductor pattern used for isolation is completely removed. In other example embodiments, the internal spacers can be omitted or can be partially formed. Furthermore, the epitaxial process for forming the source / drain regions can be performed simultaneously with substrate exposure, thereby preventing performance degradation caused by strain loss.

[0022] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0023] Figure 1This is a top view showing a semiconductor device according to an example embodiment. Figure 2 It is along Figure 1 The cross-sectional view taken from lines I-I' and II-II' in the diagram.

[0024] Reference Figure 1 and Figure 2 In the example embodiment, the semiconductor device 100 may include a substrate 101 and a transistor TR disposed on the substrate 101. For example... Figure 1 As shown, the well W of substrate 101 can be implemented as an n-type well or a p-type well. When the well W is an n-type well, the transistor TR can be implemented as a P-MOSFET. When the well W is a p-type well, the transistor TR can be implemented as an N-MOSFET.

[0025] The transistor TR may include an active region 104 extending on the substrate 101 along a first direction (e.g., the X direction). The active region 104 may have protruding fin structures extending in the first direction. For example, the substrate 101 may be implemented as a semiconductor substrate such as a silicon substrate or a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0026] The device isolation layer 105 may define an active region 104 and may be formed of, for example, an oxide film, a nitride film, or a combination thereof. The device isolation layer 105 may be disposed on a substrate 101 and may cover the side surface of the active region 104 of the substrate 101. The upper surface of the device isolation layer 105 may be disposed at a horizontal height lower than the upper surface of the active region 104.

[0027] like Figure 2 As shown, the transistor TR may include a plurality of channel layers CH disposed on the active region 104 and spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction). Additionally, the transistor TR may include a gate electrode GE surrounding the plurality of channel layers CH and extending in a second direction (e.g., the Y direction) intersecting the first direction (e.g., the X direction). For example, the gate electrode GE may surround the plurality of channel layers CH on at least three sides in a plane extending along the second direction and perpendicular to the upper surface of the substrate 101.

[0028] The transistor TR may include a source / drain region SD disposed in an active region 104 disposed on at least one side of the gate electrode GE, the source / drain region SD being connected to a plurality of channel layers CH. In an example embodiment, the source / drain region SD may be disposed on the active region 104 on each of the two sides of the gate electrode GE. The source / drain region SD may be connected to both sides of each of the plurality of channel layers CH in a first direction (e.g., the X direction). In an example embodiment, three channel layers CH may be disposed, but the number of channel layers CH is not limited thereto. The channel layers CH may include a semiconductor pattern. For example, the semiconductor pattern may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0029] The source / drain region SD may include an epitaxial layer formed using multiple channel layers CH and active region 104 as seed crystals. The source / drain region SD may include at least one of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC). In some example embodiments, the source / drain region SD may be configured to provide tensile strain to the channel layers CH. As an example, when the semiconductor pattern 104 includes silicon (Si), the source / drain region SD may include silicon (Si) or silicon carbide (SiC). In other example embodiments, the source / drain region SD may be configured to provide compressive strain to the channel layers CH. As an example, when the channel layers CH include silicon (Si), the source / drain region SD may include silicon germanium (SiGe). The source / drain region SD may also include a dopant. Dopants may be used to improve the electrical properties of the transistor including the source / drain region SD. When the transistor TR is an N-MOSFET, for example, the dopant may be phosphorus (P). When the transistor TR is a P-MOSFET, the dopant may be boron (B).

[0030] The gate structure used in the example embodiment may include a gate electrode GE, a gate insulating layer GI, a gate spacer GS, and a gate cover pattern GP. The gate insulating layer GI is disposed between the gate electrode GE and the channel layer CH. The gate spacer GS is disposed on the side surface of the gate electrode GE. The gate cover pattern GP is disposed on the upper surface of the gate electrode GE.

[0031] The gate insulating layer GI can extend into the space between the gate electrode GE and the gate spacer GS, and the uppermost surface of the gate insulating layer GI can be substantially coplanar with the upper surface of the gate electrode GE. The gate electrode GE can cover the uppermost surface of the channel layer CH, and can also cover the two side surfaces of the channel layer CH in the second direction (see [reference]). Figure 2 (See the right side of the diagram). The gate electrode GE can extend in the second direction and can cover the upper surface of the device isolation layer 105.

[0032] The gate electrode GE can be disposed in the space between the channel layers CH (see Figure 2 (See the left side of the figure). The gate insulating layer GI may be located between each channel layer CH and the gate electrode GE, and may surround the outer surface of each channel layer CH. Each channel layer CH and the gate electrode GE may be isolated from each other by the gate insulating layer GI located therebetween. The gate insulating layer GI may extend along the bottom surface of the gate electrode GE, and may be located between the gate electrode GE and the active region 104 and between the gate electrode GE and the device isolation layer 105.

[0033] As described above, the gate electrode GE, the channel layer CH, and the source / drain region SD can be included in a gate-all-around type field effect transistor.

[0034] The gate electrode GE may include a doped semiconductor, a conductive metal nitride, or a metal. For example, the gate electrode GE may include metal nitrides such as TiN, WN, and TaN, or metals such as Ti, W, and Ta. The gate insulating layer GI may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high-dielectric film. The high-dielectric film may include a material with a dielectric constant higher than that of the silicon oxide film. Examples of materials with a dielectric constant higher than that of silicon oxide may be a hafnium oxide film (HfO), an aluminum oxide film (AlO), or a tantalum oxide film (TaO). Each of the gate spacer GS and the gate cover pattern GP may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0035] like Figure 2 As shown, in the example embodiment, internal spacers IS can be disposed on both sides of the gate electrode GE in the first direction between multiple channel layers CH. Therefore, internal spacers IS can be disposed between each source / drain region SD and the gate electrode GE.

[0036] Internal spacers IS can be disposed on one side of the gate electrode GE and can be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction). The internal spacers IS and the channel layers CH can be stacked alternately and repeatedly in a direction perpendicular to the upper surface of the substrate 101. The internal spacers IS can be disposed in the space between adjacent channel layers CH. The source / drain regions SD can contact the channel layers CH respectively and can be spaced apart from the gate electrode GE by the internal spacers IS located between the source / drain regions SD and the gate electrode GE. Since the gate insulating layer GI is located between the gate electrode GE and each channel layer CH, the gate insulating layer GI can be configured to extend into the space between the gate electrode GE and each internal spacer IS. Each internal spacer IS can contact the gate insulating layer GI between the channel layers CH.

[0037] Each internal spacer IS can have a width in the first direction. For example, the width of each internal spacer IS can be... Within the range of 10 nm. In some example embodiments, the surface of each internal spacer IS directly adjacent to the gate electrode GE can be configured to have a substantially flat surface or a substantially circular surface.

[0038] In some example embodiments, the internal spacer IS may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN. For example, the internal spacer IS may include silicon nitride. In example embodiments, the internal spacer IS may include a semiconductor without dopant or a semiconductor with dopant of a conductivity type different from that of the source / drain regions.

[0039] In the example embodiment, the transistor TR may include an isolation film 155 disposed between the lowest channel layer CH_b and the active region 104 among a plurality of channel layers CH. The isolation film 155 can serve as a structure to prevent current leakage through sub-regions between adjacent transistors. In the example embodiment, the isolation film 155 may be disposed at a horizontal height higher than the bottom surface of the source / drain region SD, such as... Figure 2 As shown. For example, the isolation film 155 may be located above the active region 104 at a horizontal height above the bottom surface of the source / drain region in a direction perpendicular to the upper surface of the substrate 101 (i.e., the Z direction).

[0040] The isolation membrane 155 may include insulating regions 154, wherein the insulating regions 154 may be respectively disposed on both sides of the isolation membrane 155 in a first direction. Semiconductor regions 153 may be disposed between the insulating regions 154.

[0041] The width W2 of each insulating region 154 in the first direction can be configured to be greater than the width W1 of each inner spacer IS in the first direction. The insulating region 154 may comprise a material similar to that of the inner spacer IS. The insulating region 154 may be formed together with the inner spacer IS in the process of forming the inner spacer IS.

[0042] The semiconductor region 153 of the isolation film 155 may include a semiconductor material different from the semiconductor material of the multiple channel layers CH. For example, when the semiconductor material of the multiple channel layers CH is Si, the semiconductor region 153 of the isolation film 155 may include SiGe. The semiconductor region 153 may include a relatively high content of Ge. For example, the semiconductor region 153 may include a Ge content of about 35% or higher, and may include a SiGe content of about 50% or higher.

[0043] An interlayer insulating film 123 may be disposed on the substrate 101 and may cover the gate structure and the source / drain region SD. The interlayer insulating film 123 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a low-dielectric film. The upper surface of the gate cover pattern GP may be substantially coplanar with the upper surface of the interlayer insulating film 123. A gate spacer GS may be located between the gate cover pattern GP and the interlayer insulating film 123.

[0044] Contact plugs (CTs) can be provided that penetrate the interlayer insulating film 123 and are respectively connected to the source / drain regions SD. The contact plugs (CTs) can contact the source / drain regions SD. The contact plugs (CTs) can include conductive metal nitrides or metals. For example, the contact plugs (CTs) can include metal nitrides such as TiN, WN, and TaN, or metals such as Ti, W, and Ta.

[0045] Figures 3A to 3F This is a perspective view illustrating a portion of the process of a method for manufacturing a semiconductor device according to an example embodiment.

[0046] Reference Figure 3A A semiconductor layer 113 for isolation can be formed on the substrate 101, and a stacked structure ST in which a first semiconductor layer 111 and a second semiconductor layer 112 are alternately stacked can be formed.

[0047] The semiconductor layer 113 for isolation can be disposed at the bottom of the stacked structure ST. A second semiconductor layer 112 can be disposed on the semiconductor layer 113 for isolation. The top layer of the stacked structure ST can be configured as the second semiconductor layer 112, but exemplary embodiments are not limited thereto. The first semiconductor layer 111 and the second semiconductor layer 112 can be formed using epitaxial growth methods, but the methods for forming the first semiconductor layer 111 and the second semiconductor layer 112 are not limited thereto. The semiconductor layer 113 for isolation, the first semiconductor layer 111, and the second semiconductor layer 112 can comprise materials with different etch selectivity. In subsequent processes, when the first semiconductor layer 111 is etched, the second semiconductor layer 112 may not be etched and may remain unchanged. The first semiconductor layer 111 can be used as a sacrificial layer for forming a gate electrode, and the second semiconductor layer 112 can be retained and can be used as a channel layer.

[0048] In the example embodiment, the semiconductor layer 113 used for isolation may be formed of a material having an etch rate higher than that of the first semiconductor layer 111. The etch rate of the semiconductor layer 113 used for isolation may be used instead of the etch rate of the first semiconductor layer 111, provided that the first semiconductor layer 111 can be selectively etched. The selectivity of the semiconductor layer 113 used for isolation and the selectivity of the first semiconductor layer 111 may be based on differences in Ge content. For example, the first semiconductor layer 111 may comprise SiGe containing a first Ge content, and the semiconductor layer 113 used for isolation may comprise SiGe containing a second Ge content higher than the first Ge content. The second Ge content may be higher than the first Ge content (e.g., 10%, 35%, 50%, or more). The second semiconductor layer 112 may comprise one of Si and III-V compound semiconductors.

[0049] A first mask pattern M1 extending in a first direction (e.g., the X direction) can be formed on the stacked structure ST. The first mask pattern M1 can be formed from at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0050] Reference Figure 3B The stacked structure ST can be etched using the first mask pattern M1 to form the fin structure AF.

[0051] The fin structure AF may include a semiconductor pattern 153' for isolation and a second semiconductor pattern 152 and a first semiconductor pattern 151 alternately stacked on the semiconductor pattern 153' for isolation. An active region 104 having a protruding portion that protrudes along with the fin structure AF can be formed by etching a portion of the upper surface of the substrate 101, and a device isolation layer 105 can be formed around the protruding portion. The upper surface of the device isolation layer 105 may be disposed at a lower horizontal height than the upper surface of the protruding portion of the active region 104. The fin structure AF may be formed along a first direction.

[0052] Reference Figure 3C An etch stop layer and a dummy gate layer can be formed to cover the fin structure AF, and an etch process can be performed using a second mask pattern M2 formed in a second direction (e.g., the Y direction) to form an etch stop pattern 131 and a dummy gate pattern DG.

[0053] The dummy gate pattern DG may intersect with a portion of the fin structure AF and may extend in a second direction (e.g., the Y direction). For example, the etch stop pattern 131 may be formed of silicon oxide, silicon nitride, or a combination thereof. For example, the dummy gate pattern DG may be formed of either polycrystalline silicon or amorphous silicon.

[0054] Reference Figure 3D Gate spacers GS can be formed on the sidewalls of the dummy gate pattern DG.

[0055] For example, in this process, a spacer film covering the dummy gate pattern DG and the fin structure AF can be conformally formed, and the spacer film can be etched back to form a gate spacer GS retained on the sidewalls of the dummy gate pattern DG. The gate spacer GS may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof. In an example embodiment, each gate spacer GS may be constructed as a single film, but the example embodiments are not limited thereto. The gate spacer GS may have a multilayer film structure.

[0056] Reference Figure 3E The fin structure AF exposed on both sides of the dummy gate pattern DG and the gate spacer GS can be removed, thereby forming a groove R in the fin structure AF.

[0057] In the subsequent process for forming the source / drain regions, the sidewalls of the active region 104 providing the bottom surface of the groove R and the sidewalls of the fin structure AF providing the side surface of the groove R can be used as epitaxial seed crystals. In this process or in subsequent processes, processes for forming internal spacers and isolation films can be performed. Figures 4A to 4C This is a cross-sectional view illustrating a portion of the process (forming source / drain regions) of a method for manufacturing a semiconductor device according to an example embodiment.

[0058] Figure 4A It is along Figure 3E The cross-sectional view taken from lines I-I' and II-II' in the diagram.

[0059] Reference Figure 4A As described above, a groove R can be formed in the portion of the fin structure AF located below both sides of the dummy gate pattern DG.

[0060] The process of removing the aforementioned portion of the fin structure AF may include a process of partially etching the fin structure AF using a mask pattern M2 and gate spacers GS as an etching mask.

[0061] An etching process can be performed until the upper surface of the active region 104 is exposed on both sides of the dummy gate pattern DG. Using this process, the fin structure AF may include a first side surface S1 that is opposite to each other in a first direction (e.g., the X direction) and a second side surface S2 that is opposite to each other in a second direction (e.g., the Y direction).

[0062] The second side surface S2 of the fin structure AF can be covered by a dummy gate pattern DG. For example, the dummy gate pattern DG can cover the upper surface and the second side surface S2 of the fin structure AF, and can also cover the upper surface of the device isolation layer 105. An etch stop pattern 131 can be located between the dummy gate pattern DG and the fin structure AF, and the etch stop pattern 131 can extend into the space between the dummy gate pattern DG and the device isolation layer 105. The first side surface S1 of the fin structure AF may not be covered by the dummy gate pattern DG and may be exposed by the groove R.

[0063] The fin structure AF may include a semiconductor pattern 153' for isolation disposed on the active region 104, and a first semiconductor pattern 151 and a second semiconductor pattern 152 alternately stacked on the semiconductor pattern 153' for isolation. The second semiconductor pattern 152 may be directly disposed on the semiconductor pattern 153' for isolation. For example, the second semiconductor pattern 152 may include Si, and the semiconductor pattern 153' for isolation and the first semiconductor pattern 151 may include SiGe. The Ge content included in the semiconductor pattern 153' for isolation may be higher than the Ge content included in the first semiconductor pattern 151. In some embodiments, the Ge content included in the semiconductor pattern 153' for isolation may be higher than the Ge content included in the first semiconductor pattern 151 (e.g., by 10% or 20%).

[0064] Reference Figure 4B The first semiconductor pattern 151 exposed to the groove R can be selectively etched.

[0065] In this process, the second semiconductor pattern 152 may not need to be etched. The exposed portion of the first semiconductor pattern 151 may be etched, thereby forming a first recessed region r1 on both sides of each first semiconductor pattern 151 in a first direction (e.g., the X direction). In a selective etching process, the two side surfaces of the isolation semiconductor pattern 153' exposed together with the first semiconductor pattern 151 may also be etched. Therefore, for example, a second recessed region r2 may be formed on both sides of each isolation semiconductor pattern 153' in the first direction.

[0066] As described above, by using the difference in Ge content, the etching rate of the semiconductor pattern 153' used for isolation can be higher than the etching rate of the first semiconductor pattern 151. Therefore, as Figure 4BAs shown, the width of the second recessed region r2 can be greater than the width of the first recessed region r1. The semiconductor region 153, partially retained from the semiconductor pattern 153' used for isolation, can be disposed in the central region in the first direction between the lowermost second semiconductor pattern 152 and the active region 104. The semiconductor region 153 can form part of the isolation film. In the example embodiment, the semiconductor pattern 153' used for isolation can be configured to be partially retained, but the example embodiment is not limited thereto. The semiconductor pattern 153' used for isolation can be removed by increasing the difference in etch rate (e.g., difference in Ge content). When the semiconductor pattern 153' used for isolation is removed, the isolation film can be formed of an insulator (see [link to documentation]). Figure 7 ).

[0067] Reference Figure 4C Internal spacers IS and insulator regions 154 can be formed in the first recessed region r1 of the first semiconductor pattern 151 and the second recessed region r2 of the semiconductor pattern 153' for isolation. Then, source / drain regions SD can be formed in the groove R. Figure 4C It is along Figure 3F The cross-sectional view taken from lines I-I' and II-II' in the diagram.

[0068] By performing an oxidation process, the first side surface S1 of the fin structure AF can be oxidized. As a result, internal spacers IS can be formed on both sides of each first semiconductor pattern 151 in the first direction, and insulating regions 154 can be formed on both sides of the semiconductor pattern 153' used for isolation in the first direction. The internal spacers IS can be disposed between the source / drain regions and the gate electrode formed in subsequent processes.

[0069] For example, the internal spacer IS can be formed of an insulating layer or a semiconductor layer without dopant. In some example embodiments, the internal spacer IS may include at least one insulating material selected from SiN, SiCN, SiOCN, SiBCN, and SiBN. For example, the internal spacer IS may include silicon nitride. In example embodiments, the internal spacer IS may include an undoped semiconductor or a semiconductor with a doped type of conductivity different from that of the impurities in the source / drain regions.

[0070] Since the insulating region 154 is formed together with the internal spacer IS in the same oxidation process, the insulating region 154 may include the same material as the internal spacer IS. The width of the insulating region 154 in the first direction (e.g., the X direction) may be greater than the width of the internal spacer IS in the first direction (e.g., the X direction).

[0071] Therefore, an isolation film 155, including a semiconductor region 153 and insulating regions 154 located on both sides of the semiconductor region 153, can be provided between the fin structure AF and the active region 104. Since the isolation film 155 provided in the example embodiment can have electrical insulating properties, the isolation film 155 can effectively prevent current leakage through the substrate (or active region 104) between adjacent devices.

[0072] Epitaxial growth processes can be performed on the fin structure AF to fill the groove R, thereby forming the source / drain region SD.

[0073] The source / drain region SD can be directly connected to the second semiconductor pattern 152, which serves as the channel layer, and can be insulated from the first semiconductor pattern 151 by internal spacers IS. Epitaxial regions grown on both sides of the dummy gate pattern DG can be configured as source / drain regions SD. The epitaxial growth process can be performed using the sidewalls of the active region 104 providing the bottom surface of the recess R and the sidewalls of the fin structure AF providing the side surface of the recess R as seed crystals. For example, the source / drain region SD can comprise silicon germanium (SiGe) doped with p-type dopant and can provide a p-MOSFET. The source / drain region SD can have various shapes that define a crystallographically stable surface during the growth process. For example, the source / drain region SD or the epitaxial region can have a pentagonal cross-section in a second direction (e.g., the Y direction).

[0074] In another example embodiment, the source / drain region SD can be formed by different epitaxial growth processes and can include silicon carbide (SiC) or silicon (Si) doped with an n-type dopant. The source / drain region SD can have a hexagonal or polygonal cross-section formed at a gentle angle in a second direction (e.g., the Y direction).

[0075] As described above, before forming the epitaxial layer for the source / drain region SD, the first recessed region r1 and the second recessed region r2 can be formed by further etching the side surfaces of the first semiconductor pattern 151 and the side surfaces of the semiconductor pattern 153' for isolation. A process for selectively forming internal spacers IS and insulating regions 154 in the first recessed region r1 and the second recessed region r2 can then be performed. In this process, an isolation film 155 providing electrical isolation between the fin structure AF and the active region 104 can be formed. In the example embodiment, the isolation film 155 may include insulating regions 154 respectively disposed on both sides of the isolation film 155 in a first direction and semiconductor regions 153 disposed between the insulating regions 154.

[0076] A process can be performed to replace the dummy gate pattern with the gate electrode, thereby manufacturing a semiconductor device. Figures 5A to 5CThis is a cross-sectional view illustrating a portion of the process for manufacturing a semiconductor device according to an example embodiment, showing the process for forming a gate electrode.

[0077] Reference Figure 5A It can form an interlayer insulating film 123 and perform a planarization process to expose the dummy gate pattern DG.

[0078] The interlayer insulating film 123 can be formed to cover the source / drain region SD, the dummy gate pattern DG, and the gate spacer GS on the substrate 101. Alternatively, the interlayer insulating film 123 can be planarized until the dummy gate pattern DG is exposed.

[0079] In this planarization process, the second mask pattern M2 can be removed. The interlayer insulating film 123 may include at least one of a low-k material, an oxide film, a nitride film, and an oxide nitride film. The low-k material may include flowable oxide (FOX), Tonen silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or combinations thereof.

[0080] Reference Figure 5B The dummy gate pattern DG can be removed by the exposed area of ​​the dummy gate pattern DG, and the first semiconductor pattern can be selectively removed.

[0081] In this process, the dummy gate pattern DG can be removed, and an opening region H can be formed between the gate spacers GS. The exposed etch stop pattern 131 can be selectively removed through the opening region H. After removing the etch stop pattern, the second side surfaces S2 of the first semiconductor pattern 151 and the second semiconductor pattern 152 of the fin structure AF can be exposed through the opening region H. Using this process, the first semiconductor pattern 151 can be selectively removed, and an additional opening region h connected to the opening region H can be formed. The additional opening region h can be provided between the second semiconductor pattern 152 or the channel layer CH. Therefore, the opening region H and the additional opening region h connected to the opening region H can be configured as space for the gate structure.

[0082] Reference Figure 5C The gate insulating layer GI and the gate electrode GE can be formed in the opening region H and the additional opening region h formed by the above process.

[0083] In this process, a gate insulating layer GI can be conformally formed on the exposed surfaces of the opening region H and the additional opening region h. The gate insulating layer GI can be formed around each second semiconductor pattern 152. The gate insulating layer GI can also be conformally formed on the sidewalls of the gate spacer GS exposed to the opening region H and on the surfaces of the source / drain regions SD exposed to the additional opening region h.

[0084] The gate electrode GE can be formed on the gate insulating layer GI and can extend in the second direction (Y direction). For example, the gate electrode GE can be formed in the space between the gate insulating layers GI and in the space between the second semiconductor patterns 152.

[0085] The gate insulating layer GI may comprise a high-k material with a dielectric constant higher than that of the silicon oxide film. For example, the gate insulating layer GI may comprise one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but examples of materials are not limited thereto.

[0086] The gate electrode GE may include a conductive material. For example, the gate electrode GE may include at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, and Al. In this figure, the gate electrode GE is constructed as a single layer, but its exemplary embodiments are not limited thereto. For example, the gate electrode GE may include a work function conductive layer that performs work function adjustment and a fill conductive layer that fills the space formed by the work function conductive layer that performs work function adjustment.

[0087] In the example embodiment, the semiconductor pattern 153' used for isolation may be partially removed, but the example embodiment is not limited thereto. The semiconductor pattern 153' used for isolation may also be completely removed, and a semiconductor material may be selected as a replacement material for the insulating material. Therefore, the structure of the isolation film can be changed, and... Figures 6 to 8 An example embodiment of it is shown in the figure.

[0088] Figures 6 to 8 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0089] Reference Figure 6 Semiconductor device 100A can be similar to Figure 1 and Figure 2The semiconductor device 100 shown is different from semiconductor device 100A in that internal spacers may not be formed on both sides of the channel layer CH in semiconductor device 100A. Unless otherwise stated, the elements of semiconductor device 100A described below can be compared with those of semiconductor device 100A. Figure 1 and Figure 2 The semiconductor device 100 shown has the same or similar components.

[0090] Similar to the aforementioned example embodiments, the fin structure AF may include a gate electrode GE surrounding the channel layer CH, and the two sides of the fin structure AF may be connected to the source / drain region SD. In the example embodiments, the gate electrode GE may not be located on either side of the gate electrode GE in the first direction (X direction) or may not be located between the gate electrode GE and the source / drain region SD, thus forming an internal spacer. Figure 2 (Internal spacers IS). The gate electrode GE can be isolated from the source / drain region SD through the gate insulating layer GI.

[0091] In the example embodiment, the isolation film 155A may include edge regions 154A disposed on both sides of the isolation film 155A in a first direction (e.g., the X direction) and a central region 153A disposed between the edge regions 154A. In some example embodiments, the edge regions 154A may include an insulating material similar to the insulating material described in the foregoing example embodiments. However, in the above example embodiments, since no internal spacers are formed, the edge regions 154A may be formed of different materials without considering the process for forming the internal spacers. For example, the edge regions 154A may include a semiconductor material doped with a dopant having a conductivity type different from that of the dopant in the source / drain regions SD, or an undoped semiconductor material. Similar to the semiconductor region 153 described in the foregoing example embodiments, the central region 153A may include SiGe containing a relatively high Ge content.

[0092] Reference Figure 7 Semiconductor device 100B can be similar to Figure 1 and Figure 2 The semiconductor device 100 shown is different from semiconductor device 100B in that the isolation film 155 can be configured to have a single structure within semiconductor device 100B. Unless otherwise stated, the elements of semiconductor device 100B described below can be used with... Figure 1 and Figure 2 The semiconductor device 100 shown has the same or similar components.

[0093] Similar to the aforementioned example embodiments, the fin structure AF may include a gate electrode GE surrounding the channel layer CH. The two sides of the fin structure AF may be connected to the source / drain region SD. Internal spacers IS may be disposed on both sides of the gate electrode GE between the channel layers CH.

[0094] In an example embodiment of the separator 155B, the edge region and surrounding region of the separator 155B may comprise the same material as the inner spacer IS. In some example embodiments, when the inner spacer IS comprises an insulator, the separator 155B may be formed of the same material. As described in the foregoing manufacturing process (see...). Figures 4A to 4C The insulating region of the separator can be expanded based on the selection of the materials (difference in the SiGe to Ge content ratio) of the first semiconductor pattern 151 and the second semiconductor pattern 152, as well as the selective etching process performed on the first semiconductor pattern 151. In the example embodiment, the surrounding region of the separator can be replaced with an insulator (e.g., the proportion of the insulating region in the entire separator region can be changed to a proportion between 10% and 100%).

[0095] In other example embodiments, when the internal spacer IS comprises a semiconductor with a dopant of a second conductivity type or an undoped semiconductor, the isolation film 155B may also be formed of the same semiconductor.

[0096] In the example embodiment, in the process of forming the internal spacers IS (see...) Figure 4B In the process of [the process], the semiconductor pattern used for isolation can be sufficiently selective relative to the first semiconductor pattern to remove a portion of the semiconductor pattern used for isolation. For example, when the semiconductor pattern used for isolation is formed of SiGe, the Ge content (e.g., 75% or higher) can be configured to be higher than the Ge content included in the first semiconductor pattern (e.g., 40% or lower).

[0097] Reference Figure 8 Semiconductor device 100C can be similar to Figure 1 and Figure 2 The semiconductor device 100 shown is different from semiconductor device 100C. In semiconductor device 100C, internal spacers IS can be formed on a portion of the channel layer CH, and the internal spacers can have different widths in the first direction (X direction). Unless otherwise stated, the elements of semiconductor device 100C described below can be compared with those in… Figure 1 and Figure 2 The semiconductor device 100 shown in the figure has the same or similar components.

[0098] Similar to the aforementioned example embodiments, the fin structure AF may include a gate electrode GE surrounding the channel layer CH, and both sides of the fin structure AF may be connected to the source / drain region SD. In the example embodiment, an internal spacer IS may be formed between a portion of the gate electrode GE and the source / drain region SD. Figure 8 As shown, the internal spacers IS may not be formed on both sides of the uppermost gate electrode GE, but may be formed on both sides of the other two gate electrodes GE. Furthermore, the internal spacers IS disposed in the two gate electrodes GE may have different widths.

[0099] In the example embodiment, the separator 155C may include an edge region 154C and a central region 153C disposed between the edge regions 154C. The edge regions 154C are respectively disposed on both sides of the separator 155C in a first direction and are formed of the same material as the internal spacer IS. In some example embodiments, the edge regions 154C may include the same insulating material or the same semiconductor material as the internal spacer IS. Similar to the semiconductor region 153 described in the foregoing example embodiment, the central region 153C may include SiGe with a relatively high Ge content.

[0100] According to the above example embodiments, a semiconductor device and a method of manufacturing the semiconductor device can be provided, which has improved electrical properties by preventing current leakage through the substrate between adjacent devices (e.g., transistors).

[0101] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; An active region that protrudes from the substrate and extends in a first direction; Multiple channel layers are disposed on the active region and spaced apart from each other in a direction perpendicular to the upper surface of the substrate; An isolation membrane is disposed between the lowest channel layer of the plurality of channel layers and the active region, and includes a semiconductor region; A gate electrode that surrounds the plurality of channel layers and extends in a second direction intersecting the first direction; and Source / drain regions are disposed on at least one side of the gate electrode and connected to each of the plurality of channel layers. The isolation membrane is positioned at a height higher than the bottom surface of the source / drain region. Wherein, the semiconductor region of the isolation film comprises SiGe with a Ge content of 35% or higher, and Each of the plurality of channel layers contains a semiconductor material that is different from the semiconductor material of the semiconductor region of the isolation film.

2. The semiconductor device according to claim 1, wherein, The isolation membrane further includes an insulating region disposed on both sides of the semiconductor region in the first direction.

3. The semiconductor device according to claim 2, further comprising internal spacers disposed between the plurality of channel layers on both sides of the gate electrode in the first direction.

4. The semiconductor device according to claim 3, wherein, The width of each of the insulating regions in the first direction is greater than the width of each of the internal spacers in the first direction.

5. The semiconductor device according to claim 3, wherein, The insulating region and the internal spacer contain the same material.

6. The semiconductor device according to claim 3, wherein, Two or more of the internal spacers have different widths in the first direction.

7. A semiconductor device, the semiconductor device comprising: Substrate; An active region that protrudes from the substrate and extends in a first direction; Multiple channel layers are disposed on the active region and spaced apart from each other in a direction perpendicular to the upper surface of the substrate; An isolation membrane is disposed between the lowest channel layer of the plurality of channel layers and the active region; A gate electrode that surrounds the plurality of channel layers and extends in a second direction intersecting the first direction; Internal spacers are disposed between the plurality of channel layers and on both sides of the gate electrode in the first direction; and Multiple source / drain regions are disposed on both sides of the gate electrode in the first direction and connected to the multiple channel layers. Wherein, the internal spacers and the separating membrane contain the same material at their edge regions on both sides in the first direction. The isolation membrane is positioned at a horizontal height higher than the bottom surface of the source / drain region. The isolation film includes an inner region disposed between the edge regions of the isolation film in the first direction, and contains a semiconductor material. Each of the plurality of channel layers contains a semiconductor material that is different from the semiconductor material of the internal region of the isolation membrane.

8. The semiconductor device according to claim 7, wherein, The internal spacer contains an insulator.

9. The semiconductor device according to claim 7, in, The source / drain region comprises a semiconductor doped with a first conductivity type, and The internal spacers include semiconductors with dopants of a second conductivity type or undoped semiconductors.

10. The semiconductor device according to claim 7, wherein, The internal region of the isolation membrane contains SiGe.

11. The semiconductor device according to claim 7, wherein, The internal spacers contain a semiconductor material that is different from the semiconductor material of the internal region.

12. The semiconductor device according to claim 7, wherein, The width of each edge region of the isolation membrane in the first direction is greater than the width of each internal spacer in the first direction.

13. A semiconductor device, the semiconductor device comprising: Substrate; An active region that protrudes from the substrate and extends in a first direction; Multiple channel layers are disposed on the active region and spaced apart from each other in a direction perpendicular to the upper surface of the substrate; A gate electrode that surrounds the plurality of channel layers and extends in a second direction intersecting the first direction; Internal spacers are disposed between the plurality of channel layers and on both sides of the gate electrode in the first direction; An isolation membrane is disposed between the lowest channel layer of the plurality of channel layers and the active region, wherein the edge regions of the isolation membrane on both sides in the first direction and the internal spacers have the same insulating material, and the isolation membrane includes a semiconductor region; and Source / drain regions are disposed on each of the two sides of the gate electrode in the first direction, the bottom surface of the source / drain regions is disposed at a horizontal height lower than the isolation film, and the source / drain regions are connected to each of the plurality of channel layers. Each of the plurality of channel layers contains a semiconductor material that is different from the semiconductor material of the semiconductor region of the isolation film.

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