A substrate for PERC cells, a PERC cell, and a method for fabricating the same.

Abstract

The present invention provides a substrate for a PERC cell, a PERC cell and a preparation method thereof. The substrate comprises a silicon wafer layer having a PN junction, and a back passivation layer and a protective layer sequentially arranged from the back of the silicon wafer layer having a PN junction to the outside; a plurality of grooves are provided on the back passivation layer and the protective layer, and the grooves penetrate the back passivation layer and the protective layer; the grooves include a first groove area and a second groove area along the depth direction, the second groove area is located at the bottom of the first groove area and is connected to the first groove area, and the opening area of ​​the first groove area is larger than the opening area of ​​the second groove area. The PERC cell comprises: the above-mentioned substrate, a back field layer arranged on the back of the substrate, and a front passivation layer and a front electrode sequentially arranged from the front of the substrate to the outside. The present invention can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering by using the grooves of the above structure on the PERC cell.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a substrate for a PERC cell, a PERC cell and a preparation method thereof. Background Art

[0002] Among the existing sustainable energy sources, solar energy is undoubtedly the cleanest, most common and most promising energy source. Solar power generation devices, also known as solar cells or photovoltaic cells, can directly convert solar energy into electrical energy. Its power generation principle is based on the photovoltaic effect of semiconductor PN junction.

[0003] High efficiency and low cost are the main goals pursued by crystalline silicon solar cells at present. Partially contacted back passivated (PERC) solar cells are the main technology to improve the performance of crystalline silicon solar cells. The core is to cover the backlight side of the silicon wafer with aluminum oxide or silicon oxide film (5 to 100 nanometers) to passivate the surface and improve the long-wave response, thereby improving the conversion efficiency of the battery.

[0004] However, during the high-temperature sintering of aluminum paste to form an aluminum back field, the passivation effect of aluminum oxide or silicon oxide will be destroyed. Therefore, a silicon nitride protective layer is usually covered on the aluminum oxide or silicon oxide back passivation layer to play a protective role. However, aluminum oxide, silicon oxide and silicon nitride are not conductive, so it is necessary to partially groove the back passivation layer and the protective layer to facilitate the aluminum back field to contact the silicon substrate and collect current. The structure of a common PERC cell is from the back to the front: a silver back electrode, an aluminum back field, a protective film, a back passivation film, a silicon wafer with a PN junction, a front passivation film and a front silver electrode. Through grooves are provided on the protective film and the back passivation film.

[0005] The existing method of grooving the back passivation layer and protective layer of PERC cells is to irradiate the laser once, and the groove formed is hemispherical. When printing aluminum paste, the edge area of ​​such a structure cannot be well filled with aluminum paste, and voids are easily generated after sintering (such as Figure 8 As shown in the figure, the contact resistance between the aluminum back field and the silicon substrate is large, and the battery efficiency is low, which needs to be solved. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention aims to provide a substrate for PERC cells, a PERC cell and a preparation method thereof. The groove structure used in the PERC cell has a relatively flat upper portion and a narrow lower portion. Compared with a one-step formed groove of the same depth, it can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering, increase the interlayer contact area, and reduce the contact resistance.

[0007] To achieve this object, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a substrate for a PERC cell, comprising a silicon wafer layer having a PN junction, and a back passivation layer and a protective layer sequentially arranged from the back side of the silicon wafer layer having a PN junction to the outside; a plurality of grooves are formed on the back passivation layer and the protective layer, and the grooves penetrate the back passivation layer and the protective layer;

[0009] The groove includes a first groove area and a second groove area along a depth direction, the second groove area is located at the bottom of the first groove area and is connected to the first groove area, and the opening area of ​​the first groove area is larger than the opening area of ​​the second groove area.

[0010] It should be noted that the "back" in the present invention refers to the side facing away from light in the application, and the "front" refers to the side receiving light in the application. The first groove area and the second groove area are not two physically separated areas, but are two areas artificially divided for the convenience of explaining the structure of the groove.

[0011] As a preferred technical solution of the present invention, the cross-sectional area of ​​the groove perpendicular to the depth direction decreases as the depth increases.

[0012] Preferably, the plurality of grooves are arranged periodically.

[0013] Preferably, the total depth of the groove is 4-12 μm; for example, it may be 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm or 12 μm.

[0014] Preferably, the depth of the first groove zone is 1.8-5.4μm, for example, it can be 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm, 3μm, 3.2μm, 3.5μm, 3.8μm, 4μm, 4.2μm, 4.5μm, 4.8μm, 5μm, 5.2μm or 5.4μm, etc.; the depth of the second groove zone is 2.2-6.6μm, for example, it can be 2.2μm, 2.5μm, 2.8μm, 3μm, 3.2μm, 3.5μm, 3.8μm, 4μm, 4.2μm, 4.5μm, 4.8μm, 5μm, 5.2μm, 5.5μm, 5.8μm, 6μm, 6.2μm, 6.5μm or 6.6μm, etc.

[0015] Preferably, the ratio of the depth of the first groove area to the depth of the second groove area is 1:1.5-1.5:1, for example, 1:1.5, 1:1.4, 1:1.3, 1:1.2, 1:1.1, 1:1, 1.1:1, 1.2:1, 1.3:1, 1.4:1 or 1.5:1, etc. More preferably, 1:1.

[0016] As a preferred technical solution of the present invention, the opening shape of the first groove area and the opening shape of the second groove area are circular.

[0017] Preferably, the opening diameter of the first groove area is 14-34μm; for example, it can be 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 22μm, 23μm, 25μm, 26μm, 28μm, 30μm, 32μm, 33μm or 34μm, etc.

[0018] Preferably, the ratio of the opening diameter of the second groove area to the opening diameter of the first groove area is 1-3:4, for example, it can be 1:4, 1.2:4, 1.3:4, 1.5:4, 1.6:4, 1.8:4, 2:4, 2.2:4, 2.3:4, 2.5:4, 2.6:4, 2.8:4 or 3:4, etc.

[0019] In the present invention, if the depth or opening size of the groove is too large, the contact area between the back field layer material of the PERC cell and the silicon substrate will be too large, defects will increase, the passivation effect will deteriorate, and the efficiency of the PERC cell will be affected; if the depth or opening size of the groove is too small, the contact area between the back field layer material and the silicon substrate will be reduced, affecting current transmission.

[0020] In the present invention, if the depth and opening size of the second groove area are too large or too small compared to the first groove area, the shape of the groove will be close to the shape of the laser groove, and the effect of reducing the voids between the back field layer material and the silicon substrate will not be obvious or even have no effect.

[0021] As a preferred technical solution of the present invention, the thickness of the back passivation layer is 10-15 nm; for example, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm.

[0022] Preferably, the thickness of the protective layer is 80-120 nm; for example, it may be 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm or 120 nm.

[0023] In a second aspect, the present invention provides a method for preparing the above substrate, comprising the following steps:

[0024] (a) performing a first laser groove on the back side of a silicon wafer having a PN junction and coated with a back passivation layer and a protective layer to form an upper groove;

[0025] (b) performing a second laser grooving at the bottom of the upper groove to form a lower groove, wherein the laser spot size of the second laser grooving is smaller than the laser spot size of the first laser grooving, and the areas of the upper groove and the lower groove together constitute a groove on the back side of the substrate.

[0026] The preparation method is to prepare the substrate by using two laser grooving processes instead of the existing one laser grooving process, wherein the depth of the first laser grooving is shallow, and the second laser grooving is performed on the basis of the first laser grooving and has a narrower width. Compared with the one laser grooving process, the groove structure formed by the two laser groovings is relatively flat on the upper part and narrow on the lower part. The substrate thus formed can make the subsequently printed back field layer material better contact with the silicon substrate, avoid the generation of voids after sintering, thereby increasing the contact area and reducing the contact resistance.

[0027] As a preferred technical solution of the present invention, the diameter of the laser spot of the first laser grooving is 14-34μm; for example, it can be 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 22μm, 23μm, 25μm, 26μm, 28μm, 30μm, 32μm, 33μm or 34μm, etc.

[0028] Preferably, the ratio of the diameter of the laser spot of the second laser grooving to the diameter of the laser spot of the first laser grooving is 1-3:4.

[0029] Preferably, the depth of the first laser grooving is 2-6μm, for example, it can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm or 6μm, etc.; the depth of the second laser grooving is 2-6μm, for example, it can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm or 6μm, etc.

[0030] It should be noted that the depth of the second laser grooving in the present invention is equal to the distance from the bottom of the upper groove to the bottom of the lower groove. Since the upper groove profile formed by the first laser grooving is an arc surface, its cross-sectional dimension perpendicular to the depth direction decreases with increasing depth. Therefore, during the second laser grooving, a part of the side wall of the upper groove is also laser etched (the boundary point between the unetched side wall of the upper groove and the newly etched side wall of the second laser grooving is located on the same plane, and the first groove area and the second groove area use this plane as the boundary), so that the depth of the first groove area is slightly smaller than the depth of the first laser grooving, and the depth of the second groove area is slightly larger than the depth of the second laser grooving.

[0031] In a third aspect, the present invention provides a PERC cell, comprising: the substrate provided in the first aspect of the present invention, a back field layer arranged on the back side of the substrate, and a front passivation layer and a front electrode arranged in sequence from the front side of the substrate outward;

[0032] The portion of the back field layer located in the groove of the substrate is connected to the silicon layer with a PN junction in the substrate.

[0033] That is, the PERC cell includes: a silicon wafer layer with a PN junction, a back passivation layer, a protective layer and a back field layer sequentially arranged from the back side of the silicon wafer layer with a PN junction to the outside, and a front passivation layer and a front electrode sequentially arranged from the front side of the silicon wafer layer with a PN junction to the outside;

[0034] A plurality of grooves are formed on the back passivation layer and the protective layer, the grooves penetrate the back passivation layer and the protective layer, and the portion of the back field layer located in the grooves is connected to the silicon wafer layer with the PN junction;

[0035] The groove includes a first groove area and a second groove area along a depth direction, the second groove area is located at the bottom of the first groove area and is connected to the first groove area, and the opening area of ​​the first groove area is larger than the opening area of ​​the second groove area.

[0036] It should be noted that the front electrode is usually arranged to penetrate the front passivation layer and be connected to the silicon wafer layer having the PN junction.

[0037] By adopting the groove of the above structure on the PERC battery, the present invention can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering, increase the interlayer contact area, and reduce the contact resistance, compared with the groove of the same depth formed once.

[0038] As a preferred technical solution of the present invention, the PERC cell further comprises a back electrode disposed on the back field layer, the back electrode penetrates the back field layer and is connected to the protective layer, wherein the back electrode material may be silver.

[0039] Preferably, the thickness of the back field layer is 10-30 μm; for example, it may be 10 μm, 12 μm, 13 μm, 15 μm, 16 μm, 18 μm, 20 μm, 22 μm, 23 μm, 25 μm, 26 μm, 28 μm or 30 μm.

[0040] Preferably, the thickness of the front passivation layer is 60-100 nm; for example, it may be 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm.

[0041] The present invention has no special restrictions on the materials of each layer of the PERC cell, and those skilled in the art can make a selection based on general technical knowledge. Generally, when the main material of the silicon wafer layer with a PN junction is P-type silicon, the back passivation layer is an aluminum oxide film, the protective layer is a silicon nitride film, the front passivation layer is a silicon nitride film, or a stack of silicon oxide film and silicon nitride film; when the main material of the silicon wafer layer with a PN junction is N-type silicon, the back passivation layer is a silicon oxide film, the protective layer is a silicon nitride film, the front passivation layer is a silicon nitride film, or a stack of aluminum oxide film and silicon nitride film. The back field layer material can be aluminum, and the front electrode material can be silver.

[0042] In a fourth aspect, the present invention provides a method for preparing a PERC battery, comprising the following steps:

[0043] (1) Texturing the silicon wafer;

[0044] (2) performing front diffusion on the silicon wafer processed in step (1) to form an emitter;

[0045] (3) etching the silicon wafer processed in step (2) to remove the oxide layer;

[0046] (4) coating a back passivation layer and a protective layer on the back side of the silicon wafer treated in step (3), and coating a front passivation layer on the front side;

[0047] (5) performing a first laser grooving on the back of the PERC cell semi-finished product obtained after the process in step (4) to form a plurality of upper grooves arranged periodically; then performing a second laser grooving on the bottom of the upper grooves to form lower grooves, wherein the laser spot size of the second laser grooving is smaller than the laser spot size of the first laser grooving, and the areas of the upper grooves and the lower grooves together constitute the groove on the back of the PERC cell;

[0048] (6) printing a back field layer slurry on the back side of the semi-finished PERC cell processed in step (5), and printing a front electrode slurry on the front side;

[0049] (7) Sintering the PERC cell semi-finished product after processing in step (6) to obtain a PERC cell.

[0050] As a preferred technical solution of the present invention, the silicon wafer in step (1) is a P-type silicon wafer or an N-type silicon wafer.

[0051] Preferably, the diffusion in step (2) is boron diffusion or phosphorus diffusion.

[0052] Preferably, the etching method in step (3) is chain wet etching or plasma dry etching.

[0053] Preferably, the coating method in step (4) is tubular PECVD (plasma chemical vapor deposition) coating.

[0054] Preferably, before printing the back field layer slurry in step (6), the back electrode slurry is also printed on the back side of the PERC cell semi-finished product processed in step (5).

[0055] Preferably, the sintering temperature in step (7) is 740-820°C, for example, it can be 740°C, 750°C, 760°C, 770°C, 780°C, 790°C, 800°C, 810°C or 820°C, etc.; the time is 10-30s, for example, it can be 10s, 12s, 15s, 18s, 20s, 22s, 25s, 28s or 30s, etc.

[0056] Compared with the prior art, the present invention has the following beneficial effects:

[0057] The present invention adopts two laser grooving processes instead of one laser grooving process to prepare substrates and PERC cells, wherein the depth of the first laser grooving is relatively shallow, and the second laser grooving is performed on the basis of the first laser grooving process and has a relatively narrow width. Compared with the one-time laser grooving process, the groove structure formed by the two laser grooving processes has a relatively flat upper part and a narrow lower part. By adopting the groove of the above structure on the PERC cell, the present invention can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering, increase the interlayer contact area, and reduce the contact resistance, compared with the groove formed once with the same depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A schematic diagram of the cross-sectional structure of a PERC cell provided in Example 1 of the present invention;

[0059] Figure 2 A schematic diagram of the cross-sectional structure of a PERC cell provided in Example 2 of the present invention;

[0060] Figure 3 A schematic diagram of the cross-sectional structure of a PERC cell provided in Example 3 of the present invention;

[0061] Figure 4 This is a schematic diagram of the arrangement of the grooves on the back of a PERC cell in an embodiment of the present invention;

[0062] Figure 5 for Figure 1 , Figure 2 and Figure 3 An enlarged view of the A region in the middle, in which the dotted line between the first groove region and the second groove region represents the interface between the two;

[0063] Figure 6 A schematic diagram of the cross-sectional structure of an upper groove formed by the first laser grooving in an embodiment of the present invention;

[0064] Figure 7A schematic diagram of the cross-sectional structure of a lower groove formed by the second laser grooving in an embodiment of the present invention;

[0065] Among them, 1 is a silicon wafer layer with a PN junction, 2 is a back passivation layer, 3 is a protection layer, 4 is a back field layer, 5 is a front passivation layer, 51 is a front first passivation layer, 52 is a front second passivation layer, 6 is a front electrode, 7 is a groove, 71 is a first groove area, 72 is a second groove area, and 8 is a back electrode;

[0066] D 1 is the opening diameter of the first groove area, D 2 is the opening diameter of the second groove area, d 1 is the depth of the first laser groove, d 2 is the depth of the second laser grooving, and d is the total depth of the groove;

[0067] Figure 8 This is a scanning electron micrograph of the cross section of the groove of a PERC cell that has been laser-grooved once. The circled part is the cavity between the back field layer material and the silicon substrate. DETAILED DESCRIPTION

[0068] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementations. It should be understood by those skilled in the art that the specific implementations are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0069] Example 1

[0070] This embodiment provides a PERC battery, such as Figure 1 , Figure 4 and Figure 5 As shown, it includes: a silicon wafer layer 1 with a PN junction, a back passivation layer 2, a protection layer 3 and a back field layer 4 arranged in sequence from the back side of the silicon wafer layer 1 with a PN junction to the outside, and a front passivation layer 5 and a front electrode 6 arranged in sequence from the front side of the silicon wafer layer 1 with a PN junction to the outside;

[0071] A plurality of periodically arranged grooves 7 are provided on the back passivation layer 2 and the protective layer 3, the grooves 7 penetrate the back passivation layer 2 and the protective layer 3, and the portion of the back field layer 4 located in the grooves 7 is connected to the silicon wafer layer 1 having a PN junction;

[0072] The groove 7 includes a first groove area 71 and a second groove area 72 along the depth direction. The second groove area 72 is located at the bottom of the first groove area 71 and is connected to the first groove area 71. The area of ​​the cross section of the groove 7 perpendicular to the depth direction decreases as the depth increases.

[0073] The opening shape of the first groove area 71 is circular, and the opening diameter D 1 =24 μm;

[0074] The opening shape of the second groove area 72 is circular, and the opening diameter D 2 =12μm;

[0075] The total depth of the groove 7 is d=8 μm.

[0076] In this embodiment, the PERC cell is prepared by the following method:

[0077] (1) Select a P-type silicon wafer for texturing;

[0078] (2) performing front phosphorus diffusion on the P-type silicon wafer processed in step (1) to form an N-type emitter;

[0079] (3) performing chain wet etching on the silicon wafer after the treatment in step (2) to remove the oxide layer and form a silicon wafer layer 1 having a PN junction;

[0080] (4) using a tubular PECVD method, a 10 nm thick aluminum oxide film is deposited on the back of the silicon wafer layer 1 with a PN junction obtained in step (3) to form a back passivation layer 2; a 80 nm thick silicon nitride film is deposited on the back passivation layer 2 to form a protective layer 3; a 60 nm thick silicon nitride film is deposited on the front of the silicon wafer layer 1 with a PN junction to form a front passivation layer 5;

[0081] (5) Using a laser, setting the laser power to 10 W, the laser frequency to 1500 kHz, the scanning speed to 30 m / s, and the spot diameter to 24 μm, the back of the PERC cell semi-finished product obtained after the treatment in step (4) is subjected to the first laser grooving, and the grooving depth is d 1 = 4 μm, forming periodically arranged upper grooves (such as Figure 6 shown);

[0082] The laser power was set to 10 W, the laser frequency to 1500 kHz, the scanning speed to 30 m / s, and the spot diameter to 12 μm. The second laser grooving was performed at the bottom of the upper groove with a grooving depth of d. 2 = 4 μm, forming a lower groove (such as Figure 7 As shown), the areas of the upper groove and the lower groove together constitute the groove 7;

[0083] (6) After the processing in step (5), the back of the semi-finished PERC cell is screen-printed with aluminum paste with a thickness of 20 μm, and the front is screen-printed with silver paste, and sintered at 800° C. for 20 seconds to form a back field layer 4 and a front electrode 6, respectively, to obtain a PERC cell.

[0084] This embodiment uses two laser grooving operations instead of one laser grooving operation. The formed groove structure has a relatively flat upper portion and a narrow lower portion. Compared with a groove of the same depth formed once, it can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering, increase the interlayer contact area, and reduce the contact resistance.

[0085] Example 2

[0086] This embodiment provides a PERC battery, such as Figure 2 , Figure 4 and Figure 5 As shown, it includes: a silicon wafer layer 1 with a PN junction, a back passivation layer 2, a protection layer 3 and a back field layer 4 arranged in sequence from the back side of the silicon wafer layer 1 with a PN junction to the outside, and a front passivation layer 5 (composed of a front first passivation layer 51 and a front second passivation layer 52) and a front electrode 6 arranged in sequence from the front side of the silicon wafer layer 1 with a PN junction to the outside;

[0087] A plurality of periodically arranged grooves 7 are provided on the back passivation layer 2 and the protective layer 3, the grooves 7 penetrate the back passivation layer 2 and the protective layer 3, and the portion of the back field layer 4 located in the grooves 7 is connected to the silicon wafer layer 1 having a PN junction;

[0088] The groove 7 includes a first groove area 71 and a second groove area 72 along the depth direction. The second groove area 72 is located at the bottom of the first groove area 71 and is connected to the first groove area 71. The area of ​​the cross section of the groove 7 perpendicular to the depth direction decreases as the depth increases.

[0089] The opening shape of the first groove area 71 is circular, and the opening diameter D 1 =14μm;

[0090] The opening shape of the second groove area 72 is circular, and the opening diameter D 2 =7μm;

[0091] The total depth of the groove 7 is d=4 μm.

[0092] In this embodiment, the PERC cell is prepared by the following method:

[0093] (1) Select an N-type silicon wafer for texturing;

[0094] (2) performing front boron diffusion on the N-type silicon wafer processed in step (1) to form a P-type emitter;

[0095] (3) performing chain wet etching on the silicon wafer after the treatment in step (2) to remove the oxide layer and form a silicon wafer layer 1 having a PN junction;

[0096] (4) using a tubular PECVD method, a 15 nm thick silicon oxide film is deposited on the back of the silicon wafer layer 1 with a PN junction obtained in step (3) to form a back passivation layer 2; a 120 nm thick silicon nitride film is deposited on the back passivation layer 2 to form a protective layer 3; a 50 nm thick aluminum oxide film (front first passivation layer 51) is first deposited on the front of the silicon wafer layer 1 with a PN junction, and then a 50 nm thick silicon nitride film (front second passivation layer 52) is deposited to form a front passivation layer 5;

[0097] (5) Using a laser, setting the laser power to 5 W, the laser frequency to 1500 kHz, the scanning speed to 30 m / s, and the spot diameter to 14 μm, the back of the PERC cell semi-finished product obtained after the treatment in step (4) is subjected to the first laser grooving, and the grooving depth is d 1 = 2 μm, forming periodically arranged upper grooves (such as Figure 6 shown);

[0098] The laser power was set to 5W, the laser frequency to 1500kHz, the scanning speed to 30m / s, and the spot diameter to 7μm. The second laser grooving was performed at the bottom of the upper groove with a grooving depth of d. 2 = 2 μm, forming a lower groove (such as Figure 7 As shown), the areas of the upper groove and the lower groove together constitute the groove 7;

[0099] (6) After the processing in step (5), the back of the semi-finished PERC cell is screen-printed with aluminum paste with a thickness of 30 μm, and the front is screen-printed with silver paste, and sintered at 800° C. for 20 seconds to form a back field layer 4 and a front electrode 6, respectively, to obtain a PERC cell.

[0100] This embodiment uses two laser grooving operations instead of one laser grooving operation. The formed groove structure has a relatively flat upper portion and a narrow lower portion. Compared with a groove of the same depth formed once, it can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering, increase the interlayer contact area, and reduce the contact resistance.

[0101] Example 3

[0102] This embodiment provides a PERC battery, such as Figure 3 , Figure 4 and Figure 5 As shown, it includes: a silicon wafer layer 1 with a PN junction, a back passivation layer 2, a protective layer 3, a back field layer 4 and a back electrode 8 arranged in sequence from the back side of the silicon wafer layer 1 with a PN junction to the outside, and a front passivation layer 5 (composed of a front first passivation layer 51 and a front second passivation layer 52) and a front electrode 6 arranged in sequence from the front side of the silicon wafer layer 1 with a PN junction to the outside;

[0103] A plurality of periodically arranged grooves 7 are provided on the back passivation layer 2 and the protective layer 3, the grooves 7 penetrate the back passivation layer 2 and the protective layer 3, and the portion of the back field layer 4 located in the grooves 7 is connected to the silicon wafer layer 1 having a PN junction;

[0104] The groove 7 includes a first groove area 71 and a second groove area 72 along the depth direction. The second groove area 72 is located at the bottom of the first groove area 71 and is connected to the first groove area 71. The area of ​​the cross section of the groove 7 perpendicular to the depth direction decreases as the depth increases.

[0105] The opening shape of the first groove area 71 is circular, and the opening diameter D 1 =34 μm;

[0106] The opening shape of the second groove area 72 is circular, and the opening diameter D 2 =17μm;

[0107] The total depth of the groove 7 is d=12 μm.

[0108] In this embodiment, the PERC cell is prepared by the following method:

[0109] (1) Select a P-type silicon wafer for texturing;

[0110] (2) performing front phosphorus diffusion on the P-type silicon wafer processed in step (1) to form an N-type emitter;

[0111] (3) performing chain wet etching on the silicon wafer after the treatment in step (2) to remove the oxide layer and form a silicon wafer layer 1 having a PN junction;

[0112] (4) using a tubular PECVD method, a 12 nm thick aluminum oxide film is deposited on the back of the silicon wafer layer 1 with a PN junction obtained in step (3) to form a back passivation layer 2; a 100 nm thick silicon nitride film is deposited on the back passivation layer 2 to form a protective layer 3; a 40 nm thick silicon oxide film (front first passivation layer 51) is first deposited on the front of the silicon wafer layer 1 with a PN junction, and then a 40 nm thick silicon nitride film (front second passivation layer 52) is deposited to form a front passivation layer 5;

[0113] (5) Using a laser, setting the laser power to 15 W, the laser frequency to 1500 kHz, the scanning speed to 30 m / s, and the spot diameter to 34 μm, the back of the PERC cell semi-finished product obtained after the treatment in step (4) is subjected to the first laser grooving, and the grooving depth is d 1 = 6 μm, forming periodically arranged upper grooves (such as Figure 6 shown);

[0114] The laser power was set to 15 W, the laser frequency to 1500 kHz, the scanning speed to 30 m / s, and the spot diameter to 17 μm. The second laser grooving was performed at the bottom of the upper groove, with a grooving depth of d. 2 = 6μm, forming a lower groove (such as Figure 7 As shown), the areas of the upper groove and the lower groove together constitute the groove 7;

[0115] (6) After the processing in step (5), the back of the semi-finished PERC battery is first screen-printed with silver paste, and then screen-printed with aluminum paste with a thickness of 10 μm; the front is screen-printed with silver paste, and sintered at 800° C. for 20 seconds to form a back electrode 8, a back field layer 4 and a front electrode 6, respectively, to obtain a PERC battery.

[0116] This embodiment uses two laser grooving operations instead of one laser grooving operation. The formed groove structure has a relatively flat upper portion and a narrow lower portion. Compared with a groove of the same depth formed once, it can effectively reduce the generation of voids between the back field layer material and the silicon substrate after sintering, increase the interlayer contact area, and reduce the contact resistance.

[0117] Comparative Example 1

[0118] A PERC cell is provided, which differs from Example 1 in that in step (5), laser grooving is performed only once, the grooving depth is 8 μm, and the opening diameter of the groove is 24 μm.

[0119] Comparative Example 2

[0120] A PERC cell is provided, which differs from Example 2 in that in step (5), laser grooving is performed only once, the grooving depth is 4 μm, and the opening diameter of the groove is 14 μm.

[0121] Comparative Example 3

[0122] A PERC cell is provided, which differs from Example 3 in that in step (5), laser grooving is performed only once, the grooving depth is 12 μm, and the opening diameter of the groove is 34 μm.

[0123] At 1000W / m 2 The conversion efficiency, voltage, current, fill factor, R s (series resistance) and R sh (parallel resistance) was tested, and the performance data was automatically analyzed by Halm software (model 18KW-05). The results are shown in Table 1 below:

[0124] Table 1

[0125]

[0126] By comparing the electrical performance parameters of the PERC cells provided by Examples 1-3 and Comparative Examples 1-3, it can be seen that the PERC cells provided by the present invention have higher conversion efficiency, smaller series resistance, and higher fill factor, indicating that the back aluminum of the PERC cells prepared by two laser groovings of the present invention is in closer contact with the silicon substrate and fewer voids are formed.

[0127] The applicant declares that the above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention shall fall within the protection scope and disclosure scope of the present invention.

Claims

1. A substrate for a PERC cell, characterized in that: The substrate comprises a silicon wafer layer with a PN junction, and a back passivation layer and a protective layer sequentially arranged from the back of the silicon wafer layer with a PN junction to the outside; a plurality of grooves are formed on the back passivation layer and the protective layer, and the grooves penetrate the back passivation layer and the protective layer; The groove includes a first groove area and a second groove area along the depth direction, the second groove area is located at the bottom of the first groove area and is connected to the first groove area, and the opening area of ​​the first groove area is larger than the opening area of ​​the second groove area; The thickness of the protective layer is 80-120 nm.

2. The substrate according to claim 1, characterized in that The area of ​​the cross section of the groove perpendicular to the depth direction decreases as the depth increases.

3. The substrate according to claim 1, characterized in that The plurality of grooves are arranged periodically.

4. The substrate according to claim 1, characterized in that The total depth of the grooves is 4-12 μm.

5. The substrate according to claim 1, characterized in that The depth of the first groove region is 1.8-5.4 μm, and the depth of the second groove region is 2.2-6.6 μm.

6. The substrate according to claim 1, characterized in that The ratio of the depth of the first groove area to the depth of the second groove area is 1:1.5-1.5:

1.

7. The substrate according to claim 6, characterized in that The ratio of the depth of the first groove region to the depth of the second groove region is 1:

1.

8. The substrate according to claim 1, characterized in that The opening shape of the first groove area and the opening shape of the second groove area are circular.

9. The substrate according to claim 8, characterized in that The opening diameter of the first groove area is 14-34 μm.

10. The substrate according to claim 8, characterized in that The ratio of the opening diameter of the second groove area to the opening diameter of the first groove area is 1-3:

4.

11. The substrate according to claim 1, characterized in that The thickness of the back passivation layer is 10-15 nm.

12. A method for preparing a substrate according to any one of claims 1 to 11, characterized in that: The preparation method comprises the following steps: (a) performing a first laser groove on the back side of a silicon wafer having a PN junction and coated with a back passivation layer and a protective layer to form an upper groove; (b) performing a second laser grooving at the bottom of the upper groove to form a lower groove, wherein the laser spot size of the second laser grooving is smaller than the laser spot size of the first laser grooving, and the areas of the upper groove and the lower groove together constitute a groove on the back side of the substrate.

13. The preparation method according to claim 12, characterized in that: The diameter of the laser spot of the first laser grooving is 14-34 μm.

14. The preparation method according to claim 12, characterized in that: The ratio of the diameter of the laser spot of the second laser grooving to the diameter of the laser spot of the first laser grooving is 1-3:

4.

15. The preparation method according to claim 12, characterized in that: The depth of the first laser grooving is 2-6 μm, and the depth of the second laser grooving is 2-6 μm.

16. A PERC cell, characterized in that: The PERC cell comprises: a substrate according to any one of claims 1 to 11, a back field layer arranged on the back side of the substrate, and a front passivation layer and a front electrode arranged in sequence from the front side of the substrate outward; The portion of the back field layer located in the groove of the substrate is connected to the silicon layer with a PN junction in the substrate.

17. The PERC cell according to claim 16, characterized in that: The PERC cell further includes a back electrode disposed on the back field layer, wherein the back electrode penetrates the back field layer and is connected to the protective layer in the substrate.

18. The PERC cell according to claim 16, characterized in that: The thickness of the back field layer is 10-30 μm.

19. The PERC cell according to claim 16, characterized in that: The thickness of the front passivation layer is 60-100 nm.

20. A method for preparing a PERC cell according to any one of claims 16 to 19, characterized in that: The preparation method comprises the following steps: (1) Texturing the silicon wafer; (2) performing front diffusion on the silicon wafer processed in step (1) to form an emitter; (3) etching the silicon wafer processed in step (2) to remove the oxide layer; (4) coating a back passivation layer and a protective layer on the back side of the silicon wafer treated in step (3), and coating a front passivation layer on the front side; (5) performing a first laser grooving on the back of the PERC cell semi-finished product obtained after the process in step (4) to form a plurality of upper grooves arranged periodically; performing a second laser grooving on the bottom of the upper grooves to form lower grooves, wherein the laser spot size of the second laser grooving is smaller than the laser spot size of the first laser grooving; (6) printing a back field layer slurry on the back side of the semi-finished PERC cell processed in step (5), and printing a front electrode slurry on the front side; (7) Sintering the PERC cell semi-finished product after processing in step (6) to obtain a PERC cell.

21. The preparation method according to claim 20, characterized in that: The silicon wafer in step (1) is a P-type silicon wafer or an N-type silicon wafer.

22. The preparation method according to claim 20, characterized in that: The diffusion in step (2) is boron diffusion or phosphorus diffusion.

23. The preparation method according to claim 20, characterized in that: The etching method in step (3) is chain wet etching or plasma dry etching.

24. The preparation method according to claim 20, characterized in that: The coating method in step (4) is tubular PECVD coating.

25. The preparation method according to claim 20, characterized in that: In step (6), before printing the back field layer slurry, the back electrode slurry is also printed on the back of the PERC cell semi-finished product processed in step (5).

26. The preparation method according to claim 20, characterized in that: The sintering temperature in step (7) is 740-820° C. and the sintering time is 10-30 seconds.

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